Chapter 5

Arithmetic Logic Functions

Page 2

This Chapter..

We will be looking at multi-valued arithmetic and logic functions

Bitwise AND , OR, EXOR, SHIFT etc: Logic functions

ADD, SUBTRACT, etc. Arithmetic functions

Page 3

Iterative Functions and circuits

Multi-bit logical functions (AND, OR, etc.) have functional independence between bits E.G. for a multi-bit AND where we want to find

F= A. B we have

On the other hand, Arithmetic functions DO have dependence bit to bit (carry or borrow)

The functions are the same at each bit position but dependent on the previous bit

These functions are known as ITERATIVE

iii B A F

Page 4

Iterative Functions

cell or stagei-1

cell or stage

i

cell or stagen-1

cell or stage

0

BiAi

Fi

Xi

Yi

Bi-1Ai-1

Fi-1

Xi-1

Yi-1

B0A0

F0

X0

Y0

Bn-1An-1

Fn-1

Xn-1

Yn-1

. . .

. . .. . .. . .

Page 5

Networks for Binary Addition

Half Adder - adds two bits together; generates sum and carry

Half-adder Schematic

Carry

Sum A i

B i

Ai 0 0 1 1

Bi 0 1 0 1

Sum 0 1 1 0

Carry 0 0 0 1

AiBi

0 1

0

1

0 1

1 0

Sum = Ai Bi + Ai Bi

= Ai + Bi

AiBi

0 1

0

1

0 0

10

Carry = Ai Bi

Page 6

Networks for Binary Addition

Full Adder - adds three bits, one being a carry bit

Cascaded Multi-bit

Adder

usually interested in adding more than two bits

this motivates the need for the full adder

stage0

B0A0

S0

C1stage1

S1

C2stage0

S2

C3stage0

S3

C4

B1A1B2A2B3A3

C0

Page 7

Networks for Binary Addition

Full Adder

S = Cin xor A xor BCout = B Cin + A Cin + A B But we can also write in long form

=AB+CinA’B+CinAB’

= Cin (A xor B) + A B

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

Cin0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

Cout 0 0 0 1 0 1 1 1

A BCin

0

1

00 01 11 10

0

1

1

0

1

0

0

1

A B

Cin

0

1

00 01 11 10

0

0

0

1

0

1

1

1

S

COut

x

Page 8

Networks for Binary AdditionFull Adder/Half Adder implementation

Alternative Implementation: 5 Gates

Standard Approach: 6 Gates

A

AA

B

BB

Cin

CinS

Cout

Half Adder

A

B

Half Adder

A + B

Cin

A + B + CinS S

CoutCoutCin (A+ B)A B

S

Cout

Cout= A B + Cin (A xor B)

Page 9

Networks for Binary Addition

Page 10

Parallel(Ripple-Carry) Adder

Page 11

Parallel Adder-Subtractor

Parallel Adder-Subtractor with 2’s complement numbers:

To subtract, we take the 2’s complement of the second number and add

To take 2’s complement use the approach: Take 1’s complement(Complement bit by bit) and add 1.

To add 1, we will use the carry-in to the rightmost FA.

Assume a select line called Add/subtract

Page 12

Networks for Binary AdditionParallel Adder/Subtractor - assumes 2’s complement representation

A - B = A + (-B) = A + B + 1

A B

CO

S

FA CI

A B

CO

S

FA CI

A B

CO

S

FACI

A B

CO

S

FA CI

0 1

Add/Subtract

A 3 B 3 B 3

0 1

A 2 B 2 B 2

0 1

A 1 B 1 B 1

0 1

A 0 B 0 B 0

Sel Sel Sel Select

S 3 S 2 S 1 S 0

Overflow

Remember subtraction is the same as taking the 2’s complement and adding,so

if add/subtract=1, complement b and add 1 from the rightmost Cin

2x1 mux

Page 13

Networks for Binary Addition

The Propagation Delay in Above Circuit: 3 gate delays for each full adder, but waits for 2

gate delays For a 32 bit adder/subtractor, longest total delay is

32*2+1= 65 gate delays(will show in the next slide)

Too long-should be a shorter way Assume A, B and C0 are presented to the input at

the same time and all gates have the same delay

Page 14

Networks for Binary AdditionCarry Lookahead Circuits - making things fast

Critical delay: the propagation of carry from low to high order stages

latearrivingsignal

two gate delaysto compute Cout

4 stageadder

final sum andcarry

@N+2

A 0

B 0

C 0

S 0 @2

A 1

B 1

C 1 @3

S 1 @4

A 2

B 2

C 2 @5

S 2 @6

A 3

B 3

C 3 @7

S 3 @8

C 4 @9

0

1

2

3

A

A

B

B

Cin Cout

@0@0

@0@0

@N

@1

@1

@N+1

Calculated in parallel

Page 15

Networks for Binary Addition

Carry Lookahead Logic

Carry Generate Gi = Ai Bi must generate carry when A = B = 1

Carry Propagate Pi = Ai xor Bi carry in will equal carry out here

Si = Ai xor Bi xor Ci = Pi xor Ci

Ci+1 = Ai Bi + Ci (Ai xor Bi)

Ci+1 = Gi + Ci P i

Sum and Carry can be reexpressed in terms of generate/propagate:

Idea: each carry can be expressed in terms of Ai, Bi and C0

Page 16

Networks for Binary AdditionCarry Lookahead Logic

Reexpress the carry logic as follows:

C1 = G0 + P0 C0

C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0

C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0

C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0

Each of the carry equations can be implemented in a two-level logic network

Variables are the adder inputs and carry in to stage 0!

Page 17

Networks for Binary AdditionCarry Lookahead Implementation

Adder with Propagate and Generate Outputs

Increasingly complex logic

C0

G3

Pi @ 1 gate delay

Ci Si @ 2 gate delays

BiAi

Gi @ 1 gate delay

C0P0

G0

C1

C0P0

G0

P1

P1

G1

C2

P0

G0P1

P1

G1P2

P2

P2

G2

C3

C0P0

G0P1

P1

G1P2

P2

P2

G2P3

P3

P3

P3

C4

Page 18

Networks for Binary AdditionCarry Lookahead Logic

Cascaded Carry Lookahead

Carry lookaheadlogic generatesindividual carries

sums computedmuch faster

A 0

B 0

C 0

S 0 @2

A 1

B 1

C 1 @3

S 1 @4

A 2

B 2

C 2 @3

S 2 @4

A 3

B 3

C 3 @3

S 3 @4

C 4 @3

Page 19

Ripple Carry adder

Carry-save adder

Carry-lookahead unit

Partial Full Adder

Page 20

Networks for Binary Addition

Propagation Delay in CLA Adder: Assume a 4-bit adder Since each carry will be generated in with a

2-level And-or network, there will be a delay of 2 in CLA unit

Other delays: 2 in PFA So total delay: 4 Ripple carry delay: was 8

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When the number of bits increase, the savings become more appearent but the CLA fan-in will increase unacceptably

What to do? Use cascaded approach

Page 22

Networks for Binary AdditionCarry Lookahead Logic

Cascaded Carry Lookahead

4 bit adders with internal carry lookahead

second level carry lookahead unit, extends lookahead to 16 bits

4-bit Adder

4 4

4

A [15-12] B [15-12] C 12 C 16

S [15-12]

P G 4-bit Adder

4 4

4

A [1 1-8] B [1 1-8] C 8

S [1 1-8]

P G 4-bit Adder

4 4

4

A [7-4] B [7-4] C 4

S [7-4]

P G 4-bit Adder

4 4

4

A [3-0] B [3-0] C 0

S [3-0]

P G

Lookahead Carry Unit C 0

P 0 G 0 P 1 G 1 P 2 G 2 P 3 G 3 C 3 C 2 C 1

C 0

P 3-0 G 3-0

C 4

@3 @2

@0

@4

@4 @3 @2 @5

@7

@3 @2 @5

@8 @8

@3 @2

@5

@5 @3

@0

C 16

Page 23

BCD AdditionDecimal digits 0 thru 9 represented as 0000 thru 1001 in binary

Addition:

5 = 0101

3 = 0011

1000 = 8

5 = 0101

8 = 1000

1101 = 13!

Problemwhen digit

sum exceeds 9

Solution: add 6 (0110) if sum exceeds 9!

5 = 0101

8 = 1000

1101

6 = 0110

1 0011 = 1 3 in BCD

9 = 1001

7 = 0111

1 0000 = 16 in binary

6 = 0110

1 0110 = 1 6 in BCD

Page 24

BCD Addition

Adder Design

Add 0110 to sum whenever it exceeds 1001 (11XX or 1X1X)

F A F A F A F A

F A F A

Cin

A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0

Cout S 3 S 2 S 1 S 0

0

CO CI

S

CO CI

S

CO CI

S

CO CI

S

CO CI

S

CO CI

S

1 1XX A1

A2 1X1X

Page 25

Incrementing and Decrementing by 1

Use ‘value fixing’ İf you want S= A+1, then use

adder/subtractor as: A= A, B=0 Cin= 1, function: add How about S= A-1? A=A, B= 00001, Cin=0, Fn: subtractOr, B=1111111, Cin=0, fn: add May have inc/dec in the same circuit Make at home

Page 26

Multiplication and Division by Constants

Shift function: a word can be shifted right or left as many positions as you like with proper circuitry

For a binary number, shifting left one digit means dividing by 2! Shifting right means multiplying by 2!

But be careful with inserted digits. Will study later with shift registers.