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Chapter 5 Interrupt

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Chapter 5 Interrupt. INTERRUPTS. is an event that requires the CPU to stop normal execution and perform some service related to the event. . Interrupt Structure. The PIC18F microcontrollers support multiple interrupts: internal interrupts external interrupts. . Interrupt Structure. - PowerPoint PPT Presentation
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Page 1: Chapter 5 Interrupt

Chapter 5

Interrupt

1

Page 2: Chapter 5 Interrupt

is an event that requires the CPU to stop normal execution and perform some service related to the event.

2

INTERRUPTS

Page 3: Chapter 5 Interrupt

3

Interrupt Structure

The PIC18F microcontrollers support multiple interrupts:

• internal interrupts• external interrupts.

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Interrupt StructureInterrupt priority • allows interrupt sources to be assigned

a high-priority level will branch to 0x0008h

a low-priority level will branch to 0x0018h

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Interrupt Structure

• High-priority interrupt events will interrupt any low-priority interrupts.

• Low-priority interrupts are not processed while high-priority interrupts are in progress.

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Interrupt Structure• Each interrupt has an

individual interrupt flag and mask bit.

• It has an associated request bit (IF), enable bit (IE) and priority bit (IP).

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Interrupt Structure

All the interrupts can be • enabled by setting or

• disabled by clearing the GIE bit.

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Interrupt StructureIt supports two modes:

Legacy mode: • supports only 1 interrupt vector and

• branches to 0x00008h for others.

• can be selected by clearing the IPEN bit in RCON register.

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Interrupt StructureThere are ten registers which are used to control interrupt operation. These registers are:

• PIR2• PIE1• PIE2• IPR1• IPR2

• RCON• INTCON• INTCON2• INTCON3• PIR1

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Interrupt StructureInterrupt sources have 3 bits to control their operation. They are:

Flag bit to indicate that an interrupt event occurred.

Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set.

Priority bit to select high priority or low priority.

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The Interrupt Priority• is enabled by setting the IPEN bit

(RCON<7>).

• When interrupt priority is enabled, there are two bits which enable interrupts globally.  

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The Interrupt Priority

• Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set. (high priority).

• Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared. (low priority).

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The Interrupt Priority• When the IPEN bit is cleared (default

state), the interrupt priority feature is disabled.

INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources.

INTCON<7> is the GIE bit, which enables/disables all interrupt sources.

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The Interrupt Priority

• All interrupts branch to address 0008h in Compatibility mode.

• The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE bit which re-enables interrupts..

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PIC18 Interrupt Logic

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RCON Register

• Bit (IPEN) to enable interrupt priority • The other bits are used to indicate the

cause of reset.

R/W-0 U-0 R/W-1 R-1 R-1 R/W-0(1) R/W-0

IPEN — RI TO PD POR BOR

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INTCON Registers

These 3 registers contain • enable, • priority and• flag bits for external INT pins, portB pin change and TIMER0 (TMR0) overflow interrupts.

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INTCON RegistersINTCON: INTERRUPT CONTROL REGISTER

REGISTER 5-2: INTCON: INTERRUPT CONTROL REGISTER

INTCON2: INTERRUPT CONTROL REGISTER2

INTCON3: INTERRUPT CONTROL REGISTER

R/W- 1 R/W- 1 U-0 R/W- 0 R/W- 0 U-0 R/W- 0 R/W- 0

INT2IP INT1IP —

INT2IE INT1IE — INT2IF INT1IF

R/W- 0 R/W- 0 R/W- 0 R/W- 0 R/W- 0 R/W- 0 R/W- 0 R/W- xGIE/GIEH

PEIE/ GIEL TMR0E INT0IE RBIE TMR0F INT0IF RBIF(1)

R/W- 1 R/W- 1 R/W- 1 R/W- 1 U-0 R/W- 1 U-0 R/W- 1

RBPU

INTEDG0

INTEDG1

INTEDG2 —— TMR0I

P —— RBIP

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INTx Pin Interrupts

• edge-triggered.• If the corresponding INTEDGx bit in the

INTCON2 register is set (= 1), the interrupt is triggered

by a rising edge; cleared (= 0), the trigger is on the

falling edge.

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TMR0 Interrupt

In 8-bit mode

• an overflow in the TMR0 register (FFh →00h) will set flag bit, TMR0IF.

In 16-bit mode

• an overflow in the TMR0H:TMR0L register pair (FFFFh →0000h) will set flag bit,TMR0IF.

• The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>).

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PORTB Interrupt-on-Change

• An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>).

• The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>).

• Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>).

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RESET

The main function is to establish appropriate values for key registers so that the MCU can start or restart properly.

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RESET

The PIC18 MCU differentiates between various kinds of reset:• Power-On reset (POR).• MCLR pin reset during normal operation.• MCLR pin reset during SLEEP.• Watchdog timer (WDT) reset.• Programmable brown-out reset (BOR).• RESET instruction.• Stack Full reset.• Stack Underflow reset.


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