Chapter 5 - Slide_Part_IV

8/10/2019 Chapter 5 - Slide_Part_IV

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Counters

Circuits that can increment or decrement a

count by 1

Designed using T and D flip-flops

Asynchronous Counters:

Up-Counter with T Flip-Flops

Down-Counter with T Flip-Flops

Synchronous Counters:

Synchronous Counter with T Flip-Flop

Synchronous Counter with D Flip-Flop


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Counters

Counters with Parallel Load

Normally, initial count being equal to 0

Sometimes it is desirable to start with differentcount

Other types of counters:

BCD CounterRing Counter

Johnson Counter


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Asynchronous Counter

Asynchronousevents that do not occur at

the same time

An asynchronous counter is one in which

the flip-flops within the counter do not

change states at exactly the same time

because they do not have a common clockpulse


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Up-Counter with T Flip-Flops

3-bit counter from 0 to 7

Clock inputs are connected in cascade

T input of each flip-flop is connected to

constant 1

Because it counts in the upward direction,

we call it an up-counter


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Figure 5.19. A three-bit up-counter.

T Q

QClock

T Q

Q

T Q

Q

1

Q0 Q1 Q2

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 4 5 6 7 0

(b) Timing diagram


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Example 1

Implement 3-bit up-counter using JK flip-

flops?


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Answer


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Down-Counter with T Flip-Flops

Clock inputs of the 2ndand 3rdflip-flops are

driven by the Q outputs of the preceding

stages

The circuit counts in the sequence

0,7,6,5,4,3,2,1,0,7,6

Because it counts in downward direction,we call it down-counter


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Figure 5.20. A three-bit down-counter.

T Q

QClock

T Q

Q

T Q

Q

1

Q0 Q1 Q2

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 7 6 5 4 3 2 1 0

(b) Timing diagram


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Synchronous Counter

Asynchronous counters are simple, but not

very fast

The delays caused by the cascaded clocking

scheme may become too long

We can build a faster counter by clocking

all flip-flops at the same time synchronous counter


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Table 5.1. Derivation of the synchronous up-counter.

00

1

1

01

0

1

01

2

3

0

0

1

0

1

0

4

5

6

1 17

00

0

0

1

1

1

1

Clock cycle

0 08 0

Q2 Q1 Q0Q1 changes

Q2changes

Synchronous Counter with

T Flip-Flops


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T Flip-Flops T0= 1

T1= Q0

T2= Q0Q1

Example 4-bit synchronous up-counter

Instead of using AND gates of increasedsize for each stage, we use a factored

arrangement


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Figure 5.21. A four-bit synchronous up-counter.

T Q

QClock

T Q

Q

T Q

Q

1Q0 Q1 Q2

(a) Circuit

Clock

Q0

Q1

Q2

Count 0 1 2 3 5 9 12 14 0

(b) Timing diagram

T Q

Q

Q3

Q3

4 6 87 10 11 13 15 1


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Enable & Clear Capability

Often it is desirable to be able to inhibit

counting, so that the count remains in its

present state

This may be accomplished by including an

Enable control signal

The clear inputs on all flip-flops isnecessary to start with the count equal to

zero


15/33

Figure 5.22. Inclusion of Enable and Clear capability.

T Q

QClock

T Q

Q

Enable

Clear_n

T Q

Q

T Q

Q


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D Flip-Flops Example - 4-bit up-counter that counts in

the sequence 0, 1, 2, . . . , 14, 15, 0, 1,

and so on IfEnable= 1, D could be expressed as

figure


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Figure 5.23. A four-bit counter with D flip-flops.


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Sometimes it is desirable to start with a

different count

To allow this mode of operation, a countercircuit must have some inputs through

which the initial count can be loaded

A two-input multiplexer is inserted beforeeach D input


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One input to the multiplexer is used to

provide the normal counting operation

The other input is a data bit that can beloaded directly into the flip-flop

A control input,Load, is used to choose the

mode of operation The circuit counts whenLoad= 0

A new initial value, D3D2D1D0, is loaded

into the counter whenLoad

= 1



20/33Figure 5.24. A counter with parallel-load capability.


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Reset Synchronization

Synchronous reset

AND in the next clock pulse

Asynchronous reset

Clear feature

Example - a modulo-6 counter, for which

the counting sequence is 0, 1, 2, 3, 4, 5, 0, 1,and so on


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Figure 5.25. A modulo-6 counter with synchronous reset.

Enable

Q0Q1

Q2

D0D1

D2

Load

Clock

1

0

0

0

Clock

0 1 2 3 4 5 0 1

Clock

Count

Q0

Q1

Q2

(a) Circuit

(b) Timing diagram


23/33

Figure 5.26. A modulo-6 counter with asynchronous reset.

T Q

QClock

T Q

Q

T Q

Q

1Q0 Q1 Q2

(a) Circuit

Clock

Q0

Q1

Q2

Count

(b) Timing diagram

0 1 2 3 4 5 0 1 2


24/33

Example 2

Which one is better? Synchronous reset or

Asynchronous reset and, Why?


25/33

Answer

The timing diagrams in Figures 5.25(b) and

5.26(b) suggest that synchronous reset is a

better choice than asynchronous reset The flip-flops are cleared to 0 a short time

after the NAND gate has detected the count

of 5


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Example 3


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Answer


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Example 4


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Answer


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Example 5


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Answer (continued)


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Other Types of Counter

BCD Counter

Binary-Coded-Decimal (BCD) Counter uses

decimal counting sequence

Ring Counter

Johnson Counter

Both (Ring & Johnson) counting sequence donot represent binary numbers

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Chapter 5 - Slide_Part_IV

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