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Chapter 6

Design, Simulation and Measurements of Parameters

6.1 Introduction

In this chapter, we present the experimental results for the designed stages in monolithic

IA. The CMOS monolithic IA has been designed with standard CMOS technology -

0.25μm.The SPICE models have been used for the experimental simulations. Also, the IA

have been designed using different Library enriched Industry standard tools like TANNER

and CADENCE. All the building blocks of IA circuits are designed, implemented and

simulated for desired parameters. The length (L) of the MOSFETs is kept at higher value

except for those used as current source loads at cascode op amp, to get desired gain and

linear operation. If L is selected of lower value, the higher bandwidth can be obtained but

at the cost of reduced gain and nonlinear operation. Width of MOSFETs is calculated to

meet the requirement of gain, maximum output voltage swing and power dissipation. The

different stages in the IA are designed to meet the performance parameters and their

frequency & phase responses are plotted. For every stage the design is carried out to meet

utmost design parameters. The design process is implemented using TANNER EDA tool

in 250 nm technology and CADENCE EDA tool in 180 nm technology. The research is

limited to schematic of the IA, the verification of its parameters; CMRR, ICMR, frequency

and phase response and preparation of layout at last to get the size of chip.

6.2 CAD Tools Available & Deployed

1. SPICE (Simulation Program for Integrated Circuits Emphasis) [54] is an analog circuit

simulator tool developed at University of Berkeley. Many different versions of SPICE

are available from many different vendors. Common SPICEs include HSPICE,

PSPICE, and B2SPICE. It has parts library over 30000 parts and graphical editor also.

SPICE takes a circuit net list and performs mathematical simulation of the circuit

behavior. It also provides log of simulation process, errors, warnings, and statistic at

each simulation run.

2. MICROWIND & DSCH: Microwind 3 is a user friendly PC based for Windows tool

(95, 98, NT, XP) for designing and simulating microelectronic circuits at layout level

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[55]. The tool features full editing facilities (cut, paste, duplicate, move, stretch),

attractive views (MOS characteristics, 2-D cross-section, 3-D cross-section), atomic

views and an on line analog simulator. DSCH3 is the companion software for logic

design. Based on primitives, a hierarchical circuit is built and simulated. Interactive

symbols are used for friendly simulation, which includes power consumption,

evaluation. It also provides model and assembly support for 8051 and PIC 16F84

microcontrollers.

3. MAGIC SOFTWARE: MAGIC [56] features real-time design rule checking which

some costly commercial VLSI designs software packages do not feature. MAGIC

currently runs under Linux, although versions exist for DOS, OS/2 and other operating

systems. MAGIC is frequently used in the conjunction with IRSIM and other

simulation programs.

4. MENTOR GRAPHICS: It provides Simulation tools for analog, digital as well as

mixed-signal design [57]. It provides number of powerful tools, some of them are:

ModelSim: is a popular hardware simulation and debug environment. It provides

seamless, scalable performance and capabilities. A single compiler and library system

is used for all ModelSim configurations. ModelSim allows many debug and analysis

capabilities to be employed post simulation on saved results as well as during live

simulation runs.

Eldo: is an analog simulator offering many simulation and modeling options which

can deliver accurately high-performance and high-speed simulation.

Calibre: is the industry standard platform for physical verification and also offers

superior performance and capacity. Calibre xRC is an accurate transistor-level, gate-

level and hierarchical parasitic extraction.

5. CADENCE: Cadence® Virtuoso® Schematic Editor provides numerous capabilities to

facilitate fast and easy design entry, including design assistants that speed common

tasks by as much as 5x. Well-defined component libraries allow faster design at device

levels. Sophisticated wire routing capabilities further assist in connecting devices.

6. TANNER EDA tools: The EDA tool Tanner provides a complete software solution that

catalyzes innovation for the design, layout and verification of analog and mixed-signal

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(A/MS) integrated circuits (ICs). It incorporates fully integrated front end and back end

tools; from schematic capture, circuit simulation, and waveform probing to physical

layout and verification. Also its advanced features improve designer productivity,

including foundry-compatible physical verification, Verilog-A simulation, interactive

auto-routing, and device layout automation.

Different Modules in tanner

1. S-Edit

2. T Spice

3. W Edit

4. L Edit

5. LVS

6.3 Tanner EDA Software Tools - Driving Innovation for Analog IC, Mixed

Signal & MEMS Design

With Tanner EDA providing [59] a complete line of software solutions for integrated

circuits (ICs), customers are creating breakthrough applications in areas such as power

management, displays and imaging, automotive, consumer electronics, life sciences, and

RF devices. Design team productivity is improved by low learning curve, high

interoperability, and a powerful user interface and enabled a low Total Cost of Ownership

(TCO). The low support requirements and high support capability match capability and

performance that brings advanced capabilities to A/M S designs. Tanner EDA solutions

deliver the right mixture of features, functionality and usability.

Tanner EDA provides powerful and most flexible tools for design, layout and verification

of analog, mixed-signal, RF and MEMS ICs. The fully integrated front end and back end

tools consist of schematic capture, circuit simulation, and waveform probing to physical

layout and verification. Its advanced features improve designer productivity, including

foundry-compatible physical verification, Verilog-A simulation, interactive auto-routing,

and device layout automation.

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A complete flow for IC design is formed by Tanner tools including schematic capture,

analog simulation, physical layout and verification. Following are important tools:

Schematic capture with S-Edit.

Circuit simulator T-Spice.

Waveform viewer W-Edit.

Physical layout with L-Edit.

Schematic driven layout with SDL.

Creating device layout with T-Cell Builder.

Physical Verification with HiPer.

Parasitic Extraction with HiPer PX.

Out of these toolset available, S-Edit is used for drawing schematic of a circuit. T-Spice

writes a program for simulation and W-edit is a waveform editor, L-Edit is used for layout

of the circuit whereas LVS is used for drawing layout from schematic.

6.4 Tanner Tools Vs Other Tools

Most of the IC designers deal with heterogeneous flow, comparing among tools for

compelling business reasons:

• Cost – Even if most of the designs require only a fraction of the functionality and

expense of a Mentor Graphics tool suites, some companies procure full Mentor Graphics

tool sets for occasional, large, or complex designs.

• Foundry – For full-chip layout, many foundries consider Calibre® as the gold

standard for physical verification, so designers obtain Calibre licenses and use Tanner

Tools for layout and schematic entry.

• Learning curve – Designers in small scale industries need easy-to-use, affordable,

PC-based tools which can be trained on very quickly for most of their work, while still

needing Mentor Graphics tools for complex applications and foundry standards. However,

the back-and-forth movement of files in a heterogeneous flow is inefficient and potentially

risky. As designers work around binary incompatibilities and move text files from one

system to another, this flow introduces errors and several problems.

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• Loss of data – A wrong move during the export/import step could result in the use

of the wrong file, or at worst in loss or corruption of data. Interoperability among EDA

tools removes the manual step and minimizes this risk.

• Loss of time – A layout designer may run DRC file between 200 and 1,000 times

during a project, and a heterogeneous flow can increase DRC- or LVS-time by up to two

minutes per run. Interoperability among tools can greatly shorten a design project.

• Loss of efficiency – As heterogeneous flow can be cumbersome and time

consuming, layout engineers may hold off on running DRC/LVS, thereby leaving

problems undetected until late in the project, when it generally takes longer to address

them. Interoperability improves designers‘ productivity and encourages ongoing DRC

throughout the project instead of leaving it until the end.

Hence, considering cost and license renewal issues, Tanner EDA is preferred and it is also

interoperable among all other EDA tools.

6.5 Cadence EDA Tool

The automation of non-critical aspects of custom IC design allows us to focus on

precision-crafting their designs. Cadence EDA [58] solutions facilitate fast and accurate

entry of design concepts, which includes managing design objective in a way that flows

naturally in the schematic. This EDA tool is advanced and parasitic-aware. Thus, we can

abstract and visualize the many interdependencies of an analog, RF, or mixed-signal

design to understand and determine their effects on circuit performance.

1. Cadence® Virtuoso® Schematic Editor provides numerous capabilities to facilitate fast

and easy design entry, including design assistants that speed common tasks by as much

as 5x. Well enriched component libraries allow faster design at both the gate and

transistor levels. Sophisticated wire routing capabilities further support in connecting

devices. For larger and more complex designs, Virtuoso Schematic Editor not only

supports multi-sheet designs but also provides the ability to design hierarchically, with

no limit on the number of levels used. The Hierarchy Editor makes hierarchical designs

easy to traverse, and automatically ensures all connections are maintained accurately

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throughout the design. The symbolic representation can be accomplished for

complicated circuits with pin outs.

Features/Benefits

Speeds common design entry tasks by 5x (GXL).

Enables adding design constraints to the schematic to maintain consistency and

preserve the designer‘s objective on critical pieces of the design.

Simplifies the development of multiple tests over multiple conditions to validate a

design‘s performance against the target specifications.

Allows advanced user to quickly execute commands using user-programmable bind

keys and object-sensitive pop-up menus, which display relevant operations.

2. Cadence® Virtuoso® Analog Design Environment is the advanced design and

simulation environment for the Virtuoso platform. It is designed to help users to create

manufacturing-robust designs. It also gives designers access to a new parasitic

estimation and comparison flow and optimization algorithms that help to center designs

better for yield improvement and advanced matching and sensitivity analyses. Virtuoso

Analog Design Environment sets the standard in fast and accurate design verification,

by supporting extensive exploration of multiple designs against their objective

specifications.

Features/Benefits

Reduced learning curve with a simulator-independent environment.

Maximum efficiency in the script-driven mode.

Accelerated debug process using a variety of built-in analog analysis tools.

Facilitated design correction via easy comparison of pre- and post-parasitic

extracted designs.

Quick detection of circuit problems via a clear visualization cockpit.

3. Cadence® Virtuoso® Visualization and Analysis is a waveform display and analysis

tool that efficiently and thoroughly analyses the performance of analog, RF, and

mixed-signal designs. Integrated with the industry-leading Virtuoso custom design

platform, it provides a comprehensive set of capabilities to display, measure, analyze,

and debug simulation results, and to create documentation for design reviews.

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Developed using the latest software technologies, Virtuoso Visualization and Analysis

is optimized for fast loading of large datasets. The parametric analysis can be done by

varying one of the parameters within full range with suitable steps.

Features/Benefits

High-performance waveform database optimized for fast loading of large amounts

of simulation data.

Extensive mixed-signal display capabilities for efficient data visualization.

Single waveform tool for all Virtuoso simulators.

Seamless integration with the industry-leading Virtuoso custom design platform.

Refresh plotting (customized waveform display set-up and refresh with new data

set after each simulation).

SKILL and OCEAN programming for complex user-developed post-processing

scripts.

Customizable calculator with a rich set of functions and features.

6.6 Design of CMOS IA

The proposed IA as shown in Fig.6.1 consists of five stages. The IA circuit is to operate

with 3 V supply and the power consumption 810 µW. Desired bandwidth is about 4 MHz

with CMRR maintained at 80-90 dB. Using CMOS analog circuit design techniques the

various stages are designed to meet the specifications and are simulated using EDA tools

Tanner V14.1 and Cadence.

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Figure 6.1 Schematic of proposed IA

6.6.1 Input OTA Stage

The input stage of proposed CMOS IA is OTA which dictates noise performance. As the

bandwidth of the IA extends to 4 MHz, thermal noise dominates over flicker noise. Hence,

input-referred noise of the IA can be calculated as,

where k is the Boltzmann‘s constant, T is the absolute temperature, and Δf is the

bandwidth in Hz over which the noise is evaluated. Resistor R1 is selected of small value

(around 400Ω) to minimize the thermal noise contribution.

The input pair of MOSFETs is chosen PMOS to eliminate the body effect in the input pair.

The input stage MOSFETs are biased with a quiescent drain current of 38 µA to keep input

referred noise less than 40 µV rms. The maximum differential input voltage range should

be limited to the value of the product 2IsR1 (≈30mV here) where Is is the quiescent drain

current of the input stage MOSFETs. If input signal is increased beyond this limit, the

harmonic distortion in output increases. Let us start design with allotment of overdrives,

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The MOSFETs Mi1,2 and Md1,2 carry constant current 38 µA all the time whereas either of

Ms1,2 may carry current up to 76 µA. As the drain terminals of Mi1,2 are going to drive the

NMOS devices of fully differential amplifier, the quiescent voltage at these terminals need

to be at least 0.7 V. Thus allotting overdrive 0.73 V to Md1,2, and 0.14 V to Mi1,2. The Ms1,2

may carry maximum current, hence allotting them overdrive of 0.25 V, leaving behind

1.87 V for swings of voltages at source and drain Mi1,2.

Assuming for standard MOS devices the parameters µnCox=2µpCox=60 µA/V2, the device

dimensions can be evaluated using (4.6) as,

(W/L)i1,2 = 112, (W/L)d1,2 = 2.38, (W/L)s1,2 = 83.2

Initially starting with L=0.5µm at which λn=0.2V-1

and and λp=0.1V-1

. Let us find the

theoretical voltage gain of circuit Av, given by,

Where gm and ro can be found out using (4.15) and (4.17) as,

gmi2=543.7 roi2=263kΩ and rod2=131.58kΩ

Thus Av becomes,

Av=-47.683

This gain is not sufficient, hence can be increased by scaling (W/L) of MOSFETs keeping

their ratio constant that means without changing gm and ID increasing ro. The dimensions of

MOSFETs are modified as,

(W/L)i1,2 = (330/3), (W/L)d1,2 = (12/5), (W/L)s1,2 = (200/2.5) all dimensions in µm/µm

accordingly λ of MOSFETs get modified as λ is inversely proportional to L.

103

Figure 6.2 OTA stage simulated

Then the values of gm and ro become,

gmi2=543.7 roi2=1578kΩ and rod2=789kΩ

Modified voltage gain becomes,

Av=-285.8

The circuit is simulated with EDA tool Tanner V14.1 as shown in Fig.6.2. The voltage

gain of circuit comes out to be 272.

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Figure 6.3 Frequency and phase response of the OTA stage.

The frequency response in Fig.6.3 shows that the bandwidth of the OTA stage measures

153.26 kHz which will be increased when this circuit is used in a feedback arrangement

with fully differential amplifier.

6.6.2 Fully (Balanced) Differential Amplifier

As the first stage OTA is designed to provide high gain, the fully differential amplifier can

be designed to provide low gain. The outputs of this stage provide the gate drive to the two

MOSFETs which act as current sources making equal and opposite excursions [62]. These

equal and opposite excursions in current sources make amount of current to flow through

R1 such that drop across R1 equals input differential voltage. Starting from small signal

voltage applied at the inputs of the OTA, then passed through this differential amplifier

and applied to the MOSFETs, the output current of which when passed through R1 make

differential input voltage to drop across R1. Thus total loop gain must be equal to one given

as,

Av of OTA x Av of Differential amplifier x gm MOFET acting as current source x R1 = 1

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Calculated gm of Ms1,2 comes out to be 0.939 µS and the gain of OTA is set to 272, which

gives that the gain of fully differential amplifier should be 2.236.

As the gain to be provided by fully differential amplifier is low, the configuration of

differential amplifier shown in Fig. 5.4 (a) which is with diode-connected load can be used.

The gain of this circuit given by (5.13) can be set to 2.236 as,

Thus, (W/L)3 = 2.5 (W/L)5

Selecting (W/L)3=300/3 µm/µm, we get (W/L)5= 100/2.5 µm/µm. The tail current source

is to provide a bias current of 38 µA which can be set by single NMOS device with

appropriate gate bias. The circuit is simulated along with OTA with EDA Tanner as shown

in Fig. 6.4.

Figure 6.4 The Fully Differential Amplifier simulated along with OTA

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Figure 6.5 Frequency and phase response of differential amplifier simulated with the OTA

The frequency response in Fig 6.5 shows that the bandwidth provided by input stage gets

increased to 9.2 MHz. The outputs of the fully differential amplifier will be identical but

out of phase with each other. Thus one signal will be forcing to increase the current of Ms1

while other forcing to reduce the current of Ms2 by same amount maintaining current

through Mi1 and Mi2 same. The difference in the currents of Ms1 and Ms2 flows through R1,

forcing input voltage to fall across it.

6.6.3 Output OTA Stage

This output OTA stage is just similar to the input OTA stage. In fact the output stage

consists of a CMOS OTA and cascode single ended differential amplifier [64] [65]. The

outputs of the fully differential amplifier drive the two MOSFETs M13 and M16 in a way

just similar as that of Ms1 and Ms2 of the input OTA forcing same amount of current

through R2 as that of R1. The small signal voltage drop R2 is nothing but the output voltage

through the action of buffer same as that of input stage. As the drop across R2 is output

voltage and identical current flows through R1 and R2, the overall gain of the IA becomes

R2/R1.

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This stage also is biased at same quiescent current of 38 µA for each branch of the OTA.

The dimensions of the MOSFETs M13 and M16 are selected same as that of Ms1 and Ms2,

that is (W/L)13,16=200/2.5 µm/µm. The drop across R2 now will be larger, hence overdrive

allotted to Mo1 and Mo2 will be lower. Due to this dimensions of Mo1 and Mo2 will be

selected (W/L)o1,o2=100/1 µm/µm keeping ratio of W and L same but multiplication low as

compared to Mi1 and Mi2. Being followed by cascode op amp with very high gain, the gain

of this stage is set to very low value (1-2). Thus, the load for this can be diode connected

(M7 and M10) which form the current mirrors with the two MOSFETs, M8 and M11 of

cascode op amp. The voltage gain of this stage is set keeping (W/L) of M10 (40/1)µm/µm

and using (4.31) as,

Figure 6.6 Schematic of the output OTA stage

The schematic of the output OTA simulated with EDA tool Tanner V14.1 is shown in Fig.

6.6 with its frequency and phase response shown in Fig. 6.7. The frequency and phase

response start to decline from frequency 20 MHz onwards.

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Figure 6.7 Frequency and phase response of the output OTA stage

6.6.4 Cascode Op Amp Stage

The design procedure of the cascode op amp will be same as that of design example of

section 5.2.1. The technique for improving output voltage swing is used as discussed in

chapter 5 through Fig. 5.11. The quiescent current allotted to each branch is 38 µA. The

maximum swing in output voltage is 2.4 V, leaving behind 0.6 V for overdrives of

MOSFETs. The desired DC gain is about 10000. The overdrives are allotted as,

Vod8 = Vod11= 0.18V, Vod9 = Vod10 = 0.075V, Vod15 = Vod18 = 0.105V, Vod14 = Vod17 = 0.18V

The dimensions of MOSFETs can be calculated using equation of the drain current in

terms of the overdrive and aspect ratio (W/L).

(W/L)8,11 = 40, (W/L)9,12 = (W/L)15,18 = 220, and (W/L)14,17 = 80

Selecting the aspect ratios as,

(W/L)8,11=(40/1)µm/µm, (W/L)9,12=(W/L)15,18=(80/0.35) µm/µm and (W/L)14,17=(80/1)

µm/µm

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Figure 6.8 Schematic of single ended cascode op amp

The dimensions are selected keeping in view that M9 and M12 act as a common gate

amplifier and thus making a channel short to increase the bandwidth. Also one of the pairs

of constant current sources M15 and M18 is made short for same purpose.

With current and overdrive fixed, the transconductances can be found using (4.15) as,

gm8,11= gm14,17=4.2 x 10-4

A/V, gm15,18= 7.23 x 10-4

A/V, gm9,12= 10.13 x 10-4

A/V

The theoretical voltage gain can be calculated as.

A ≃ gm11 [(gm12 ro12ro11)( gm18 ro18ro17) ≈1000

Where ro of MOSFETs are calculated using (4.17).

The schematic of this single ended cascode op amp is simulated with EDA Tanner as

shown in Fig. 6.8 and simulation of its frequency and phase response is shown in Fig. 6.9

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Figure 6.9 Frequency and phase response of single ended cascode op amp

The voltage gain of cascode op amp comes out to be 975 whereas the bandwidth is 600

kHz. The bandwidth will get increased when this stage is connected in feedback with the

output OTA. This stage mainly decides bandwidth of the IA.

6.6.5 Source Follower Stage

The source follower is desired to have voltage gain close to unity, output resistance 50Ω

and maximum input voltage swing of 2.4 Vp-p. The design procedure is same as design

example 2 of chapter 5. As the desired output resistance is low, it can be achieved by

making gm large which in turn can be ended by increasing drain current Id. Thus, making

Id=3mA and as required maximum input/output voltage swing is 2.4V, taking VDD=5V.

As desired voltage gain is close to unity, PMOS source follower should be preferred and

let voltage gain be 0.99. Assuming ro of both the MOSFETs large enough, we can write,

and

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Where gm1 is a transconductance of main MOSFET and gmb1 its transconductance due to

body effect. Thus,

gm1= 0.99/50 = 0.0198 A/V

Also,

gm1=2ID/Vod1

Thus, Vod1=0.303V

Using equation of ID, aspect ratio (W/L) can be found as,

(W/L)1=2178 ≈ 2000

Figure 6.10 Schematic of PMOS source follower

Both the MOSFETs handle same current and hence we can write,

and using equation of ID we can find,

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(W/L)2= 200

One of the assumption was ro of both MOSFETs are too large and we desire a bandwidth

in excess of 10 MHz. Hence selecting L 3µm, we get,

(W/L)1= (6000/3) µm/µm and (W/L)1= (600/3) µm/µm

The circuit of PMOS source follower is simulated with EDA tool Tanner as shown in Fig.

6.10. The frequency and phase response of the circuit show voltage gain of 1 and

bandwidth of 100 MHz as seen in Fig. 6.11. The measured output resistance is 33.33Ω.

Figure 6.11 Frequency and phase response of PMOS source follower

6.6.6 Complete IA

The schematic of complete IA is formed by interconnecting the various circuit blocks

which are designed and simulated in this section. The differential gain of the IA is set to

50V/V by setting R1= 400Ω and R2= 20kΩ. The body (bulk) terminal of each NMOSFET

is connected to lowest potential in the circuit (0V) while that of each PMOSFET is

connected to its source terminal due to n-well technology used to fabricate PMOSFETs.

This minimizes the body effect in the devices. The source follower is not shown in the

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Figure 6.12 Schematic of IA simulated with EDA tool Cadence

Figure 6.13 Common mode response of IA simulated with EDA tool Cadence

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schematic which after connection does not affect the frequency response or CMRR of the

IA. The MOSFETs M9, M12 are biased by external DC source Vbias1 of 1.2V and M15, M18

by Vbias2 of 1.8V. The reference dc level of the output voltage Vo is set by the external

voltage source Vref of 1V. The circuit is operated with power supply of 3V and total current

consumption without source follower is 266 µA, thus power consumption comes out to be

798 µW. The circuit schematic is simulated with EDA tool Cadence and its common mode

response is measured as shown in Fig.6.12 and 6.13 respectively.

Figure 6.14 Schematic of IA simulated on EDA tool Tanner

The same circuit is simulated with EDA tool Tanner as shown in Fig. 6.15. Same results

are obtained as that of Cadence tool. The frequency and phase response of the IA shown in

Fig. 6.16 demonstrates that the phase margin and gain margin are 6 MHz and 10 MHz

respectively. Thus, even if the bandwidth of the IA is around 4.5 MHz, it won‘t be utilized

as phase margin is lower than gain margin and the circuit may become unstable when used

with feedback. This difficulty can be overcome by creating a dominant pole to set the -3dB

bandwidth of lower value by placing a capacitor C2 in parallel with R2 [66]. Hence to set

bandwidth of 2 MHz the capacitor C2 will be needed as given by,

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Figure 6.15 Frequency and phase response of the IA

Figure 6.16 Frequency and phase response of the IA with capacitor C2 added for frequency

compensation

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Thus we get C2 as 4 pF. Placing C2 across R2 the frequency and phase response are verified

through simulation as shown in Fig. 6.15. It is seen that with bandwidth reduced to 2 MHz

the gain margin also gets reduced to 4 MHz making the IA a stable circuit.

Improved Circuit: -

In order to improve the noise interference immunity and bandwidth of the IA two

improvements are done. First improvement is to suppress the low frequency noise and

second to improve higher cut-off frequency as described below:

1. The first order high-pass filter is included in the output stage to filter out the low

frequency signals coupled with human body such as mains signals [63]. This filter is

included in a feedback path formed between the output terminal and one of the input

terminals of the output OTA in place of Vref applied. The high-pass filter is

implemented by a simple operational transconductance amplifier with

transconductance Gm and a capacitor C as shown in the block diagram of proposed IA,

Fig. 3.6. The cut off frequency of this high-pass filter is given by,

The value of capacitor and OTA is selected to provide the fL of 100Hz.

2. The bandwidth of IA is restricted by the frequency response of telescopic cascode op-

amp. This stage is designed to give maximum differential gain with the help of cascode

combination. The bandwidth of this stage can be increased by operating some of the

devices in triode region instead of saturation [36]. The junction capacitances of

MOSFET can be given as

(for triode region)

(for saturation region)

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This shows that higher bandwidth would be achieved if MOSFETs are operated in

triode region, but at the cost of reduced small signal gain. The MOSFETs M9, M12, M15

and M18 in the cascode op-amp are operated in triode region by applying zero volts to

their gate terminals. M9 and M12 form a common gate configuration whereas M15 and

M18 form load for cascode combination. Due to this the small signal gain gets reduced.

The IA is designed for a differential gain of 2.5. The R1 and R2 are set to 400 Ω and 1kΩ to

get a differential gain of 2.5. The circuit used for simulation is shown in Fig. 6.16 and the

frequency and phase response is shown in Fig. 6.17. The frequency response shows that

the bandwidth of IA is extended to 4 MHz. The other parameters measured are the power

dissipation 810 µW, the CMRR of 85 dB, area of chip 0.038 mm2, the input referred noise

36 µVrms.

The performance of this work is compared with results benchmark reported in paper [31]

as shown in table 6.1. The bandwidth is increased, the power dissipation is reduced, the

CMRR is slightly reduced, the input referred noise is increased and the area of chip is

reduced.

The layout is prepared with EDA tool Cadence which gives the dimension of chip as 144

µm X 116 µm.

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Figure 6.17 Schematic of improved IA circuit

Figure 6.18 Frequency and phase response of improved IA circuit

119

Table 6.1 Performance Summary

Parameters [31] Our work

Technology 0.35µm CMOS 0.25 µm CMOS

Active area 0.068mm2 0.038mm

2

Power supply 3V 3V

Power consumption 870µW 810µW

Gain 50 2.5

CMRR (dB) 90 85

Bandwidth (-3dB) 2M 4M

Total input referred

noise 16µV

rms 36 µV

rms

6.6.7 Layout of IA

In the CMOS current feedback instrumentation amplifier design, careful layout is essential

to ensure the good performance of the circuit as well as maximize the yield of the design.

The matching properties of critical devices in the circuit always depend extensively on the

layout approaches used due to many practical issues in fabrication environment, like

process variation, parasitic effects etc. If the layout is not considered critically from the

perspectives of devices placement, the circuit performance will get affected badly [61].

In this circuit design, pair matching layout is used associated with the input and output

OTAs to enhance matching characteristics of the differential input pairs. The power supply

is one of the sources of noise coming into the analog section. In the layout, the width of

each power line is determined by the maximum current and voltage drop allowable in the

design to prevent electro migration.

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Figure 6.19 Layout of final improved IA prepared with Cadence.

To conclude, the circuits discussed till now are designed and simulated using an EDA Tool

Tanner to meet the desired specifications of the IA. The circuits are designed for most

favorable and efficient performances. The final circuit of IA is also simulated with another

industry standard EDA Tool Cadence which gives same results. Cadence offers quite a

lower technology channel length L, but this circuit being analog one and intended for

higher gain cannot utilize the lower technology. Two new concepts suggested theoretically

by reference books are explored here to improve performance of the IA. First concept is to

operate two of the MOSFETs in telescopic cascode op amp at the edge of the triode region

to improve output voltage swing and ICMR. The other concept is to operate the CG stage

and one of the MOSFETs in the cascode current source load of telescopic cascode op amp

in triode region so that these will offer low junction capacitances thereby improving

bandwidth.

*****