Chapter 6 Speed Independent Control Circuits

8/3/2019 Chapter 6 Speed Independent Control Circuits

1/90

Chapter 6 Speed-Independent

Control CircuitsIntroduction

Signal transition graphs

The basic synthesis procedure

Implementations using state-holding gates

Initialization

Summary of the synthesis process

Petrify: A tool for synthesizing SI circuits from STGs

Design examples using Petrify


2/90

Control Circuits

Many methods, tools, assumptions, frameworks

Balsa generated both control and data-path

We now consider one method / tool for control-only

spec, verification and synthesis: Assumption: Speed independent control for speed

independent bundled data

Method: Signal Transition Graph

A special type of Petri net Tool: Petrify (mostly from Jordi Cortadella at UPC)

Universitat Politecnica de Catalunya (Technical Universityof Catalonia, Barcelona, Spain)


3/90

Delay Models

Fixed delay: d=c

Min-max delay: choose d[m,M] Max delay: d[0,M]

Low-bounded delay: d[m,)

Unbounded delay: d[0,)

Pure delay (in VHDL = transport delay)

Simply shifts any signals waveform later in time Inertial delay: Glitches are filtered.

Pulses shorter than the reject time are filtered out

We dont assume inertial delays in async control design


4/90

Hazards

Static-1 hazard

Desired signal: 1_1, actual signal: 1_101_1

Static-0 hazard

Desired signal: 0_0, actual signal: 0_010_0

Dynamic-10 hazard

Desired signal: 1_1 0_0, actual signal: 1_1010_0

Dynamic-01 hazard

Desired signal: 0_0 1_1, actual signal: 0_0101_1


5/90

Minimalist

A comprehensive CAD package for the automatedsynthesis and optimization of asynchronouscontrollers

Principal Architects: Robert Fuhrer

Steven Nowick in Columbia Univ

Book: Sequential Optimization of Asynchronous andSynchronous Finite-State Machines: Algorithms and

Tools. Kluwer Academic Publishers, 2001.(TK7868 .A79 F84)

http://www1.cs.columbia.edu/~nowick/
http://www.wkap.nl/prod/b/0-7923-7425-8http://www.wkap.nl/prod/b/0-7923-7425-8http://www.wkap.nl/prod/b/0-7923-7425-8http://www.wkap.nl/prod/b/0-7923-7425-8http://www.wkap.nl/prod/b/0-7923-7425-8http://www.wkap.nl/prod/b/0-7923-7425-8http://www.wkap.nl/prod/b/0-7923-7425-8http://www.wkap.nl/prod/b/0-7923-7425-8http://www.wkap.nl/prod/b/0-7923-7425-8


6/90

Minimalist -- book chapters Introduction (Async)

Background (FSM) Burst-mode synthesis path walk-through

CHASM: Optimal state assignment

OPTIMIST: Optimal state minimization for

synchronous FSMs OPTIMISTO: Synchronous state minimization for

optimum output logic

OPTIMISTA: Asynchronous state minimization for

optimum output logic MINIMALIST: An extensible toolkit for burst-mode

synthesis

Conclusions


7/90

Petri net, Signal Transition Graph (STG)

Jordi Cortadella, Luciano Lavagno, and AlexYakovlev, Advanced tutorial HardwareDesign and Petri Nets, 21st Intl. Conf. onApplication and theory of Petri Nets, 2000

Jordi Cortadella, M. Kishinevsky, A.Kondratyev, Luciano Lavagno, and AlexYakovlev, Logic Synthesis for Asynchronous

Controllers and Interface, Springer, 2002(TK7868 .L6 L5864)


8/90

Advanced tutorial Hardware Design and

Petri Nets

Introduction to hardware design and petri nets (0.5hrs)

Hardware modeling with petri nets (0.5 hrs)

Direct synthesis of petri nets (0.5 hrs) Logic synthesis of async circuits from STGs (1.5 hrs)

Analysis and verification (1 hr)

Petri nets and hardware description languages (1.5

hrs) Performance analysis (0.5 hrs)

Petri net models for quasi-static-scheduling (1 hr)


9/90

Logic Synthesis for Asynchronous

Controllers and Interface Introduction

Design flow

Background

Logic synthesis State encoding

Logic decomposition

Synthesis with relative timing

Design examples Other work

Conclusions


10/90

The classic design process involves the

following steps

The intended sequential circuit is specified inthe form of a primitive flow table

A minimum-row reduced flow table is

obtained by merging compatible states in theprimitive flow table

The states are encoded

Boolean equations for output variables andstate variables are derived


11/90

The synthesis process involves the following

steps

Specify the desired behavior of the circuit andits (dummy) environment using STG

Check that the STG satisfies 5 properties

Check that the specification satisfiescomplete state encoding

Select an implementation template and

derive the Boolean equations


12/90

The synthesis process involves the following

steps

Derive the Boolean equations for the desiredimplementation template

Manually modify the implementation such

that the circuit can be forced into the desiredinitial state by an explicit reset or initializationsignal

Enter the design into a CAD tool and performsimulation and layout of the circuit


13/90

Petri net, Signal Transition Graph (STG)

a+ b+

c+

a- b-

c-

a+ b+

c+

a- b-

c-


14/90

Separating Inputs, Outputs and Internals

a+ b+

c+

a- b-

c-

a+ b+

c+

a- b-

c-


15/90

In the STG:

PN transition are signal transitions

PN places and arcs are causal relations

Simple places (one arc in, one arc out) areomitted

MARKING

assignment of tokens to places

state of the circuit


16/90

State Graph (SG)

abc000

State:100 010

110

011 101

111

001

SG more complex than STG

Bad for design spec

Needed for synthesis

a+ b+

b+ a+

c+

a- b-

b- a-

c-


17/90

State Graph (SG)

000

100 010

110

011 101

111

001

a+ b+

b+ a+

c+

a- b-

b- a-

c-

Quiescent Region QR(c=0)


Excitation Region ER(c=R)

Excitation Region ER(c=F)


18/90

State Graph (SG)



Excitation Region ER(c=R)

Excitation Region ER(c=F)

000

100 010

110

011 101

111

001

a+ b+

b+ a+

c+

a- b-

b- a-

c-

SET C

RESET C

KEEP C=1

KEEP C=0


19/90

Synthesis: C Element

Two methods:

Using gates

Using SR latch


20/90

Synthesis: C Element using gates

000

100 010

110

011 101

111

001

a+ b+

b+ a+

c+

a- b-

b- a-

c-

SET C

KEEP C=1

0 0 R 0

F 1 1 1

0

1

00 01 11 10c\ab

c=ab+ac+bc

a

bc

!

Hazardous

Material !


21/90

Hazardous Hazards

SLOW

a

bc

ac

ab

bc

a

b

c

ac

ab

bc (slow)


22/90

Hazardous Hazards

Hazards are no big deal in sync circuits

Hazards are deadly in (some) async circuits

Now you know why you were taught aboutthem in school

We can build hazard-free circuits

We can (sometimes) make timing

assumptions and add delays


23/90

Hiding Hazards Behind Delays

SLOW

a

bd

ac

ab

bc

c

a

b

c

ac

abbc (slow rise)

d

Do you like slowing your circuit ?


24/90

Avoiding Hazards with Complex Gates

ab c

c

a

b

a b

a

b

a b

c

cT1

Theoretically, samehazard problem

(e.g. T1 slow)

Must use cautionor delay output


25/90

RESET C

KEEP C=0

Synthesis: C Element using SR Latch

000

100 010

110

011 101

111

001

a+ b+

b+ a+

c+

a- b-

b- a-

c-

SET C

KEEP C=1

0 0 R 0

F 1 1 1

0

1

00 01 11 10c\ab

set=ab reset=ab

ab c

S

R

Q


26/90

Synthesis using SR latches

Needs SET, RESET regions

May use KEEP 0, KEEP 1 regions

May use unreachable states (more later)

Area / performance / power may be more orless than gate circuits

May use C elements instead of SR latches

SR latches enable implementation withstandard libraries


27/90

Implementation using Latches or C

elements

S

R

QSETLOGIC

RESETLOGIC

CSETLOGIC

RESETLOGIC


28/90

Generalized C Element

ab C

+

-cz

set(z) = ab

reset(z) = b'c'

z

reset

setb

a

c

b

z

a

b

c

z

reset

setb

a

c

b

a

b

cset

reset

DYNAMIC (Pseudostatic) STATIC

z

b c

b a


29/90

More interesting PNs and STGs

FORKs

JOINs

(input) CHOICE

MERGE

CONTROLLEDCHOICE

MUTUALLYEXCLUSIVE

MUTUALLYEXCLUSIVE

x+

x+

x+

x+


30/90

STG with Input Choice

x+y+

z+ b+

y- x-

z- b-


31/90

A Simple Choice Net

a

b

c

d

a

bc

d

d+

a-

a+b+ c-

c+ b- b+

c+

d-

RR00b+

01R0c+

0F10

a+

b+

1R00

110R

c-

0F10b-

d+

11R1

a-

F110

111Fd- c+

I II


32/90

Unreachable States

RR00b+

01R0c+

0F10

a+

b+

1R00

110R

c-

00F0b-

d+

11R1

a-

F110

111Fd- c+

00

01

00 01 11 10cd\ab

x x x

x x x

x

11

10


33/90

Regions and Maps

RR00b+

01R0c+

0F10

a+

b+

1R00

110R

c-

00F0b-

d+

11R1

a-

F110

111Fd- c+

For c

00

01

00 01 11 10cd\ab

0 R 0 0

x x R x

x x 1 x

F 1 1 x

11

10

c=d+ab+bcset(c)=d+ab

reset(c)=b


34/90

c=d+ab+bc

set(c)=d+ab

reset(c)=b

ab

cd

C cab

d


35/90

Regions and Maps

RR00b+

01R0c+

0F10

a+

b+

1R00

110R

c-

00F0b-

d+

11R1

a-

F110

111Fd- c+

For d

00

01

00 01 11 10cd\ab

0 0 R 0

x x 1 x

x x F x

0 0 0 x

11

10

d=abcset(d)=abc

reset(d)=c


36/90

Walks on SG and KM

RR00b+

01R0c+

0F10

a+

b+

1R00

110R

c-

00F0b-

d+

11R1

a-

F110

111Fd- c+

00

01

00 01 11 10cd\ab

x x x

x x x

x

11

10

I

II

I

Exercise: A decomposed gate implementationis not speed-independent due to hazards. Explain, using the walks.

II


37/90

STG Rules

Any STG: Input free-choiceOnly mutex inputs may control the

choice)

1-BoundedMaximum 1 token per place

LivenessNo deadlocks

STG for Speed Independent circuits: Consistent state assignmentSignals strictly alternate

between + and

PersistencyExcited signals fire, namely they cannotbe disabled by another transition

Synthesizable STG: Complete state codingDifferent markings must

represent different states


38/90

We use the following circuit to explain STGrules:

req

ack

REQ

ACK


39/90

1-Bounded (Safety)

STG is safeif no place or arc can ever contain more than one token

Often caused by one-sided dependency

STG is not safe:If left cycle goes fast and right cycle lags,

then arc ack+REQ+accumulates tokens.(REQ+ depends on both ack+andACK- )

Possible solution: stop left cycle by right cycle

REQ+ ACK+

REQ-ACK-

req+ ack+

req-ack-


40/90

Liveness

STG is liveif from every reachable marking, everytransition can eventually be fired

The STG is not live:

Transitions reset, reset_okcannot be repeated. But non-liveness is useful for initialization

reset_ok-reset- req+ ack+

req-ack-


41/90

Consistent State Assignment

The following subset of STG makes no sense:

a+ a+

a- a-


42/90

Persistency

STG is persistentif for all arcs a* b*, other arcs ensure that b*fires before opposite transition of a* (*is either + or -)

Non-persistency may be caused by one-sided relations

STG is not persistent (in addition to being unsafe):

If left cycle goes fast and right cycle lags,

then ack+ack-beforeREQ+.Danger: Logic design may be REQ+ = ack+Exception: Ifa*b*, assume that the environment assures persistency.Possible solution: stop left cycle by right cycle.

REQ+ ACK+

REQ-ACK-

req+ ack+

req-ack-


43/90

Complete State Coding

STG has a complete state codingif no two differentmarkings have identical values for all signals.

REQ+ ACK+

REQ-ACK-

ack- req+

ack+req-

1000 1010

req,ack,REQ,ACK:

1011

100110001100

0100

0000

00

01

00 01 11 10cd\ab

11

10

Disaster!


44/90

Complete State Coding

Possible solution: Add an internal statevariable

x- x+

req,ack,REQ,ACK,x:

REQ+ ACK+

REQ-ACK-

ack- req+

ack+req-

10000 10100

1000111001


45/90

Petrify : A tool for synthesizing SI circuits

from STGs

Petrify Environment :

STG

EQNdraw_astg

ps

write_sg

SG

libpetrify


46/90

Petrify

Unix (Linux) command line tool

petrify hfor help (flags etc.)

petrify cgfor complex gates

petrifygc

for generalized C-elements

petrify tmfor tech mapping

draw_astgto draw

write_sgto create state graphs

Documented on line, incl. tutorial See http://www.lsi.upc.es/~jordic/petrify/petrify.htm


47/90

A faster STG?

Does it need an extra variable?

ack-

req+

ack+

req-

ACK-

REQ+

ACK+

REQ-


48/90

Drawn bydraw_astg

Note reverse colors

Th SG


49/90

The SGreq,ack,REQ,ACK:

0000

r+

1000

a+ R+1100 1010

r-

0100

R+

1110

a+ A+

1011A+

1111

a+r-

0110

R+a-

a- A+

0111

r-

0011

a-

R-

1001R-

1101

a+

R-

0101

r-

0001

a-R-

A-

1000A-

1100

a+

A-

0100

r-

a-A-1011

r+

1001

r+R-

A-

1111

a+

R-1101

a+

A-0111

r-

R-

0101

r-

A-

a-

a-

Th SG


50/90

The SGreq,ack,REQ,ACK:

0000

r+

1000

a+ R+1100 1010

r-

0100

R+

1110

a+ A+

1011A+

1111

a+r-

0110

R+a-

a- A+

0111

r-

0011

a-

R-

1001R-

1101

a+

R-

0101

r-

0001

a-R-

A-

1000A-

1100

a+

A-

0100

r-

a-A-1011

r+

1001

r+R-

A-

1111

a+

R-1101

a+

A-0111

r-

R-

0101

r-

A-

a-

a-

R+

R+

R+


51/90

Drawn bywrite_sg & draw_astg


52/90

Extra states inserted bypetrify


53/90

Rearranged STG

ack-

req+

ack+

req-

c1-

c1+

c0-

ACK-

REQ+

ACK+

REQ-

c2-

c2+

c0+

Initial Internal State: c0=c1=c2=1


54/90

The new State Graph


55/90

The Synthesized Complex Gates Circuit

INORDER = r A a R csc0 csc1 csc2;

OUTORDER = [a] [R] [csc0] [csc1] [csc2];

[a] = a (csc2 + csc0) + csc1';[R] = csc2 (csc0 (a + r) + R);

[csc0] = csc0 (csc1' + a') + R' csc2;

[csc1] = r' (csc0 + csc1);

[csc2] = A' (csc0' (csc1' + a') + csc2);


56/90

Technology Mapping



[0] = R'; # gate inv: combinational

[1] = [0]' A' + csc2'; # gate oai12: combinational

[a] = a csc0' + [1]; # gate sr_nor: asynch

[3] = csc1'; # gate inv: combinational

[4] = csc0' csc2' [3]'; # gate nor3: combinational

[5] = [4]' (csc1' + R'); # gate aoi12: combinational

[R] = [5]'; # gate inv: combinational

[7] = (csc2' + a') (csc0' + A'); # gate aoi22: combinational

[8] = csc0'; # gate inv: combinational

[csc0] = [8]' csc1' + [7]'; # gate oai12: combinational

[csc1] = A' (csc0 + csc1); # gate rs_nor: asynch

[11] = R'; # gate inv: combinational[12] = csc0' ([11]' + csc1'); # gate aoi12: combinational

[csc2] = [12] (r' + csc2) + r' csc2; # gate c_element1:asynch


57/90

The Synthesized Gen-C Circuit



[0] = csc0' csc1 (R' + A);

[1] = csc0 csc2 (a + r);

[2] = csc2' A;[R] = R [2]' + [1]; # mappable onto gC

[4] = a csc1 csc2';

[csc0] = csc0 [4]' + csc2; # mappable onto gC

[6] = r' csc0;

[csc1] = csc1 r' + [6]; # mappable onto gC

[8] = A' csc0' (csc1' + a');[csc2] = csc2 R' + [8]; # mappable onto gC

[a] = a [0]' + csc1'; # mappable onto gC

A f STG?


58/90

A safer STG?

ack-

req+

ack+

req-

ACK-

REQ+

ACK+

REQ-

A f STG?


59/90

A safer STG?

Th f STG i i l i i


60/90

The safer STG is a serial circuit

INORDER = r A a R;

OUTORDER = [a] [R];

[a] = A;

[R] = r;

ack-

req+

ack+

req-

ACK-

REQ+

ACK+

REQ-

req

ack

REQ

ACK

Y h STG?


61/90

Yet another STG?

ack-

req+

ack+

req-

ACK-

REQ+

ACK+

REQ-

Y h STG?


62/90

Yet another STG?


63/90

O H d h k Fi


64/90

Output Handshake First

ack-

req+

ack+

req-

ACK-

REQ+

ACK+

REQ-

S ill i l ll


65/90

Still a serial controller

S h i


66/90

Synthesis

INORDER = r A a R csc0;

OUTORDER = [a] [R] [csc0];

[a] = csc0 A'; # gate and2_1: combinational

[R] = r csc0'; # gate and2_1: combinational

[2] = A' (csc0' + r'); # gate aoi12: combinational

[csc0] = [2]'; # gate inv: combinational

A

r

c0S

R

Q

Q

Aa

r R

c0

cA

r

c0

Aa

r R

c0

+

-=

A diff STG


67/90

A different STG

ack-

req+

ack+

req-

ACK-

REQ+

ACK+

REQ-

Redundant,will be ignoredby petrify

A diff t STG


68/90

A different STG

S th i


69/90

Synthesis

INORDER = r A a R;OUTORDER = [a] [R];

[a] = R;

[1] = r A';

[2] = r' A;

[R] = R [2]' + [1]; # mappable onto gC

R = R(Ar)+Ar = R(A+r)+Ar = Ar + RA +Rr

A

r Rca

L t h C t l


70/90

Latch Control

req

ack

REQ

ACK

req

ack

REQ

ACK

Enable

Data-less fifo:

Latch:Lt

Enable=0:transparent


71/90

Constraints on sequence of events

Must keep input data available until after it islatched

Assume input data available only when req=1

Once ack+, req- (and input data invalid) canfollow very fast

Lt+ before ack+

L t h C ntr l STG Fr m nts


72/90

Latch Control: STG Fragments

ack-

req+

ack+

req-

ACK-

REQ+

ACK+

REQ-

req+ ACK-

REQ+

Lt+

ack+

req- ACK+

REQ-

Lt-

ack-

Latch Control: Combined STG


73/90


ack-

req+

ack+

req-

ACK-

REQ+

ACK+

REQ-

Lt+

Lt-



74/90



75/90


76/90

INORDER = Rin Aout Ain Rout Lt;

OUTORDER = [Ain] [Rout] [Lt];

[Ain] = Lt;

[1] = Aout' Rin;

[2] = Aout Rin';[Rout] = Rout [2]' + [1]; # mappable onto gC

[Lt] = Rout;

R = R(Ar)+Ar = R(A+r)+Ar = Ar + RA +Rr

A

r Rc

Lt

a

MUX Control


77/90

MUX Control

So far all examples are doable by hand

A deceptively simple example:Control for 4-phase bundled data mux

PUSHchannels

4 phase Bundled data Mux


78/90

4-phase Bundled-data Mux

We have already drawn this (dual-rail control):

y z

x

yz

x

ctl.tctl.f

y-ackz-ack

x-ack

y-req

z-req

x-req

C

C

ctl

0

1

C

Cctl.f

ctl.t

ctl-ack

Easier to start with the dual-rail control

The environment


79/90

The environment

Four independentenvironments (rCf, rCt share aC)

Must not specify any dependency by mistake:

a0-

r0+

a0+

r0-

a1-

r1+

a1+

r1-

aC-

rCf+

aC+

rCf-

A-

R+

A+

R-

In0 In0 Ctl.f Out

aC-

rCt+

aC+

rCt-

Ctl.t

The control


80/90

The control

A+ must precede a0+ or a1+ (make sure datapassed through and were captured)

In0 and In1 handshakes must be made MUTEX

Choices are matches with Merges


81/90

a0+

a1+

r0+

A+

rCf+

rCt+

aC-

r1+

R+

InputFreeChoice

P3 P1 aC+ P2

rCf-

rCt-

P4

r0-

r1-

P5

ControlledChoice

Merge

Duplicate arrow

mux g


82/90

mux.g

mux gc


83/90

mux.gc

Replicated transitions: R+,

R+/1

Inserted state variable toretain In0 vs. In1 info

Compact state graph


84/90

Compact state graph

Mux Control Synthesis


85/90

Mux Control Synthesis

INORDER = r0 r1 rCf rCt A a0 a1 aC R csc0 csc1;OUTORDER = [a0] [a1] [aC] [R] [csc0] [csc1];

[0] = r0 csc0;

[a1] = csc1 r1;

[2] = csc1 (A + csc0);

[3] = rCt' rCf' csc1';

[aC] = aC [3]' + [2]; # mappable onto gC

[R] = a0' csc0' csc1 r0 + csc0 csc1';

[6] = a0' csc1 A r0 + csc1' r1 A';

[7] = aC (r0' + a0);

[csc0] = csc0 [7]' + [6]; # mappable onto gC

[9] = r0 A' + csc0 A;

[10] = r0' csc0' r1';

[csc1] = csc1 [10]' + [9]; # mappable onto gC[a0] = a0 r0 + [0]; # mappable onto gC


86/90

Another Mux (4p ctl, bd) (Fig 6.24)

SG for the Fig 6 24 mux


87/90

SG for the Fig 6.24 mux

All-bundled Mux


88/90

All bundled Mux

All-bundled Mux Synthesis


89/90

All bundled Mux Synthesis

INORDER = In0Req OutAck In1Req Ctl CtlReq In1Ack In0Ack OutReq CtlAckcsc0;

OUTORDER = [In1Ack] [In0Ack] [OutReq] [CtlAck] [csc0];

[In1Ack] = OutAck csc0';

[In0Ack] = OutAck csc0;

[2] = CtlReq (In1Req csc0' + In0Req Ctl');

[3] = CtlReq' (In1Req' csc0' + In0Req' csc0);[OutReq] = OutReq [3]' + [2]; # mappable onto gC

[5] = OutAck' csc0;

[CtlAck] = CtlAck [5]' + OutAck; # mappable onto gC

[7] = OutAck' CtlReq';

[8] = CtlReq Ctl;

[csc0] = csc0 [8]' + [7]; # mappable onto gC

Reduced concurrency mux


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Reduced concurrency mux

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Chapter 6 Speed Independent Control Circuits

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