Chapter 7 Integration Technology using TSV

Chapter 7 Introduction to 3D

Integration Technology using TSV

Jin-Fu LiDepartment of Electrical Engineering

National Central UniversityJungli, Taiwan

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

Why 3D Integration An Exemplary TSV Process Flow Stacking Strategies Concept of 3D IC Design Summary

Outline

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU

IC Technology Evolution

Chip

Single-chip package

Printed wiring board(PCB)

3D-SIP

3D-IC Energy/Power

Processor

Memory Stack

RFADCDAC

NanoDeviceMEMS

Other Sensors,Imagers

Chemical &Bio Sensors


Why 3D Integration Integrating more and more transistors in a

single chip to support more and more powerful functionality is a trend Using 2D integration technology to implement such

complex chips is more and more expensive and difficult

Some alternative technologies attempting to cope with the bottlenecks of 2D integration technology have been proposed

3D integration technology using through silicon via (TSV) has been acknowledged as one of the future chip design technologies


3D Integration Technology Using TSV

3D integration technology using TSV Multiple dies are stacked and TSV is used for the

inter-die interconnection

The fabrication flow of a 3D IC Die/wafer preparation Die/wafer assembly

Die 1Die 2

Die 3

TSV


What is TSV Through Silicon Via (TSV):

A via that goes through the silicon substrate Used for dies stacking

Typical TSV technologies Via-first, via-middle, and via-last technologies

CMOS

Top Bump

Top Bump

SiO2 insulatorVia made by laser

Diameter

Al wiring TSVWiring layer

50 um or less


Via-First TSV

Via-First TSV Technology

Source: Yole, 2007.

(1) Before CMOS

(2) After CMOS & BEOL


Via-Last TSV

Via-Last TSV Technology

Source: Yole, 2007.

(1) After BEOL & before bonding

(2) After bonding

Step 1: A wafer with CMOS circuits


An Exemplary Via-Last Process Flow (1/6)

… …

MOSFET

…

MOSFET

Substrate

Ref ：ITRI

Step 2: via etching



… …

MOSFET

…

MOSFET

Substrate

Via machining(by etching or laser dilling)

Ref ：ITRI

Step 3: via filling



… …

MOSFET

…

MOSFET

Substrate

Via filling

Ref ：ITRI

Step 4: wafer thinning



… … …

Wafer thinning

50 ~ 100 μm

Ref ：ITRI

Step 5: micro bump forming



… … …

Micro Bump

Ref ：ITRI

Step 6: stacking



TSV

Micro (μ) Bump

ABF(Ajinomoto Built-in Film)

… … …

… … …

Ref ：ITRI


An Exemplary 3D IC using Via-Last TSV

N Well N Well N Well

P-Substrate 2nd Chip

TSVN+ N+ N+ N+ N+ N+ N+P+P+P+P+P+

N Well N Well N Well

P-Substrate 1st Chip

TSVN+ N+ N+ N+ N+ N+ N+P+P+P+P+P+

P-Substrate 3rd Chip

BondingAdhesive

BondingAdhesive


3-Tier 3D IC Cross-Section

Source: E. G. Friedman, University of Rochester.


Die/Wafer Assembly Bonding technologies for 3D ICs Wafer-to-wafer (W2W), Die-to-Wafer (D2W), and

Die-to-Die (D2D) Comparison of different bonding technologies

D2D D2W W2WYieldFlexibilityProduction Throughput

HighHighLow

HighGoodGood

LowPoorHigh


Stacking Strategies

Lewis, D.L. et al, “A ScanIsland Based Design Enabling Prebond Testability in DieStacked Microprocessors,” in proc. IEEE International Test Conference (ITC), 2007, pp. 1-8

Metal

Active Si

Bulk Si

D2D Vias

Die2

Die1

μ Bump

TSV

face-to-face back-to-back face-to-back

μ Bump μ Bump


Fabrication Steps for Face-to-Face Stacking

Metal

Active Si

Bulk Si

Die1 Die2 Die1

Metal

Active Si

Bulk Si

Die1 Die2

Metal

Active Si

Bulk Si

Die2

Metal

Active Si

Bulk Si

Die1

Die2

Metal

Active Si

Bulk Si

Die1

Die211 22 33 44 55

Loh, Gabriel H. et al, “Processor Design in 3D Die-Stacking Technologies,” in IEEE Micro, vol.27, issue 3, pp. 31-48, 2007


Fabrication Steps for Face-to-Back Stacking

Metal

Active Si

Bulk Si

Die1 Die2

Metal

Active Si

Bulk Si

Die1 Die2

Metal

Active SiBulk Si

Die1 Die2

Metal

Active Si

Bulk Si

Die1

Die2

Metal

Active Si

Bulk Si

Die1

Die211 22 33 44 55

Handle wafer



Electrical Characteristics of TSV

Capacitance of TSV

CMOS

Top Bump

Diameter

Al wiring TSVWiring layer

TSV Length

Dielectric Thickness

TSV Dia[um]

TSV DielThk [nm]

TSV Length[um]

Cap [fF]

5 50 20 239.5

5 100 20 135.2

10 50 20 496.4

10 100 20 288.3

Source: Proceedings of IEEE, pp. 101, Jan. 2009


RC Characteristics of TSV

… …Die1

Die2

MOSFET

M1

M2

M9

via9

via1

via2RCviastack

~ 0.35*RCviastackD

2D v

ia

1-mm top-level metal

4x minimum size

F2F D2D via

1 FO4 = 22 ps(BSIM 70nm)

225 ps> 11 FO4

8 ps~ 1/3*FO4



Benefits of 3D integration over 2D integration High functionality High performance Small form factor Low energy

Benefits of 3D Integration

Source: Proceedings of IEEE, Jan. 2009


High Functionality

Heterogeneous integration Combine disparate

technologies DRAM, flash, RF, etc.

Combine different technology nodes E.g., 65nm technology and 45nm

technology

Energy/Power

Processor

Memory Stack

RFADCDAC

NanoDeviceMEMS

Other Sensors,Imagers

Chemical &Bio Sensors



High Performance

3D integration technology can reduce the length of the long interconnections using TSV

For example,

3 4

1 2

A

By

y

x x

y 3 4

A

1 2

B

x x

z

L2D=x+2y L3D=x+y+z


High Bandwidth 3D IC allows much more IO resources than 2D

IC For example, Stacking of processor and memory

Memory

CPU

Bandwidth is limited by IOs

CPU

Memory

Many TSVs are allowed for high bandwidth transportation


Low Energy

SIP

3D-IC

SOBEnergy

Technology


3D IC Design Approaches

CPU

L2

L2

L2

MultipleCores

L2

I$

D$tlb

robIdq

IFbpred

rfrs

aludec

stq

VDD

gndX

Y

Transistors (circuit) LevelLogic gates (FUB splitting)

Function Unit Block (FUB)Entire Core


2D RAM

Blo

ck 0

WL

Dec

Mux & SA

Blo

ck 1

WL

Dec

Mux & SA

Blo

ck 2

WL

Dec

Mux & SA

Blo

ck 3

WL

Dec

Mux & SA

Blo

ck 4

WL

Dec

Mux & SA

Blo

ck 4

WL

Dec

Mux & SA

Blo

ck 4

WL

Dec

Mux & SA

Blo

ck 4

WL

Dec

Mux & SA

WL Pre-DecAddress input

Data output

WordlinesBitlines

128

WLs

256 BLsRAM Subarray

Y.-F. Tsai et al, “Design Space Exploration for 3-D Cache,” IEEE Transactions on Very Large Scale Integration (TVLSI), vol.16, issue 4, pp. 444-555, 2008


3D Wordline-Partitioned RAM

128

WLs

Blo

ck 0

-2

WL

Dec

SA 0-2

WL Pre-Dec

Blo

ck 1

-2

WL

Dec

SA 1-2

Blo

ck 2

-2

WL

Dec

SA 2-2

Blo

ck 3

-1

WL

Dec

SA 3-1

Blo

ck 4

-2

WL

Dec

SA 4-2

Blo

ck 5

-2

WL

Dec

SA 5-2

Blo

ck 6

-2

WL

Dec

SA 6-2

Blo

ck 7

-1

WL

Dec

SA 7-1

Blo

ck 0

-2

WL

Dec

SA 0-2

WL Pre-DecAddress inputData output

Blo

ck 1

-2

WL

Dec

SA 1-2

Blo

ck 2

-2

WL

Dec

SA 2-2

Blo

ck 3

-2

WL

Dec

SA 3-2

Blo

ck 4

-2

WL

Dec

SA 4-2

Blo

ck 5

-2

WL

Dec

SA 5-2

Blo

ck 6

-2

WL

Dec

SA 6-2

Blo

ck 7

-2

WL

Dec

SA 7-2

128 BLs



3D Bitline-Partitioned RAM

Block 0-2WL

Dec

Mux & SA

WL Pre-Dec

Block 1-2WL

Dec

Mux & SA

Block 2-2WL

Dec

Mux & SA

Block 3-1WL

Dec

Mux & SA

Block 4-1

WL

Dec

Mux & SA

Block 5-1

WL

Dec

Mux & SA

Block 6-1

WL

Dec

Mux & SA

Block 7-1

WL

Dec

Mux & SA

64 W

Ls

256 BLs

Block 0-2

WL

Dec

Mux & SA

WL Pre-DecAddress inputData output

Block 1-2

WL

Dec

Mux & SA

Block 2-2

WL

Dec

Mux & SA

Block 3-2

WL

Dec

Mux & SA

Block 4-2

WL

Dec

Mux & SA

Block 5-2W

L D

ec

Mux & SA

Block 6-2

WL

Dec

Mux & SA

Block 7-2

WL

Dec

Mux & SA



Design Example: 3D RAM

Source: G. H. Loh, ISCA 2008


Design Example

Source: ASP-DAC 2009.


Road Map of 3D Integration with TSVs



Summary

3D integration technology using TSV is one of future IC design technologies

It can offer many advantages over the 2D integration technology

However, there are some challenges should be overcome before volume-production of TSV-based 3D IC becomes possible

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Chapter 7 Integration Technology using TSV

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