+ All Categories
Home > Documents > Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights...

Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights...

Date post: 05-Aug-2020
Category:
Upload: others
View: 3 times
Download: 0 times
Share this document with a friend
82
Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 7 Microarchitecture
Transcript
Page 1: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

1 Copyright © 2013 Elsevier Inc. All rights reserved.

Chapter 7

Microarchitecture

Page 2: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

2 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.1 State elements of MIPS processor

Page 3: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

3 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.2 Fetch instruction from memory

Page 4: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

4 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.3 Read source operand from register file

Page 5: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

5 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.4 Sign-extend the immediate

Page 6: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

6 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.5 Compute memory address

Page 7: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

7 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.6 Write data back to register file

Page 8: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

8 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.7 Determine address of next instruction for PC

Page 9: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

9 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.8 Write data to memory for sw instruction

Page 10: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

10 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.9 Datapath enhancements for R-type instruction

Page 11: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

11 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.10 Datapath enhancements for beq instruction

Page 12: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

12 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.11 Complete single-cycle MIPS processor

Page 13: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

13 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.12 Control unit internal structure

Page 14: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

14 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.13 Control signals and data flow while executing or instruction

Page 15: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

15 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.14 Single-cycle MIPS datapath enhanced to support the j instruction

Page 16: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

16 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.15 Critical path for lw instruction

Page 17: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

17 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.16 State elements with unified instruction/data memory

Page 18: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

18 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.17 Fetch instruction from memory

Page 19: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

19 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.18 Read source operand from register file

Page 20: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

20 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.19 Sign-extend the immediate

Page 21: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

21 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.20 Add base address to offset

Page 22: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

22 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.21 Load data from memory

Page 23: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

23 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.22 Write data back to register file

Page 24: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

24 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.23 Increment PC by 4

Page 25: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

25 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.24 Enhanced datapath for sw instruction

Page 26: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

26 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.25 Enhanced datapath for R-type instructions

Page 27: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

27 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.26 Enhanced datapath for beq instruction

Page 28: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

28 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.27 Complete multicycle MIPS processor

Page 29: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

29 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.28 Control unit internal structure

Page 30: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

30 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.29 Fetch

Page 31: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

31 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.30 Data flow during the fetch step

Page 32: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

32 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.31 Decode

Page 33: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

33 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.32 Data flow during the decode step

Page 34: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

34 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.33 Memory address computation

Page 35: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

35 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.34 Data flow during memory address computation

Page 36: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

36 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.35 Memory read

Page 37: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

37 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.36 Memory write

Page 38: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

38 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.37 Execute R-type operation

Page 39: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

39 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.38 Branch

Page 40: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

40 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.39 Complete multicycle control FSM

Page 41: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

41 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.40 Main controller states for addi

Page 42: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

42 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.41 Multicycle MIPS datapath enhanced to support the j instruction

Page 43: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

43 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.42 Main controller state for j

Page 44: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

44 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.43 Timing diagrams: (a) single-cycle processor, (b) pipelined processor

Page 45: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

45 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.44 Abstract view of pipeline in operation

Page 46: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

46 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.45 Single-cycle and pipelined datapaths

Page 47: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

47 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.46 Corrected pipelined datapath

Page 48: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

48 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.47 Pipelined processor with control

Page 49: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

49 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.48 Abstract pipeline diagram illustrating hazards

Page 50: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

50 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.49 Abstract pipeline diagram illustrating forwarding

Page 51: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

51 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.50 Pipelined processor with forwarding to solve hazards

Page 52: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

52 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.51 Abstract pipeline diagram illustrating trouble forwarding from lw

Page 53: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

53 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.52 Abstract pipeline diagram illustrating stall to solve hazards

Page 54: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

54 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.53 Pipelined processor with stalls to solve lw data hazard

Page 55: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

55 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.54 Abstract pipeline diagram illustrating flushing when a branch is taken

Page 56: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

56 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.55 Abstract pipeline diagram illustrating earlier branch decision

Page 57: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

57 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.56 Pipelined processor handling branch control hazard

Page 58: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

58 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.57 Pipelined processor handling data dependencies for branch instructions

Page 59: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

59 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.58 Pipelined processor with full hazard handling

Page 60: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

60 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.59 MIPS single-cycle processor interfaced to external memory

Page 61: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

61 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.60 Assembly and machine code for MIPS test program

Page 62: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

62 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.61 Contents of memfile.dat

Page 63: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

63 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.62 Datapath supporting overflow and undefined instruction exceptions

Page 64: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

64 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.63 Datapath supporting mfcO

Page 65: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

65 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.64 Controller supporting exceptions and mfc0

Page 66: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

66 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.65 Cycle time and instruction time versus the number of pipeline stages

Page 67: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

67 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.66 2-bit branch predictor state transition diagram

Page 68: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

68 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.67 Superscalar datapath

Page 69: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

69 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.68 Abstract view of a superscalar pipeline in operation

Page 70: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

70 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.69 Program with data dependencies

Page 71: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

71 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.70 Out-of-order execution of a program with dependencies

Page 72: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

72 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.71 Out-of-order execution of a program using register renaming

Page 73: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

73 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.72 Packed arithmetic: four simultaneous 8-bit additions

Page 74: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

74 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.73 4004 microprocessor chip

Page 75: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

75 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.74 80386 microprocessor chip

Page 76: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

76 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.75 80486 microprocessor chip

Page 77: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

77 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.76 Pentium microprocessor chip

Page 78: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

78 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.77 Pentium III microprocessor chip

Page 79: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

79 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.78 Pentium 4 microprocessor chip

Page 80: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

80 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.79 Core Duo microprocessor chip

Page 81: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

81 Copyright © 2013 Elsevier Inc. All rights reserved.

Figure 7.80 Core i7 microprocessor chip

(Source: http://www.intel.com/pressroom/archive/releases/2008/20081117comp_sm.htm.

Courtesy Intel)

Page 82: Chapter 7 Microarchitecture - Elsevier · 2013-06-18 · Copyright © 2013 Elsevier Inc. All rights reserved. 82 UNN Figure 1. Title: Slide 1 Author: CEPHA Created Date: 8/27/2012

82 Copyright © 2013 Elsevier Inc. All rights reserved.

UNN Figure 1


Recommended