No. 7-1
Chapter #7: Sequential Logic Case Studies
Contemporary Logic Design
No. 7-2
Storage RegisterGroup of storage elements read/written as a unit
4-bit register constructed from 4 D FFsShared clock and clear lines
Q1
CLR
D3D2D1D0
171
Q1
Q0Q0
CLK Q3Q3Q2Q2
11
109
5
67
432
14
13
151
12
No. 7-3
Input/Output Variations
Selective Load CapabilityTri-state or Open Collector OutputsTrue and Complementary Outputs
74377 Octal D-type FFswith input enable
74374 Octal D-type FFswith output enable
EN enabled low andlo-to-hi clock transitionto load new data into
register
OE asserted lowpresents FF state to
output pins; otherwisehigh impedence
D3
D6Q5
Q2
377
Q1Q0
Q3
EN CLK
Q6
Q4
Q7
D5
D2D1D0
D4
D7
1
3478
13141718
11
256912151619
HGFEDCBA
QHQGQFQEQDQCQBQA
OE
37411
1
3478
13141718
256912151619
CLK
No. 7-4
Register FilesTwo dimensional array of flipflopsAddress used as index to a particular wordWord contents read or written
74670 4x4 Register File withTri-state Outputs
Separate Read and Write EnablesSeparate Read and Write AddressData Input, Q Outputs
Contains 16 D-ffs, organized asfour rows (words) of four elements (bits)
670
Q4
D1
D4D3D2
Q3Q2Q1
WE
WAWB
RE
RARB
54
11
1413
12
15123
10976
No. 7-5
Shift RegistersStorage + ability to circulate data among storage elements
Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal
Wrap around from rightmost element to leftmost element Master Slave FFs: sample inputs while
clock is high; change outputs on falling edge
Shift Direction\Reset
\ResetShift
CLK CLK CLK CLK
Q 1 1 0 0 0
Q 2 0 1 0 0
Q 3 0 0 1 0
Q 4 0 0 0 1
Shift
Shift
Shift
No. 7-6
Shift Register I/OSerial vs. Parallel InputsSerial vs. Parallel OutputsShift Direction: Left vs. Right
74194 4-bit UniversalShift Register
Serial Inputs: LSI, RSIParallel Inputs: D, C, B, AParallel Outputs: QD, QC, QB, QAClear SignalPositive Edge Triggered Devices
S1,S0 determine the shift functionS1 = 1, S0 = 1: Load on rising clk edge synchronous loadS1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element DS1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element AS1 = 0, S0 = 0: hold state
Multiplexing logic on input to each FF!
Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications
No. 7-7
Shift Register Application: Parallel to Serial Conversion
QAQBQCQD
S1S0LSIDCBARSICLKCLR
QAQBQCQD
S1S0LSIDCBARSICLKCLR
D7D6D5D4
Sender
D3D2D1D0
QAQBQCQD
S1S0LSIDCBARSICLK
CLR
QAQBQCQD
S1S0LSIDCBARSICLK
CLR
Receiver
D7D6D5D4
D3D2D1D0
Clock
194 194
194194
ParallelInputs
Serialtransmission
ParallelOutputs
No. 7-8
Counters
- Proceed through a well-defined sequence of states in response to count signal
- 3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, …
- 3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, …
- Binary vs. BCD vs. Gray Code Counters
A counter is a "degenerate" finite state machine/sequential circuitwhere the state is the only output
A counter is a "degenerate" finite state machine/sequential circuitwhere the state is the only output
No. 7-9
Johnson (Mobius) Counter
End-Around
8 possible states, single bit change per state, useful for avoiding glitches
J CLK K
S
R
Q
Q
+
+
+ +
0 1
Shift
Q 1 Q 2 Q 3 Q 4
\Reset
J
K
S
R
Q
Q
J
K
S
R
Q
Q
J
K
S
R
Q
Q CLK CLK CLK
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Shift
Q 1
Q 2
Q 3
Q 4
100
No. 7-10
Catalog Counter
74163 Synchronous4-Bit Upcounter
Synchronous Load and Clear Inputs
Positive Edge Triggered FFs
Parallel Load Data from D, C, B, A
P, T Enable Inputs: both must be asserted to enable counting
RCO: asserted when counter enters its highest state 1111, used for cascading counters "Ripple Carry Output"
74161: similar in function, asynchronous load and reset
QAQBQCQD
163RCO
PT
ABCD
LOAD
CLR
CLK2
710
15
9
1
3456
14
1211
13
No. 7-11
74163 Detailed Timing Diagram
CLK
A
B
C
D
LOAD
CLR
P
T
Q A
Q B
Q C
Q D
RCO 12 13 14 15 0 1 2
Clear Load Count Inhibit
No. 7-12
Counter Design Procedure
Introduction
This procedure can be generalized to implement ANY finite state machine
Counters are a very simple way to start: no decisions on what state to advance to next current state is the output
No. 7-13
Example: 3-bit Binary Upcounter
State TransitionTable
FlipflopInput Table
Decide to implement withToggle Flipflops
What inputs must bepresented to the T FFsto get them to change
to the desired state bit?
This is called"Remapping the Next
State Function"
PresentState
NextState
FlipflopInputs
No. 7-14
Counter Design ProcedureIntroduction
This procedure can be generalized to implement ANY finite state machine
Counters are a very simple way to start: no decisions on what state to advance to next current state is the output
Example: 3-bit Binary Upcounter
State TransitionTable
FlipflopInput Table
Decide to implement withToggle Flipflops
What inputs must bepresented to the T FFsto get them to change
to the desired state bit?
This is called"Remapping the Next
State Function"
PresentState
NextState
FlipflopInputs
No. 7-15
Count
\Reset
Q C
Q B
Q A
100
K-maps for Toggle Inputs:
Resulting Logic Circuit:
Timing Diagram:
T
CLK
\Reset
Q
Q
S
R
QAT
CLK
Q
Q
S
R
QBT
CLK
Q
Q
S
R
QC
Count
+
TB = A
TC = A • B
T A = 1
CB A
C
00 01 11 10
0
1
B
1 1 1 1
1 1 1 1
CB A
C
00 01 11 10
0
1
B
0 0 0 0
1 1 1 1
CB A
C
B
00 01 11 10
0
1
0 0 0 0
0 1 1 0
No. 7-16
More Complex Count Sequence
Step 1: Derive the State Transition Diagram
Count sequence: 000, 010, 011, 101, 110
Step 2: State Transition Table
PresentState
NextState
No. 7-17
Step 1: Derive the State Transition Diagram
Sequence: 000, 010, 011, 101, 110
Step 2: State Transition Table
Note the Don't Care conditions
PresentState
NextState
No. 7-18
Step 3: K-Maps for Next State Functions
CB00 01 11 10A
0
1
C+ =
CB00 01 11 10A
0
1
A+ =
CB00 01 11 10A
0
1
B+ =
No. 7-19
Step 3: K-Maps for Next State Functions
C+
A+
B+
No. 7-20
Step 4: Choose Flipflop Type for Implementation Use Excitation Table to Remap Next State Functions
Toggle ExcitationTable
Remapped Next StateFunctions
PresentState
ToggleInputs
No. 7-21
Counter Design ProcedureMore Complex Counter Sequencing
Step 4: Choose Flipflop Type for Implementation Use Excitation Table to Remap Next State Functions
Toggle ExcitationTable
Remapped Next StateFunctions
PresentState
ToggleInputs
No. 7-22
Remapped K-Maps
TC =
TB =
TA =
CB00 01 11 10A
0
1
TC
CB00 01 11 10A
0
1
TA
CB00 01 11 10A
0
1
TB
No. 7-23
Remapped K-Maps
TC = A C + A C = A xor C
TB = A + B + C
TA = A B C + B C
TC
TA
TB
No. 7-24
Resulting Logic:
Timing Waveform:
5 Gates13 Input Literals + Flipflop connections
TCT
CLK
Q
Q
S
RCount
T
CLK
Q
Q
S
R
TBC
\C
B A
\B \A
TAT
CLK
Q
Q
S
R
\Reset
0
0
0
0
0
0
0
1
0
0
1
1
1
0
1
1
1
0
0
0
0
100
Count
\Reset
C
B
A
No. 7-25
Self-Starting CountersStart-Up States
At power-up, counter may be in possible state
Designer must guarantee that it (eventually) enters a valid state
Especially a problem for counters that validly use a subset of states
Self-Starting Solution:Design counter so that even the invalid states eventually transition to valid state
Two Self-Starting State Transition Diagrams for the Example Counter
Implementationin Previous
Slide!
No. 7-26
Self-Starting CountersDeriving State Transition Table from Don't Care Assignment
TC
TB
TA
C+
B+
A+
Present State
Next State
C+ 0 1 0 1 0 1 0 1
B+ 1 1 1 0 1 1 0 0
A+ 0 1 1 1 1 0 0 1
C 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
A 0 1 0 1 0 1 0 1
Inputs to Toggle Flip-flops State Changes
State Transition Table
No. 7-27
Implementation with Different Kinds of FFsR-S Flipflops
Continuing with the 000, 010, 011, 101, 110, 000, ... counter example
RS Exitation Table
Remapped Next State Functions
PresentState
NextState Remapped Next State
Q+ = S + R Q
No. 7-28
Implementation with Different Kinds of FFsR-S Flipflops
Continuing with the 000, 010, 011, 101, 110, 000, ... counter example
RS Exitation Table
Remapped Next State Functions
PresentState
NextState Remapped Next State
Q+ = S + R Q
No. 7-29
Implementation with Different Kinds of FFsRS FFs Continued
RC =
SC =
RB =
SB =
RA =
SA =
CB00 01 11 10A
0
1
RC
CB00 01 11 10A
0
1
RA
CB00 01 11 10A
0
1
RB
CB00 01 11 10A
0
1
SC
CB00 01 11 10A
0
1
SA
CB00 01 11 10A
0
1
SB
No. 7-30
Implementation with Different Kinds of FFsRS FFs Continued
RC = A
SC = A
RB = A B + B C
SB = B
RA = C
SA = B C
RC
RA
RB
SC
SA
SB
No. 7-31
Implementation With Different Kinds of FFs
RS FFs Continued
Resulting Logic Level Implementation: 3 Gates, 11 Input Literals + Flipflop connections
CLK CLK CLK \ A R
S A
C
\ C
Q
Q
RB
\ B
R
S
Q
Q \ B
B C
SA
R
S
A
\A
B
A C B
\C RB SA
Q
Q
Count
No. 7-32
Implementation with Different FF Types
J-K FFs
J-K Excitation Table
Remapped Next State Functions
PresentState
NextState Remapped Next State
Q+ = J Q + K Q
No. 7-33
Implementation with Different FF Types
J-K FFs
J-K Excitation Table
Remapped Next State Functions
PresentState
NextState Remapped Next State
Q+ = J Q + K Q
No. 7-34
Implementation with Different FF TypesJ-K FFs Continued
JC =
KC =
JB =
KB =
JA =
KA =
CB00 01 11 10A
0
1
JC
CB00 01 11 10A
0
1
JA
CB00 01 11 10A
0
1
JB
CB00 01 11 10A
0
1
KC
CB00 01 11 10A
0
1
KA
CB00 01 11 10A
0
1
KB
No. 7-35
Implementation with Different FF TypesJ-K FFs Continued
JC = A
KC = A
JB = 1
KB = A + C
JA = B C
KA = C
JC
JA
JB
KC
KA
KB
No. 7-36
Implementation with Different FF TypesJ-K FFs Continued
Resulting Logic Level Implementation: 2 Gates, 10 Input Literals + Flipflop Connections
CLK CLK CLK J
K
Q
Q
A
\ A
C
\ C KB
J
K
Q
Q
B
\ B
+
J
K
Q
Q
JA
C
A
\ A
B \ C
Count
A C KB JA
No. 7-37
Implementation with Different FF TypesD FFs
Simplest Design Procedure: No remapping needed!
DC = A
DB = A C + B
DA = B C
Resulting Logic Level Implementation: 3 Gates, 8 Input Literals + Flipflop connections
CLK CLK
D Q
Q
A
\ A
D Q
Q
DA DB B
\ B CLK
D Q
Q
A C
\ C Count
\ C \ A
\ B
B \ C DA DB
No. 7-38
Implementation with Different FF TypesComparison
• T FFs well suited for straightforward binary counters
But yielded worst gate and literal count for this example!
• No reason to choose R-S over J-K FFs: it is a proper subset of J-K
R-S FFs don't really exist anyway
J-K FFs yielded lowest gate count
Tend to yield best choice for packaged logic where gate count is key
• D FFs yield simplest design procedure
Best literal count
D storage devices very transistor efficient in VLSI
Best choice where area/literal count is the key
No. 7-39
Asynchronous vs. Synchronous CountersRipple Counters
Deceptively attractive alternative to synchronous design style
Count signal ripples from left to right
State transitions are not sharp!
Can lead to "spiked outputs" from combinational logic decoding the counter's state
Can lead to "spiked outputs" from combinational logic decoding the counter's state
T
Count
Q
QA
T Q
QB
T
CLK
Q
QC
CLK CLK
No. 7-40
Asynchronous vs. Synchronous CountersCascaded Synchronous Counters with Ripple Carry Outputs
First stage RCOenables second stage
for counting
RCO assertedsoon after stageenters state 1111
also a functionof the T Enable
Downstream stageslag in their 1111 to
0000 transitions
Affects Count periodand decoding logic (1) Low order 4-bits = 1111
(2) RCO goes high
(3) High order 4-bits are incremented
No. 7-41
Clock
Load
D
C
B
A
100
Asynchronous vs. Synchronous CountersThe Power of Synchronous Clear and Load
Starting Offset Counters: e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, ...
Use RCO signal to trigger Load of a new state
Since 74163 Load is synchronous, state changes only on the next rising clock edge
0110is the state
to be loaded
D C B A
L O A D
C L R
C L K
R C O
P T
Q A
Q B
Q C
Q D1
6 3
Load
D C B A
0 1++
No. 7-42
Asynchronous vs. Synchronous CountersOffset Counters Continued
Ending Offset Counter: e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000
Decode state todetermine when to
reset to 0000
Clear signal takes effect on the rising count edge
Replace '163 with '161, Counter with Async ClearClear takes effect immediately!
D C B A
C L R
L O A D
C L KP T
1 6 3
R C O
Q Q Q Q D C B A
CLR
D C B A
1 0
