Chapter 9 Memory Testing

Chapter 9Chapter 9Memory Testing Memory Testing

Jin-Fu LiAdvanced Reliable Systems (ARES) LabAdvanced Reliable Systems (ARES) Lab.

Department of Electrical EngineeringNational Central Universityy

Jhongli, Taiwan

Outline

Overview of Memory StructuresFunctional Fault ModelsFunctional Fault ModelsTest AlgorithmsM BISTMemory BIST

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

MemoriesVolatile memory

SRAM (Static random access memory)DRAM (Dynamic random access memory)CAM (Content addressable memory)FIFO (First in first output memory)…

Nonvolatile memoryROM (Read only memory)PROM (Programmable ROM)EPROM (Electric programmable ROM)Fl h Flash memory…


RAM ArchitectureVolatile memories may be divided into the following categories

R d Random access memorySerial access memoryContent addressable memoryContent addressable memory

A RAM architecturerow decoder

2m+k bits

row decoder

row decoder

row decoder2n-k words

row decoder

column decoder

column mux,sense amp,

it b ffn-bit address

k

m-bit data I/Os


write buffers

RAM CircuitGeneric RAM circuit

Bit line conditioning ClocksBit line conditioning Clocks

RAM Cell

n-1:k

Sense Amp, Column WriteSense Amp, Column Mux, Write Buffers Clocks

write data read dataAddress

k-1:0


write data read data

RAM Cells

6-T SRAM cell

d liword line

bit - bit

4-T SRAM cell

bit - bit

word line

bit


bit - bit

RAM Cells

4-T DRAM cellword lineword line

bit - bit

3-T DRAM cellReadWrite

Write d t Read


data Read data

RAM Cells

1-T DRAM cell

word line word line

bit bit

A sample of 1-T DRAM cell layout word lineVdd

bit


DRAM Retention Time

Write and hold operation in a DRAM cell

WL=1 WL=0

onCs Vs

+

-+off

Cs Vs

+

Input Vdd --

s s-

Write Operation HoldWrite Operation Hold

max tnDDs VVVV −==)(max

max

tnDDs

tnDDs

VVCQ −=


DRAM Retention Time

Charge leakage in a DRAM cellVs(t)

WL=0

IL

Vmax

V1Minimum logic 1

voltageoffCs Vs(t)

+

-t

V1

th

voltage

sL dt

dQI −= )(

th

ssL

Vdt

dVCI

Δ

−= )(

ss

h

ssL

VICtt

tVCI

Δ≈Δ=

ΔΔ

−≈

)(||

)(


sL

h I

DRAM Retention Time

As an example, if IL=1nA, CS=50fF and the difference of VS is 1V, the hold time isS

st h μ5.011011050

9

15

=×××

= −

−

To overcome the charge leakage problem, the DRAM arrays employ a refresh operation where

0

y p y pthe data is periodically read from every cell, amplified, and rewrittenThe refresh cycle must be performed on every cell in the array with a minimum refresh frequency of abo t about

hrefresh t

f21

≈


h

RAM Read Operation

Timing diagram of SRAM Read operation

prechargeprecharge

precharge

bit, -bit

word lineword

bit- bitdata

data


data

RAM Address Decoder

A design sample of a row decoder

word<3> word<0>

word<2> word<1>

word<1> word<2>

word<0> word<3>

a<1> a<0> a<1> a<0>


a<1> a<0> a<1> a<0>

RAM Address Decoder

Symbolic layout of row decoder

output

VssVddVss


RAM Address DecoderPredecoded row decoder

word<7>

word<5>

word<6>

word<3>

word<4>

word 3

word<2>

word<1>

word<0>

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15a0a1a2

RAM Address Decoder

Row decoder with enable signal (actual implementation)p )

a0

2a3a4

a0 lk

a1a2 word

Implementation with Pseudo-NMOS logic

-a0 clk

worda0


a1 a2 en

RAM Address DecoderColumn decoder

bit<7>bit<6>bit<5>bit<4>bit<3>

selected-data

bit<2>bit<1>bit<0>

-bit<7>-bit<6>

to sense amps and write ckts

-bit<5>-bit<4>

-bit<3>-selected-data

-bit<2>-bit<1>-bit<0>


a0 -a2a2-a1a1-a0

Multi-Ported RAMs

write

-rbit1 -rbit0 -rwr data rbit1rbit0rwr data

writeread0read1

_ _

writeread0read1


-rbit1 -rwr_data rbit0rwr_data

Functional RAM Model

address latch

column decoderaddress latch

r

memorycell array

row deco

lifi

oder

it d i sense amplifierwrite driver

d t i tread/write & data registeread/ te &enable

data data


data out

data in

Reduced Functional ModelReduced functional RAM model

M Raddressdecoder

Mem

ory carray

Read/w

ritlogic

address

data

The address latch the row and the column-

s r cell

te The address latch, the row, and the columndecoder are combined to the address decoder

They all concern addressing the right cell or wordThey all concern addressing the right cell or word

The write driver, the sense amplifier, and the data register are combined to the read/write data register are combined to the read/write logic

They all concern the transport of data from and to


y pthe memory cell array

RAM Functional FaultsSingle-cell faults

Stuck-at fault (SAF): SA0, SA1Transition fault (TF): TFu, TFd…

Two-cell faultsState coupling fault (CFst)Idempotent coupling fault (CFid)Inversion coupling fault (CFin)…

Multiple-cell faultsNeighborhood pattern sensitive fault (NPSF)…


Address decoder faults

Single-Cell Faults

Stuck-at faultDefinition: The logic value of a stuck-at cell or line gis always 0 (SA0) or 1 (SA1). That is, it is always at state 0 or in state 1 and cannot be changed to the opposite statethe opposite stateDetection requirement: For each cell or line, a 0 or 1 must be read1 must be read

Transition faultDefinition: A cell that fails to undergo a 0 to 1Definition: A cell that fails to undergo a 0 to 1transition when it is written is said to contain an up transition fault (TFu).A down transition fault (TFd) indicates that a cell fails to undergo a 1 to 0 transition


Single-Cell Faults

A TF can be thought of as a set/reset (S/R)-type flip-flop with a SAF on the set or reset yp p pinput

SA0 S QS Q

R Q

Detection requirementDetection requirementEach cell should undergo up and down transitions and be read after each transition before undergoing and be read after each transition before undergoing further transitions


State Diagram for SAFs & TFsFaults can be described with state diagramsState diagram of a good cell is shown belowg g

S S

w1

w1w0

State diagrams of SAFs

S0 S1w1

w0 w0

State diagrams of SAFs

S0w0 w1 S1w0 w1 SA0 fault SA1 fault

State diagram of TF

0 1SA0 fault SA1 fault

S0w0

w1

S1w0 TFu


w1 w0

Two-Cell Faults

Inversion coupling fault (CFin)A 0 to 1 (or 1 to 0) transition in one cell inverts the ( )content of a second cellAn CFin can be thought of as a D-type flip-flop with

t l k i t C d th Q’ t t ti d t th an extra clock input Cd and the Q’ output tied to the D input, as depicted in the following figure

D Q

Cd

D Q

QCn

d


Two-Cell Faults

Idempotent coupling fault (CFid)A 0 to 1 (or 1 to 0) transition in one cell forces the ( )content of a second cell to a certain value, 0 or 1An idempotent coupling fault can be thought of as

S/R t fli fl ith OR t i th S t an S/R-type flip-flop with an OR-gate in the Set or Reset line, as depicted in the following figure. Sn is the normal set input whereas Sd is the undesired the normal set input whereas Sd is the undesired set input due to coupling with one or more other flip flops

SdS QSn

R QRn


Two-Cell Faults

State coupling fault (CFst)A 0 or 1 state in one cell forces the content of a second cell to a certain value, 0 or 1It can be thought of as a D-type flip-flop with an OR/AND t i th d t li (D) d i t d i th OR/AND-gate in the data line (D), as depicted in the following figure. Dn is the normal set input whereas Dd is the undesired set input due to coupling with Dd is the undesired set input due to coupling with one or more other flip flops

DDd

D Q

Q

Dn

clk Qclk


State Diagrams for CFin & CFidState diagram of two good cells

w0/iw1/j S00

w0/i, w1/j S01

w0/i, w0/j

w0/i w1/i

j

w0/j

w0/i w1/i

S10 S11

w0/i w1/i w0/i w1/i

w1/j w0/j

w1/i, w1/j w1/i,

w0/j

State diagrams of CFin & CFid

jj

S w0/i, Sw0/i w0/j w0/iw0/i w0/j S00,

w1/j S01w0/i, w0/j

w0/i w1/i

j

w0/i w1/i

S00w0/i, w1/j S01

w0/i, w0/j

w0/i w1/i

w0/j

w0/i w1/i

w1/j w1/j

S10 S11w1/j w0/j

w1/i, w1/j w1/i,

w0/j S10 S11w0/j w1/i, w1/j

w1/i, w0/j

w1/j


State diagram of an CFin<u;i> State diagram of an CFid<u;1>

State Diagrams for CFst & TFState diagram of two good cells

w0/iw1/j S00

w0/i, w1/j S01

w0/i, w0/j

w0/i w1/i

j

w0/j

w0/i w1/i

S10 S11

w0/i w1/i w0/i w1/i

w1/j w0/j

w1/i, w1/j w1/i,

w0/j

State diagrams of CFst & TF

jj

S w0/iSw0/iw1/j

S w0/iSw0/i w0/j S00w0/i, w1/j S01

w0/i, w0/j w0/j S00

w0/i, w1/j S01

w0/i, w0/j

w0/i w1/i

j

w0/i w1/i w1/j

w1/i w1/i w0/i w0/i

S10 S11w1/j w0/j

w1/i, w1/j

w1/i, w0/j S10 S11

w1/j w0/j

w1/i, w1/j

w1/i, w0/j

w0/i w0/i


State diagram of a CFst<1;1> State diagram of TFu & TFd

Summary for CFs

Note that all definitions talk about single-way faults, that is, the presence of a CF from cell i, , pto cell j does not imply the presence of a CF from cell j to cell iSuppose that a transition or state in cell j can induce a coupling fault in cell i. Cell i is then said to be coupled cell (or victim); cell j is called the coupling cell (or aggressor)A test that has to detect and locate all coupling faults should satisfy

For all coupled cells, each cell should be read after a series of possible coupling faults may have occurred


Multiple-Cell Faults

Neighborhood pattern sensitive fault (NPSF)A subset of the Pattern Sensitive Fault (PSF)( )

Pattern sensitive fault is defined as follows:The content of a cell is affected by the contents of a The content of a cell is affected by the contents of a group of cells

The PSF is the most general k-couping fault, g p g ,where k=n (all of the memory)In the PSF, the neighborhood could be , ganywhere in the memory array, whereas in a NPSF, the neighborhood must be in a single position surrounding the base cell


NPSFThe neighborhood types of NPSF

Type-I neighborhood

0Base cell

Deleted1 2 3

4

Deleted neighborhood

Type-II neighborhood

0 1 23 4 53 4 56 7 8


Types of NPSF

Three types of NPSF (most used)Active NPSF (ANPSF)( )Passive NPSF (PNPSF)Static NPSF (SNPSF)

ANPSFThe base cell changes due to a change in the g gpattern of the deleted neighborhoodAn ANPSF test has this necessary condition

Each base cell must be read in state 0 and state 1, for all possible deleted neighborhood pattern changes

PNPSFPNPSFA specific neighborhood pattern prevents the base cell from changing


ce o c a g g

Types of NPSF

The necessary condition to detect and locate a PNPSF

Each base cell must be written and read in state 0 and in state 1, for all deleted neighborhood pattern permutationsp

SNPSFThe base cell is forced into a particular state when pthe deleted neighborhood contains a particular patternh d fThe necessary condition of test is

Each base cell must be read in state 0 and in state 1, for all deleted neighborhood pattern permutationsfor all deleted neighborhood pattern permutations


Fault ModelingRelation between faults and defects

Defect d1 (inverse node shorted to Vdd) causes a SA0 fault

Vdd

RR

Defect d2 (true node shorted to Vss) causes a SA0 faultDefect d3 (open true node gate) cause a SA1 faultd7

WL

RR cause a SA1 faultDefect d4 (an open word line) causes all cells after the WL fault to be inaccessible (AF)

d1 d4

7

V

( )Defect d5 (a short between the true node and BL) will pull BL down if the cell contains a 0, but will not affect BL if the cell

d2d3

d5 d6

Vss

BLBL

will not affect BL if the cell contains 1. This is the state coupling fault <0;0>Defect d6 (short between inverse 6 (node and BL’) is similar, as is the state coupling fault <1;1>Defect d7 (open BL’) prevents cells after the open defect from


cells after the open defect from passing a logic 1 value on BL’


Defect d1 (a word line connected to Vss) causes all cells in the word line

b k

Vdd

RR

to be stuck open.A defect in the poly silicon layer covering a diffusion region may result in the creation of an extra pass

WL

RRd3

result in the creation of an extra pass transistor. This defect (d2) causes a transition fault.Defect d3 (a broken pull up resistor)

Vd2

3 ( p p )introduces a data retention fault. If the cell is not accessed, the cell node with the broken pull up resistor can be floating high or active low If the Vss

BLBL

2 be floating high or active low. If the node is floating high, the leakage current from the cell node to the substrate will decline the voltage at gthe node. If the node voltage passes the threshold voltage Vth the data in the cell will invert. If the node is active low the cell will function


active low, the cell will function correctly.


WLDefect d1 (a short between two WLs) results in an AND bridging fault WL

d2

g gbetween pairs of cells located in the same column for the two shorted WLsD f t d ( it WL h t)

WLDefect d2 (a capacitor-WL short) causes a SA1 faultDefect d3 (a short between two capacitors) causes a state coupling

WL

d1 d3d4

d5

capacitors) causes a state coupling faultDefect d4 (a shorted capacitor) is a SA0 fault5Defect d5 (a short between capacitor and BL) is an AND bridging fault with all cells in the same column

BL BL BLDefect d6 (a short between two neighboring BLs) causes an AND bridging fault between pairs of cells on the same word line and on the

d6


on the same word line and on the shorted bit lines

Fault Mapping

A reduced functional model has been defined consisting of three blocks:g

The address decoder, the memory cell array, and the read/write logic

When one wants to test a memory for SAFs, three tests would be necessary

One test that detects SAFs in the address decoderOne test that detects SAFs in the memory cell arrayOne test that detects SAFs in the read/write logic

Most faults occurring in the read/write logic d th dd d d b d t and the address decoder can be mapped to

faults in the memory cell array


Fault MappingMapping read/write logic faults into memory array faults

A test that detects SAFs in the memory array will also detect SAFs in the read/write logic

A SAF i th d/ it l i ill l A SAF in the read/write logic will appear as a large group of cells stuck-at faults

The same arguments are valid for TFs and CFse sa e a gu e ts a e a d o s a d C s

For NPSFs, this cannot be proven generallyA test that detects NPSFs in the memory cell array A test that detects NPSFs in the memory cell array will also detect NPSFs in the read/write logic under the condition

Each neighborhood in the data register is a subset of a neighborhood in the cells of the memory cell array


Fault MappingFor example

A test for defecting Type 1 NPSFs can also detect the i hb h d f l i d ineighborhood faults in data register

A test for detecting column neighborhood faults can not detect the neighborhood faults in the data registerg g

w5w4 w6

Type 1 neighborhood Column neighborhood

w2b2x2 z2

w5w4 w6x5x4 x6b5b4 b6

y2 y5y4 y6z5z4 z6

b1x1 z1 b3u3 v3


Data register

Address Decoder FaultsAn address decoder fault (AF) represents an address decoding errorAssumptions

The decoder logic does not become sequentialThe fault is the same during both read and write operations

AFs can be classified into four casesFault 1: no cell is accessed for a certain addressFault 2: no address can access a certain cellFault 3: with a particular address, multiple cells are simultaneously accessedsimultaneously accessedFault 4: a particular cell can be accessed with multiple addresses


p

Address Decoder Faults

Cx CxAx

Ax Cx Ax Cy Ay

Fault 1 Fault 2 Fault 3 Fault 4

Address decoder faults

Ax Cx Ax Cx Ax Cx

Ax Cx Ay Cy Ay Cy Ay Cy

Combinations of AFs that must be testedFault A (1+2) Fault B(1+3) Fault C(2+4) Fault D (3+4)



Fault A & fault B are inherently unlinkedIt is impossible to mask the fault occurring when p gone reads Ax

Fault C & fault D may be linkedIt is possible that writing in Ax masks the fault that occurred when Cx was erroneously written through AAy

Therefore, fault C & fault D are extended to the general case with more than two the general case, with more than two addresses

See the figure shown in the next pageSee the figure shown in the next page



Av Cv Av Cv

Aw Cw Aw Cw Ax Cx Av Cv

Ax Cx Ax Cx Ay Cy Aw Cw

Ay Cy Ay Cy Az Cz Ax Cx

Az Cz Az Cz

Fault C Fault D Fault D Fault DFault C Fault D1 Fault D2 Fault D3

Note that any number of cells and addresses with the same fault can be inserted bet een and and bet een and


inserted between v and w and between y and z.

Address Decoder FaultsIf multiple cells are accessed simultaneously with a single address, as in fault D, a read operation

i ld f th f ll i t ltcan yield one of the following two resultsAll addressed cells have the same contents Not all add essed cells ha e the same contents T o Not all addressed cells have the same contents Two cases can be distinguished

The memory returns a value that is a deterministic The memory returns a value that is a deterministic function of the contents of all addresses cellsThe memory returns a random or pseudorandom resultresult

In general, it is safest for AF tests to expect the memory to return a random value except for the memory to return a random value, except for the case in which all cells contain the same value

The tests should be designed such that they are not


g yinfluenced by random results

Specific Faults in Multi-Ported RAMs

The memory cell array faults can be detected as the single-port RAMsg pMulti-port RAM specific faults should be covered

Inter-port faults

Intra-port faultst a po t au ts

To reduce the test complexity, usually, the testing of inter-port and intra-port faults is testing of inter port and intra port faults is based on the following assumption

Physical layout is knowny y


March Tests

A march test consists of a finite sequence of march elementsA march element

A finite sequence of Read and/or Write operations q / papplied to every cell in memory in either increasing address order (cell 0 to cell n-1) or decreasing address order (cell n 1 to cell 0)address order (cell n-1 to cell 0)

All operations of a march element are done before proceeding to the next addressbefore proceeding to the next addressThe march tests are a preferred method for RAM testingRAM testing

Linear complexity, regularity, and symmetry


Mach Test Notation

rx: a read x operationwx: a write x operationwx: a write x operation

: increasing addressing sequence (from 0 to n-1)⇑n 1)

: decreasing addressing sequence (from n-1 to 0)⇓to 0)

: either increasing or decreasing addressing sequencecsequence


An Example of March Test

March test: )}0,1();1({ wrw ⇓⇑

Addressing Addressing Addressing Addressing

1 XX

1 1X

1 11

1 11

(w1)

Addressing cell 0

Addressing cell 1

Addressing cell 2

Addressing cell 3

X X X X 1 X 1 1Initial state

X XX X

1 1 1 00 0 0 0

Addressing cell 0

Addressing cell 1

Addressing cell 2

Addressing cell 3

1 1 1 1 1 1 10(r1,w0)

0 11 1

0 01 1

0 00 1

0 00 0


SAF & TF Testing

MATS+:MATS+ detection of SA0 fault

)}0,1();1,0();0({ wrwrw ⇓⇑c

MATS+ detection of SA0 fault

0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0

G d G d G dGood memory after M0

Good memory after M1


0 0 0 0 0 0 0 0 0

1 1 1 0 1 1 1 1 1

0 0 0 0 0 0 0 0 0

Bad memory after M0

Bad memory after M1

Bad memory after M2


SAF & TF TestingMATS+ detection of SA1 fault

0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0

Good memory Good memory Good memoryGood memory after M0



0 0 0 1 0 0 0 0 0

1 1 1 1 1 1 1 1 1

0 0 0 1 0 0 0 0 0

Bad memory after M0

Bad memory after M1

Bad memory after M2

MATS+ detection of TFu & TFd can be proved in the same way


CFs TestingMarch C-:Detection of CFs

)}0();0,1();1,0();0,1();1,0();0({ rwrwrwrwrw cc ⇓⇓⇑⇑

1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 M1 is 0 0 0 0 0 0Cell 0 is

0 0 0 0 0 0Cell 1 is

0 0 0 0 0 0Cell 2 is

1 0 0 0 0 0Cell 3 is

1 1 1 1 1 1Cell 8 is

M1 is executed

addressed addressed addressed addressed addressed

0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 1 1

0 0 0 0 0 0 1 1 1

0 0 0 0 0 1 1 1 1

1 1 1 1 1 1 1 1 1

M3 is executed 0 0 1

Cell 0 is addressed

0 1 1Cell 1 is

addressed

1 1 1Cell 2 is

addressed

1 1 1Cell 3 is

addressed

1 1 1Cell 8 is

addressed


CFs TestingConditions for detecting CFs

A march test which contains one of the two pairs of h l t f C A & C B d t t i l march elements of Case A & Case B can detect simple

CFs (CFin, CFst, CFid)Case A

1. 2.

C B

),,( xwrx L⇑ ),,( wxxr L⇑),,( xwrx L⇓ ),,( wxxr L⇓

Case B1.2.

),,( wxxr L⇑ ),,( xwrx L⇑)( wxxr L⇓ )( xwrx L⇓

A.1 (A.2) will sensitize the CFs, and it will detect the fault, when the value of the fault effect is x’ (x),

),,( wxxr⇓ ),,( xwrx⇓

by the rx (rx’) operation of the first (second) march element when the coupled cell has a higher (lower) address than the coupling cell


address than the coupling cell

AFs TestingConditions for detecting AFs

Condition Element

),,( xwrx L⇑

Condition Element

1

Condition 1

),,( wxxr L⇓2

Condition 1Read the value x from cell 0, then write x’ to cell 0 read the value x from cell n-1 then write x’ to 0, …, read the value x from cell n 1, then write x to cell n-1

Condition 2Read the value x’ from cell n-1, then write x to cell n-1, …, read the value x’ from cell 0, then write x to


cell 0

AFs TestingSufficiency of the conditions for detecting AFs

Fault A & B:Detected by every test that detects SAFs. When address Ax is written and read, Cx will appear either SA0 or SA1.

Fault C:Fault C:Detected by first initializing the entire memory to an expected value x or x’. Any subsequent march element

i h d h d l d d b i ioperation that reads the expected value x and ends by writing x’ detects fault C

Fault D:Fault D:The memory may return a random result. The fault must be generated when Ax is written, and detected when either Aw

d A i dand Av is readCondition 1 detects fault D1 and D2Condition 2 detects fault D1 and D3


Condition 2 detects fault D1 and D3

AFs Testing

Necessity of the conditions for detecting AFsRemove rx from Condition 1

A test can not detect fault A or B for the case they always return x’

R ’ f C diti 2Remove rx’ from Condition 2A test can not detect fault A or B for the case they always return xalways return x

Remove rx or wx’ from Condition 1A test can not detect fault D2

Remove rx’ or wx from Condition 2A test can not detect fault D3

Remove both write operationsA test can not detect fault C and fault D1


NPSFs TestingNeighborhood Pattern Sensitive Faults (NPSFs)

Type 1 and type 2 neighborhoods

T 1 T 2Type 1 Type 2

The physical layout of the RAM core and the t h l d t i hi h ll ld ff t technology determine which cells could affect each other

U ll t 1 i hb h d i d b th Usually type 1 neighborhood is used because the deleted neighborhood is most likely affects the based cell


NPSFs Testing

Type 1 tiling neighborhoodThe figure shows that a cell-2 as base cellgThe deleted neighborhood of all base cells-2 is formed by a cell-0, a cell-1, a cell-3, and a cell-4

02 3 0

02 31 04

1 2 3 4 1 24

3 412 3

4 02 34

1

02 34

102 31

2 34

102 34

1

02 34

1

0

4 4

3

1

00214 2 3

41 40

2 34

1302 34

02 34

102 34

1 02 310

02 310

24

1

14 4 2 3

410

2 34

12 34

102 34

1 020 1

02 3103


NPSFs Testing

Five base cells using type-1 tiling neighborhood

143

20 20

4

31 31

0

42

4213 03

2442

53 03

14

SNPSF testWhen all static neighborhood patterns are applied When all static neighborhood patterns are applied With n/5*25 Write operations


NPSFs Testing

Type 2 tiling neighborhoodSimilar to type 1 NPSFs tiling methodyp g

325 34 5

03 4 5

1 2 0 1 0 14

2 033

6 75 38

46

58 67

3 46 7 8

5 4 3

03 4 5

1 2 03 4 5

1 2 03 4 5

1 2 033 4

6 7 85 3 4

6 7 85 3 4

6 7 85

03 4 5

1 2 03 4 5

1 2 03 4 5

1 263

033 4

6 7 85 3 4

6 7 85 3 4

6 7 85

63

20 1 20 1 20 1 0


NPSFs Testing

Two-group method for type 1 neighborhoodBased on the duality of cells: a cell is a base cell in yone group while it is a deleted neighborhood cell in the other group

A 2 B 2 A 2 B 22 C 2 D 2 C 2 DB 2 A 2 B 2 A 2

1 A 1 B 1 A 1 BC 1 D 1 C 1 D 11 B 1 A 1 B 1 AB 2 A 2 B 2 A 2

2 D 2 C 2 D 2 CA 2 B 2 A 2 B 22 C 2 D 2 C 2 D

1 B 1 A 1 B 1 AD 1 C 1 D 1 C 11 A 1 B 1 A 1 BC 1 D 1 C 1 D 12 C 2 D 2 C 2 D

B 2 A 2 B 2 A 22 D 2 C 2 D 2 C

C 1 D 1 C 1 D 11 B 1 B 1 A 1 AD 1 C 1 D 1 C 1

This method can not extend to test type 2 NPSFs because it depends on the duality concept


Tests for Word-Oriented MemoriesFault models for word-oriented memories (WOMs)

Only the class of memory cell array faults for bit-oriented memories (BOMs) has to be extended in order to cover WOMsorder to cover WOMs

The fault models for WOMs can be classified into two classesinto two classes

Single-cell faultsSAFs TFs data retention faults (DRFs) etcSAFs, TFs, data retention faults (DRFs), etc.

Faults between memory cellsCFs

Two classes of faults between memory cells for WOMs needed to be considered


Tests for Word-Oriented MemoriesCFs in BOMs

CFs in WOMsCFs in WOMsInter-word CFs & intra-word CFs

Intra-word CF

Inter-word CF


Converting BOM Tests to WOM Tests

Any given BOM march test can be converted to a WOM march test

With additional tests to cover intra-word faults

A WOM march test is a concatenation of two march tests

{Inter-word march test, intra-word march test}

The inter-word march test can directly be obtained from the BOM march test

Replace the bit-operation “r0”, “w0”, “r1”, and “w1”with the word-operation “rD”, “wD”, “rD’”, and “wD’”,

h D i ll d d t b k dwhere D is called data background


Converting BOM Tests to WOM TestsThe intra-word faults can be detected by a single march element with different operations and data backgroundsoperations and data backgrounds

E.g., intra CFst can be covered by with various data backgrounds (DBs)

),,...,,( 11 nn rdwdrdwdwith various data backgrounds (DBs)Note that the DBs can be applied in any order

The above intra-word test can be modified as The above intra word test can be modified as follows, without any impact on the fault coverage

Extra Read operations can be added The single march element can be divided into any number of march elements and for each any number of march elements, and for each march element the addressing order can be chosen freely


y

Cocktail March Tests for WOMIf you have a bit-oriented march test, then you can obtain a compact WOM test with

Replace the bit-operation “r0”, “w0”, “r1”, and “w1”with all-0 and all-1 data backgroundsC t t h l t )( dddddConcatenate a march element for d={0101..01,0011..11, …}

For example the March C can be extended as

),,,,( rdwddrdwwd

For example, the March C- can be extended as follows to test a memory with 4-bit words

⇑⇑

);0000();0000,1111();1111,0000();0000,11111();11111,0000();0000({

rwrwrwrwrw

c

c

⇓⇓

⇑⇑

)}0011,0011,1100,1100,0011();0101,0101,1010,1010,0101(

rwrwwrwrww

c

c


)},,,,(c

Memory Built-In Self-Test

A typical RAM BIST architecture

Normal I/Os

Tes

Test Controller

RAM

st Collar

Test PatternG t rGenerator

Go/No GoComparator

Go/No-Go


Memory Built-In Self-Test

In general, two BIST approaches have been proposed for the RAMsp p

FSM-based RAM BISTROM-based RAM BIST

ControllerGenerate control signals to the test pattern generator & the memory under test

Test pattern generator (TPG)Generate the required test patterns and Read/Write signals

ComparatorEvaluate the response


ROM-Based RAM BIST The features of ROM-based BIST scheme

The ROM stores test procedures for generating test patternsSelf-test is executed by using BIST circuits controlled by the microprogram ROMcontrolled by the microprogram ROMA wide range of test capabilities due to ROM programming flexibilityprogramming flexibility

The BIST circuits consists of the following functional blocksfunctional blocks

Microprogram ROM to store the test procedureProgram counter which controls the microprogram g p gROMTPG


Comparator

ROM-Based RAM BIST Architecture

Normal I/Os

MicroprogramEnd

RAM

Test C

p gROM

RAM

CollarTPG

ComparatorGo/No-Go

Comparator


An Example (March-9N)

CLEAR WRITE(D) INC AC IF AC=MAX THEN INC PC

STEP MICROCODE0 0 0 0 0 0 0 0 1 01 0 1 0 0 0 0 1 0 0

OPERATION

WRITE(D), INC AC, IF AC=MAX THEN INC PC READ(D)WRITE(D’), INC AC, IF AC=MAX THEN INC PC ELSE DEC PCREAD(D’)

1 0 1 0 0 0 0 1 0 00 0 0 0 0 0 0 1 0 0

WRITE(D) INC AC IF AC=MAX THEN INC PC ELSE DEC PC

1 1 1 0 0 1 0 1 0 00 0 0 0 0 1 1 0 0 01 1 1 0 0 0 0 1 0 0

DEC ACREAD(D)

WRITE(D), INC AC, IF AC=MAX THEN INC PC ELSE DEC PC

WRITE(D’), DEC AC, IF AC=0 THEN INC PC ELSE DEC PCREAD(D’)

1 1 1 0 0 0 0 1 0 00 0 0 1 0 0 0 0 0 00 0 0 0 0 0 1 0 0 01 1 0 1 0 1 0 1 0 00 0 0 0 0 1 1 0 0 0

STOP

READ(D ) WRITE(D), DEC AC, IF AC=0 THEN INC PC ELSE DEC PC

0 0 0 0 0 1 1 0 0 01 1 0 1 0 0 0 1 0 00 0 0 0 0 0 0 0 0 1

IF AC=MAX/0 ELSE DEC PC INCREMENT AC DECREMENT AC EXCLUSIVE OR INVERT/NORMAL COMPARE/MASK WRITE/READ CLEAR


CTEST END

FSM-Based RAM BIST

Normal I/Os

RAM

Test C

FSM

RAM

CollarTPG

ComparatorGo/No-Go

Comparator


FSM-Based RAM BISTThe state diagram of a controller example

S0W0 NOT last address?0

S1R0NOT last address?

S2W1

SS3

S4

R1

W0NOT last address?

4

S5R0NOT last address?

S4W1


S4End

Processor-Based RAM BIST

Normal I/OsNormal I/Os

Test

Processor

RAM

CollarTPG

C tGo/No-Go

Comparator


Summary

This chapter have presented the following topicsp

Review of memory structuresRAM functional fault modelsMarch test algorithmsRAM BIST designs


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Chapter 9 Memory Testing

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