Chapter to learn java programming

7/27/2019 Chapter to learn java programming

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Introduction to Computing Systemsfrom bits & gates to C & beyond

Chapter 3

Digital Logic Structures

Transistors

Log ic gates & Boolean logicCombinational log ic

Storage Elements

Memo ry


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Copyright 2003 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside3 - 2

A

B

G

N

Open (insulating) if gate is off = 0

Closed (conducting) if gate is on = 1

P

Open (insulating) if gate is on = 1

Closed (conducting) if gate is off = 0

A

B

G

CMOS Transistors

CMOS= Complementary Metal-Oxide Semiconductor

Standard type for digital applications

Two versions: P-type (positive) and N-type (negative)

P and N-type transistors operate in inverse modes


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2.9 v

0 v

outin

In Out

0 1

1 0

Inverter Gate

When the input is on (in =

high voltage), the P-type

transistor is openand the N-

type is closed, so the output

is off (out = low voltage).

Vice-versa: when the Input is

off (in = low voltage), the

output is connected to the

high voltage.

P

N


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NOR Gate

A B C

0 0 1

0 1 0

1 0 0

1 1 0

C

A

B

2.9 v

0 v0 v

P

N

P

N


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OR Gate

D

A

BC

A B C D

0 0 1 0

0 1 0 1

1 0 0 1

1 1 0 1

= a NOR gate followed by an inverter


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NAND & AND Gates

A B C D

0 0 1 00 1 1 0

1 0 1 0

1 1 0 1

A

B

CD


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Logic Gates & Symbols

Note that gates can have more than 2 inputs.


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De Morgans Law

not(A and B) = (not A) or (not B)

not(A or B) = (not A) and (not B)

A and B A or B =

A or B A and B =


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Representation of Logic Functions A logic function can be represented as

a truth table

a logic expression

a logic circuit

Example.caa.da.b.c.cad)a.(b.cf

11111

10111

11011

0001111101

00101

11001

00001

11110

10110

01010

00010

11100

1

00

f

0100

10000000

dcba

ba

c

d f


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Types of Logic StructuresTwo types of logic structures ==> two types of logic circuits

Decis ion structu res: can make a decis ion b ased on ly on the current

inpu ts: gates belong to th is catego ry.

Storage structures: permit th e storage of informat ion (as bits) .

Combinational logic circuits

a comb inat ional logic st ructure is con structed from decis ion elements

on ly: i .e. simple gates or oth er com binat ional log ic circuits .

i ts output depends sole ly on i ts current input .

Sequential logic circuits

combine combinat ional c ircui ts & storage dev ices - well deal with

these sho rt ly .

Three examples of combinational logic circuits Decoder

Mul t iplexer (MUX)

Ful l adder


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Decoder

An n input decoder has 2n

outputs.

Outputiis 1 iff the binaryvalue of the n-bit input is i.

At any time, exactly one

output is 1, all others are 0.

1, iff A,B is 00A

B

1, iff A,B is 01

1, iff A,B is 10

1, iff A,B is 11

i = 0

i = 1

i = 2

i = 3


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Multiplexer (MUX)

In general, a MUX has

2ndata inputs

n select (or co ntro l) l ines

and 1 outpu t.

It behaves like a channel selector.

A 4-to-1 MUX:

Out takes the value of A,B, C or D

depending on the value of S (00, 01, 10, 11)

S[1:0]

A B C D

Out

.SD.SS.C.S.SSB.S.SA.Out 10101010

A B C D

Out

S0

S1


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Adder

Half Adder2 inputs

2 outputs: sum and carry

Full Adderperforms the addition in column i

3 inputs: ai

, bi

and ci

2 outputs: si and ci+1

ciis the carry in from bit position i-1

ci+1is the carry out to bit position i+1

ai bi ci + si

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Half-adder truth table

n 1 n 2 1 0

n 1 n 2 1 0

n 1 n 2 1

n 1 n 2 1 0

a a ... a a

b b ... b b

c c ... c 0

s s ... s s


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Gate Level Full Adder

Ai Bi Ci Ci+1 Si

0 0 0 0 0

0 0 1 0 1

0 1 0 0 10 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 01 1 1 1 1


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Full Adder - Expressions

).(.1 iiiiii

iiii

bacbac

cbas

where

operationORtheis

operationANDtheis.

ORexclusiveis

- verify that this corresponds to the gate-level implementation.


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A 4-bit Ripple-Carry Adder


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Storage Elements: R-S Latch

The output aof the R-S latch canbe set to 1 by momentarily settingS to 0 while keeping R at 1.

When S is set back to 1 the outputastays at 1.

Conversely, the output acan be

set to 0 by keeping S at 1 and

momentarily setting R to 0.

When R is set back to 1, the

output astays at 0.

The flip-flop (R-S latch) is a bi-stable element

10

10

1 0

1

0


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Storage Elements: Gated D Latch

The gated D latch is an extension of the R-S latch

Two inputs: data (D) and write enable (WE)

When the WE (write enable) is set to 1, the output of the latch

is set to the value of D.

The output is held until WE is asserted (set to 1) again.


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Registers

A 4-bit register made of four D latches


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Memory - 1

Address Space

nbits allow the addressing of 2nmemory locations. Example: 24 bits can address 224 = 16,777,216 locations

(i.e. 16M locations).

If each location holds 1 byte (= 8 bits) then the memory is 16MB.

If each location holds one word (32 bits = 4 bytes) then it is 64 MB.

A large number of addressable fixed size locations


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Memory - 2

AddressabilityComputers are eitherbyteor wordaddressable - i.e. each memory

location holds either 8 bits (1 byte), or a full standard word for that

computer (16 bits for the LC-3, more typically 32 bits, though now

many machines use 64 bit words).

Normally, a whole word is written and read at a time:

If the computer is wordaddressable, th is is s imply a single address locat ion.

If the computer is byteaddressable, and uses a mu lt i -byte word, then the word

address is con vent ional ly ei ther that of i ts most s igni f icant byte (big endian

machines) or of its least sig nif icant b yte (l i t t le end ian machin es).


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Building a Memory

Each bit is a gated D-latch

Each locationconsists of w bits (here w = 1)

w = 8 if the memory is byteaddressable

Addressingn locations means log2n

address bits (here 2 bits => 4

locations)decoder circuit translates

address into 1 of n locations

WE

A[1:0] D


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Memory Example

A 22by 3 bits memory:two address lines: A[1:0]

three data lines: D[2:0]

one control line: WE

One gated

D-latch


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Reading a location in memory


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Using Memory Building Blocks

Building an 8K byte memory using chips that are 2K by 4 bits.

CS= chip select:

when set, it enables

the addressing,

reading and writing

of that chip.

This is an 8KB

byte addressablememory

d

e

c

o

d

er

CS CS

CS CS

CS CS

CS CS

A10-A0

A12-A11

2K x 4 bits 2K x 4 bits

2K x 4 bits2K x 4 bits

2K x 4 bits 2K x 4 bits

2K x 4 bits2K x 4 bits


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Memory One Word Wide

Use the previous memory block of 8K x 1 byte to build a memory that is 64K

words, with each location one word of 32 bits. what are the address lines if the memory is word addressed? or byte addressed?

A? - A?

d

e

c

o

d

er

A? - A?

8K x 1B


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Sequential Logic Circuits - 1

The concept of statethe state of a system is a snapshot of all relevant elements at a

moment in time.

a given system will often have only a finite number of possible

states.

e.g. the game of tic-tac-toe has only a certain number of possible

dispositions of Xs and Os on the 3x3 grid.

A given game of tic-tac-toe will progress through a subset of

these possible states (until someone wins) - i.e. it traverses a

specific path through state space, one move at a time.

For many systems, we can define the rule which determine under

what conditions a system can move from one state to another.


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Sequential Logic Circuits - 2

The output is a function of the current input and the previous state

It is computed by the combinational log ic c i rcu i t

The state is stored in the sto rage element

The new state is also a function of the previous state and the currentinput

This can work only if we make transitions from one state to another

at well-defined times - this is why they are called sequential circuits.

Combinational

Logic Circuit

Storage

Element

outputinput


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Finite State Machines

Many systems meet the following five conditions:A finite number of states

A finite number of external inputs

A finite number of external outputsAn explicit specification of all allowed state transitions

An explicit specification of the rules for each external output value

In fact, as we will see, a microprocessor is aperfect candidate for description as a FSM.


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Finite State Machine Example - 1

Three groups of lights to be lit in a

sequence: group 1 on, groups 1 &

2 on, all groups on, all off.

The lights are on only if the main

switch is on. Four states: so we need two bits

to identify each state.

DETOUR

Combinational

Logic Circuit

Two bit

Storage

switch

clock

22

out1

out2

out3

all on grp 1,2 on

all off grp 1 on

1

1

0

0

0

1

0,1

01

10

11

00

d[1:0]

S


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When is group 1 on? in states 01, 10 and 11 - but only when the switch is on!

can you come up with a logic expression for d0and d1?

When do we switch to the next state?

the two bits of d[1:0] are updated at every clock cycle

we have to make sure that the new state does not propagate to the

combinational circuit input until the next clock cycle.

1 0 1 0. 1 0 1

2 0. 1 0 1

3 0 1

out (d .d d d d .d ).S

out (d d d .d ).S

out (d .d ).S


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The LC-3

as a

FiniteState

Machine


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Data Path ofthe LC-3

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