EE1411
© Digital Integrated Circuits2nd Timing Issues
Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective
Timing IssuesTiming Issues
Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolić
January 2003
EE1412
© Digital Integrated Circuits2nd Timing Issues
Synchronous TimingSynchronous Timing
CombinationalLogic
R1 R2Cin Cout Out
In
CLK
EE1413
© Digital Integrated Circuits2nd Timing Issues
Timing Timing DefinitionsDefinitions
EE1414
© Digital Integrated Circuits2nd Timing Issues
Latch ParametersLatch Parameters
D
Clk
Q
D
Q
Clk
tc-q
thold
PWmtsu
td-q
Delays can be different for rising and falling data transitions
T
EE1415
© Digital Integrated Circuits2nd Timing Issues
Register ParametersRegister Parameters
D
Clk
Q
D
Q
Clk
tc-q
thold
T
tsu
Delays can be different for rising and falling data transitions
EE1416
© Digital Integrated Circuits2nd Timing Issues
Clock UncertaintiesClock Uncertainties
2
4
3
Power Supply
Interconnect
5 Temperature
6 Capacitive Load
7 Coupling to Adjacent Lines
1 Clock Generation
Devices
Sources of clock uncertainty
EE1417
© Digital Integrated Circuits2nd Timing Issues
Clock NonidealitiesClock Nonidealities
Clock skew Spatial variation in temporally equivalent clock
edges; deterministic + random, tSK
Clock jitter Temporal variations in consecutive edges of the
clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS
Long term tJL
Variation of the pulse width Important for level sensitive clocking
EE1418
© Digital Integrated Circuits2nd Timing Issues
Clock Skew and JitterClock Skew and Jitter
Both skew and jitter affect the effective cycle time Only skew affects the race margin
Clk
Clk
tSK
tJS
EE1419
© Digital Integrated Circuits2nd Timing Issues
Clock SkewClock Skew
# of registers
Clk delayInsertion delay
Max Clk skew
Earliest occurrenceof Clk edgeNominal – /2
Latest occurrenceof Clk edge
Nominal + /2
EE14110
© Digital Integrated Circuits2nd Timing Issues
Positive and Negative SkewPositive and Negative Skew
R1In
(a) Positive skew
CombinationalLogicD Q
tCLK1CLK
delay
tCLK2
R2
D Q CombinationalLogic
tCLK3
R3• • •D Q
delay
R1In
(b) Negative skew
CombinationalLogicD Q
tCLK1
delay
tCLK2
R2
D Q CombinationalLogic
tCLK3
R3• • •D Q
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© Digital Integrated Circuits2nd Timing Issues
Positive SkewPositive Skew
CLK1
CLK2
TCLK
TCLK
th
2
1
4
Launching edge arrives before the receiving edge
EE14112
© Digital Integrated Circuits2nd Timing Issues
Negative SkewNegative Skew
CLK1
CLK2
TCLK
TCLK +
2
1
4
3
Receiving edge arrives before the launching edge
EE14113
© Digital Integrated Circuits2nd Timing Issues
Timing ConstraintsTiming Constraints
R1
D QCombinational
LogicIn
CLK tCLK1
R2
D Q
tCLK2
tc qtc q, cdtsu, thold
tlogict
Minimum cycle time:T - = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )
EE14114
© Digital Integrated Circuits2nd Timing Issues
Timing ConstraintsTiming ConstraintsR1
D QCombinational
LogicIn
CLK tCLK1
R2
D Q
tCLK2
tc qtc q, cdtsu, thold
tlogict
Hold time constraint:t(c-q, cd) + t(logic, cd) > thold +
Worst case is when receiving edge arrives lateRace between data and clock
EE14115
© Digital Integrated Circuits2nd Timing Issues
Impact of JitterImpact of Jitter
CLK
-tji tter
TC LK
t j itter
CLK
InCombinat ional
Logic
tc-q , tc-q, cdt log ict log ic, cdtsu, thold
REGS
tjitter
EE14116
© Digital Integrated Circuits2nd Timing Issues
Longest Logic Path in Longest Logic Path in Edge-Triggered SystemsEdge-Triggered Systems
Clk
T
TSU
TClk-QTLM
Latest point of launching
Earliest arrivalof next cycle
TJI +
EE14117
© Digital Integrated Circuits2nd Timing Issues
Clock Constraints in Clock Constraints in Edge-Triggered SystemsEdge-Triggered Systems
If launching edge is late and receiving edge is early, the data will not be too late if:
Minimum cycle time is determined by the maximum delays through the logic
Tc-q + TLM + TSU < T – TJI,1 – TJI,2 -
Tc-q + TLM + TSU + + 2 TJI < TSkew can be either positive or negative
EE14118
© Digital Integrated Circuits2nd Timing Issues
Shortest PathShortest Path
ClkTClk-Q TLm
Earliest point of launching
Data must not arrivebefore this time
ClkTH
Nominalclock edge
EE14119
© Digital Integrated Circuits2nd Timing Issues
Clock Constraints Clock Constraints in Edge-Triggered Systemsin Edge-Triggered Systems
Minimum logic delay
If launching edge is early and receiving edge is late:
Tc-q + TLM – TJI,1 < TH + TJI,2 +
Tc-q + TLM < TH + 2TJI+
EE14120
© Digital Integrated Circuits2nd Timing Issues
How to counter Clock Skew?How to counter Clock Skew?
RE
G
RE
G
R
EG
.
RE
G
log Out
In
Clock Distribution
Positive Skew
Negative Skew
Data and Clock Routing
EE14121
© Digital Integrated Circuits2nd Timing Issues
Flip-Flop – Based TimingFlip-Flop – Based Timing
Flip-flop
Logic
Flip-flop delay
Skew
Logic delay
TSU
TClk-Q
Representation after M. Horowitz, VLSI Circuits 1996.
EE14122
© Digital Integrated Circuits2nd Timing Issues
Flip-Flops and Dynamic LogicFlip-Flops and Dynamic Logic
Logic delay
TSU
TClk-Q
Logic delay
TSU
TClk-Q
PrechargeEvaluateEvaluatePrecharge
Flip-flops are used only with static logic
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© Digital Integrated Circuits2nd Timing Issues
Latch timingLatch timing
D
Clk
Q
tD-Q
tClk-Q
When data arrives to transparent latch
When data arrives to closed latch
Data has to be ‘re-launched’
Latch is a ‘soft’ barrier
EE14124
© Digital Integrated Circuits2nd Timing Issues
Single-Phase Clock with LatchesSingle-Phase Clock with Latches
Latch
Logic
Clk
P
PW
Tskl Tskl TsktTskt
EE14125
© Digital Integrated Circuits2nd Timing Issues
Latch-Based DesignLatch-Based Design
L1Latch
Logic
Logic
L2Latch
L1 latch is transparentwhen = 0
L2 latch is transparent when = 1
EE14126
© Digital Integrated Circuits2nd Timing Issues
Slack-borrowingSlack-borrowing
QDIn CLB_A QD QD
CLK1
L1 L2 L1
CLK2 CLK1
CLB_Btpd,A tpd,B
CLK1
CLK2
TCLK
a b c d e
tpd,A
a valid b val id
tDQtpd,B
c valid d valid
tDQ
e valid
slack passed to next stage
EE14127
© Digital Integrated Circuits2nd Timing Issues
Latch-Based TimingLatch-Based Timing
L1Latch
Logic
Logic
L2Latch
L1 latch
L2 latch
Skew
Can tolerate skew!
Longpath
Shortpath
Static logic
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© Digital Integrated Circuits2nd Timing Issues
Clock DistributionClock Distribution
CLK
Clock is distributed in a tree-like fashion
H-tree
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© Digital Integrated Circuits2nd Timing Issues
More realistic H-treeMore realistic H-tree
[Restle98]
EE14130
© Digital Integrated Circuits2nd Timing Issues
The Grid SystemThe Grid System
D r iv e r
D r iv e r
Dri
ver
Driv
er
G C L K G C L K
G C L K
G C L K
•No rc-matching•Large power
EE14131
© Digital Integrated Circuits2nd Timing Issues
Example: DEC Alpha 21164Example: DEC Alpha 21164Clock Frequency: 300 MHz - 9.3 Million Transistors
Total Clock Load: 3.75 nF
Power in Clock Distribution network : 20 W (out of 50)
Uses Two Level Clock Distribution:
• Single 6-stage driver at center of chip
• Secondary buffers drive left and right sideclock grid in Metal3 and Metal4
Total driver size: 58 cm!
EE14132
© Digital Integrated Circuits2nd Timing Issues
21164 Clocking21164 Clocking 2 phase single wire clock,
distributed globally 2 distributed driver channels
Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver width
Local inverters for latching Conditional clocks in caches to
reduce power More complex race checking Device variation
trise = 0.35ns tskew = 150ps
tcycle= 3.3ns
Clock waveform
Location of clockdriver on die
pre-driver
final drivers
EE14133
© Digital Integrated Circuits2nd Timing Issues
Clock Drivers
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© Digital Integrated Circuits2nd Timing Issues
Clock Skew in Alpha ProcessorClock Skew in Alpha Processor
EE14135
© Digital Integrated Circuits2nd Timing Issues
2 Phase, with multiple conditional buffered clocks 2.8 nF clock load 40 cm final driver width
Local clocks can be gated “off” to save power
Reduced load/skew Reduced thermal issues Multiple clocks complicate race
checking
trise = 0.35ns tskew = 50ps
tcycle= 1.67ns
EV6 (Alpha 21264) ClockingEV6 (Alpha 21264) Clocking600 MHz – 0.35 micron CMOS600 MHz – 0.35 micron CMOS
Global clock waveform
PLL
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© Digital Integrated Circuits2nd Timing Issues
21264 Clocking21264 Clocking
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© Digital Integrated Circuits2nd Timing Issues
EV6 Clock ResultsEV6 Clock Results
GCLK Skew(at Vdd/2 Crossings)
ps5101520253035404550
ps300305310315320325330335340345
GCLK Rise Times(20% to 80% Extrapolated to 0% to 100%)
EE14138
© Digital Integrated Circuits2nd Timing Issues
EV7 Clock HierarchyEV7 Clock Hierarchy
GCLK(CPU Core)L2
L_C
LK(L
2 C
ache
)
L2R
_CLK
(L2
Cac
he)
NCLK(Mem Ctrl)
DLL
PLL
SYSCLK
DLL
DLL
+ widely dispersed drivers
+ DLLs compensate static and low-frequency variation
+ divides design and verification effort
- DLL design and verification is added work
+ tailored clocks
Active Skew Management and Multiple Clock Domains
EE14139
© Digital Integrated Circuits2nd Timing Issues
Self-timed and Asynchronous Self-timed and Asynchronous DesignDesign
Functions of clock in synchronous design
1) Acts as completion signal
2) Ensures the correct ordering of events
Truly asynchronous design
2) Ordering of events is implicit in logic
1) Completion is ensured by careful timing analysis
Self-timed design
1) Completion ensured by completion signal2) Ordering imposed by handshaking protocol
EE14140
© Digital Integrated Circuits2nd Timing Issues
Synchronous Pipelined DatapathSynchronous Pipelined Datapath
In
tpd,reg tpd1
D
R1
Q
CLK
LogicBlock #1
tpd2
D
R2
QLogic
Block #2
tpd3
D
R3
Q D
R4
Q
EE14141
© Digital Integrated Circuits2nd Timing Issues
Self-Timed Pipelined DatapathSelf-Timed Pipelined Datapath
R2 OutF2In
tpF2
Start Done
R1 F1
tpF1
Start Done
R3 F3
tpF3
Start Done
Req Req Req Req
Ack Ack Ack ACKHS HS HS
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© Digital Integrated Circuits2nd Timing Issues
Completion Signal GenerationCompletion Signal Generation
LOGIC
NETWORK
DELAY MODULE
In Out
Start Done
Using Delay Element (e.g. in memories)
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© Digital Integrated Circuits2nd Timing Issues
Completion Signal GenerationCompletion Signal Generation
Using Redundant Signal Encoding
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© Digital Integrated Circuits2nd Timing Issues
Completion Signal in DCVSLCompletion Signal in DCVSL
PDN
B0
PDN
In1In1In2In2
B1
Start
Start
VDD VDD
DoneB0
B1
EE14145
© Digital Integrated Circuits2nd Timing Issues
Self-Timed AdderSelf-Timed Adder
P0
C0
P1
G0
P2
G1
P3
G2 G3
VDD
Start
Start
P0
C0
P1
K0
P2
K1
P3
K2 K3
VDD
Start
Start
C0 C1 C2 C3 C4 C4
C4C0 C1 C2 C3 C4
VDD
Start
C4
C3
C2
C1
C4
C3
C2
C1
Start Done
(a) Differential carry generation
(b) Completion signal
EE14146
© Digital Integrated Circuits2nd Timing Issues
Completion Signal Using Current SensingCompletion Signal Using Current Sensing
Min Delay Generator
StartGNDsense
VDD
Inputs
Current Sensor
Static CMOS Logic
Inpu
t R
egis
ter
Done
Output
A
B
tdelay
toverlap
tpd-NOR
tMDG
Start
A
B
Done
Output valid
EE14147
© Digital Integrated Circuits2nd Timing Issues
Hand-Shaking ProtocolHand-Shaking Protocol
11
3RECEIVERSENDER
ReqReq
Ack
Data
Ack
Data
(a) Sender-receiver configuration
(b) Timing diagram
cycle 1 cycle 2
Sender’s actionReceiver’s action
Two Phase Handshake
EE14148
© Digital Integrated Circuits2nd Timing Issues
Event Logic – The Muller-C ElementEvent Logic – The Muller-C ElementA B Fn1
0
0
1
1
0
1
0
(b) Truth table(a) Schematic
1
0
Fn
Fn
1
F
A
B
S
FF
R
QA
B
(a) Logic
(b) Majority Function
(c) Dynamic
A B
B
B
A
VDD
B
FA
B
VDDVDD
EE14149
© Digital Integrated Circuits2nd Timing Issues
2-Phase Handshake Protocol2-Phase Handshake Protocol
Advantage : FAST - minimal # of signaling events (important for global interconnect)
Disadvantage : edge - sensitive, has state
Senderlogic
Receiverlogic
Data
Handshake logic
Data ready Data accepted
CReq
Ack
EE14150
© Digital Integrated Circuits2nd Timing Issues
Example: Self-timed FIFOExample: Self-timed FIFO
All 1s or 0s -> pipeline empty
Alternating 1s and 0s -> pipeline full
C C
R1In Out
En
Acki
Reqi
R2 R3
CReq0
Acko
Done
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© Digital Integrated Circuits2nd Timing Issues
2-Phase Protocol2-Phase Protocol
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© Digital Integrated Circuits2nd Timing Issues
ExampleExample
From [Horowitz]
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© Digital Integrated Circuits2nd Timing Issues
ExampleExample
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© Digital Integrated Circuits2nd Timing Issues
ExampleExample
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© Digital Integrated Circuits2nd Timing Issues
ExampleExample
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© Digital Integrated Circuits2nd Timing Issues
4-Phase Handshake Protocol4-Phase Handshake Protocol
Slower, but unambiguous
Also known as RTZ
1 1
2
3 5
4Req
Ack
Data
Cycle 1 Cycle 2
Sender’s action
Receiver’s action
EE14157
© Digital Integrated Circuits2nd Timing Issues
4-Phase Handshake Protocol4-Phase Handshake ProtocolImplementation using Muller-C elements
Handshake logic
Data ready Data accepted
ReqS
Ack
C C
Senderlogic
Receiverlogic
Data
EE14158
© Digital Integrated Circuits2nd Timing Issues
Self-Resetting LogicSelf-Resetting Logic
PrechargedLogic Block(L1)
PrechargedLogic Block(L2)
PrechargedLogic Block(L3)
completiondetection
(L1)
completiondetection
(L2)
completiondetection
(L3)
VDD
A B C
intout
Post-chargelogic
EE14159
© Digital Integrated Circuits2nd Timing Issues
Clock-Delayed DominoClock-Delayed Domino
PulldownNetwork
CLK1
GND
CLK2 (to next stage)
Q1 (also D2)
D1
VDD
EE14160
© Digital Integrated Circuits2nd Timing Issues
Asynchronous-Synchronous InterfaceAsynchronous-Synchronous Interface
Asynchronoussystem
Synchronous system
Synchronization
fCLK
fin
EE14161
© Digital Integrated Circuits2nd Timing Issues
Synchronizers and ArbitersSynchronizers and Arbiters
Arbiter: Circuit to decide which of 2 events occurred first
Synchronizer: Arbiter with clock as one of the inputs
Problem: Circuit HAS to make a decision in limited time - which decision is not important
Caveat: It is impossible to ensure correct operation
But, we can decrease the error probability at the expense of delay
EE14162
© Digital Integrated Circuits2nd Timing Issues
A Simple Synchronizer A Simple Synchronizer
• Data sampled on rising edge of the clock
• Latch will eventually resolve the signal value,but ... this might take infinite time!
CLK
int
I2
I1D Q
CLK
EE14163
© Digital Integrated Circuits2nd Timing Issues
Synchronizer: Output Trajectories Synchronizer: Output Trajectories
Single-pole model for a flip-flop
2.0
1.0
0.00 100 200 300
Vou
t
time [ps]
EE14164
© Digital Integrated Circuits2nd Timing Issues
Mean Time to FailureMean Time to Failure
EE14165
© Digital Integrated Circuits2nd Timing Issues
ExampleExampleTf = 10 nsec = T
Tsignal = 50 nsec
tr = 1 nsec
t = 310 psecVIH - VIL = 1 V (VDD = 5 V)
N(T) = 3.9 10-9 errors/secMTF (T) = 2.6 108 sec = 8.3 yearsMTF (0) = 2.5 sec
EE14166
© Digital Integrated Circuits2nd Timing Issues
Influence of NoiseInfluence of Noise
Initial Distribution
p(v)
0 VIL VIH
T
Uniform distributionaround VM
Still Uniform
logarithmic reduction
Low amplitude noise does not influence synchronization behavior
EE14167
© Digital Integrated Circuits2nd Timing Issues
Typical SynchronizersTypical Synchronizers
1
2
Q
Q
1
2
Using delay line
2 phase clocking circuit
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© Digital Integrated Circuits2nd Timing Issues
Cascaded Synchronizers Reduce MTFCascaded Synchronizers Reduce MTF
Sync Sync SyncIn O1 O2 Out
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© Digital Integrated Circuits2nd Timing Issues
ArbitersArbiters
Req1
Req2
Req1
Req2
Ack1
Ack2Arbiter
Ack1
Ack2
(a) Schematic symbol
(b) Implementation
A
B
Req1
Req2
A
B
Ack1 t
(c) Timing diagramVT gap
metastable
EE14170
© Digital Integrated Circuits2nd Timing Issues
PLL-Based SynchronizationPLL-Based Synchronization
DigitalSystem
Divider
CrystalOscillator
PLL
Chip 1
DigitalSystem
PLL
Chip 2
fsystem = N x fcrystal
fcrystal 200<Mhz
Data
ClockBuffer
referenceclock
EE14171
© Digital Integrated Circuits2nd Timing Issues
PLL Block DiagramPLL Block Diagram
Phasedetector
Chargepump
Divide byN
Loopfilter
VCO
Referenceclock
Localclock
SystemClock
Up
Down
v
EE14172
© Digital Integrated Circuits2nd Timing Issues
Phase DetectorPhase Detector
ref
localclock
localclock
Output
Output
ref
VDD
-180 -90 90 180 phase error (deg)
Output (Low pass filtered)(a)
(c)
(b)
Output before filtering
Transfercharacteristic
EE14173
© Digital Integrated Circuits2nd Timing Issues
Phase-Frequency DetectorPhase-Frequency Detector
(c) Timing waveforms
(a) schematic (b) state transition diagram
A
B
UP
DN
A
B
UP
DN
D Q
D Q
A
B
Rst
Rst
UP
DN
UP = 0DN = 1
UP = 0DN = 0
UP = 1DN = 0
B
B A
A
A B
EE14174
© Digital Integrated Circuits2nd Timing Issues
PFD Response to FrequencyPFD Response to Frequency
A
B
UP
DN
EE14175
© Digital Integrated Circuits2nd Timing Issues
PFD Phase Transfer CharacteristicPFD Phase Transfer Characteristic
VDD
phase error (deg)
Average (UP-DN)
2
2
EE14176
© Digital Integrated Circuits2nd Timing Issues
Charge PumpCharge Pump
VDD
UP
DN
To VCO Control Input
EE14177
© Digital Integrated Circuits2nd Timing Issues
PLL SimulationPLL Simulation
00.0
0.2
0.4
0.6
0.8
1.0
1 2 3 4 5
Con
trol
Vo
ltage
(V
)
Time ( s)
ref
div
vco
ref
div
vco
EE14178
© Digital Integrated Circuits2nd Timing Issues
Clock Generation using DLLsClock Generation using DLLs
PhaseDet
ChargePump
Filter
DL
PD CP VCO÷N
Delay-Locked Loop (Delay Line Based)
Phase-Locked Loop (VCO-Based)
U
D
U
D
fREF
fO
fO
fREF
Filter
EE14179
© Digital Integrated Circuits2nd Timing Issues
Delay Locked LoopDelay Locked Loop
Phasedetect
Chargepump
VCDLFREF
PH
U
DC
VCTRL
FO
REF
OUT
UP
DN
Delay
PH
VCTRL
(a)
EE14180
© Digital Integrated Circuits2nd Timing Issues
DLL-Based Clock DistributionDLL-Based Clock Distribution
VCDL
CP/LF
PhaseDetector
VCDL
CP/LF
PhaseDetector
DigitalCircuit
•••
DigitalCircuit
•••
GLOBAL CLK