Chapter1_v.1.3__2007

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MOS Scaling Rules, Small Geometry Effects & Latchup

EE4646 VLSI Technology 1

1.1 MOSFET SCALING - AN INTRODUCTION

The steady down scaling of CMOS device dimensions

has been the main stimulus to the growth of microelectronics

and the computer industry over the past two decades.

Figures1-1 and 1-2 show the increase in density trends for

memories (1K to 256M) and microprocessors (4bit to 32bit),

and the reduction in feature sizes, respectively, in the past

three decades.

Fig.1-1. Device density trends.

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Fig.1-2. Feature size trends.

The Semiconductor Industry Association (SIA, USA)

projected an accelerating shrinkage in the size of the

minimum resolvable IC feature (or node) in 1999. Figures 1-3

and 1-4 show the projection of the device density trends and

feature size trends for the future from year 2000 to 2015,

respectively.

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0.01

0.1

1

10

100

1000

1998 2001 2004 2007 2010 2013

Year

N u m b e r o f T r a n s i s t o r s P e r

C h i p ( G

)

Fig. 1-3. Projection of the device density trends for DRAMs

and Microprocessors.

0

40

80

120

160

200

1998 2001 2004 2007 2010 2013

Year

M

i n i m u m F

e a t u r e S i z e

( n m )

Fig.1-4. Projection of minimum feature size trend.

DRAM

Microprocessor

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CMOS devices with shorter channel lengths will use less

power. Lower power–supply and threshold voltages (VDD

and VT) and thinner gate oxides (Tox) will accompany the

shrinking channel lengths, as shown in Fig.1-5.

0.01

0.1

1

10

0.01 0.1 1

MOSFET Channel Length ( m)

P o w e r S u

p p l y a n d

T h r e s h o l d

V o l t a g e ( V )

1

10

100

1000

G a t e O x i d e T h i c k n e s s ( n m )

Vdd

Vt

tox

Fig.1-5. Reduction of the VDD, VT and Tox with the shrinking

channel lengths.

Scaling of CMOS devices to smaller sizes will lead to the

decrease of the delay time, and it will push the clock

frequency of microprocessors above 1GHz. Fig.1-6 shows

the delay time and clock frequency vs. minimum features for

Cu/SiO2 technology.

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400

800

1200

1600

2000

2400

50100150200250

Minimum feature size (nm)

C l o c k f r e q u e n c y ( M H z )

0

200

400

600

800

1000

1200

D e l a y t i m e ( p s

)

Clock frequency (logicdepth=12 gates)Delay time of 12 logicstages

Fig.1-6. Delay time and clock frequency vs. minimum

features for the Cu/SiO2 technology.

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1.2 SMALL-DIMENSION MOS TRANSISTORS

1.2.1 Miniaturization and Circuit Speed

The purpose of micro-miniaturization is to increase the

packing device density and to improve the circuit

performance such as circuit speed.

It is obvious that as device dimensions are reduced we

can put more transistors on a chip with the same chip area. It

is, however, not obvious what it will do to the circuit speed.

In a MOS circuit, the output current of the MOSFET is

used to discharge its load capacitance, as shown in Fig.1-7.

The discharge time affects the circuit speed.

Fig.1-7. Load capacitor discharged by output current in an

MOSFET circuit.

R1

VDD

VDD

0 C ∆V = VDD

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∆V = voltage of the capacitor,

∆t = the discharge time,

charge to be discharged ∆Q = C∆V.

Neglecting the current through R1, the discharge current

≈ ID (the drain current). Therefore

t I V C Q D∆≈∆=∆ (1-1)

or D I V C t ∆≈∆ (1-2)

The delay time

D D I V C t ∆≈∆≈τ (1-3)

If the logic swing = VDD and output load (the capacitor) is an

identical transistor gate, employing2

2)(

0

T Gn

D V V I L

W C −=

and DDT G V V V ≈− , we have

2

2

0

DDn

D V I L

W C µ = (1-4)

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The load capacitance C is the gate capacitance of the

following stage. Therefore

WLC C 0= (1-5)

where the gate capacitance per unit areaox

ox

T C

ε =0 , Tox is the

thickness of the gate oxide, L is the channel length, W is the

gate width, and µ n is the electron mobility.

From the above equations, we have

DDn D V

Lµ τ

22≈ (1-6)

Hence, the delay time will be reduced if the channel length is

scaled down, and thus the circuit speed will increase.

In addition, the down scaling of CMOS device

dimensions also improves other circuit performance (such as

reduction of supply voltage and power consumption).

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1.2.2 Experimental Short-Channel Characteristics

When the dimensions of an MOSFET are reduced, 3

distinct features are seen in the device’s characteristics:

I. Drain Current, ID

The drain current is found to increase with the drain

voltage beyond pinchoff. The drain current is large at VG = 0

for large VD.

Fig.1-8 (long channel) shows the I-V characteristics for a

device with identical parameters as the device for Fig.1-9

(short channel), except that channel length is reduced to

0.23µm.

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Fig.1-8. I-V characteristics of a MOSFET with 0.73µ m channel

length.

Fig.1-9. I-V characteristics of a MOSFET with 0.23µ m channel length.

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II. Transistor Failed to Function as A Switch

Referring to Fig.1-10, the device with a 5µm channel

length L exhibits clearly the long-channel ideal transfercharacteristics. As L is reduced, the transfer curve shifts to

the left as a result of a drop of the threshold voltage. The

shape of the curve starts to change when L<1.5µm and ID

cannot be reduced to zero. When L = 0.8µm, the gate

voltage does not control the drain current. In other words, the

output current cannot be turned off and the transistor can no

longer function as a switch.

Fig.1-10. Transfer characteristics (ID vs. VG) for various

channel lengths L. VDS = 2V, VBS = 0V.

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III. Shift in Threshold Voltage

In long-channel MOSFETs, VT is not a function of the

channel length. However, as shown in Fig.1-11, VT

decreases with L with a sharp drop for L < 2µm (this can be

explained by examining the space charge in the depletion

layer).

Fig. 1-11. Experimental threshold voltage vs. channel length.

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1.2.3 Space Charge in the Depletion Layer

The depletion-layer width Xd and its associated space

charge QB in an MOSFET with a p-type substrate are givenby

2/1)(2

0

⎥⎦⎤

⎢⎣⎡=

+

A

s

qN

V

d X φ ε

(1-7)

[ ] 2/10 )(2 V N q N qX Q As Ad B +== φ ε (1-8)

Where φ 0 represents the built-in potential for a pn junction or

the surface band bending in the MOS transistor and V is the

reverse-bias voltage.

At the onset of current saturation (pinchoff), zeroinversion-layer charge is situated at the drain end (point y ) of

the channel at the drain voltage VDSAT (Fig.1-12a). If the drain

voltage is increased to VDSAT + ∆V, the depletion layer of the

substrate/drain pn junction is widened so the pinchoff location

is moved into the channel (point y’ ), as shown in Fig.1-12b.

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Fig.1-12. Channel-length modulation in an MOSFET.

y

n+ n+

S

G

D

VD = VDSAT

Depletion Region

L

p-Si

(a)

y’

n+ n+

S

GD

VD = VDSAT + ∆V

Depletion Region

L’

p-Si

∆L

b

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I. Drain Current

The drain current in the saturated region is given by

2)(2

2'2

)(

)(

0

0

T Gn

T Gn

D

V V

V V I

L L

W C

L

W C

−=

−=

∆−

µ

µ

(1-10)

As ∆L increases with the drain voltage, the drain current will

increase as the drain voltage increases (the drain current isnot saturated). This gives rise to the poor I-V

characteristics observed in Fig.1-9.

II. Subthreshold Current

The subthreshold current is caused by carrier diffusion from

the source to the drain. Consequently, it behaves like a

bipolar transistor, which is very sensitive to the base width,

i.e., the channel length in this case. The subthreshold current

is increased for a smaller L’, moving the I-V curve upward in

Fig.1-10 (a shift towards the left).

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As the channel length continues to decrease, the depletion

layer of the drain starts to interact with the source/channel

(the substrate) junction to lower the potential barrier of this junction – drain-induced barrier lowering (DIBL).

• The lowering of the source junction barrier allows

electrons to be injected into the channel regardless of the

gate voltage.

• As a result, the gate voltage loses control of the drain

current in the subthreshold regime.

• Note that the DIBL is initiated before the punch-through is

reached.

• The punch-through condition is defined when the source

and the drain depletion layers meet.

• A heavily doped channel by ion implantation can reduce

this short-channel effect.

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• The large subthreshold current is really a leakage current

preventing the turning off of the transistor. The

magnitude of subthreshold current determines the

standby power dissipation, which is important in low

power battery operation, the switching speed, and the

refresh time for dynamic memories and circuits.

1.2.4 Geometry Effect on Threshold Voltage

The threshold voltage can be expressed as

0C Qsi B

FBT V V +Φ+= (1-11)

Where VFB is the flat-band voltage, Φ si is the strong-inversion

silicon band-bending at the surface. QB is the bulk charge

(space charge) under the gate (per unit gate area), and C0 is

the gate capacitance (per unit area).

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I. Short-Channel Effect

The total charge contributing to the threshold voltage

under the gate is QBWL. However, if we assume part of

this charge is shared by the source and the drain such that

the area inside the trapezoid is controlled by the gate (as

shown in Fig.1-13), the total effective bulk charge becomes

LW QW X qN LW Q Bdm A B L L L L L )('

2'

2' ++ == (1-12)

where QB’ is the effective bulk charge per unit area, Xdm is

the depth of the depletion region under the gate, and

QB=qN AXdm.

Fig.1-13 Charge sharing with source and drain (Yau’s

model).

Xdm

L

r 2

L’

r n+n+

p-Si

SG

D

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It is obvious that

B B QQ L

L L

2

'

'

+

= (1-13)

and thus QB’ < QB because L’ < L.

If we assume the Xdm is equal to the width of the depletion

layers of the pn junctions (source/substrate and

drain/substrate), r 2 as defined in Fig.1-13 may be expressed

as

dm j X r r +=2 (1-14)

Therefore

])11(21[

))([2

)(2'

2

22

222

L

r

r

X j

j

dm

jdmdm j

jdm

L

r X X r L

r X r L L

−+−=

−−+−=

−−−=

(1-15)

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Thus QB’ can be expressed as

B j

j

dm

B B

Q

QQ

L

r

r X

L L L

])11(1[

'

2

2'

−+−=

= +

(1-16)

This allows the threshold voltage for a short-channel device to

be expressed as

])11(1[

'

2

0

0

L

r

r

X

C

Q

C Q

j

j

dm BsiFB

BsiFBT

V

V V

−+−+Φ+=

+Φ+= (1-17)

It is evident from the above equation that the threshold

voltage will decrease as the channel length decreases if the L is comparable to the junction depth r j of the source and drain

junctions. This explains the experimental threshold-voltage

variation as a function of channel length shown in Fig.1-11.

In general:

• Threshold-voltage variation is smaller for longer devices

(larger L) with a shallower junction (smaller r j).

• Reducing the QB/C0 term can minimize the short-channel

effect.

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II. Narrow-Channel Effects

MOS transistors that have channel widths W on the same

order of magnitude as the maximum depletion region

thickness Xdm at the silicon surface are defined as narrow-

channel devices. For typical doping profiles, widths of 4µm

or less can be considered narrow.

The narrow-width effect is the increase in the threshold

voltage as the channel width is reduced.

The increase of the threshold voltage is due to the extra

gate-induced space charge in the fringing fields, as shown in

Fig.1-14.

Fig.1-14 MOS width crosses section showing actual and

ideal depletion shapes.

Xdm

SiO2

W PolySi

Si

Ideal Depletion Boundary Actual Depletion Boundary

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The amount of this extra depletion charge (two sides) can

be expressed as

L X qN Q dm A

2δ =∆ (1-18)

where δ is a fitting parameter to account for the shape of the

transition region. This extra charge contributes an additional

voltage to the threshold voltage of

W C

X qN

WLC

L X qN

WLC

Q dm Adm AT V

0

2

0

2

0

δ δ ===∆ ∆ (1-19)

Therefore, for a narrow-width MOSFET, its threshold voltage

is

T T T V V V chananelwidechannelnarrow ∆+= −− )()( 0 (1-20)

As ∆VT increases with the reduction of channel width W, the

threshold voltage of a narrow-channel device will increase as

the channel width is reduced, as shown in Fig.1-15.

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Fig.1-15 Threshold voltage variation versus channel width W.

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1.2.5 Hot Carrier Effect

The large electric fields resulting from shrinking device

dimensions, while not scaling supply voltages, cause hot

carriers.

In the reverse-bias drain-to-substrate junction, the

electric field may be quite high in short-channel devices.

Carriers that are injected into the depletion region are

accelerated by high field, and some of them may gain enough

energy to cause impact ionization. These carriers have

higher energy than the thermal energy and are called hot

carriers.

Carriers can be considered to be hot when their kinetic

energy is in excess off the Si-SiO2 barrier of height 2.7 eV,

allowing some of the carriers to surmount the barrier (hot

carrier injection).

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Fig.1-16 Hot-carrier generation and current components.

Holes reaching the source. Electron injection from

the source. Substrate hole current. Electroninjection into the oxide.

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Mechanisms

Holes generated by multiplication can flow to the

substrate, giving rise to a large Substrate current.

Some of the holes may find their way to the source,

effectively lowering the source barrier to induce electron

injection.

The drain-channel-source structure now acts as an npn

transistor with a floating base and with its collector under

avalanche multiplication. Thus, the injected electrons from

the source will reach the drain depletion region, leading to

more carrier multiplication.

The electrons generated in the drain depletion region are

attracted to the positive gate, as shown in Fig.1-16. If these

electrons have an energy > 2.7 eV, they may be able to

surmount the Si-SiO2 barrier to inject into the gate oxide, and

some may tunnel through the oxide to produce a gate

current. The injected electrons may be trapped inside

the gate oxide, thus changing the threshold voltage and

the I-V characteristics.

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Substrate current

The behavior of the substrate current ISUB as a function of

gate voltage is shown in Fig.1-17.

ISUB initially increases for increasing the gate voltage VG

as a result of the increase of electrons entering the depletion

region. The electrons are induced by the gate voltage, and

they experience multiplication, giving rise to a large number of

holes which exit through the substrate.

Fig.1-17 Substrate current as a function of gate voltage.

ID

E

VG ≈ VD/2

VG

ISUB

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The lateral electric field along the channel is shown in

Fig.1-18.

Fig.1-18. Lateral electric field along the channel.

When VG is increased, the pinchoff point moves towards

the drain.

• Both the area of the drain depletion region near the Si-

SiO2 interface and the electric field in this region are

reduced.

• Thus the impact ionization (the generation of electron-

hole pairs) is reduced.

• As a result, the substrate current is reduced for a high

gate voltage.

Pinchoff

points

VG1

VG2

Constant VDS

VG1 < VG2 E

S D

Drain

depletion

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Influence of hot-carrier effects

• Electron trapping in the gate oxide gives rise to the

increase of threshold voltage.

• The drain current in the saturated region decreases

because (VG – VT) becomes smaller, as shown in Fig.1-

19. Note that the drain current2

2)(

0T G

n D V V I

L

W C −= .

• A large substrate current may induce latchup in CMOS

circuits.

Fig.1-19 Degradation of the drain current in the saturated

region after hot-carrier stressing.

ID

Before Stress

After Stress

VD

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1.2.6 Drain Engineering

It has been determined that hot-carrier effects will causeunacceptable performance degradation in NMOS devices

built with conventional drain structures if their channel lengths

are less than 2 µm.

Appropriate drain engineering techniques, which results

in special drain structures that reduced hot carrier effects (i.e.,

double-diffused drains and lightly-doped drains), have been

implemented.

One of the most effective ways to minimize hot carrier

effects is to reduce the maximum electric field in the device.

The maximum electric field occurs near the

drain/substrate metallurgical junction.

This peak electric field can be reduced by grading the

drain implant concentration.

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Double diffused drain (DDD)

The earliest attempt at drain engineering used a process

module known as the double diffused drain.

In this technique both phosphorus (P) and arsenic ( As)

are implanted into the substrate to form the source and drain

diffusions. Fig.1-20 shows the fabrication process of the P-

As device structure.

Fig.1-20 Fabrication process of the P-As device structure.

Poly SiSiO2

P

N _

implantation

Poly SiSiO2

As

N+

implantation

N2annealing

Poly SiSiO2

N _

N+

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Since phosphorus is a faster diffuser than arsenic,

• near the channel edge the predominant profile is that of

the phosphorus;• the junction is not as sharp.

• the lower doping concentration near the drain edge

reduces the peak electric field.

It is possible in this way to reduce the peak field by >

20%. Even this modest reduction in field has a pronounced

effect on the hot carrier injection rate.

Problems of DDD structures:

• Increased junction depth ⇒ short channel behavior.

• Final doping profile is still determined by diffusion, hence

difficult to reliably produce the correct phosphorus profile.

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Fig.1-21 Process sequence used to form LDD structures.

SiO2

(b)

N- drain formed

Poly SiSiO2

N _

(c)

N+ implantation

Poly SiSiO2

N _

(a)

N

_

implantation

Poly SiSiO2

(d)

N+ drain formed

Poly Si

N _

N+

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Disadvantages of LDD:

• Process complexity;

• Increase in series resistance ⇒ available ID is reduced.

To maintain ID, a higher VDD is required.

Higher voltage leads to higher power dissipation.

Power-delay tradeoff must therefore be considered as

well as the heat generation.

The LDD structure is a popular structure, and it has been

widely used in NMOS and CMOS circuits.

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• Supply voltage

VDD’ = VDD / k (1-25)

• Threshold voltage

k

V

k T

T V

T

simsSBsi Aseff ox

ox

simsSBsi Aseff ox

oxT

k V kN qQ

V qN Q

≈

Φ+Φ++Φ+−=

Φ+Φ++Φ+−=

)(})]/()[(2{

)()}'('2{'

)/(

'

ε ε

ε ε

(1-26)

if (Φ ms + Φ si) is small.

Where Qeff is the net oxide charge, ε ox the dielectric

constant of the oxide, ε s the dielectric constant of silicon,

Φ ms

the work function difference, Φ si

the strong-inversion

silicon band-bending at the surface, and VSB the

substrate bias.

• Gate capacitance

k C

k T k L

k W

T LW ox

ox

ox

ox

oxoxC === )/('

''' ε ε (1-27)

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• Drain current in saturation region

k I

k V k V

V V I

D

T Goxn

T G

oxn

D

k L

k C

L

C

/

)]/()/[(

)''('

2

)/(2

)/(

2

'2

'

2

2

=

−=

−=µ

µ

(1-28)

If the logic swing = supply voltage VDD’ and VG’ – VT’ ≈

VDD’, then the maximum saturated drain current

k I k V V I Dsat DDoxn

DDoxn

Dsat k L

k C

L

C /)/(''

2

)/(2

)/(2

'2

'22

=== µ µ

(1-29)

• Power dissipation / gate

2/''' k PV I Pk

V

k

I DD Dsat DD Dsat === (1-30)

• Power dissipation density

D D PPWLP

k Lk W

k P

LW P ====

)/)(/(

)/(

'''

2

' (1-31)

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• On-resistance of MOSFET

ON D D D DON

Rk I k V I V R === )//()/('/'' (1-32)

• Gate delay time

k k C RC R oxON oxON /)/(''' τ τ === (1-33)

Benefits from scaling:

• Logic gate area reduced by k2 → higher device density;

• Delay time reduced by k → faster switching speed;

• Power dissipation reduced by k2 → lower power

consumption per device.

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Some effects of interconnection and contact scaling

• If the interconnect length (l), width (w) and thickness ( t )

are reduced by a factor of k, the interconnection line

resistance

L L kR Rk t k w

k l

t wl ===

)/)(/(

)/(

'''' ρ ρ (1-34)

• If the capacitance CL’ associated with the interconnection

is reduced by k, the RC time constant will remain

constant:

L L L L L L k C kRC R τ τ === )/(''' (1-35)

However, in some cases, the parasitic capacitance does

not scale or it can increase, and thus the RC time

constant will increase. This will reduce the switching

speed.

• If the area of contact windows is reduced by k2, then the

contact resistance

cc Rk R2

'= (1-36)

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• Contact voltage drop

cccc kV Rk R I V k I

=== ))(('''2

. (1-37)

This is undesirable since all other voltages are reduced

by k.

Therefore, scaling of the interconnects and contact

windows degrades performance and should be avoided.

Also, other device characteristics such as the sub-

threshold current and the built-in potential do not scale.

These problems have prompted other scaling laws to be

introduced to either enhance a particular device

characteristic, such as switching speed, or to achieve other

design goals.

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1.2.8 Velocity Saturation

The mobility dependence on the horizontal electric field

appears in the form of velocity saturation.

• As carriers are accelerated in an electric field, they gain

velocity and kinetic energy.

• The increase in energy increases the scattering

probability between the carriers and the lattice.

• Imparting of the carrier energy to the lattice generates

phonons which limit the carrier velocity at high electric

fields.

• Velocity saturation affects the performance of short-

channel devices by reducing gm in the saturation mode.

Carrier velocity as a function of electric field is shown in

Fig.1-22. At low electric fields, the velocity increases linearly

with the electric field. However, the velocity becomes

saturated at high fields above a critical value.

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The critical field Ec is defined as the intersecting point

between the linear and horizontal lines, as shown in Fig.1-22.

Thus the velocity v can be expressed as

⎩⎨⎧

>>

<<=

c

c

E E for v

E E for E v

max (1-38)

Fig.1-22 Carrier velocity becomes constant for fields above a

critical value.

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Current saturation is defined as the condition when the

charge in the inversion layer at y = L (see Fig.1-12a)

becomes zero. This corresponds to the pinchoff condition of

T G DS V V V −= (1-39)

which is satisfied at y = L. The average electric field inside

the channel is given by

L

V V T Gav E

−= (1-40)

Example

Assume VG = 5V & VT = 1V and L = 1 µ m, Eav = 4 × 104 V/cm

which is above the critical value (see Fig.1-22).

Under this condition, the drain current is limited by carrier

velocity so that

max0max )( 2 vV V WC vQW I

DS

T G D

V

−−== (1-41)

where Q is the average inversion charge (per unit gate area),

and C0 is the capacitance (per unit gate area).

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Differentiating the above equation, we obtain the

transconductance

max0vWC gG

Dm V

I == ∂∂

(1-42)

• Note: gm is independent of VG, VD and L;

• The velocity saturation tends to compress the ID as

shown in Fig.1-23.

• The ID is saturated not by pinchoff but by velocity

saturation leading to a constant gm.

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Fig.1-23 Theoretical comparison of drain current vs. drain

voltage for (a) a device with constant mobility (no

velocity saturation) and (b) a device exhibiting

velocity saturation.

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1.3 CMOS LATCH-UP

The major problem in CMOS circuits is device latch-up,an internal feedback mechanism that gives rise to temporary

or permanent loss of circuit function.

Latch-up is a strong function of circuit density, nMOS-to-

pMOS separation in particular. As CMOS feature size

continue to shrink, lateral and vertical dimensions are scaled,

resulting in better parasitic bipolar transistors. Consequently,

latch-up is a problem of increasing concern in VLSI.

A CMOS structure has inherent pnp and npn parasitic

bipolar transistors. For the n-well CMOS shown in Fig.1-24,

the p+, n-well and p-substrate form a parasitic vertical pnp

bipolar transistor, whereas the n+, p-substrate and n-well

produce a parasitic lateral npn device. The simplest lumped-

element equivalent circuit model is illustrated by the bold lines

shown in the figure.

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Fig.1-24 Schematic and equivalent circuit of parasitic bipolartransistors in a CMOS.

When the substrate current (Is) and the well current (Iw)

are sufficient to cause an ohmic drop of approximately 0.7V,

the base-emitter junctions for both transistors are sufficiently

forward-biased (VBE ≅ 0.7V) to provide significant current to

trigger a bipolar transistor action. Bipolar devices are

therefore in the active mode.

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Because the base of the pnp connects to the collector of

the npn and conversely, a feedback loop is formed by the two

bipolar transistors with the loop gain equal to the beta

product ( β pnp β npn). β pnp and β npn are the common-emitter

current gains for the pnp and npn transistors, respectively. If

the loop gain is less than one, Ib decays to zero as does I. To

have positive feedback, the loop gain must be greater than

one. This condition is necessary for latch-up to occur.

1.3.1 Basic Switching Operation

Consider the effect of well and substrate resistances.

The fact that the 0.7 V ohmic drop is produced is due to the

finite resistance associated with the well and the substrate;

they should be included in the circuit model, as shown in

Fig.1-25.

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Fig.1-25 Schematic and equivalent circuit of parasitic

resistors and bipolar transistors in a CMOS.

The npn collector current made of electrons (Ib β npn) does

not flow entirely into the pnp base because a part of it is

shunted to the n+ well contact through the well resistor (RW).

This current is denoted as IRW. The remaining current Ib β npn –

IRW, becomes the pnp base current. Thus, the pnp collector

current is (Ib β npn – IRW) β pnp.

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Similarly, a portion of the pnp collector current (denoted

as IRS) is shunted to the substrate contact through the

substrate resistance (RS). The feedback current flowing into

the npn base is now the pnp collector current offset by IRS, i.e.

(Ib β npn – IRW) β pnp – IRS. To cause positive feedback, this

current must be greater than the initial npn base current.

This condition can be written as

b RS pnp RW npnb I I I I >−− β β )( (1-43)

and rearranged as

pnp RW RS pnpnpnb I I I β β β +>− )1( (1-44)

Ib can be expressed in terms of total supply current Idd as

)1( ++= npnb RS dd I I I β (1-45)

which can be rearranged as

)1/()( +−= npn RS dd b I I I β (1-46)

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Thus the following condition for latch-up to occur can be

obtained

)(

))(1(1

RS dd

pnp RW RS npn

I I

I I

pnpnpn −++

+> β β

β β (1-47)

where IRS and IRW are approximately equal to Vben/RS and

Vbep/RW, respectively. Vben and Vbep are the base-emitter

voltages of the npn and the pnp transistors, respectively.They are approximately 0.7V.

The beta product ( npn pnp) must now be greater than

a value larger than one. This values increases as the

resistance (RS or RW) is decreased.

To make the latch-up requirement more difficult to meet,

one can

• increase IRS and / or IRW by lowering RW and / or RS;

• reduce β npn and / or β pnp (a lower loop gain).

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If a large reverse bias is applied across the n-well-to-p-

substrate junction, the avalanche condition sets in. A large

well/substrate current will produce latch-up.

Latch-up is often characterized by measuring the total

current through the pnpn path wile overstressing the anode

voltage. Typical I-V characteristics for avalanche induced

latch-up are shown in Fig.1-26.

Fig.1-26 Typical I-V characteristics for avalanche induced

latch-up.

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The switching (or critical) voltage Vs is the maximum

voltage below which the device is in a blocking or OFF state.

At Vs, both bipolar transistors become active and, if

sufficient loop gain is present, the pnpn regeneration

switches the device to a high-current, low-voltage state,

referred to as the ON or latched state.

The current at this switching point, Is, is also referred to

as the critical (or switching) current for entering a latched

state.

The voltage required to sustain this state, shown as VH in

the figure, is usually referred to as the holding voltage. This

voltage is the one at which the device enters into the low-

impedance state. The current at this voltage is called the

holding current (IH).

The current in the ON state can be very large, and itcould destroy the device.

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1.3.2 Causes of Latch-Up

Causes of latch-up:• Terminal overvoltage stress;

• ESD (electrostatic discharge) stress;

• Transient displacement currents (sudden transients in

power or ground);

• Radiation (x-rays, cosmic rays, or alpha particles) maygenerates enough electron-hole pairs in both the

substrate and well regions and thus trigger latch-up;

• Leakage currents in well junctions can cause large

enough lateral current.

Under normal CMOS operating conditions, the base-

emitter junctions for both bipolar transistors are reversed-

biased, which makes latch-up impossible.

A successful circuit design must, however, preclude

latch-up under any conditions that might be experienced by

the circuit.

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1.3.3 Latch-up Characterization

I. Steady state latch-up triggering

To trigger latch-up, one of the two parasitic transistors

must become active. In an n-well configuration, this

activation can be done by forward biasing an n+ -to-p-

substrate or a p+ -to-n-well junction .

Two methods can be used to forward bias the two pn

junctions:

• Raise the p+ voltage above VDD (triggering by p+

overvoltage)• Lower the n+ voltage below VSS (triggering by n+

overvoltage)

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Triggering by p+ overvoltage (Fig.1-27a). The p+

diffusion is ramped above VDD while the supply is held at

VDD, which is 5V.

The current forced into the p+ just before latch-up is

triggered is the trigger current, and the corresponding

supply current is defined as the critical current. The

voltage at the onset of triggering is defined as the trigger

voltage. Fig.1-27b shows the I-V characteristics measured

using a HP4145 parameter analyzer.

As the voltage at the p+ region (Vp) increases, both the

current flowing to the p+ region (Ip) and the supply current

(Is) increases until the currents are so large that latch-up is

induced, marked as the sharp rise in both currents. Ip and Is

just before this increase occurs are the trigger and critical

current, respectively. They can be expressed as

)/( s pnpbenTRIG p RV I I α ≅= (1-48)

sbenCRIT s RV I I /≅= (1-49)

where α pnp is the common base current gain for the vertical

pnp transistor.

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Fig.1-27 Latch-up triggering by p+ overvoltage: (a)

measurement technique; (b) I-V characteristics.

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Triggering by n+ overvoltage (Fig.1-28). The n+

diffusion is ramped below VSS while the VSS is grounded.

Again, the current forced into the n+ node (In) justbefore latch-up is triggered is the trigger current, and the

corresponding supply current (Id) is defined as the critical

current. In and Id can be expressed as

)/( W npnbepTRIGn RV I I α ≅= (1-50)

W bepCRIT d RV I I /≅= (1-51)

Fig.1-28 Latch-up triggering by n+ overvoltage, i.e.,

forward-bias n+ to p-substrate junction.

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II. Steady state latch-up holding

The supply current and voltage required to sustain latch-

up are defined as holding current and holding voltage.

To characterize them, a device is first triggered into the

latched state by a method such as overvoltage stress, then

the holding conditions are found by removing the triggering

stimulus and ramping the supply voltage down until the

device returns to the high impedance state.

Fig.1-29(a) and (b) show the schematic and I-V

characteristics in measuring holding conditions. Latch-up isfirst triggered by p+ overvoltage, and then VDD is ramped

down until the power supply current (ID) suddenly drops.

The voltage and current at this point are denoted as the

holding vol tage and holding current.

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Fig.1-29 (a) Holding measurement; (b) I-V characteristics

during holding condition.

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1.3.4 Latch-Up Prevention

Latch-up in CMOS can be prevented if β n β p < 1 at all time.

This is not always possible because of other device design

constraints. Practical methods to avoid latch-up follow two

approaches known as bipolar spoiling and bipolar

decoupling.

I. Bipolar spoiling

• By decreasing the injection efficiency or the transport

factor, e.g., through the reduction of carrier lifetime by gold

doping and neutron radiation.

However, gold doping or neutron irradiation introduces

leakage current and is difficult to control.

• Alternatively, Schottky-barrier source and drain contacts

are used to eliminate minority- carrier injection.

However, Schottky-barrier contacts increase the series

resistance of the MOS transistor and degrade the gm.

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II. Bipolar decoupling

Retrograde well. A retrograde well provides a

higher doping concentration at the bottom of the well, hence a

low well resistance (RW) can be obtained. The low RW offers

an effective path in shunting the well current, decreasing the

coupling of the two bipolar devices. Improvement is most

significant when latch-up is triggered by n+ overvoltage,

because both triggering and critical currents during n+

overvoltage stress are inversely proportional to RW.

Epitaxial substrate. The well and the substrate provide

two parasitic resistors (RW and RS), which sink a portion of the

transistor collector currents to the power supply rails (VSS and

VDD), thereby reducing positive feedback induced by bipolar

coupling. This decoupling of the bipolar devices becomes

more effective as RS and or RW are reduced. RS can be

decreased by using a lightly doped thin epitaxial layer on a

heavily doped substrate. Because the heavily-doped

substrate is farther away from the active channel region, this

method does not affect the MOSFET performance.

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III. Guard bands

The n+ and p+ diffusion used for the well or substrate

contact can be placed between the n- and p-channel

MOSFETs, as shown in Fig.1-30.

In this configuration, majority carriers are pre-collected by

the contact diffusions before they inject to a bipolar base or

cause an ohmic drop in the well or substrate. These

diffusions are referred to as guard bands, which are

commonly used in I/O circuits, where latch-up is more of a

problem.

Fig.1-30 CMOS inverter structure showing guard bands.

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Fig.1-31 shows the n+ guard band in an n-well. The n+

guard band serves the purpose of electron current steering in

the well.

Fig.1-31 Majority carrier guard (n+) in well to steer current away

from vertical pnp.

Similar effects appear for the p+ guard band in a p-

substrate (Fig.1-32). The p+ guard band steers the hole

current away from the n+ junction.

Fig.1-32 Majority carrier guard (p+) in substrate to steer

current away from lateral npn.

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IV. Dependence of latch-up on n+ -to- p+ separation

Fig.1-33 shows the trigger and critical currents versus n+

-to- p+ separation for both p+ and n+ overvoltage induced

triggering. For n+ overvoltage stress, the triggering

current increases rapidly as n+ -to- p+ separation is

enlarged. As n+ -to- p+ spacing is increased, αnpn

decreases, and thus ITRIG (≅ Vbep/(α npnRW)) is increased.

Fig.1-33 Latch-up critical and trigger currents versus n+

to p+ separation.

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A higher trigger or critical current means more difficult to

trigger latch-up. Therefore, a large n+ to p+ spacing can

prevent latch-up.

On the other hand, holding voltage also increases as n+

to p+ spacing increases, as shown in Fig.1-34.

If the holding voltage is larger than the supply voltage

VDD, latch-up cannot be maintained with the supply voltage,

and the circuit is latch-up immune. Therefore, a large n+

to p+ spacing can enhance the latch-up immunity.

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