Characterisation Of The NA62 GigaTracker End Of Column ...

Characterisation Of The NA62 GigaTracker End OfColumn Readout ASIC

M. Noy1,a G. Aglieri Rinellaa M. Fiorinia P. Jarrona J. Kaplona

A. Klugea E. Martinb M. Morela L. Perktolda

aCERN, CH-1211 Geneva 23, Switzerland

bUniversite Catholique de Louvain 1, Place de l’Universite BE-1348 Louvain-la-Neuve

TWEPP-10.20th-24th September 2010

Aachen.

[email protected]. Noy (PH-ESE-FE, CERN) NA62 GTK EOC TWEPP-10. 21.09.2010 1 / 25

1 GTK Architecture and Requirements

2 Demonstrator ASIC

3 Testing Ethos and Methodology

4 ResultsTDC PerformanceTest Pixel PerformanceElectrical Charge Injection: ASIC Full Chain

5 Synopsis

M. Noy (PH-ESE-FE, CERN) NA62 GTK EOC TWEPP-10. 21.09.2010 2 / 25

GTK Architecture and Requirements


2 Demonstrator ASIC



5 Synopsis



The GigaTracker



Beam Profile



Beam and Detector Profile



GigaTracker Requirements

Radiation Environment 1014n cm−2 yr−1

Columns/Readout Chip 40Pixels/Column 45

Pixel Size 300µm x 300µmBeam Rate 800MHz → 1GHz

Dynamic Range ∼ 1fC → 10fCQMP 2.4 fC

Front End Peaking Time ∼ 4nsTime Binning ∼ 97 ps

Momentum Resolution 0.4%Efficiency ≥ 99%


Demonstrator ASIC


2 Demonstrator ASIC



5 Synopsis


Demonstrator ASIC

EoC Design Overview

x1x20x40

Final ASIC :

Hit Register 0

Hit Register 1

Hit Register 2

Hit Register 8

DLL

Co

un

ters

Co

arse

High Precision

Ser

ialis

atio

nR

ead

ou

t

Hit Arbiter

45:9

Single Test Column: 45 Pixels

Clock: 320MHz

9x 320Mbit/s

Pixel 44 Pixel 43 Pixel 42 Pixel 0

Final ASIC: x 40

4 x 1.5Gbit/s

2 x 3 Gbit/s

On−Chip Transmission lines

Final ASIC :

Pixel Array End Of Column


Demonstrator ASIC

EoC DLL-Based TDC

PhaseDetector

Charge Pump

DLL Clock

Leading

Trailing

Delay Line

Hit

Reg

iste

rs

#HITHIT

Speed Control

0 1 2 29 30 31

Early

Late

320MHz clock, 32 starved delay cells → 97 ps time bin.


Demonstrator ASIC

Time Over Threshold Time Walk Correction

1T T2

T0

ThresholdV

Time Walk

Time Over Threshold

DiscriminatorOutput

Pre−AmpOutput

Peaking Time = 4 ns


Demonstrator ASIC

EoC: Chip Top Level Layout


Demonstrator ASIC

EoC: Chip Top Level Layout


Demonstrator ASIC

EoC Chip


Demonstrator ASIC

EoC Assembly


Testing Ethos and Methodology


2 Demonstrator ASIC



5 Synopsis



Mechanisms

Electrical20 fF Charge injection capacitor included in the pixelVoltage step induces charge injection at front end of 1 (or more)pixel(s)

Radioactive Source

Absolute gain calibration from pulse height spectra (analogue pixel)109Cd and 241Am γ emissions used

Laser Charge Injection

60 ps FWHM, 1060nm LaserLight pulse timing is good to ∼5 ps RMSspot size ∼10µm at focal distanceX-Y stage to scan laser spot across pixel matrix

Beam test

10GeV π+/p+ beam at PS (T9)4 cards placed in beam with GasTOFunderway now (16th → 29th September 2010)



Mechanisms


Radioactive SourceAbsolute gain calibration from pulse height spectra (analogue pixel)109Cd and 241Am γ emissions used

Laser Charge Injection

60 ps FWHM, 1060nm LaserLight pulse timing is good to ∼5 ps RMSspot size ∼10µm at focal distanceX-Y stage to scan laser spot across pixel matrix

Beam test




Mechanisms



Laser Charge Injection60 ps FWHM, 1060nm LaserLight pulse timing is good to ∼5 ps RMSspot size ∼10µm at focal distanceX-Y stage to scan laser spot across pixel matrix

Beam test




Mechanisms



Laser Charge Injection60 ps FWHM, 1060nm LaserLight pulse timing is good to ∼5 ps RMSspot size ∼10µm at focal distanceX-Y stage to scan laser spot across pixel matrix

Beam test10GeV π+/p+ beam at PS (T9)4 cards placed in beam with GasTOFunderway now (16th → 29th September 2010)



Testing Setup

EthernetSwitch

Chip CardChip

Pulse Generator

Lecroy

Oscilloscope

TEK

Ctrl/Config

Private TCP/IP Network

AFG3252

AlteraStratix III Dev Board

Clk320

Readout

SRS CG 635

CLK320

Synch.

SDA 13000

Linux PC



Testing Setup

Y

X

EthernetSwitch

Chip CardChip

Lecroy

Oscilloscope

Private TCP/IP Network

AlteraStratix III Dev Board

WaveRunner104MXi−A

USB/RS232

Keithley 2410

Source Meter

Readout

Ctrl/Config

HV Bias

& Controllers

Zaber X and Y Stages

Laser Driver

Laser

Pulse Generator

TEK AFG3252

AttenuatorOptical

Discriminated

Output

Fibre

USB

USB

Clk Gen Clk320

LinuxPC


Results


2 Demonstrator ASIC



5 Synopsis


TDC Performance

Results TDC Performance

EoC TDC Non-Linearity

Differential:

Time Bin Interval0 5 10 15 20 25 30

DN

L (

LS

Bs)

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

RMS DNL = 0.17

Differential Nonlinearity

Integral:

Time Bin0 5 10 15 20 25 30

INL

(L

SB

s)-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

RMS INL = 0.27

Integral Nonlinearity

DLL TDC Jitter = 7 ps


Test Pixel Performance

Results Test Pixel Performance

T1 RMS Jitter: Qin and Qth

Qin (fC)2 4 6 8 10

T1

RM

S J

itte

r (s

)

0

0.05

0.1

0.15

0.2

0.25

0.3-910×

T1 RMS Jitter vs Qin, Trise=2.5ns

Qth=0.5fCQth=0.6fC

Qth=0.7fCQth=0.8fCQth=0.9fC

T1 RMS Jitter vs Qin, Trise=2.5ns

Electrical charge injection.No detector∼ 40 ps RMS at 2.4 fCENC ∼ 130 e−

Estimated Charge (fC)0 2 4 6 8 10 12

T1

RM

S J

itte

r (s

)

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4-910×

RMS T1 vs Estimated Q

Qth = 0.6fCQth = 0.7fC

Qth = 0.8fCQth = 0.9fC

RMS T1 vs Estimated Q

Laser Charge Injection.Detector biased at 300V.∼ 70 ps RMS at 2.4 fCENC ∼ 180 e−



Analogue Pixel Pulse Height Spectrum with 241Am



T1 RMS Jitter: Operation Frequency

Frequency (kHz)0 20 40 60 80 100 120 140 160

T1

RM

S J

itte

r (s

)

20

30

40

50

60

70

80-1210×

T1 vs Fin

Qin=1.0fC

Qin=1.2fC

Qin=1.4fC

Qin=1.6fC

Qin=1.8fC

Qin=2.0fC

Qin=3.0fC

Qin=4.0fC

Qin=5.0fC

Qin=6.0fC

Qin=7.0fC

Qin=8.0fC

Qin=9.0fC

Qin=10.0fC

T1 vs Fin


Electrical Charge Injection: ASICFull Chain

Results Electrical Charge Injection: ASIC Full Chain

T0 Transfer Function

Pulse Generator Offset (ps)0 500 1000 1500 2000 2500 3000

TD

C T

ime

(ps)

23500

24000

24500

25000

25500

26000

26500

27000

TDC Time vs Pulse Generator Offset, Qinj=3fC



T0 and T1 as a function of Injected Charge

Q (fC)2 4 6 8 10

Tim

e (p

s)

24500

25000

25500

26000

26500

27000

27500Uncorrected

Corrected

Measured and Corrected times as a function of Q



RMS T0 Jitter Vs Q: Average Case

Q(fC)0 2 4 6 8 10

T0

RM

S J

itte

r (p

s)

0

20

40

60

80

100

120

140

Mean T0 RMS Jitter

Time walk compensated, full chain readout, all pixels firing.



Systematic (uncorrectable) Residual TimeWalk

T0_ResidualsEntries 4396Mean -0.001592RMS 14.45Underflow 0Overflow 0

T)δ<T0(Q)> - T0(Q, -200 -150 -100 -50 0 50 100 150 200 2500

20

40

60

80

100

120

140T0_Residuals

Entries 4396Mean -0.001592RMS 14.45Underflow 0Overflow 0

T0 Residuals


Synopsis


2 Demonstrator ASIC



5 Synopsis


Synopsis

Synopsis

The GigaTracker represents a very challenging project< 200 ps RMS time resolution> 800MHz beam rateHarsh radiation environment< 0.5%X0

Demonstrator ASIC and detector implemented

DLL Based TDC which gives 97 ps nominal time binning

monotonic behaviourRMS DNL ∼ 0.17LSBsRMS INL ∼ 0.27LSBs

Excellent Pixel Performance

Leading Edge Jitter ∼ 40 ps bare ASIC at 2.4 fCLeading Edge Jitter ∼ 70 ps Full depleted sensor with light injection at2.4 fC

Full chain and time walk correction

timewalk correction mechanism shown to work wellResidual systematic remainder < 15 ps RMSRMS T0 Jitter ∼ 70 ps at 2.4 fC (bare ASIC)


Synopsis

Synopsis


Demonstrator ASIC and detector implementedDLL Based TDC which gives 97 ps nominal time binning


Excellent Pixel Performance

Leading Edge Jitter ∼ 40 ps bare ASIC at 2.4 fCLeading Edge Jitter ∼ 70 ps Full depleted sensor with light injection at2.4 fC




Synopsis

Synopsis




Excellent Pixel PerformanceLeading Edge Jitter ∼ 40 ps bare ASIC at 2.4 fCLeading Edge Jitter ∼ 70 ps Full depleted sensor with light injection at2.4 fC




Synopsis

Synopsis




Excellent Pixel PerformanceLeading Edge Jitter ∼ 40 ps bare ASIC at 2.4 fCLeading Edge Jitter ∼ 70 ps Full depleted sensor with light injection at2.4 fC

Full chain and time walk correctiontimewalk correction mechanism shown to work wellResidual systematic remainder < 15 ps RMSRMS T0 Jitter ∼ 70 ps at 2.4 fC (bare ASIC)


Backup Slides

DLL Jitter

Trigger Time (s)2.9 3 3.1 3.2 3.3 3.4 3.5

-910×0

100

200

300

400

500

Trigger Time for Falling transition 25trigger_distribution_tdc_bin_25

Entries 4522Mean 3.018e-09RMS 2.811e-11Underflow 0Overflow 0

Trigger Time for Falling transition 25

allbinedgesEntries 32Mean 6.859e-12RMS 9.98e-13Underflow 0Overflow 0

RMS Bin Edge (s)0 5 10 15 20 25 30

-1210×0

2

4

6

8

10

allbinedgesEntries 32Mean 6.859e-12RMS 9.98e-13Underflow 0Overflow 0

RMS of Bin Edges


Chip 6 Full Column S-Curve @ 50V

DAC Code (dec)2600 2800 3000 3200 3400

0

2000

4000

6000

8000

10000

digital s-curve for pixel 1

Charges 1.0 fC → 5.5 fC


Chip 6 Full Column S-Curve @ 50V: Zoom

DAC Code (dec)2970 2980 2990 3000 3010 3020 3030 30400

2000

4000

6000

8000

10000

digital s-curve for pixel 1


Chip 6 Full Column Transfer Functions @ 50V

Q(fC)1 2 3 4 5

Pea

k H

eig

ht

(mV

)

750

800

850

900

950

1000

1050

1100

Chip 6 Transfer Function @ 50V .

All 45 pixels from the full column are shown here


Chip 6 Full Column Gains @ 50V

pixel_gainsEntries 45Mean 66.53RMS 1.376Underflow 0Overflow 0

Absolute Pixel Gain (mV/fC)30 40 50 60 70 80 90 100 110

0

2

4

6

8

10

pixel_gainsEntries 45Mean 66.53RMS 1.376Underflow 0Overflow 0

Chip 6: Distribution of Pixel Gains


Chip 6 Full Column Offsets @ 50V

pixel_offsetsEntries 45Mean 1110RMS 11.63Underflow 0Overflow 0

Offset (mV)1040 1060 1080 1100 1120 1140 1160 1180

0

0.5

1

1.5

2

2.5

3 pixel_offsetsEntries 45Mean 1110RMS 11.63Underflow 0Overflow 0

Chip 6: Distribution of Pixel Offsets


Chip 6 Full Column ENC @ 50V

Q(fC)1 1.5 2 2.5 3

EN

C (

elec

tro

ns)

100

120

140

160

180

200

220

240

ENC Vs Q at 50V, Chip6.

ENC is under 180 e−


Chip 6 Test Pixel ENC @ 50V

Charge (fC)1 1.5 2 2.5 3

No

ise

(ele

ctro

ns)

100

120

140

160

180

200

220

240Test Pixel 0

Test Pixel 1

Test Pixel 2

Test Pixel 3

Test Pixel 4

Noise Vs Electrical Charge Injected: HV=50V

ENC is under 180 e−


Extended Range T1

Q (fC)0 2 4 6 8 10 12 14 16 18 20

T1

(s)

19

20

21

22

23

24

25

26

27

28

29-910×

Tinj = 2.5 nsTinj = 3.5 nsTinj = 4.5 nsTinj = 5.5 nsTinj = 6.5 ns

T1 as a function of Q over extended range.


Extended Range T1 Jitter

Q (fC)0 2 4 6 8 10 12 14 16 18 20

T1

RM

S J

itte

r (s

)

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5-910×


T1 Jitter as a function of Q over extended range.


Extended Range T2

Q (fC)0 2 4 6 8 10 12 14 16 18 20

T2

(s)

32

34

36

38

40

42

44

46

-910×


T2 as a function of Q over extended range.


Extended Range T2 Jitter

Q (fC)0 2 4 6 8 10 12 14 16 18 20

T2

RM

S J

itte

r (s

)

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5-910×


T2 Jitter as a function of Q over extended range.


Extended Range TOT

Q (fC)0 2 4 6 8 10 12 14 16 18 20

TO

T (

s)

6

8

10

12

14

16

18

20

22

24-910×


TOT as a function of Q over extended range.


Extended Range TOT Jitter

Q (fC)0 2 4 6 8 10 12 14 16 18 20

TO

T R

MS

Jit

ter

(s)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8-910×


TOT Jitter as a function of Q over extended range.


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Characterisation Of The NA62 GigaTracker End Of Column ...

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