IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-16, NO, 6, DECEMBER 1981 621

Kenji Kaneko was born in Sapporo, Japan, on Takaahirajh Iwasaki received the B.S. degree inMay 3, 1949. He received the B.S. and M.S. 1965 from Musashi Institute of Technology,degrees from Hokkaido University, in 1972 and Tokyo, Japan.1974, respectively. From 1.965 to 1969 he was engaged in the

In 1974 he joined the Central Research Labo- improvement of diode characteristics at Kofuratory, Hitachi Ltd., Tokyo, Japan, where he Works, Hitachi Ltd. Since 1969 he has been en-has been working in the field of IIL devices andtheir applications.

gaged in the development of linear IC’S at Mu-

Mr. Kaneko is a member of the Institute ofsashi Works, Hitachi Ltd. He is presently a

Electronics and Communication Engineers ofSenior Engineer of Hitachi Ltd.

Japan.Mr. Iwasaki is a member of the Institute of

Electrical Engineers of Japan.

Charge-Coupled Analog-to-Digital

CHONG MIN KYUNG

Abstruct-In this paper, we report on the experimental results of a4-bit charge-coupled A/D converter which was proposed earlier by theauthors, and has been implemented in a monolithic chip form. Mwasfabricated using p-channel CCD technology and has a die size of 4200mii2, The typical operating frequency range was from 250 Hz to 100kHz. A discussion is made on a layout technique to conserve the nomi-nat binary ratio of (8: 4:2:1) among the areas of four charge-measuringpotentiat wells (M wells).

The effect of “dump dot;’ which has been hypothesized as the causeof excessive nonlinearity (> ~ LSB) in the A/D conversion, is described.A novel input scheme esdled “slot zero insertion; which has been de-vised to circumvent the “dump slot” effect, is described.

I. INTRODUCTION

THEREareapplications requiring small, but relatively fast

analog-to-digital (A/D) conversion that can be integratedin MOS technology along with other functions. In this con-

text, the charge-coupled A/D conversion (CCADC) scheme re-cently disclosed by Tompsett [1], and by Kyung and Kim[2], with its smaii chip area and small power consumption, isespecially suitable for low cost, medium performance applica-tions. A/D conversion procedures of the two schemes [1] -[2] are basicaiiy the same including the measurement of sig-

nal charge in a set of binary-ratioed potential wells. However,

a comparison shows that, in the latter scheme [2], the number

of charge transfers and logic operations per bit is significantlyless, and the signal charge is measured in a more precise way

due to the incorporation of an implanted barrier and a dc gate

Manuscript received April 3, 1981; revised July 1, 1981. This workwas supported in part by the Korea Science and Engineering Foundation.

C. M. Kyung is with Bell Laboratories, Murray HiU, NJ 07974. He ison leave from the Korea Advanced Institute of Science and Technol-ogy, Chongyangni, Seoul, Korea.

C. K. Kim is with the Korea Advanced Institute of Science and Tech-nology, Chongysngni, Seoul, Koxea.

AND CHOONG KI KIM

Converter

bias instead of the pulsed barrier in [1]. This paper deals withan experimental verification of the CCADC scheme in [2]using a 4-bit p-channel prototype.

In the CCADC to be described, neither a bulky comparatorarray as required in the “flash” technique [3] , nor compli-cated control circuitry as required in the successive approxi-

mation type A/D converters [4] are needed. Instead, ahnost

dl the logic operations required for the successive approxi-mation algorithm have been internally implemented in thecharge domain. The sample and hold circuit, which is imple-mented separately in conventional A/D converters, is replacedby a simple CCD input structure. Another notable advantageof the CCADC scheme is that N contiguous analog signrd sam-ples, where Al becomes the number of bits in the A/D conver-sion, are processed simultaneously in a pipelined configurationutilizing the analog sampled data property of CCD’S.

The principle of operation of the charge-coupled A/D con-verter is described in Section II with a 2-bit example. Designconsiderations of the experimental prototype are discussed inSection III. Experimental results on the 4-bit device are pre-sented in Section IV. In Section IV, the occurrence of a non-ideai behavior in the A/D conversion is explained, and a modi-fied input scheme is described that overcomes this problem.

II. PRINCIPLE OF CHARGE-COUPLED A/DCONVERSION (CCADC)

The schematic layout [2] of a 2-bit p-channel CCADC is

shown in Fig. 1. The input stage consisting of the p+ source

and two adjacent input gates samples under input gate 2 anamount of charge (holes) proportional to the difference of thevoltages applied to these two input gates [5] . This held chargeis transferred by 1~ phase clocking, where @o and @l are dc

phase and clocked phase, respectively. In the 1~ phase clock-

0018-9200/81 /1200-0621 $00.75 @ 1981 IEEE

622 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-16, NO. 6, DECEMBER 1981

Fig. 1.

Sense Amp. 1

,.P+Ni

Schematic layout of the monolithic part of a 2-bitcoupled A/D converter.

charge-

ing scheme, the clock-coupled noise, and consequently, theconversion error, is significantly suppressed since the measure-ment and sensing of signal charge occur under the quiet dcbiased electrode. Dotted region ~ denotes a channel stop.Shaded region T is a transfer stage of each clock electrode andwas implanted with phosphorus ions to ensure the unidirec-tional flow of charge in the 1~ phase clocking scheme. An-

other shaded region a is a potential barrier implemented by aphosphorus implant. The surface potential in the a is adjusted

such that it is always lower than, or at least the same as, thatof T under the same @oelectrode.

When $1 goes high, the signal charge is transferred out of 11well into Ml well since the direct charge transfer into S1 wellis blocked by the channel stop & If the size of the charge

packet is larger th~ the charge storing capability of Ml well,which is set equal to the magnitude of the most significant bit

(MSB)-in this case, 21 bit–only the excess charge is trans-ferred into SI well. Whether the MSB is “ONE” or “ZERO” is

determined by the presence or absence of the split charge inS’l well, which is sensed with a floating diffusion amplifiercoqnected to the S1 well. If the MSB is “ONE ,“ the chargestored in Ml well is drained to the p+ drain-1 by turning onthe dump gate, and only the split charge stored in S1 well istransferred to the next stage–10 well. If the MSB is “ZERO ,“~ the charge stored in Ml well is transferred to 10 well. Dur-ing this transfer of the fiust charge packet into 10 well, the

input stage takes the next signal sample and transfers the cor-responding amount of holes into 11 well. In the next clock

cycle, holes which have arrived at 10 well are used for deter-mining the next significant bit—2° bit—using the combination

of 10, M., and So wells in exactly the same way as before ex-cept that the area of the M well is halved. Therefore, 2° bitof the first and 21 bit of the second signal sample are deter-mined simultaneously and independently. This pipelinedproperty of the CCADC should permit a large throughput rateand an effective utilization of chip area. The binary outputfor all bits of an analog signal sample can be made available

simultaneously at the output port by including on-chip MOSdigital shift registers which are driven by the same clock asthat for driving the CCD.

III. DESCRIPTION OF THE EXPERIMENTAL PROTOTYPE

For an experimental verification of the CCADC scheme, a4-bit p-channel experimental prototype was designed and fab-

ricated. The fabrication process of the CCADC chip was car-ried out in PMOS technology with an additional phosphorus

implantation for a potential barrier and an aluminum anodiza-tion process [6] for an overlapped electrode structure.

A. Layout Considerations

Fig. 2 shows schematically the layout of a 4-bit CCADCchip. One and one-half phase clocking is achieved with @lb,

@l~, 00~, and @o~,where @o~, @o~are dc phases denoted asclear regions and @l~, @l~ are clocked phases denoted asdotted regions. @ob and @l~ act as barrier electrodes neededfor the unidirectional charge flow. The L-shaped black region

in Fig. 2 denotes a phosphorus implant where the vertical sec-tion acts as a channel stop, and the horizontal section as a po-tential barrier. The sensing circuitry to detect the charge in Swell is achieved with a floating diffusion (sensing diffusion)connected to an on-chip MOST source follower, which is theoutput stage of the CCADC chip.

In the CCADC scheme, the conservation of binary ratio

among the charge capacities of the four 11 wells throughoutthe photolithographic and chemical etching procedure is essen-tial for an accurate A/D conversion. If we assume that the

oxide thickness, implant dose, wafer doping density and thef~ed charge in the oxide are uniform across a chip, the prob-lem of maintaining the conversion linearity is reduced to that

of preserving the binary ratio among the areas of the M wells.The horizontal nominal dimensions of the M wells were givenan identical value of 30 ~m for all M wells. on the other hand,the upper side of each M well is defined by the implanted po-tential barrier. If the lower side of each M well is defined by

the same mask as that for the implanted potential barrier, thevertical dimension of each M well will not be affected from the

misalignment error which normally exists between two mask-ing steps. For this reason, a dummy phosphorus implant (notshown in Fig. 2) has been incorporated to define the loweredges of the M wells.

B. Dump Slot

Fig. 3(a) shows a schematic layout in the vicinity of thedump diffusion and. the dump gate. According to the earlier

device description, two transfer paths-PAm 1 and PATH 2–

are possible for tie signal charge which have been stored in theM well depending on whether the dump gate is “oN” or

“OFF ?’ In this context, we will consider the surface potentialprofde rdong the line A-A’ shown in Fig. 3(a). Let us assumethat the dump MOS transistor has not been connected to thedump diffusion (p+ ). Then, the surface potential in the float-ing p+ diffusion region will be equilibrated with the surface po-

tential in non-p+ regions under the same gate electrode by theinstantaneous movement of holes. Fig. 3(b) shows the surfacepotential profile rdong A-A’ in that case.

Next, consider the case when the dump gate is turned on.To completely drain off the signal holes which have beenstored in the M well, the voltage applied to the dump gateVDG should be sufficiently negative so that the surface poten-tial under the dump gate ~~ (V~G ) is lower than, or at least thesame as, the surface potential in non-p+ region under the same

@o~ electrode YS($OJ. That k, 4~(vDG) < I),(@oJ, where theIJIS’Sare negative quantities. While the surface potential in

KYUNG AND KIM: ANALOG-TO-DIGITAL CONVERTER 623

- 15voltQ

[–’!-Vq

lG 1 IG2 Sensing- 15V

N/ Diffusion 1 ‘

XL

-15V

V52

PL V53Input

StageH .

- $5v

--+ V54

PotentialBarrier ~ .,,

‘}’‘‘Gm3DDL’)-D‘rain.Orl -1-Os

&-_-,

7 Drain

Drain

Dr$in

Fig. 2. Layout of the 4-bit p-channel CCADC chip. Shaded area de-notes p-diffusion, and black area denotes phosphorus implant.

slot”) in the surface potential profile along A-A’ is shown.If, in this instance, a charge packet is transferred along thePATH 1, it should undergo a charge loss, shown as QDS in (c),to ffl up the dump slot. The associated charge loss in the

dump slot QDS would be expressed as

QDS = CDS I44bG) - tir(I#Jos)l

where CDS is the capacitance of the p+ diffusion area (dumpdiffusion).

Let us consider the realization of the dump gate. In Fig. 3,the dump gate is shown connected to the CCADC channel re-

gion via a p+ diffusion. This is to facilitate the layout of theclock electrodes while usiqg only two metal layers. Eachdump gate has been connected to the @o$clock stage next toeach relevant M well. If the dump diffusion and the dumpgate were connected directly to the M well the charge storingcapacity of the M well will be perturbed, since the additionalcapacitance due to the part of the p+ diffusion, which wouldprotrude outside the M well, would have to be charged and dis-

charged in exactly the same way as the M well capacitance. Asa result of this layout schemle, the dump gate is to be turnedon, if necessary, one clock period after the measuring of thesignal charge in the M well.

~ob ‘#’a~ +7b

m“

&——– - PATH 1A A’

P+ diffusion

PATH 2

(a)

1%1DumpGate ~

!Dump Drain

DG ‘OFF ‘

(b)

VE””’es

DG ‘ON’

%

—— --’+s (+05)....:.

(c) QDs ‘“’””’ ---– -Ik(vDG)

(dump slot )

Fig. 3. (a) A schematic layout in the neighborhood of the dump gate.(b) Surface Potential along A-A’ when the dump gate (DG) is “OFF.”(c) When the DG k “oN.” C Slot Zero Insertion

In the context of the for]mer discussion, it can be readilyunderstood that if a dummy charge packet, just large enoughto fdl out all the dump slots, is transferred after every signalcharge packet, the “dump slc)t” effect would be circumvented.This dmy charge to compensate for the dump slot is namedhere as “slot zero.” The upper limit on the amount of “slot

non-p+ region remains at r/.J~(@oJ after the signal charge is

drained off the channel, the surface potential in the p+ region

will fall to IJIS(~DG) due to the additional draining of holeswhich are majority carriers in the p+ region. This descriptionis retlected in Fig. 3(c) where tne formation of a slot (“dump

624 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-I 6,NO. 6,DECEMBER 1981

Fig. 4. Chip photograph of CCADC.

Fig. 5. Oscillomun showing the nro~atzation of a single charge packet.[a) An input~inal wavef;rm appli;d;t the input ga~e 2. (b~ Transferclock. (c1)-(c4) Waveforms at the first, second, third, and fourthsource follower’soutput.

zero” charge is to be determined by the charge handling capa-bility of the last transfer stage where the channel width is thenarrowest in this particular CCD. The maximum allowable

“slot zero” for the experimental device has been found to betypically 1.35 pC, which corresponds to 3 LSB’S (1 LSB =

0.45 pC in the experimental devices). Therefore, if the dump

gate ON voltage is adjusted such that the sum of charge capaci-ties of all the dump slots are kept within the charge magnitudeof 3 LSB’S, all the dump slots can be filled up by the injected

“slot zero.” In the “slot zero insertion” scheme each bit sens-ing circuitry is activated only for the time interval duringwhich the “signal” charge is expected to be in the S well, thendisabled when the “slot zero” charge is in the S well. The ef-fective conversion throughput of the A/D converter is reduced

to one half by this process.

IV. EXPERIMENTAL RESULT

Fig. 4 shows a photograph of the CCADC chip which has adie size of 4200 mi12. In Fig. 5, (c1)-(c4) are the typicalwaveforms observed at the four consecutive source followers’outputs, i.e., V&-V&, respectively, due to the propagation ofa single charge packet; (a] is an input signal voltage waveform,and (b) is the transfer clock waveform (@JIJ. Fig. 6 shows theideal transfer characteristic of the CCADC chip. The x-axis

Vs, /

&?

zL/j~-1$

3!I30w

ANALOG SIGNAL MAGNITUDE [unit : 1LS81

Fig. 6. Ideal input-output transfer characteristic of CCADCchip.

Fig. 7. (a) Linearly increasing ramp input signal. (bl)-(b4) Resultantwaveforms at the four consecutive source followers’ outputs.

represents the anrdog signrd magnitude in the unit of 1 LSB,while the voltage magnitudes, V~l -V~4, are represented in they-axis. From the earlier device description in Section III, it isapparent that one, two, four, and eight varieties of charge

transfer paths are possible for the charge packet to appear inS1, S2, S3, and S4 wells, respectively, which correspond

(v~q-l,”””v~~ - 8) in Fig. 6. It is shown as an example

that an analog signal (VX in Fig. 8) with a magnitude between11 LSB and 12 LSB would be converted to the binary code,

(101 1). Fig. 7 shows an experimental result for a ramp inputsignal linearly increasing in the negative direction; (a) is theramp. input signal, and (b 1), (b2), (b3), and (b4) are the wave-forms at the first, second, third, and fourth source follower’soutput– V~l -V~4, respectively. In Fig. 8, the four traces,(bl)-(b4), are the parallel binary code obtained through the

comparator and the data sequencer, while the top trace (a) is awaveform reconstructed from the binary code using a 4-bitD/A converter. An example illustrating the performance ofthe 4-bit, charge-coupled A/D converter is shown in Fig. 9;(a) shows a triangular signal, and (b) is the waveform recon-structed from the A/D and D/A conversion. While a, mono-tonically increasing staircase has been observed on the risingportion of the reconstructed waveform, an error (denoted by

KYUNG AND KIM: ANALOG-TO-DIGITAL CONVERTER

Fig, 8. Reconstructed staircase waveform. (bl)-(b4) Parallel binarycode, 23, 22, 21, and 2° bit, respectively.

Fig. 9. (a) A triangular input signaL (b) Reconstructed trian@w wave-form. A/D conversion errors (indicated by arrows) are shown in thethree major bit transition points of the lowering portion.

arrow in the figure) with a magnitude of 1 LSB has appearedrespectively at the three major bit transition points, that is,(1100 + 1011), (1000 +0111), and (0100 +0011), in thelowering portion of the reconstructed waveform. These

glitches are due to the loss of signal charge in the “dump slot”described in Section III.

The “dump slot” effect also causes some undesirable shiftof the bit transition points in the rising portion of the recon-structed waveform, although it is not noticeable in Fig. 9(b).Fig. 10 shows a successful reconstruction (lower trace) of a tri-

angular signal by the “slot zero insertion” input scheme men-tioned in Section III. The upper trace shows the associatedinput signal waveform which is shown to be multiplexed be-tween the “slot zero” level and the “signal” level.

The maximum conversion rate of the 4-bit p-channel

CCADC, being limited by the charge transfer time, was about100 kHz in this experiment, where the nominal LSB well sizewas 20 X 30 Km. An estimation [2] of the conversion rateof the CCADC scheme shows that for a 4-bit n-charinel, squarewell geometry device with the LSB well size of 10 X 10 Hm,

up to 1 MHz conversion is possible. The lower limit of the

conversion rate of the CCADC chip depends on the magnitudeof dark current density and the operating temperature, andfound out, in this experiment, to be about 250 Hz at room

Fig. 10. Upper trace; triangular input signal waveform in the slotzero insertion input scheme. Lower trace; reconstructed triangularwaveform.

temperature. The dark current density of the experimental

prototype was about 5 vA/cm2 at room temperature, an ab-

normally large value. No special processing steps to reduce the

dark current density has been included in preparing for sample

devices.

V. CONCLUDING REMARKS

We have demonstrated a new monolithic A/D converterwhich is realizable with CCD/MOS technology. Hardware

complexity is nearly minimal in the proposed A/D converter,

since almost all the logic operations are internally implementedin charge domain, and moreover, JV contiguous analog signalsamples (N= number of bits) are processed simultaneously and

independently in the pipelined structure of the CCD.The proposed charge-coupled A/D converter could fmd its

major applications in low cost, medium performance systems.Since the throughput rate decreases with the number of bits(as the bit number increases, the well dimensions increase ex-ponentially, which in turn retards the charge transfer), a com-

promise has to be made between the number of bits and the

throughput rate [2].

ACKNOWLEDGMENT

The authors wish to thank many people who have contrib-uted to this work, but in particular, J. S. Yang and S. H. Choefor their help in mask making, H. S. Chang for process con-tributions, and I. C. Chung and S. H. Kim for chip assembly.The authors are rdso indebted to Y. S. Shin and O. H. Kim fortheir many good ideas in the fabrication and testing procedure.They also appreciate the helpful comments by M. F. Tompsetton both language and matters of fact.

REFERENCES

[1] M, F. Tompsett, “Semiconductor charge-coupled device analog-to-digital converter: U.S. Patent 4136335, Jan. 23,1979.

[2] C. M. Kyung and C. K. Kim, “Pipeline analog-to-digital conversionwith charge-coupled devices,” IEEE J. Solid-State Circuits, VOLSC-15, pp. 255-257, APr. 1980.

[3] C. E. Woodward, K. ii. Konkle, and M. L. Naiman, “A monolithicvoltage-comparator array for A/D convertersfl IEEEJ. Solid-StateCircuits, vol. SC-10, pp. 392--399, Dec. 1975.

[4] J. McCreary and P.R. Gray, “’A1l-MOScharge-redistribution anrdog-

626 IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL. SC-16,NO. 6,DECEMBER 1981

[5]

[6]

to-digital conversion technique, Part 1,“ IEEE J. Solid-State Cir-cuits, vol. SC-10, pp. 371-379, Dec. 1975.M. F. Tompsett, “Surface potential equilibration method of set-ting charge in charge-coupled devices,” IEEE Trans. Electron De-vices, vol. ED-22, pp. 305-309, June 1975.D. R. Collins et al., “Charge-coupled devices fabricated using Al-Al, 0~-Al double level metallization.” J Electrochem. Sot.. vol.125, ~P. 521-526,1973.

Chong Min Kyung was born in Seoul, Korea, onJune 21, 1953. He received the B.S. degreefrom Seoul National University, Seoul, Korea,in 1975, and the MS. and Ph.D. degrees in elec-trical engineering from the Korea AdvancedInstitute of Science and Technology, Seoul,Korea, in 1977 and 1981, respectively.

He is currently a Postdoctoral Member ofthe Technical Staff at Bell Laboratories, MurrayHill, NJ, working on the modeling and simula-tion of short-channel MOS devices.

Choong Ki Kim was born in Seoul, Korea, onOctober 1, 1942. He received the B.S. degreefrom Seoul National University, Seoul, Korea,in 1965, and the M.S. and Ph.D. degrees in elec-trical engineering from Columbia University,New York, NY, in 1967 and 1970, respectively.

From 1970 to 1975, he was with the Re-search and Development Laboratory, Fairchild,,~

, : Camera and Instrument, Inc., Palo Alto, CA,‘:,”’ where he worked on the development of linear/

area charge- coupled device image sensor. In1975, he left Fairchild to join the faculty of the Department of Electri-cal Science, Korea Advanced Institute of Science and Technology,Seoul, Korea, as an Associate Professor, and has taught on integratedcircuit design and semiconductor device physics. He founded the Inte-grated Circuit Laboratory at the Korea Advanced Institute of Scienceand Technology, where he is presently a Professor. His current researchinterest includes integrated injection logic, charge- coupled device ana-log signal processors, three-dimensional device structures and laserannealing on silicon, etc. He has authored and coauthored over 25technical articles and has several U.S. patents. He is the author of“Physics of Charge Coupled Devices: Chapter 1 of Charge Coupled De-vices and Systems (New York: Wiley, 1979).

Dr. Kim is a senior member of the Korea Institute of ElectricrdEngineers.

An Open Loop Programmable Amplifier withExtended Frequency Range

ROBERT A. BLAUSCHILD, MEMBER,IEEE

Abstract–The use of localized positive feedback and nonlinearity errorcorrection has led to an “open loop” amplifier with a gain-bandwidtlrproduct up to 1 GHz using a conventional IC process. The circuitachieves a bandwidtJr of 20 MHz at a gain of 30, and a bandwidth of10 MHz at a gain of 100. Linearity for a 1 VP.P output signal is 0.1percent over a gain range that is programmable from zero to above 100.

INTRODUCTION

cONVENTIONAL monolithic operational amplifiers haveuntil recently been limited in gain bandwidth product to

around 20 MHz. There are several reasons for this limit, themost prevalent being the need for high open loop gain, lowpower dissipation, and wide input and output voltage ranges.If these characteristics are not necessary for a particular appli-cation, then all n-p-n resistive load gain stages can be used withsmall signal swings to obtain moderate gain at high frequencies.In both cases, performance limitations are caused by topologieswhich suffer due to very limited linear dynamic range, as illus-

trated by the simplified op amp shown in Fig. 1.

Manuscript received May 14, 1981; revised July 1, 1981.The author is with the SigneticsCorporation, Sunnyvale, CA 94086.

The linearity of the input differential pair is poor for signalsabove a few millivolts, and unacceptably bad for signals in the50-100 mV range. The gain of the second stage is extremely

high and not well controlled, in addition to being nonlinearover large voltage swings. The output buffer has poor loadregulation unless biased with a high quiescent current. The

performance of each of these stages is unfortunately akoheavily temperature and process dependent.

The typical system solution is to use negative feedbackaround the amplifier. This has a major advantage in thatmany bad characteristics (such as nonlinearity and high out-put resistance) are divided by a large factor. The biggestdisadvantage is that the system will be unstable for loopgains equal to or greater than one with phase margin equal tozero. To avoid this generally requires bandwidth reduction ofthe forward gain path, typically done with a compensationcapacitor and an input stage transconductance reductionscheme. The basic problem with this approach is that it tradesbandwidth for Iinearity and process insensitivity.

To avoid this tradeoff, a linear system can be designed withblocks (Fig. 2) which achieve excellent linearity without

0018-9200/81 /1200-0626$ 00.75 @ 1981 IEEE