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CHEMICAL-MECHANICAL PLANARIZATION (CMP)

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HIGH-K DEVICES NON-VOLATILE MEMORIES 2 CHEMICAL-MECHANICAL PLANARIZATION (CMP) THE CMP PROCESS Highly integrated circuits, like logic and memory chips, consist of many material layers. In the course of manufacturing the surfaces have to be planarized over and over again to obtain sufficient process windows for critical processes like lithography and etching. Furthermore planarization ensures defined sizes of the structures, thus in the end reliable functioning of the electronic elements. Chemical-mechanical planarization (CMP) is the state of the art to reach the necessary planarity. The continuous shrinking in the semiconductor technology goes along with a higher demand for accuracy, as well as a higher number of materials used. Therefore it is necessary to understand the various CMP processes and to develop novel processes for newly introduced materials to be able to fulfill the demands of the coming technology nodes. ADVANTAGES • Industry matched 300 mm CMP-system for efficient portability into large-scale production • Extensive experience in the field of consumable screening and characterization • Long-standing experience in process characterization and development • Close location and cooperation with semiconductor manufacturers and research institutions in Silicon Saxony • Established qualification and contamination protocols for customer demos and loop of production wafers • Test wafer availability • Extensive metrology and analytics • Electrical characterization and reliability tests • Pre and post processing in house (barrier/liner/ seed deposition, copper ECD, anneal, etc.) • ISO 9001 certified FRAUNHOFER INSTITUTE FOR PHOTONIC MICROSYSTEMS IPMS Fraunhofer Institute for Photonic Microsystems IPMS Center Nanoelectronic Technologies (CNT) Königsbrücker Str. 178 01099 Dresden Germany Dr. Benjamin Uhlig +49 351 2607 3064 [email protected] www.ipms.fraunhofer.de INTERCONNECTS 1 300 mm CMP tool @ Fraunhofer IPMS MATERIAL SUPPLIERS IC MANUFACTURERS EQUIPMENT MANUFACTURERS BASIC RESEARCH INSTITUTIONS
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Page 1: CHEMICAL-MECHANICAL PLANARIZATION (CMP)

HIGH-K DEVICES NON-VOLATILE MEMORIES

2

CHEMICAL-MECHANICALPLANARIZATION (CMP)

T H E C M P P R O C E S S

Highly integrated circuits, like logic and

memory chips, consist of many material

layers. In the course of manufacturing the

surfaces have to be planarized over and over

again to obtain suffi cient process windows

for critical processes like lithography

and etching. Furthermore planarization

ensures defi ned sizes of the structures,

thus in the end reliable functioning of the

electronic elements. Chemical-mechanical

planarization (CMP) is the state of the

art to reach the necessary planarity. The

continuous shrinking in the semiconductor

technology goes along with a higher demand

for accuracy, as well as a higher number

of materials used. Therefore it is necessary

to understand the various CMP processes

and to develop novel processes for newly

introduced materials to be able to fulfi ll the

demands of the coming technology nodes.

A D VA N TA G E S

• Industry matched 300 mm CMP-system foreffi cient portability into large-scale production

• Extensive experience in the fi eld ofconsumable screening and characterization

• Long-standing experience in processcharacterization and development

• Close location and cooperation withsemiconductor manufacturers and researchinstitutions in Silicon Saxony

• Established qualifi cation and contaminationprotocols for customer demos and loop ofproduction wafers

• Test wafer availability

• Extensive metrology and analytics

• Electrical characterization and reliability tests

• Pre and post processing in house (barrier/liner/seed deposition, copper ECD, anneal, etc.)

• ISO 9001 certifi ed

F R A U N H O F E R I N S T I T U T E F O R P H O T O N I C M I C R O S Y S T E M S I P M S

Fraunhofer Institute for

Photonic Microsystems IPMS

Center Nanoelectronic

Technologies (CNT)

Königsbrücker Str. 178

01099 Dresden

Germany

Dr. Benjamin Uhlig

+49 351 2607 3064

[email protected]

www.ipms.fraunhofer.de

INTERCONNECTS

1

300 mm CMP tool @ Fraunhofer IPMS

MATERIALSUPPLIERS

MATERIALSUPPLIERIC MANUFACTURERS

EQUIPMENT MANUFACTURERS

BASIC RESEARCHINSTITUTIONS

Page 2: CHEMICAL-MECHANICAL PLANARIZATION (CMP)

v i s i t w w w . i p m s . f r a u n h o f e r. d ew w w . s c r e e n i n g - f a b . c o m

A P P L I C AT I O N S

• CMP process development and optimization

• CMP design for manufacturing strategy development

with semiconductor product manufacturers

• CMP consumables screening and characterization- Polishing pad- Conditioner- Slurry- Post CMP cleaning chemistry- Brush- Filter

- and more

• CMP process characterization- Planarization- Defectivity- Removal rates, selectivity- Static etch rates

- Electrical performance and reliability

• Modeling and simulation of the planarization behavior

of patterned wafers

• CMP wafer processing on demand

I N D U S T R Y M AT C H E D E Q U I P M E N T ( 3 0 0 M M )

• Applied Materials Refl exion LK polisher with Desica cleaner

• Flexible mobile slurry system (6 x 80 l)- 4 tanks for Platen distribution

- 2 tanks for Cleaner feed

• Film thickness measurement tools- Ellipsometer (KLA Tencor Spectra CD/FX 100)

- 4-Point-Prober (KLA Tencor RS-100)

• Surface topography measurements- Profi ler (KLA Tencor HRP-340)- AFM (Veeco X3D-AFM)- Mobile confocal microscope (Nanofocus µsurf)

• X-Section and material analyses:- SEM, TEM, ToFSIMS, TXRF, XRR, XRD, etc.

• Defect control- Blanket: KLA Tencor SP2- Patterned wafer: NextIn AEGIS-I

- Review: Applied Materials SEMVision G3

• Wafer availability- Unpatterned for removal rates and particle measurements:

TEOS, ULK, Cu, Ta/TaN, Co, etc.- Patterned for defectivity and electrical data:

2x nm node CMP test chip

• Simulation capabilities- Modeling on different scales, esp. feature and chip scale- In-house developed simulation programs and routines

- FEM based commercial software COMSOL Multiphysics

• Electrical characterization- TEL Precio probe station (-55-200 °C, fully automated)- SÜSS PA300 probe station (semi-automated, fl exible)

300 mm CMP test wafer with pitch/density structures down to 28 nm node

Defect maps on patterned 300 mm

wafers with exemplary review SEM pictures

CMP pad pore structure obtained with confocal microscopy (0.7 x 0.5 mm)


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