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April 30, 2014 1
FinFET vs. FD-SOI Key Advantages & Disadvantages
Amiad Conley Technical Marketing Manager Process Diagnostics & Control, Applied Materials ChipEx-2014, Apr 2014
April 30, 2014 2
Moore’s Law
“In 1965, Gordon Moore sketched out his prediction of the pace of silicon technology. Decades later, Moore’s Law remains true, driven largely by Intel’s unparalleled silicon expertise.” (Source: Intel; Copyright © 2005 Intel Corporation)
The number of transistors on integrated circuits doubles every two years
How to maintain cost-performance ?
April 30, 2014 3
Complying with Moore’s Law Maintaining Cost-Performance
Traditional: • Shrink the feature size: ArF Immersion Double/Quad patterning EUV • Increase wafer size: 200mm 300mm 450mm Unique/New • Build vertically: 2D 3D
April 30, 2014 4 4
Cost Trends
Design cost exponentially increases coupled with reverse in cost per gate trend from 20nm
Source: Faster, Cooler, Simpler, could FD-SOI be Cheaper too? Semiwiki, 08/2013
April 30, 2014 5
End Market Growth Outlook
317 322 315 271
211 176 159 158 0
110220330440550660770880990
1100
2012 2013 2014 2015 2016 2017 2018 2019
Uni
ts (B
) Tablet Premium Tablet Utility/BasicSmartphone Premium Smartphone Utility/BasicPC Marginal Unit Growth
Smart phones are the market fuel for both Logic AP & Memory
April 30, 2014 6
• Limitations of bulk planar transistors – Channel area underneath the gate is too deep and too much of the channel is
too far away from the gate to be well-controlled – The result is higher leakage power (static/stand-by power) – Gate is never truly turned off
• Solution: Make the channel thinner so that it is well controlled by the gate
The leakage/power consumption problem
Source: Challenges of 10nm and 7nm CMOS Technologies, IEDM 2013
• Physical dimension scaling of ~103, Transistor # increased x106 in 30 years
• Cost is leakage, resulting in power consumption
Source: http://allthingsvlsi.wordpress.com/
April 30, 2014 7
FinFET FD-SOI
Possible Solutions
Fin (shaped) Field Effect Transistor Fully Depleted Silicon on Insulator
April 30, 2014 8
• Transistor with 2-3 gates which are wrapped around a Silicon fin • Trigate has 3 gates [2 sidewall vertical gates and one planar/top gate] • A version of a Trigate finFET is Double-Gate FinFET with only the 2 sidewall
vertical gates with top gate being non-functional due to thicker gate oxide
What is a FinFET? Source: Intel
April 30, 2014 9
Fully Depleted SOI Partially Depleted SOI
SOI – Silicon on Insulator – stack of Silicon-Buried Oxide Layer - Silicon What is FD-SOI?
FD-SOI advantages: • Excellent electrostatic
control of the channel • No channel doping
required • Back bias ability if BOX is
also thin
• Excellent VT variability • Low DIBL (Drain Induced Barrier Lowering) –
especially at low VDD • Limited Short Channel Effects • Very good Sub-threshold Slope • Minimum junction capacitance and diode leakage • Simpler process: no halo doping, simpler STI (End
Pointed Etch)
50-90 nm Si thickness
5-20 nm Si thickness
April 30, 2014 10
FD SOI vs. Bulk Planar Performance Comparison • The power/performance characteristics of FD SOI with body biasing, and also
without body biasing, are better than bulk CMOS at 20nm
April 30, 2014 11
FD SOI vs. Bulk HKMG Cost Comparison
Despite SOI base wafer cost ~4X higher than bulk, market analysis estimations lead to lower die costs due to projected higher die yields
Source: ECONOMIC IMPACT OF THE TECHNOLOGY CHOICES AT 28nm/20nm, IBS Inc, Jun 2012
April 30, 2014 12 12
FD-SOI Vs FinFET Performance Comparison
At matched Wfin/Hfin, equivalent performance
Source: Comparison study of FinFETs: SOI vs. Bulk/SOI Consortium Source: IEDM 2013 short 7/10 nm CMOS course
Better DIBL & SS for FinFET
April 30, 2014 13
FD-SOI vs. FinFET - Cost vs. Performance Comparison
Bulk FD SOI projected to have lower unit cost than FinFET due to higher FinFET process complexity and expected lower die yield
20nm Die Costs at 100mm2 and 200mm2
Source: ECONOMIC IMPACT OF THE TECHNOLOGY CHOICES AT 28nm/20nm, IBS Inc, Jun 2012 Source: FD=SOI Keeps Moor’s Law on Track, Advanced Substrates, Feb 2014
April 30, 2014 14 14
Unique FD SOI Process Challenges [Wafer Vendor]
Thin Si thickness & x-wafer uniformity
Buried oxide thickness & x-wafer uniformity Source: IEDM 2013 short 7/10 nm CMOS course
Tsi & BOX thickness & uniformity, critical parameters to performance, controlled by base wafer manufacturer
April 30, 2014 15
Unique FinFET – Process Challenges [Fab]
STI Oxide
Fin
Spacer • Complete spacer removal from fin area
Fin Formation: • Precision etch • Structural integrity (collapse,
erosion, thermal shock) • Precise Recess to control
fin height • Channel materials to
increase mobility
Gate Stack (high-k & metal gate) • Material selectivity • Material deposition thickness
uniformity on vertical walls • Metal gate composition uniformity/stability
Fin Junctions: • Conformal doping
on sidewalls
April 30, 2014 16
FinFET – Process Control Challenges [Fab]
Lg
Lg
Lg
Measurement of gate CD across the
Fin height
Detection & Review of defects on Fin sidewalls after
gate etch
Measurement of Fin sidewall angle to
control the 3D transistor width
April 30, 2014 17
Process Differences - Example STI Module FinFET FD-SOI Vs FinFET Bulk
Source: Comparison study of FinFETs: SOI vs. Bulk, SOI Industry Consortium
Natural Isolation between adjacent transistors by BOX, STI etch end points on BOX, minimal need for trench depth control, with no requirement for implant to complete isolation
April 30, 2014 18
• Plasma doping (PLAD) for uniform sidewall doping
Process
• Tilt CD-SEM measurements • Destructive technologies
Metrology & Inspection
Possible Solutions
April 30, 2014 19
Tilt CD-SEM – Methodology & Case Study
Applied Materials collaboration with GLOBALFOUNDRIES, proves excellent
correlation between tilted CD-SEM height measurement and TEM
April 30, 2014 20
FinFET vs. FD-SOI Category FinFet FD-SOI
Base Wafer Cost x4
Process Complexity
Overall Wafer Cost to To
Die Yields ?????? ??????
Unit Cost ?????? ??????
Process control & metrology challenges
Active transistor area density
Performance (Ion vs. Ioff) Similar Similar
April 30, 2014 21
What Next? Future Transistor Path
April 30, 2014 22
Gate All Around - Si Nanowires
SiNW buckling, may impact device performance
Source
Drain
Buckling
SiNW sample dimensions: Width ~ 3 – 12 nm, Lengths: 280 nm
Published in SPIE 2014: Applied Materials/IBM Collaboration to characterize the buckling
effect of nano-wires
April 30, 2014 23
• FinFET first generation is in high volume production
• Key manufacturers are following the FinFET path for 14nm
• FinFET is a major inflection in terms of process and metrology challenges vs. FD-SOI which is a simpler path
• The long term winner between both approaches will depend on the device/process scalability, as the cost benefit of FD-SOI vs. FinFET is based on combination of:
– base wafer cost, process complexity/cost and die yield
Summary
April 30, 2014 24
Thank You