Welcome
1
© 2013 Agilent Technologies, Inc.
Christopher Burns
RF Power Platform Development Manager /
Power Broadband Business Unit
RF Micro Devices
GaN-on-SiC RFMD High Power Doherty Design, Modeling & Measurement
Christopher T. Burns
RFMD, Chandler, AZ, [email protected]
Introduction
• Motivation
• Information-rich signals with high peak-to-average ratios
are standard in the commercial wireless infrastructure and
expanding in the military world
• Need to operate backed-off from peak power yet at the
same time maximize efficiency
• Doherty Configuration is mature technology
• PA suppliers are getting very nearly equal results
• Need a well-defined approach to arrive at best design
quickly!
Page 3
•GaN-on-SiC 48V FET technology features high impedance and
high power density to enable Doherty amplifiers with excellent
performance and bandwidth
Introduction
Doherty Design - Outline
Concept Introductions
Operational Fundamentals – Load Modulation
Doherty Design Procedure
Doherty Design Example & Results
Practical Doherty Circuit Implementation Hints
1
2
3
4
5
Page 5
Doherty Design - Outline
Concept Introductions
Operational Fundamentals – Load Modulation
Doherty Design Procedure
Doherty Design Example & Results
Practical Doherty Circuit Implementation Hints
1
2
3
4
5
Page 6
The Doherty Amplifier
• Carrier amp, biased class B or class AB, is always on
and handles signal at average power
• Peaking amp, biased class C, only handles signal peaks
• C and P’s operation is dependent on each other
C
P
Carrier Amp
Peaking Amp
Page 7
η
The Doherty Amplifier
Page 8
IV Curves & Class B load lines
10 20 30 40 50 600 70
4
8
12
16
20
0
24
VGS=-3.500VGS=-3.250VGS=-3.000VGS=-2.750VGS=-2.500VGS=-2.250VGS=-2.000VGS=-1.750VGS=-1.500VGS=-1.250VGS=-1.000VGS=-0.750VGS=-0.500VGS=-0.250VGS=0.000VGS=0.250VGS=0.500VGS=0.750VGS=1.000VGS=1.250VGS=1.500
VDS
IDS
RL
2xRL
Output Power
η
RL
2xRL
• Carrier mode:
• Carrier alone operates on 2xRL
load line
• ½ MaxPoutSingleDevice
• Peaking mode:
• Carrier and peaking each operate
on RL load line
• 2 x MaxPoutSingleDevice
Doherty Design - Outline
Concept Introductions
Operational Fundamentals – Load Modulation
Doherty Design Procedure
Doherty Design Example & Results
Practical Doherty Circuit Implementation Hints
1
2
3
4
5
Page 9
Textbook Load Modulation
• Doherty achieves Load
modulation by using the
principle of “load pulling”
using two devices*
0.5RL V
I1 I2
1
21 15.0
I
IRZ L
Page 10
RL
I1 I2
V1 RL V2
Textbook Load Modulation
LRZZ 21
0.5RL V
I1 I2
0.5RL V
I1
02I
LRZ 5.01
Case I
Both amplifiers contributing equally
Case II
Peaking amp off
Page 11
But we need Z1 = 2xRL for high
efficiency at lower power!
freq (1.000MHz to 1.000GHz)
ztos
(Zin
1)
indep(ztos(ZL)) (0.000 to 0.000)
ztos
(ZL)
indep(ztos(Z0)) (0.000 to 0.000)
ztos
(Z0)
indep(ztos(Zin)) (0.000 to 0.000)
ztos
(Zin
)
Quarter-wave Impedance Transformer
Page 12
Zin = Z02/ZL
Z0
Zin
ZL
Zin = 100Ω ZL = 25Ω
Z0 = 50Ω
Doherty Design - Outline
Concept Introductions
Operational Fundamentals – Load Modulation
Doherty Design Procedure
Doherty Design Example & Results
Practical Doherty Circuit Implementation Hints
1
2
3
4
5
Page 13
Doherty PA Concept and Practice
Simple ideal
Doherty PA
Carrier
Peak
λ/4 λ/4
RFOUT
RFIN
Implicit Assumptions: •Single Frequency
•Carrier and Peak amps are ideal current generators with no
reactive parasitics
•Carrier and Peak amps have same S21 magnitude and phase
regardless of biasing or drive level
•System Z = 0.5* optimum device RLoad
Car
Pk
CarrierIn
PeakingIn
CarrierOut
PeakingOut
Doherty PA Concept and Practice
Page 15
Output
Match
Input
Match
50Ω
•Parasitics, packaging and matching circuitry all have phase shift
•Peaking amp requires output offset line
•Carrier offset line– not necessarily 90 degrees
•Input offset lines to achieve in-phase output
•Output match to System Z0
•Impossible to achieve perfectly over frequency & power
Match
to 50Ω
Splitter
Complex in
Practice!
Car
Pk
CarrierIn
PeakingIn
??4,0 CarrierOutZ
PeakingOutZ ,0
Doherty Topology – Definitions
Page 16
Output
Match
Input
Match
POPTZ ,
COPTZ ,
HIGH POWER
LOW POWER
0Z
??2 0Z
HIGH POWER
LOW POWER
20ZZSUM
4/,50 SUMMatch ZZ
50Ω
0Z
OFFZLOW POWER
Splitter
• Wilkinson
• Gysel
• Hybrid
POPTZ , HIGH POWER
0Z2
0ZH
IGH
P
LO
W P
• At the current source plane we want RL→2xRL
• We don’t have access to the current source plane
• We need measured or reliably modeled load contours
Practical Circuit Load Modulation
High Power Low Power
Page 17
RL→2xRL ??
Carrier Device
Select Optimum Impedances from
measured or simulated load contours
• Identify maximum Pout load ZOPT,P
• Drive device well into compression
• Trade off a little, but not too much for
Gain, Efficiency
• Identify “carrier mode” target - ZOPT,C
• Obtain contours at Pout = Max Pout – 3dB
• Superimpose circle of VSWR = 2 centered
on ZOPT,P
• Find point of best Gain, Efficiency
Doherty Design Procedure 1
Page 18
indep(PAE_contours_p) (0.000 to 28.000)
PA
E_c
onto
urs_
p
indep(Pdel_contours_p) (0.000 to 51.000)
Pde
l_co
ntou
rs_p
Readout
ZOPTp
ZOPTp
indep(ZOPTp)=
Pdel_contours_p=0.006 / 2.590E-13
level=53.006379, number=1
impedance = 5.062 + j2.810E-16
8
indep(Pdel_contours_p) (0.000 to 39.000)
Pde
l_co
ntou
rs_p
indep(PAE_contours_p) (0.000 to 26.000)
PA
E_c
onto
urs_
p
indep(circle_of_rhos1) (0.000 to 314.000)
circ
le_o
f_rh
os1
212
0.340 / 62.934
ZOPTc
ZOPTc
indep(ZOPTc)=
circle_of_rhos1=0.340 / 62.934
impedance = Z0 * (1.097 + j0.751)
212
POUT
PAE
Z0=5Ω
Pout compressed
Pout backed off
Car
Pk
CarrierIn
PeakingIn
??4,0 CarrierOutZ
PeakingOutZ ,0
Doherty Design Procedure - 2
Page 19
Output
Match
Input
Match
POPTZ ,
COPTZ ,
HIGH POWER
LOW POWER
0Z
??2 0Z
HIGH POWER
LOW POWER
20ZZSUM
4/,50 SUMMatch ZZ
50Ω
0Z
OFFZLOW POWER
Splitter
• Wilkinson
• Gysel
• Hybrid
POPTZ , HIGH POWER
0Z2
0ZH
IGH
P
LO
W P
•Select ZSUM (i.e., Z0/2)
•If ZSUM is 50Ω, then no need for ZMatch line
•But then Z0 becomes 100Ω!
Car
Pk
CarrierIn
PeakingIn
??4,0 CarrierOutZ
PeakingOutZ ,0
Doherty Design Procedure - 3
Page 20
Output
Match
Input
Match
POPTZ ,
COPTZ ,
HIGH POWER
LOW POWER
0Z
??2 0Z
HIGH POWER
LOW POWER
20ZZSUM
4/,50 SUMMatch ZZ
50Ω
0Z
OFFZLOW POWER
Splitter
• Wilkinson
• Gysel
• Hybrid
POPTZ , HIGH POWER
0Z2
0ZH
IGH
P
LO
W P
•Design Output Match to transform Z0 to ZOPT,P
•Identical for both Carrier and Peaking
Car
Pk
CarrierIn
PeakingIn
??4,0 CarrierOutZ
PeakingOutZ ,0
Doherty Design Procedure - 4
Page 21
Output
Match
Input
Match
POPTZ ,
COPTZ ,
HIGH POWER
LOW POWER
0Z
??2 0Z
HIGH POWER
LOW POWER
20ZZSUM
4/,50 SUMMatch ZZ
50Ω
0Z
OFFZLOW POWER
Splitter
• Wilkinson
• Gysel
• Hybrid
POPTZ , HIGH POWER
0Z2
0ZH
IGH
P
LO
W P
•Design Input Match
•Simplest if identical for both Carrier and Peaking
•May tweak Peaking side later
Car
Pk
CarrierIn
PeakingIn
??4,0 CarrierOutZ
PeakingOutZ ,0
Doherty Design Procedure - 5
Page 22
Output
Match
Input
Match
POPTZ ,
COPTZ ,
HIGH POWER
LOW POWER
0Z
??2 0Z
HIGH POWER
LOW POWER
20ZZSUM
4/,50 SUMMatch ZZ
50Ω
0Z
OFFZLOW POWER
Splitter
• Wilkinson
• Gysel
• Hybrid
POPTZ , HIGH POWER
0Z2
0ZH
IGH
P
LO
W P
•Carrier Z0 output delay line
•When terminated in Z0/2 (low power mode), must present
selected ZOPT,C to Carrier device.
•Not necessarily exactly 90 degrees!
Car
Pk
CarrierIn
PeakingIn
??4,0 CarrierOutZ
PeakingOutZ ,0
Doherty Design Procedure - 6
Page 23
Output
Match
Input
Match
POPTZ ,
COPTZ ,
HIGH POWER
LOW POWER
0Z
??2 0Z
HIGH POWER
LOW POWER
20ZZSUM
4/,50 SUMMatch ZZ
50Ω
0Z
OFFZLOW POWER
Splitter
• Wilkinson
• Gysel
• Hybrid
POPTZ , HIGH POWER
0Z2
0ZH
IGH
P
LO
W P
•Peaking Z0 output delay line
•When Peaking device is off (Low Power operation), ZOFF must
be very high impedance.
Car
Pk
CarrierIn
PeakingIn
??4,0 CarrierOutZ
PeakingOutZ ,0
Doherty Design Procedure - 7
Page 24
Output
Match
Input
Match
POPTZ ,
COPTZ ,
HIGH POWER
LOW POWER
0Z
??2 0Z
HIGH POWER
LOW POWER
20ZZSUM
4/,50 SUMMatch ZZ
50Ω
0Z
OFFZLOW POWER
Splitter
• Wilkinson
• Gysel
• Hybrid
POPTZ , HIGH POWER
0Z2
0ZH
IGH
P
LO
W P
•Peaking and carrier input delay lines and splitter selection
•Whatever delays are necessary to get carrier and peaking
outputs in-phase at summing node
Doherty Design - Outline
Concept Introductions
Operational Fundamentals – Load Modulation
Doherty Design Procedure
Doherty Design Example & Results
Practical Doherty Circuit Implementation Hints
1
2
3
4
5
Page 25
GaN Device used for Design Example
RF IN
VGQ
Pin 1 (CUT)
RF OUT
VDQ
Pin 2
GND
BASE
Features
Advanced GaN HEMT Technology
Peak Modulated Power > 240W
Single Circuit for 865 – 960MHz
48V Operation Typical Performance
o Pout 47dBm
o Gain 20dB
o Drain Efficiency 39%
o ACP -31.5dBc
o Linearizable to -55dBc with DPD
Optimized for video bandwidth and minimized
memory effects
RF tested for 3GPP performance
RF tested for peak power using IS95
Large signal models available
Page 26
Doherty Design Example - 1
Page 27
indep(PAE_contours_p) (0.000 to 28.000)
PA
E_c
onto
urs_
p
indep(Pdel_contours_p) (0.000 to 51.000)
Pde
l_co
ntou
rs_p
Readout
ZOPTp
ZOPTp
indep(ZOPTp)=
Pdel_contours_p=0.006 / 2.590E-13
level=53.006379, number=1
impedance = 5.062 + j2.810E-16
8
ZOPT,P = 5.0 +j0 Ω
Pout = 53 dBm
PAE = 61%
Simulated Contours at Pin = 37 dBm
indep(Pdel_contours_p) (0.000 to 39.000)
Pde
l_co
ntou
rs_p
indep(PAE_contours_p) (0.000 to 26.000)
PA
E_c
onto
urs_
p
indep(circle_of_rhos1) (0.000 to 314.000)
circ
le_o
f_rh
os1
212
0.340 / 62.934
ZOPTc
ZOPTc
indep(ZOPTc)=
circle_of_rhos1=0.340 / 62.934
impedance = Z0 * (1.097 + j0.751)
212
Simulated Contours at Pin = 32 dBm
ZOPT,C = 5.5 +j3.8 Ω
Pout = 50 dBm
PAE = 53%
POUT 0.2 dB steps
PAE 2% steps
Car
Pk
CarrierIn
PeakingIn
??4,0 CarrierOutZ
PeakingOutZ ,0
Doherty Design Example - 2
Page 28
Output
Match
Input
Match
POPTZ ,
COPTZ ,
HIGH POWER
LOW POWER
0Z
??2 0Z
HIGH POWER
LOW POWER
20ZZSUM
4/,50 SUMMatch ZZ
50Ω
0Z
OFFZLOW POWER
Splitter
• Wilkinson
• Gysel
• Hybrid
POPTZ , HIGH POWER
0Z2
0ZH
IGH
P
LO
W P
•Select ZSUM = 12.5Ω
•Z0 = 25Ω
Car
Pk
CarrierIn
PeakingIn
??4,0 CarrierOutZ
PeakingOutZ ,0
Doherty Design Example - 3
Page 29
Output
Match
Input
Match
POPTZ ,
COPTZ ,
HIGH POWER
LOW POWER
0Z
??2 0Z
HIGH POWER
LOW POWER
20ZZSUM
4/,50 SUMMatch ZZ
50Ω
0Z
OFFZLOW POWER
Splitter
• Wilkinson
• Gysel
• Hybrid
POPTZ , HIGH POWER
0Z2
0ZH
IGH
P
LO
W P
•Design Output Match to transform Z0 to ZOPT,P
•Identical for both Carrier and Peaking
Doherty Design Example - 3
Page 30
•Design Output Match to transform Z0 to ZOPT,P
freq (860.0MHz to 960.0MHz)
S(1
,1)
Readout
m3
S(2
,2)
m3
freq=
S(1,1)=0.007 / 85.104
impedance = 5.006 + j0.073
900.0MHz
Doherty Design Example - 4
Page 31
•Design Input Match
•Simplest if identical for both Carrier and Peaking
Doherty Design Example - 4
Page 32
•Check Class AB and Class C Response of input match
f req (700.0MHz to 1.100GHz)
S(1
,1)
0.75 0.80 0.85 0.90 0.95 1.00 1.050.70 1.10
-15
-10
-5
-20
0
14
15
16
17
18
13
19
freq, GHz
dB
(S(1
,1))
dB
(S(2
,1))
f req (700.0MHz to 1.100GHz)
S(1
,1)
0.75 0.80 0.85 0.90 0.95 1.00 1.050.70 1.10
-20
-15
-10
-5
-25
0
-1.0
-0.5
0.0
-1.5
0.5
freq, GHz
dB
(S(1
,1))
dB
(S(2
,1))
Class AB
VGG= -3.06V
IDQ = 600 mA
Class C
VGG= -5.06V
IDQ = 0 mA
Doherty Design Example - 5
Page 33
•Carrier Z0 output delay line
•When terminated in Z0/2 (low power mode), must present
selected ZOPT,C to Carrier device.
•Not necessarily exactly 90 degrees!
20ZZSUM
Doherty Design Example - 5
Page 34
•ZOPT,C is nearly perfectly nailed with ZERO δCarrierOut.
•This is not a general result
•This means no line is needed. How is this possible?
indep(Pdel_contours_p) (0.000 to 39.000)
Pde
l_co
ntou
rs_p
indep(PAE_contours_p) (0.000 to 26.000)
PA
E_c
onto
urs_
p
indep(circle_of_rhos1) (0.000 to 314.000)
circ
le_o
f_rh
os1
212
0.340 / 62.934
ZOPTc
ZOPTc
indep(ZOPTc)=
circle_of_rhos1=0.340 / 62.934
impedance = Z0 * (1.097 + j0.751)
212
ZOPT,C = 5.5 +j*3.8 Ω
Recall our loadpull:
freq (860.0MHz to 960.0MHz)
S(1
,1)
Readout
m1
m1freq=S(1,1)=0.336 / 67.991E_len=0.000000impedance = 5.151 + j3.620
900.0MHz
ZL (12.500 to 25.000)
zto
s(Z
L,5
)
freq (860.0MHz to 960.0MHz)
S(1
,1)
Doherty Design Example - 5
Page 35
•The PCB match itself provides the required impedance inversion from
ZOPT,P to ZOPT,C! •The combination of PCB match, package, bond wires, and CDS parasitics
constitutes the 90 degree shift that allows RL -> 2xRL at the current source
plane when summing node Z goes 25Ω -> 12.5Ω.
•The only reference planes that really matter are the
devices’ current generators and the summing node
ZOPT,C
ZOPT,P
12.5Ω 25Ω
Doherty Design Procedure - 6
Page 36
•Peaking Z0 output delay line
•When Peaking device is off (Low Power
operation), ZOFF must be very high
impedance.
•Required δPeakingOut is almost exactly
90 degrees
•Inverted Doherty?
freq (900.0MHz to 900.0MHz)
S(2
,2)
Readout
m1
m1freq=S(2,2)=0.922 / 2.472E_len=90.000000impedance = 480.442 + j254.772
900.0MHz
Doherty Design example - 7
Page 37
•Select Peaking and carrier input delay
lines and splitter selection
•According to our design so far, there is
exactly 90 degree difference between
peaking and carrier path lengths on the
output side.
•An off-the-shelf, surface mount, 90
degree 3dB hybrid is a space efficient
option at 900 MHz
•Let’s use one, connect 0 deg to the
peaking and -90 deg to the carrier and
be done with it!
Doherty Design example - 8
Page 38
38 40 42 44 46 48 50 52 54 5636 58
14
16
18
12
20
VGG_DIFF=0.000VGG_DIFF=0.750VGG_DIFF=1.500VGG_DIFF=2.250
VGG_DIFF=3.000VGG_DIFF=3.750
Fund. Output Power, dBm
Transducer Power Gain, dB
38 40 42 44 46 48 50 52 54 5636 58
20
40
60
0
80
VGG_DIFF=0.000VGG_DIFF=0.750VGG_DIFF=1.500VGG_DIFF=2.250VGG_DIFF=3.000VGG_DIFF=3.750
Fund. Output Power, dBm
PAE, %
• Put it all together!
• HB 1-tone
simulation results • Vdd = 48V
• Freq = 910 MHz
• Delta VGC – VGP swept
from 0V to -3.75V
Doherty Design example - 9
Page 39
Ideal TLINE,
MLINE, etc.
Verify with Momentum
Simulation
Fabricate Circuit
Measured CW Efficiency, Gain
Freq = 895 MHz
Vdd = 48V
Power limited by
current capability
of lab VDD supply
800-1000 MHz Broadband WCDMA Performance
•No DPD correction
•Peak Output Power
measured at 0.01%
probability on CCDF
•Vdd = 48V
•Carrier Idq = 650 mA
•Peaking-Carrier delta
VGG = -3V
•Avg Pout = 50 dBm
Doherty Design - Outline
Concept Introductions
Operational Fundamentals – Load Modulation
Doherty Design Procedure
Doherty Design Example & Results
Practical Doherty Circuit Implementation Hints
1
2
3
4
5
Page 42
Practical Implementation hints
Page 43
• RF Tuning
• Phase adjustment Give yourself options!
Practical Implementation hints
Page 44
• Move coupling
capacitors to
bypass splitter /
summing node
• Test carrier and
peaking halves
independently
Summary
• The Doherty Amplifier topology can provide efficiency
benefits
• GaN-on-SiC technology has significant benefits
• Ideal theory requires numerous extensions and
adjustments to work in practice
• Understanding basics and following correct procedure
leads to functional solution
Page 45
Do You Have
Any Questions?
Page 46
Further Reading
Cripps, S., RF Power Amplifiers for Wireless
Communications, Artech House, 1999, pp. 225-235
Grebennikov, A., Bulja, S.,“High-Efficiency Doherty Power
Amplifiers: Historical Aspect and modern Trends” Proc
of IEEE, Vol. 100, No. 12, Dec. 2012, pp. 3190-3219
Page 47
Acknowledgements
David Runton
Michael LeFevre
Matt Mellor
Rod Miller
Bob Davidson
Basim Noori
Page 48
Appendix: Measured WCDMA Performance with DPD
3GPP WCDMA signal
with 7.5 dB Peak-to-
Average ratio
Digital Pre-distortion
algorithm:
7th order polynomial
with 3 memory taps
Vdd = 48V
Carrier Idq = 650 mA
Freq = 895 GHz
NO DPD
DPD ON
•DPD ON
•Peak Output Power measured
at 0.01% probability on CCDF
•Vdd = 48V
•Carrier Idq = 650 mA
•Freq = 895 GHz
Appendix: Measured WCDMA Performance with DPD
Appendix: Load modulation in simulation captured dynamically
Create an ideal directional
coupler
Use it to probe dynamic
impedances at various points
in circuit in HB simulations
RFpower (20.000 to 42.500)
zto
s(P
kZ
su
m.Z
L,2
5)
zto
s(C
arZ
su
m.Z
L,2
5)
RFpower (20.000 to 42.500)
zto
s(P
kZ
pkg
.ZL
,Zre
f1)
zto
s(C
arZ
pkg
.ZL
,Zre
f1)
Appendix: Load modulation in simulation captured dynamically
Z0=25Ω
Z0=5Ω
Carrier and
Peaking
impedances vs.
VGS,PK and Pin
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