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CIS 020 Assembly Programming
Chapter 14 - Instruction Formats &
Interrupt Codes forDEBUGGING PROGRAMS
© John Urrutia 2012, All Rights Reserved.5/27/2012 1
ObjectivesInstruction Formats – how mnemonics are
translatedDecoding The PSW and what it can tell youCommon system interrupt codes and what
they really meanThe System ABEND Dump
© John Urrutia 2012, All Rights Reserved. 25/27/2012
Standard Instruction FormatsEach instruction is in one of 26 basic formats:
E, I, RI, RIE, RIL, RIS, RR, RRD, RRE, RRF, RRS, RS, RSI, RSL, RSY, RX, RXE, RXF, RXY, S, SI, SIL, SIY, SS, SSE, and SSF, with two variations of RRF, RS, RSY, RX, and RXY, three of RI and RIL, and six of RIE and SS.
45 formats in all.We will only examine the most common with
their variations.
© John Urrutia 2012, All Rights Reserved. 35/27/2012
Instruction lengthsEvery Instruction is:
2, 4, or 6 bytes in length or 1, 2, or 3 halfwords respectively.
Consists of an Operation Code (Op Code) & one or more operands.
The size of the instruction is embedded in the Operation Code in bits 0 and 1.00 – 2 bytes - Register to Register01 or 10 – 4 bytes - Register to Storage11 – 6 bytes - Storage to Storage
© John Urrutia 2012, All Rights Reserved. 45/27/2012
Reference - zArchitecturezArchitecture Principles of Operations.pdf
figure 7.1 – 7-13 thru 7-24
© John Urrutia 2012, All Rights Reserved. 55/27/2012
RR – Register to RegisterRR – are the fastest instructions.2 Byte instruction Length with the coding
format
Translates to
© John Urrutia 2012, All Rights Reserved. 65/27/2012
RR Op Code R1 R20-7 8-11 12-15 16-19 32-35
First Halfword Second Halfword
OPERATION OPERANDS10 16
M R R 6 , R 8
B'0001 1100 1010 1000'X' 1 C 6 8'
RS – Register to StorageRS – Transfer data between a register and
storage.4 Byte instruction Length with the coding
format
Translates to© John Urrutia 2012, All Rights Reserved. 75/27/2012
B'1001 0000 1110 1100 1101 0000 0000 1100'X' 9 0 E C D 0 0 C'
OPERATION OPERANDS10 16
S T M 1 4 , 1 2 , 1 2 ( 1 3 )
RS
Op Code R1 R3 B2 D2Bits 0-7 8-11 12-15 16-19 20-31
First Halfword Second Halfword
RX – Register to Indexed StorageRX – Transfer control by mask to storage
address .4 Byte instruction Length with the coding
format
Translates to© John Urrutia 2012, All Rights Reserved. 85/27/2012
B'0100 0111 1111 0101 0110 0011 1111 1000'X' 4 7 F 5 6 3 E 8'
OPERATION OPERANDS10 16
B C 1 5 , 1 0 0 0 ( 5 , 6 )
RX
Op Code M1 R3 B2 D2Bits 0-7 8-11 12-15 16-19 20-31
First Halfword Second Halfword
RX – Register to Indexed StorageRX – Transfer data between a register and
storage.4 Byte instruction Length with the coding
format
Translates to© John Urrutia 2012, All Rights Reserved. 95/27/2012
B'0100 0000 0100 0101 0110 0011 1111 1000'X' 4 0 4 5 6 3 E 8'
OPERATION OPERANDS10 16
S T H 4 , 1 0 0 0 ( 5 , 6 )
RS
Op Code R1 R3 B2 D2Bits 0-7 8-11 12-15 16-19 20-31
First Halfword Second Halfword
SI – Storage ImmediateSI –Data imbedded in instruction to storage.4 Byte instruction Length with the coding
format
Translates to
© John Urrutia 2012, All Rights Reserved. 105/27/2012
B‘1001 0101 0110 1111 0110 0011 1111 1000'X' 9 5 6 F 6 3 E 8'
OPERATION OPERANDS10 16
C L I 1 0 0 0 ( 5 , 6 ) , C ' ? '
RS
Op Code I2 B2 D2Bits 0-7 8-15 16-19 20-31
First Halfword Second Halfword
Storage to Storage InstructionsLeast efficient instructionsSS Formats
© John Urrutia 2012, All Rights Reserved. 115/27/2012
SS
Op Code B1 D1 B2 D2Bits 0-7 16-19 20-31 32-35 36-47
L1 L2 B1 D1 B2 D28-11 12-15 16-19 20-31 32-35 36-47
L1 I3 B1 D1 B2 D28-11 12-15 16-19 20-31 32-35 36-47
First Halfword Second Halfword Third Halfword
L18-15
SS – Storage to StorageSS – Storage to Storage, Character Format6 Byte instruction Length with the coding
format
Translates to
© John Urrutia 2012, All Rights Reserved. 125/27/2012
B‘1101 0010 1111 1111 0101 0000 0000 1100 0110 0000 0000 0000'X' D 2 F F 5 0 0 C 6 0 0 0'
OPERATION OPERANDS10 16
M V C 1 2 ( 2 5 5 , 5 ) , 0( 6 )
SS
Op Code B1 D1 B2 D2Bits 0-7 16-19 20-31 32-35 36-47
First Halfword Second Halfword Third Halfword
L18-15
SS – Storage to StorageSS – Storage to Storage, Packed Decimal
Format6 Byte instruction Length with the coding
format
Translates to© John Urrutia 2012, All Rights Reserved. 135/27/2012
B‘1111 0010 0011 0110 0101 0000 0000 1100 0110 0000 0000 1000'X' F 2 3 6 5 0 0 C 6 0 0 8'
OPERATION OPERANDS10 16
P A C K 1 2 ( 4 , 5 ) , 8 ( 7 , 6 )
SS
Op Code L1 L2 B1 D1 B2 D2Bits 0-7 8-11 12-15 16-19 20-31 32-35 36-47
First Halfword Second Halfword Third Halfword
SS – Storage to StorageSS – Storage to Storage, Shift Packed
Decimal Format6 Byte instruction Length with the coding
format
Translates to© John Urrutia 2012, All Rights Reserved. 145/27/2012
B‘1111 0010 0011 0100 0101 0000 0000 1100 0000 0000 0000 0011'X' F 0 3 4 5 0 0 C 6 0 0 3'
OPERATION OPERANDS Shift Rounding10 16 Number Digit
S R P 1 2 ( 4 , 5 ) , 3 ( 0 ) , 5
SS
Op Code L1 I3 B1 D1 B2 D2Bits 0-7 8-11 12-15 16-19 20-31 32-35 36-47
First Halfword Second Halfword Third Halfword
Program Interrupts & the PSWProgram interrupts occur when you tell the
system to do something it can’t.Old School – System simply stops workingToday – System is built with redundancy and
continues to work while suspending your program execution
When an interrupt occurs, generally your program is terminated with an appropriate system code.
There are 5 types of interrupts
© John Urrutia 2012, All Rights Reserved. 155/27/2012
Program Interrupts & the PSWThere are 5 types of interrupts
External – caused by an action outside of the system.
I/O problem – external or internal associated with I/O subsystem
Program – caused by a faulty instruction or address
Machine – hardware, faulty circuit or equipment
Supervisor – caused by an error detected by the Supervisor Program.
© John Urrutia 2012, All Rights Reserved. 165/27/2012
Program Interrupts & the PSWThe PSW – Program Status Word
Identifies the state of the system at the time the interrupt occurred.
z390 PSW Consists of the following informationPSW=07050600 800FFFDA D2030000D088 MVC ABEND S0C5
© John Urrutia 2012, All Rights Reserved. 175/27/2012
0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
0 R 0 0 0 TIOEX
1 M W PEA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Key AS CCProgramMask
000000
07 05 06 00
Program Interrupts & the PSWThe PSW – Program Status Word
First Word – System statusPSW=07050600 800FFFDA D2030000D088 MVC ABEND S0C5
© John Urrutia 2012, All Rights Reserved. 185/27/2012
0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
0 R 0 0 0 TIOEX
1 M W PEA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Key AS CCProgramMask
000000
07 05 06 00
Program Interrupts & the PSWThe PSW – Program Status Word
Second Word – Address of next instruction to execute
PSW=07050600 800FFFDA D2030000D088 MVC ABEND S0C5
© John Urrutia 2012, All Rights Reserved. 195/27/2012
1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0
BA0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
80 0F FF DA
Program Interrupts & the PSWThe PSW – Addressing bits 31 &32
When bits 31 and 32 are both zero, 24-bit addressing
When bit 31 is zero and bit 32 is one, 31-bit addressing
When bits 31 and 32 are both one, 64-bit addressing
Next instruction to executeMnemonic
ABEND CodePSW=07050600 800FFFDA D2030000D088 MVC ABEND S0C5
© John Urrutia 2012, All Rights Reserved. 205/27/2012
In Class ExerciseExplain why each of the programs located inH:\Coursework\CIS 20 - Assembly Programming\
Assembly Files\Ch14ABENDs
experiences an ABEND.Explain what needs to be done to correct
these.Use your book and/or the POPS manual.
© John Urrutia 2012, All Rights Reserved. 215/27/2012