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Copyright © 2016 PCI-SIG® - All Rights Reserved

PCIe® CEM 4.0 Previews

o Dan Froelich

o CEM Workgroup Chair

o Intel Corporation


2Copyright © 2016 PCI-SIG® - All Rights ReservedPCI-SIG Developers Conference 2016

Disclaimer

The information in this presentation refers to specifications

still in the development process. This presentation reflects

the current thinking of various PCI-SIG® workgroups, but all

material is subject to change before the specifications are

released.



Agenda

o PCIe® 4.0 CEM Goals

o PCIe 4.0 CEM Connector Direction

o PCIe 4.0 Tx Limits and Test Fixtures

o Summary and Conclusions



PCI Express® 4.0 CEM Goals

o Full backwards interoperability with PCIe 1.x, PCIe 2.x,

PCIe 3.x

o Same channel reach as for PCIe 3.0 with improvements • Client: 10-14 inch, one connector

• Server: 20 inch, two connectors – requires a Retimer

o Minimize required changes to the connectors, card form

factors, or material

o Minimal changes to the measurement methodologies

from those used in the PCIe 3.x specifications

• Use eye diagrams (jitter/voltage margin requirements). Minimize

additional new requirements.



Minimum 4.0 Target

Connector Performance

High Degree of Confidence That Backwards Compatible Solutions Possible



4.0 Connector/Card Goals

o Mitigate conductor geometry that impairs performance in the PCIe connector at 16GT/s

o Preserve full backwards compatibility among combinations of 2.5-5-8-16 GT/s connectors and Add-in Cards (AIC)

o Keep the standard thru-hole pinfield, for thru-hole parts (if possible)

o Define a common surface mount connector footprint and related specifications

o Build test boards and characterize and correlate models for the proposed performance enablers



Enabler Impact on

Insertion Loss

o Resonant stubs on single ground traces

o Some resonant behavior still present at higher frequency

• Stub design should be optimized in simulation



Enabler Impact on Crosstalk

o Resonant structures help suppress peak

ground resonances by as much as 20dB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Freq [GHz]

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Diffe

ren

tia

l N

EX

T a

nd

FE

XT

Cro

ssta

lk, d

B

NEXT FEXT 96 0Flip Horseshoe Causal

Improved Lane 0↔1

Improved Lane 1↔2

Improved Lane 0↔2

Baseline 1↔2



Connector Enabler Conclusion

o These enablers indicate that a thru-hole solution is

feasible with the same motherboard pinout as 3.0

o CEM 4.0 references both approaches

(improvements to work with existing thru-hole

pinout vs SMT connectors)

o Current plan for 4.0 CEM is to support and specify

both thru-hole and SMT connectors for 4.0

o Built test boards to obtain lab data for each

potential enabler with both through-hole (PTH) and

surface mount (SMT) connectors



Signal & Ground Pin Assignment

o The pin assignments in the

connector are non-uniform

• Note that the quantity of ground pins

(Black) adjacent to the diff pairs are

“Single” or “Double”

• The electrical behavior of pairs having

“Single” or “Double” grounds differs

• Test board experiments target single or

double ground, or a combination

Single

Single

Single

Do

ub

le

Do

ub

le

Sideb

and

Sideb

and

PairTx0

PairTx1

PairTx2



PCIe 4.0 Experiments

On the Add-in Card PCB:

1. Baseline Typical 8GT/s

2. Adjacent ground vias (required)

3. Join the ground edge fi

4. Narrow the ground fingers• Improves overall insertion loss

• Ground finger resistive termination

5. Ground finger resistive termination• Suppresses all resonance

6. Place floating subsurface resonant structures beneath ground fingers• Suppresses resonant insertion

loss/crosstalk spikes

7. Multi enabler experiments

Baseboard & Connector changes:

1. Surface mount connector

2. Thru Hole with stub

3. Thru Hole with no stub

4. Thru Hole with via stub mitigation • Reduces baseboard PCB via resonance



1.30 CHAMFER REGION

4.30

0.70

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

2.00 1.00

Ground traces are 10 mils wide after finger

Ground vias10 mil Drill (0.254mm)20 mil Pad

7.85

4.40

Connector body 2.2mmabove point of contact,

7.85 mm above board edge

2.25

5.60

3.91

Test Layout 1: Baseline

o The trace between the via and ground finger is not addressed in the CEM spec

o The length, width, and shape of the ground trace has been implementation specific

o The ground traces, above the ground finger, may be straight, like here ↗ or hockey-stick, etc.

o For this baseline test, use these common PCIe 3.0 edge finger dimensions

• 2mm long, 0.508mm (20 mil) wide ground trace, as shown

Sin

gle

Sin

gle

Sin

gle

Do

ub

le

Do

ub

le

Ground traces areunconstrained in spec



Baseboard –

Thru-hole, No Via Stub

o AIC Baseline cluster. No improvements to card.

o FEXT/NEXT

spike near

7-8GHz

CHAMFER REGION

0.70

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

2.00 1.00


Ground vias10 mil Drill (0.254mm)18 mil pad



2.25

0.39

TX

4P

TX

4N

GR

OU

ND

2 4 6 8 10 12 14 16 180 20

-25

-20

-15

-10

-5

-30

0

freq, GHz

dB

(S( 1

, 2))

dB

(S( 3

, 4))

dB

(S( 5

, 6))

Differential Deembedded THRU 85 Ohm

1 2 3 4 5 6 7 8 9 10 110 12

-4

-3

-2

-1

-5

0

freq, GHz

dB

(S( 1

, 2))

dB

(S( 3

, 4))

dB

(S( 5

, 6))

m1Differential Deembedded THRU 85 Ohm

m1freq=dB(S(1,2))=-1.168dB(S(3,4))=-1.216dB(S(5,6))=-1.079

8.010GHz

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 190 20

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

0

freq, GHz

dB

(S( 1

, 4))

dB

(S( 1

, 6))

dB

(S( 3

, 6))

dB

(S( 2

, 3))

dB

(S( 2

, 5))

dB

(S( 4

, 5))

m2m6Differential Deembedded FEXT 85 Ohm

m2freq=dB(S(1,4))=-31.946dB(S(1,6))=-34.536dB(S(3,6))=-21.102dB(S(2,3))=-31.599dB(S(2,5))=-41.897dB(S(4,5))=-21.010

7.060GHz


7.410GHz

2 4 6 8 10 12 14 16 180 20

-80

-60

-40

-20

-100

0

freq, GHz

dB

(S( 1

, 3))

dB

(S( 3

, 5))

dB

(S( 1

, 5))

dB

(S( 2

, 4))

dB

(S( 2

, 6))

dB

(S( 4

, 6))

m5Differential Deembedded NEXT 85 Ohm


5.860GHz



Test Layout 2:

Adjacent Ground Vias

o Test 2a One via per finger• Fewest drills

• Not joining adjacent grounds

• Vias must fall between fingers to permit the escape of signals on the back side

• Most vias are reused by the ground fingers on the reverse side of the PCB

o Test 2b Two vias per finger• More drills, risk of mechanical

weakening

• Adjacent grounds are joined

• Additional vias for backside doubles shown

1mm pitch with 10 mil drills results in 25% reduction in

PCB “web” width (vs. no vias) ↓

1.30

5.60

CHAMFER REGION

4.40

FULL GROUND PLANE

3.45

7.85

RES

ERV

ED

GR

OU

ND

TX0

P

TX0

N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX1

P

TX1

N

TX2

P

TX2

N

GR

OU

ND

GR

OU

ND

GR

OU

ND

0.39

0.70 1.00

1.30

5.60

CHAMFER REGION

4.30

0.70FULL GROUND

PLANE1.00

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PR

ESEN

T

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

0.39

3.91



Test Layout 2:

Adjacent Ground Vias

o Test 2c One via per finger• Fewest drills

• Join Adjacent Grounds• But no middle drill

o Test 2d Very long ground connection

• Worst case 6.3mm, taken from real-world layout

Note, most vias are reused by the Rx side grounds on the

reverse side of the PCB

1.30

5.60

CHAMFER REGION

4.30

FULL GROUND PLANE1.00

RE

SER

VE

D

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PR

ESE

NT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

0.39

3.91

0.70

1.30 CHAMFER REGION

4.30

0.70

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX0

P

TX0

N

GR

OU

ND

PR

ESEN

T

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX1

P

TX1

N

TX2

P

TX2

N

GR

OU

ND

GR

OU

ND

GR

OU

ND

6.30

1.00


7.85

4.40



2.25

5.60

3.91

0.39



Baseboard –

Thru-hole, No Via Stub

o Improved AIC Test

• Lower ground

• Joined double Gnd

CHAMFER REGION

FULL GROUND PLANE

RES

ERV

ED

GR

OU

ND

TX

0P

TX

0N

GR

OU

ND

PRES

ENT

GR

OU

ND

GR

OU

ND

GR

OU

ND

TX

1P

TX

1N

TX

2P

TX

2N

GR

OU

ND

GR

OU

ND

GR

OU

ND

1.00

Ground vias10 mil Drill (0.254mm)18 mil pad



0.39

TX

4P

TX4

N

GR

OU

ND

0.70

FULL GROUND PLANE

Good suppression of FEXT/NEXT

2 4 6 8 10 12 14 16 180 20

-25

-20

-15

-10

-5

-30

0

freq, GHz

dB

(S( 1

, 2))

dB

(S( 3

, 4))

dB

(S( 5

, 6))

Differential Deembedded THRU 85 Ohm

1 2 3 4 5 6 7 8 9 10 110 12

-4

-3

-2

-1

-5

0

freq, GHz

dB

(S( 1

, 2))

dB

(S( 3

, 4))

dB

(S( 5

, 6))

m1Differential Deembedded THRU 85 Ohm

m1freq=dB(S(1,2))=-0.944dB(S(3,4))=-0.941dB(S(5,6))=-0.826

8.010GHz

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 190 20

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

0

freq, GHz

dB

(S( 1

, 4))

dB

(S( 1

, 6))

dB

(S( 3

, 6))

dB

(S( 2

, 3))

dB

(S( 2

, 5))

dB

(S( 4

, 5))

m2m3Differential Deembedded FEXT 85 Ohm


7.060GHz


7.410GHz

2 4 6 8 10 12 14 16 180 20

-80

-60

-40

-20

-100

0

freq, GHz

dB

(S( 1

, 3))

dB

(S( 3

, 5))

dB

(S( 1

, 5))

dB

(S( 2

, 4))

dB

(S( 2

, 6))

dB

(S( 4

, 6))

m6Differential Deembedded NEXT 85 Ohm


5.860GHz


17Copyright © 2016 PCI-SIG® - All Rights ReservedPCI-SIG Developers Conference 2016 17

Sideband Signal Termination

o If the floating conductors are terminated with an open circuit, they can

resonate, as they couple energy in/out of their neighbors

• Multiple reflections will manifest as a spike at the resonant frequency

• Similar results with a short circuit

Crosstalk spikes in the middle of the Gen4 band

Corresponding insertionloss dropouts

Color code for crosstalk Lane 0 ↔ Lane 1Lane 1 ↔ Lane 2Lane 0 ↔ Lane 2



Cross-talk w/wo Termination

Measured With/Without Termination

No termination resistors

Resistors onboth ends

Resistors on one end(add in card only)

Color code for crosstalk Lane 0 ↔ Lane 1 Lane 1 ↔ Lane 2 Lane 0 ↔ Lane 2


Copyright © 2016 PCI-SIG® - All Rights ReservedPCI-SIG Developers Conference 2016

Compare 120 mil vs.

62 mil Baseboard

Thicker board has higher FEXT & lower resonant frequency

Additional resonance at ~2x the frequency

Additional resonance at ~2x the frequency

120 mil baseboard 062 mil baseboard



Pinfield Ground

via Insufficiency

o Another perspective:

• Blue differential pair has four ground vias (typical pattern)

• Green differential pair has three ground vias & one sideband via

• Red differential pair has two ground vias and two sideband vias

• High speed

differential pairs

adjacent to sideband

signals don’t have as

many ground pins.Two groundsTwo sideband

Three groundsOne sideband

Four Grounds



Add 2 Baseboard Ground Vias

o Adding two vias per sideband pin improves the worst case FEXT

• Lane 0 ↔ Lane 1 FEXT drops by about 4.5dB across much of the 0-8 GHz band

• Lane 1 ↔ Lane 2 largely unaffected Lane 0 ↔ Lane 2 are

Baseboard Vias alone 62 mil BoardDashed: Baseline, no extra grounds

Solid: Two extra ground vias per pin

Color code for crosstalk Tx Lane 0 ↔ Tx Lane 1Tx Lane 1 ↔ Tx Lane 2Tx Lane 0 ↔ Tx Lane 2



Improved Baseboard

FEXT – 120 mil

o Thicker 120 mil 4-layer baseboard pinfield

• No connector, PCB Only

• Two added ground vias for each sideband signal can dramatically reduce FEXT in the thicker board across the whole frequency band

Dashed: Baseline 120Mil board, no extra ground vias

Solid: Same board + two ground vias per sideband

Color code for crosstalk Tx Lane 0 ↔ Tx Lane 1Tx Lane 1 ↔ Tx Lane 2Tx Lane 0 ↔ Tx Lane 2



Complete Connector

with Baseboard

o 8GHz Lane 0-1 FEXT is

improved from:

29.1 dB - baseline 120mil

baseboard

to

34.9 dB - 120 mil baseboard + 2

gnd vias

o The improvement is across

the whole band

BaseNo extra ground viasline 62Mil board• 42.5Ω Sideband termination resistors

Same 62Mil board stackup• Two sentry vias per pin

Mitigating Sideband/Reserved Cross-talk Important



Required Connector

Enabler Summary

o Adjacent Add-in Card Ground Vias (15 mil)

• Joined double grounds

o Sentry Vias in the Base Board Pinfield (min 2)

o Ac Sideband Termination on Add-in Cards

24

Minor PCB Changes Enable 3.0 Through-Hole CEM Connector to Work for 4.0



PCI Express 3.0/4.0

Channel Analysis

o Client• Motherboard and adapter

• 1 PCIe connector

• No vias other than connector

• Routed as mstrip

• Channel length: ~10-14”

o Server• Motherboard, riser card, and adapter

• 2 PCIe connectors

• Several vias on motherboard

• Routed primarily as stripline

• Channel length: ~20”

• Requires Retimer for 16GT/s

o Channel analysis includes corner cases

Seg Description

A MCH PKG (transmitter)

B Break Out

C MB Main 7”

D MB post cap

E Add in card main 3”

F Add in card PKG Break out

G Add in card PKG (receiver)

ACB

DE

G

FTypical Client topology

2 Connector Server topology

PCIe 4.0 targets support for the same channels and lengths as PCIe 3.0

Longest 2 connector channels will require Retimer



CEM MB Tx

Test Fixture Topology

4” test fixture

CEM spec pathfinding work showed better correlation with worst case E2E results with fixture with package model on test fixture

Parameters shown for current CEM 3.0 CLB

4.0 CLB Potential Changes

Package model will change to ~.3/.4 pf Cpad

Trace length could be reduced from 4”

CPAD

.8 pfCPIN

.25 pf

Package Parameters

CPAD = .8 pf

CPIN = 0.25 pf

Len = 1.3”

Z0 = 85 Ohms

T-line defined by

length, Z0, fixed/unit length loss

Source: Intel Corporation

Base Spec RX Package Structure



Calibrating Stressed Eye:

Base Rev 0.5 Direction

16 GT/s PRBS Generator

Combiner Test EquipmentReplica Channel

CEM Connector

Fixed TX EQ

TP1 TP2

Post Processing Scripts:Rx pkg modelBehaviorial CTLE/DFEBehavioral CDR

TP2P

Rj Source

Sj Source

Diff Interfer

ence

CM Interfer

ence

Calibration ChannelEH or EW Adjust

Small EW Adjust

Small EH Adjust

25 mV / .3 UI at E-12 BER15 mV / .3 UI at E-12 BER



CEM 4.0 Tx Limits –

System Tx Example

o Reduce noise from 14mv to 10mV

o Simulate to find System TX 4.0 CEM Eye

o This gives the System TX CEM Eye using a simplified approach

.093”

REF

CAP

THM

.06

2

4.0”

ref

3070

10.0”

800mV

3.0dB

P7, CTLE adaptive

0.25UI Jitter + 0.7ps CLK

.093”

REF

CAP

THM

.06

2

4.0”

3070

CBB variable length

5dB

BERT

CLB

85 ohm

Replica channel4.0”

Low loss PCB,

Micro-vias

800mV, P7, CTLE adaptive

0.25UI Jitter + 0.7ps CLK (same as full link) no injected voltage noise

“Card”

“MB”

Real channel(shown reference packages)

Reduced noiseno AIC noise

8mV(14-2)*70%

4mV(14-2)*30%

2mv

14mv DM Eye: 15mV\0.3UI10mv DM Eye: 19mv\0.352UI



System Rx Calibration Model

0.24 dB7.74 dB

CLB

CBB

Nominal 0.9 dBcable from signal generator

Nominal 0.9 dBcable to scope

3.24 dB nominal loss CLB variable ISI channel (including 150mm cable)

3.86 dB CLB Rx trace matched across all lanes

3.54 dB CBB Tx trace matched across all lanes

1.4 dBconnector

14.16 dB nominal loss, CBB variable ISI board (including 150 mm cables)

11.16 dB17.16 dB



Add-in Card Rx Calibration Model

30

11.16 dB17.16 dB

CLB

CBB

Nominal 0.9 dB cable from signal generator

Nominal 0.9 dBcables to scope

14.16 dB nominal loss, variable ISI channel

3.547 dB CBB Rx trace matched across all lanes

1.4 dBconnector

2.36 dB CLB Txtrace matched across all lanes



PWRBRK ECR

Available for Member Review



Summary and Conclusions

o CEM Connector must improve for PCIe 4.0 at 16GT/s• Add-in card PCB enablers for existing PTH connector

• SMT connectors

o Direction to support existing PTH connectors with add-in card improvements and SMT connectors pending connector test board data

o Same channel reach as for PCIe 3.0• Client: 14 inch, one connector

• Server: 20 inch, two connectors – with a Retimer

o Direction to make CEM reference channel same as Base RX stressed eye channel for 4.0

• CEM RX call channel/limits match Base RX without need for CEM simulation process

o For latest PCIe 4.0 specifications, visit www.pcisig.com

• 0.5 CEM 4.0

• PWRBRK ECR

http://www.pcisig.com/



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