Closed-form oriented loop Compensator design for peak current-mode controlle DC/DC regulators

J.-J. Shieh

Abstract: A formulated stepwise closed-form loop compensator design procedure for peak current- mode control DC/DC regulators is presented. As a result, a conventional computer software program such as Excel 5.0 can be used to systemise to increase the efficiency of the design process. A prototype hardware circuit is constructed and some simulation and experimental results are presented.

1 Introduction

It is desirable that controls for regulators should meet the following criteria: first, audio susceptibility and output impedance must be less than a specified maximum; secondly, as a step load change, the setting time and peak overshoot of dynamic response must be less than a specified maximum; and finally, the regulator must be stable under all possible component variations. To achieve the above objectives, multiloop control has become widely used in switching regulators with the advent of current-mode control (CMC) [l-71. Two approaches are commonly implemented as control strategies for CMC. One is averaged current-mode control (ACMC) [2, 8-1 11, and the other is peak current-mode control (PCMC) [4-7, 12, 131. ACMC has several advantages such as the elimination of the external compensation ramp to stabilise the current loop, increased low frequency current loop gain and improved noise immunity [7, 81. However, these merits are achieved at the expense of an increased complexity in the design and analysis. Additionally, the inductor current has a large ripple. The standard ACMC cannot always predict the accurate system behaviour because the so-called small ripple assumption may not be valid thus leading to inaccurate loop compensator design. Some controller designs for ACMC have been proposed to reduce or eliminate the ripple effects [9-111. However, the analysis and design of the regulator is still rather elaborate. In contrast, PCMC has some inherent characteristics such as automatic feedforward compensation and pulse-by-pulse current limit- ing [4-7, 12, 131. Hence, PCMC is widely used in hgh- performance regulators to achieve regulated output voltages [47 , 14, 151. Although the state-space averaging technique has been widely used for well over a decade to model the small-signal behaviour of CMC switching regulators [13, 161, the closed-form orientation is still needed to gain sufficient insight to design the system. This often includes simplifying the construction, tuning and maintenance of the control schemes and assessing the basic capabilities and

0 IEE, 2003 IEE Proceeclings online no. 20030010 doi: IO. 1049/ip-epa:20030010 Publication date: 6th March 2003. Paper first received 20th June 2002 The author is with the Department of EkCtnCdl Engineering, Ta Hwa Institute of Technology. Chunglin. Hsinchu, Taiwan, 30740, Republic of China

limitations in control designs intended for high performance with adequate robustness and safety margins [14, 17, 181. Hence, closed-form loop compensator design is still very attractive even though several applications of advanced adaptive and nonlinear control techniques have been explored [15, 19-23].

2 Small-signal modelling of PCMC

Several assumptions are considered as the models are derived: (i) continuous inductor current conductions; (ii) ideal switching derives; (iii) the sensed inductor current waveform is noise-free; and (iv) the input voltage is ripple- free. Fig. 1 shows the circuit diagram of a PCMC regulator where a constant frequency clock signal initiates each switchmg cycle T,. The inductor current (iL) is sensed by a resistor R, and is compared to a control voltage ( VerrOr). The duty cycle d is determined when the sensed inductor current that has a rising slope of (sn) reaches a peak value set by V,rr,lr An external ramp with slope s, is added to the sensed current waveform to stabilise the current feedback loop [12, 13, 161. Based on the geometry of the steady-state sensed inductor current waveform, the following relation- ships can be obtained:

(1)

iL.maxRs = RriL.rmn + RssndTs = - SedT. (2)

dT, R,iL = -k Rssn - 2

We then define the following perturbation equations:

d = D + d

iL =I, + i L

U , =v, + ijc ( 3 ) s, =s, + j . ,

s, =se + ie

By substituting (3) into (1) and (2) and assuming that the external ramp is not added (i,= 0), one can obtain the low- frequency control law for the duty ratio

2 = &(H,ij, + HA + H3ijy + H&) (4) where HI-H4 are shown in Table 1 for three basic switch- mode regulators, the buck, the boost and the flyback, and

( 5 ) 2

F = - (RsSn + 2Se)Ty

IEE Proc.-Electr. Poiwr Appl.. VoL 150, No. 3, May 2003 35 I

d

rf

b

Fig. 1 PCMC a block diagram for DC/DC regulators with PCMC strategy b time sequence diagram

Table 1: Parameters of PCMC for typical DC/DC regulators

-R,DT, R,DT,

-E&!?.i 0 2L 2L

Buck 1 - Rs

Boost 1 -Rs 2 L

Flyback 1 - Rs -E&% 0 2L

From (4) one can see that 2 is the linear combinations of CC, l L , 6, and 6,. Additionally, the perturbation of the input voltage 6, can be reflected to 2. In other words, PCMC intrinsically has the characteristic of automatically feedfor-

I A +

Fig. 2 Small-signal model block diagram for PCMC strutegy

ward compensating as mentioned earlier. Based on the modelling approach, the small model for the PCMC stage of the regulators can be represented as shown in Fig. 2. It should be noted that the various open-loop transfer functions of the power stage FI G ij(,/ij(,, F2 = Cold, F3 f IL/ijY, F4 i L / d , Z, ijo/io are obtained though state- space averaging and linerisation [13, 161. The derivation of these is beyond the scope of this paper. Moreover, since the boost and flyback regulators face nonmimimun-phase dynamics induced by the presence of a right-half plane (RHP) zero [13, 161, and the main task of the work is to gain insight into the design and analysis of PCMC, the case with a RHP zero is restricted here. Additionally, the boost and flyback regulators share similar model structures, so for simplicity, the isolated flyback as shown in Fig. 3 will be considered in this paper. The Appendix (Section 9) lists the transform functions of the power stage in Fig. 2.

Fig. 3 Power circuit of the irolatedflyback DCIDC reyubtor

3 compensator design

To analyse the performances of the DC/DC regulators using the PCMC strategy, one can apply Mason’s gain formula to Fig. 2 to yield the closed-loop audio

Basic principles of closed-form loop

IEE Proc-Electr. Power Appl., Vol. 150, No. 3, Muy 2003 352

susceptibility, Gcll,d, CL, and the output impedance, Zo, CL, as follows:

(6) l+T i+T" Gatui,CL E

(7)

where

Equations (6) and (7) indicate that the loop gain of the system, T,, is the phasor-sum of the voltage loop gain, Tu, and the current loop gain, TI. Moreover, the gain of the loop directly attenuates the audio susceptibility and the output impedance of the closed-loop system. Consequently, if the parameters of the power circuit, F,, F, and F4, are given, then the bode diagram of T, and Ti can be easily obtained. Basically, the loop gain must be selected not only to reduce the steady-state error and attenuate the high-order harmonics of the output voltage, but also to improve the closed-loop responses and maintain adequate stability margins with capacitive loadings. Accordingly, the K/.Y type of loop gain is a good choice for practical applications [14]. The gain, K, determines the low-frequency attenuation of the closed-loop transfer functions.

The essence of the loop gain determining rules are summarised as follows:

(i) The highest possible DC gain of the voltage loop favours reduction of the steady-state error of the output voltage. Unfortunately, the selected comparator always limits the DC loop gain. (ii) The crossover frequency of the current loop, od, must exceed that of the voltage loop, to obtain the benefits of PCMC. The high bandwidth of the current loop can improve the closed-loop responses. (iii) The phases of the two loops must not be opposed at their crossover frequency, wc,,,, when the two loops cross over to avoid a dip in the overall loop gains that would cause the system to become unstable. Generally, the limiting condition, I LT,j,ue,,, - LTi,lUc,, I < 130", is a good choice for practical applications [ 131.

4 Closed-form loop compensator design procedures

The design procedures of the proposed closed-form loop compensator design for PCMC are summarised as below.

Step 1: Determine the value of R, and the type of PWM control 1C from the variable range of the duty cycle, D, of the power supply. If the maximum duty cycle exceeds 0.5, then the control IC, including the function of compensating the external ramp slope, se, must be adapted to stabilise the power supply [12, 131. Step 2: Derive the open-loop small-signal model of power stage, as shown in Fig. 2. Step 3: First use the voltage loop gain, Tu, to determine the type of the desired loop compensator and thus maintain the loop gain type of approximately K/s for as long as possible. From (24), F2 has two poles and one zero together with RHP zero. Hence, the one zero and one pole together and

IEE Proc-Electr. Power Appl., Vol. I50, No. 3, May 2003

Fig. 4 Realisation of proposed loop compensator circuit

one pole at zero frequency type, is adopted. Fig. 4 depicts the adopted loop compensator and its corresponding transfer function is

where

1 R2c2

0, = ~

Step 4: Set the crossover frequency of the current loop, och as high as possible but not exceeding half of the switching frequency. Although the crossover frequency of the current loop can be also adjusted by se, the advantages of PCMC do not apply at an se that is too high [12, 131. Notably, the crossover frequency of the current loop will be a constant and will be automatically determined by the parameters of the power stage. Step 5: Set the crossover frequency of the current loop and voltage loop, wciu, to satisfy the condition, I LT,,uc,b - i7;,wc,,, 1 < 130". Generally, if o,;~ is maintained between a resonant frequency, o,, and the crossover frequency of the current loop, ock then the objections, as described previously, can be met. Step 6: Determine the value CO, and ocp for the loop compensator (obtained in step 3), to satisfy the requirement that the voltage loop be of type K/s. By inspection, Q.=E o, and ocp = min{w,,, o,} can be satisfied, although numer- ical analysis can be used to find the values. For practical applications, o, < wza, Hence

Step 7: The magnitudes of the current loop and the voltage loop are equal at ocju. Therefore, the following relationships can be obtained:

353

where where

KO K23 E -

Ki

and RI should be selected according to the bias current of the operational amplifier that is used as a loop compensa- tor. Step 8: From (13H15), the parameters of the adopted loop compensator can be obtained as follows:

K23 c3 = -

vs -

wur1100 22

From the preceding description, the analytic closed-form loop compensator design for the isolated flyback DC/DC regulator by PCMC is formulated stepwise and can easily be used. Thus, a conventional computer software program, such as Excel 5.0, can be used to increase the efficiency of the design process through systemisation. The same procedures can be used for various converters.

5 Simulation and experimental results

To illustrate the significance and facilitate the understanding of the theoretical results obtained in previous Sections, a prototype isolated flyback DC/DC regulator by PCMC strategy is implemented for experimental confirmation with the following parameters: V , = 48 V, V, = 12 V, L, = 100 pH, RLp = I05 mR, L, = 25 pH, RLv = 25 mR, c = 4000 pF, R, = 12 mR, R,Y = 0.2 R, R = 5 R, switching frequency f, = 150 kHz, S,": IRF 630.

The loop compensator can be designed after the power stage parameters have been determined. A PWM IC without external slope compensation, such as the UC 3842 [12], is used here since the maximum duty cycle is less than 0.5. Hence, if w,,, = 27410 k) rad/s and RI = 7.6 k 0 are selected and substituted into (1 9H21), then the parameters of the loop compensator can be immediately obtained as: R2 = 1374 KR, c2 = 362 pF and c3 = 43 pF.

Fig. 5 shows the complete circuit diagram. The output filter is constructed using Lj= 1.5 pH, ref= 10mQ cf= 100pF and r d = 0 . 5 n . Some key bode diagrams of the proposed regulator with PCMC are shown in Fig. 6. The loop gain, TI, voltage loop gain, Tu, and current loop gain, TI, agree quite well with the theoretical results. Moreover, not only the loop gain, TI , and the crossover

wbr303sct

RLS -

-

IRF630

I

.................................

output filter

2 k

Fig. 5 Completed circuit diagram for proposed reguhtor

354 IEE Proc.-Electr. Ponrr Appl., Vol. 150. No. 3, May 2003

A i t h o u t loop cbmpensator I

c C

c P -150 E

; L a

-1 00

-200

100 102 1 o4 1 06 108 frequency, rad/s

a

-250 1 U 100 1 02 I o4 106 108

frequency, radk b

L I S

-200

100 102 1 o4 106 1 08 frequency, rad/s

C

Fig. 6 Bode plots U T, and T, b TI and T, ( d ' J ( l +/TJ c To, T, and T,

frequency of the current loop, and the crossover frequency wCiu = 62788 rad/s ( 2 2n(10 k) rad/s) are in agreement with the desired results, but also a high phasor margin (nearly 84") is as expected. For reference, the audio susceptibility and output impedance are also shown in Fig. 7. Figs. 6 and 7 give confidence that the adopted closed-form loop compensator design strategy can achieve control loop stability, high loop gain and bandwidth, which usually means good output voltage regulation. To explicate the dynamic performances of the system, Fig. 8 shows the

a -200 -300 -400 1 , , y-4

I o4 106 108 1 00 1 02 frequency, rad/s

a

I I

-20

-40 - without loop compensato-

- -

ai -80

P -120 E p 100

a 0

I -50

I

1 00 IO' I o4 1 06 108 frequency, rad/s

b

Fig. 7 a audio susceptibility b output impedance

Properties of the proposed regulutor

Te

.. . . , . . . . , .

i:;

~

Fig. 8 Measured transient due to period steps 40% load current Chl = V, Ch2 = Z,

waveforms for load current period steps between 40% and 80%. From Fig. 8, one can see that operating the proposed PCMC isolated flyback regulator, a nonoscillatory

355 IEE Proc-Electr. Power Appl , Vol. 150, No. 3, May 2003

behaviour of the controlled output voltage, good regulation (setting time and peak overshoot are about 1.1 ms and 230 mV, respectively), and zero steady-state error.

6 Conclusions

T h s study presents and analyses new means of closed-form loop compensator design strategy for PCMC DC/DC regulators. Small-signal modelling of PCMC is first derived. Then, not only is a simply concept adopted to illustrate the principle of the loop compensator design, but the closed- form design method for the PCMC is also proposed. A procedure for designing the feedback compensation is given and some simulation and experimental results are presented.

7 Acknowledgment

The author would like to acknowledge the financial support of the National Science Council of the Republic of China (contract NSC 90-2213-E-233-003).

8 References

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LA, 1995, pp. 499-513 21

9 Appendix

A list of transfer functions of the isolated flyback regulator from Fig. 5 is given below. These are derived by linearisa- tion state-space averaging [13]

(23)

where

Q = - D‘ 1

1 1 QI =-

01 & + R,c

1 w, = ~

R,c

356 IEE Proc.-Elrcir. Power Appl.. Vol. 150, No. 3, Muy 2003