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Chapter 1 – Introduction (5/02/04) Page 1.0-1
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 1 – INTRODUCTION AND BACKGROUND
Chapter Outline1.1 Analog Integrated Circuit Design1.2 Technology Impact on Analog IC Design1.3 Analog Signal Processing1.4 Notation, Symbology and Terminology1.5 SummaryObjectivesThe objective of this course is to teach analog integrated circuit design using today’stechnologies and in particular, CMOS technology.Approach1. Develop a firm background on technology and modeling2. Present analog integrated circuits in a hierarchical, bottom-up manner3. Emphasize understanding and concept over analytical methods (simple models)4. Illustrate the correct usage of the simulator in design5. Develop design procedures that permit the novice to design complex analog circuits
(these procedures will be modified with experience)
Chapter 1 – Introduction (5/02/04) Page 1.0-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Organization (Second Edition of CMOS Analog IC Design)
Chapter 9Switched Capaci-
tor Circuits
Chapter 6Simple CMOS &BiCMOS OTA's
Chapter 7High Performance
OTA's
Chapter 10D/A and A/DConverters
Chapter 11AnalogSystems
Chapter 2CMOS/BiCMOS
Technology
Chapter 3CMOS/BiCMOS
Modeling
Chapter 4CMOS
Subcircuits
Chapter 5CMOS
Amplifiers
Systems
Complex
Circuits
Devices
Simple
Introduction
Chapter 8CMOS/BiCMOS
Comparators
Chapter 10D/A and A/DConverters
Fig. 1.0-01
Chapter 1 – Section 1 (5/2/04) Page 1.1-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 1.1 - ANALOG INTEGRATED CIRCUIT DESIGNWhat is Analog IC Design?Analog IC design is the successfulimplementation of analog circuits andsystems using integrated circuittechnology.
Unique Features of Analog IC Design• Geometry is an important part of the design
Electrical Design → Physical Design → Test Design• Usually implemented in a mixed analog-digital circuit• Analog is 20% and digital 80% of the chip area• Analog requires 80% of the design time• Analog is designed at the circuit level• Passes for success: 2-3 for analog, 1 for digital
IntegratedCircuitTechnology
Function orApplication
SuccessfulSolution
Fig. 1-1
Chapter 1 – Section 1 (5/2/04) Page 1.1-2
CMOS Analog Circuit Design © P.E. Allen - 2004
The Analog IC Design Flow
Conception of the idea
Definition of the design
Implementation
Simulation
Physical Verification
Parasitic Extraction
Fabrication
Testing and Verification
Product
Comparisonwith design
specifications
Comparisonwith design
specifications
Physical Definition
ElectricalDesign
PhysicalDesign
Fabrication
Testing andProduct
DevelopmentFig. 1.1-2
Chapter 1 – Section 1 (5/2/04) Page 1.1-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Analog IC Design - Continued• Electrical Aspects
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
CL
+
-
CcAnalogIntegrated
Circuit Design
W/L ratios
Topology
DC Currents
L
W
Circuit orsystems
specifications
Fig. 1.1-3
• Physical AspectsImplementation of the physical design including:- Transistors and passive components- Connections between the above- Busses for power and clock distribution- External connections
• Testing AspectsDesign and implementation for the experimental verification of the circuit afterfabrication
Chapter 1 – Section 1 (5/2/04) Page 1.1-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Comparison of Analog and Digital Circuits
Analog Circuits Digital Circuits
Signals are continuous inamplitude and can be continuousor discrete in time
Signal are discontinuous inamplitude and time - binarysignals have two amplitude states
Designed at the circuit level Designed at the systems level
Components must have acontinuum of values
Component have fixed values
Customized Standard
CAD tools are difficult to apply CAD tools have been extremelysuccessful
Requires precision modeling Timing models only
Performance optimized Programmable by software
Irregular block Regular blocks
Difficult to route automatically Easy to route automatically
Dynamic range limited by powersupplies and noise (and linearity)
Dynamic range unlimited
Chapter 1 – Section 1 (5/2/04) Page 1.1-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Skills Required for Analog IC Design• In general, analog circuits are more complex than digital• Requires an ability to grasp multiple concepts simultaneously• Must be able to make appropriate simplifications and assumptions• Requires a good grasp of both modeling and technology• Have a wide range of skills - breadth (analog only is rare)• Be able to learn from failure• Be able to use simulation correctly
Simulation “truths”:♦ (Usage of a simulator) x (Common sense) ≈ Constant♦ Simulators are only as good as the models and the knowledge of those models
by the designer♦ Simulators are only good if you already know the answers
Chapter 1 – Section 2 (5/2/04) Page 1.2-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 1.2 - TECHNOLOGY IMPACT ON ANALOG IC DESIGNTrends in CMOS Technology
• Moore’s law: The minimum feature size tends to decrease by a factor of 1/ 2 everythree years.
• Semiconductor Industry Association roadmap for CMOS
1995 1998 2001 2004 2007 2010
3.0V
2.5V
2.0V
1.5V
1.0V
0.35µm 0.25µm 0.18µm 0.13µm 0.10µm 0.07µmFeature Size
Pow
er S
uppl
y V
olta
ge
Year Fig. 1.2-1
Desktop Systems
Portable Systems
Chapter 1 – Section 2 (5/2/04) Page 1.2-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Trends in CMOS Technology - ContinuedThreshold voltages and power supply:
0.1
1
10
0.01 0.1 1Pow
er S
uppl
y an
d T
hres
hold
Vol
tage
(V
olts
)
MOSFET Channel Length, µm
2
5
0.5
0.2
0.050.02 0.2 0.5
VDD
VT
2005-2006
Fig. 1.2-2
(scenario 1)
VT (scenario 2)
AnalogHeadroom
Chapter 1 – Section 2 (5/2/04) Page 1.2-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Trends in IC TechnologyTechnology Speed Figure of Merit vs. Time:
77 79 81 83 85 87 89 91 93 95 97 99
100GHz
30GHz
10GHz
3GHz
1GHz
ft
Year
GaAs
Bipolar
CMOS
HEMTs, HBTs
3µm
2µm 1.5µm
1µm0.8µm 0.6µm
0.5µm0.35µm
0.25µm
Carrier Frequency of RFCellular Telephony
Fig. 1.2-3B
01
0.18µm0.13µm
SiGe
03 05
0.09µm
300GHz
Estimated Frequency Performance based on Scaling:
Technology ft fmax
0.35 micron 25GHz 40GHz0.25 micron 40GHz ≈ 60-70GHz0.18 micron 60GHz ≈ 90-100GHz
Chapter 1 – Section 2 (5/2/04) Page 1.2-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Innovation in Analog IC DesignIn the past, circuit innovation was driven by new technologies.
1950 1960 1970 1980 1990 2000
DiscreteTransistors
BipolarAnalog IC
MOSAnalog IC
Rate ofCircuit
Innovation
Fig. 1.2-4
Ideal
Actual?
Candidates for the future• Packaging?• Opto-electronics?• Vertically integrated transistors?
Chapter 1 – Section 2 (5/2/04) Page 1.2-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Technology-Driven versus Application-Driven Innovation
NewTechnology
GenericFunction
InnovativeSolution
StandardTechnology
NewApplication
InnovativeSolution
Technology driven circuit innovation:
Application driven circuit innovation:
Fig. 1.2-5
Chapter 1 – Section 2 (5/2/04) Page 1.2-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Implications of Technology on IC DesignThe good:• Smaller geometries• Smaller parasitics• Higher transconductance• Higher bandwidthsThe bad:• Reduced voltages• Smaller channel resistances (lower gain)• More nonlinearity• Deviation from square-law behaviorThe ugly:• Increased substrate noise in mixed signal applications• Threshold voltages are not scaling with power supply• Reduced dynamic range• Suitable models for analog design
Chapter 1 – Section 3 (5/2/04) Page 1.3-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 1.3 - ANALOG SIGNAL PROCESSINGSignal Bandwidths versus Application
Signal Frequency (Hz)
10
1
100 1k 10k 100k 1M 10M 100M 1G 10G 100G
Sonar
SeismicAcousticImaging
Video
Radar
Audio AM-FM radio, TV
Microwave
Telecommunications
1
RF
Optical
Fig. 1.3-1
Chapter 1 – Section 3 (5/2/04) Page 1.3-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Signal Bandwidths versus Technology
GaAs
Optical
Surface acousticwaves
MOS digital logic
Bipolar digital logic
Bipolar analog
MOS analog
BiCMOS
Signal Frequency (Hz)
10 100 1k 10k 100k 1M 10M 100M 1G 10G 100G1
Fig. 1.3-2
Mostly digital implementationMostly analog
implementation
Fuzzy boundary,keeps moving to
the right
Chapter 1 – Section 3 (5/2/04) Page 1.3-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Analog IC Design has Reached Maturity
There are established fields of application:• Digital-analog and analog-digital conversion• Disk drive controllers• Modems - filters• Bandgap reference• Analog phase lock loops• DC-DC conversion• Buffers• Codecs
···
Existing philosophy regarding analog circuits:“If it can be done economically by digital, don’t use analog.”
Consequently:Analog finds applications where speed, area, or power have advantages over a digital
approach.
Chapter 1 – Section 3 (5/2/04) Page 1.3-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Eggshell Analogy of Analog IC Design (Paul Gray)
VLSIDIGITALSYSTEM
PowerSource
TransmissionMedia
StorageMedia
Analog/DigitalInterfaceElectronics
AudioI/O
Imagers &Displays
PhysicalSensorsActuators
Fig. 1.3-3
Chapter 1 – Section 3 (5/2/04) Page 1.3-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Analog Signal Processing versus Digital Signal Processing in VLSIKey issues:
Analog/Digital mix is application dependentNot scaling drivenDriven by system requirements for
programmability/adaptability/testability/designability
Now:
ASP A/D DSP System
ASP A/D DSP System
Trend:
Fig. 1.3-4
Chapter 1 – Section 3 (5/2/04) Page 1.3-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Application Areas of Analog IC DesignThere are two major areas of analog IC design:• Restituitive - performance oriented (speed, accuracy, power, area)
Classical analog circuit and systems design• Cognitive - function oriented (adaptable, massively parallel)
A newly growing area inspired by biological systemsAnalog VLSI (An oxymoron):
Combination of analog circuits and VLSI philosophies• Many similarities between analog circuits and biological systems
ScalabilityNonlinearityAdaptability
• Neuromorphic analog VLSIUse of biological systems to inspire circuit design such as smart sensors and imagers
• Smart autonomous systemsSelf-guided vehicles (Mars lander)Industrial cleanup in a hazardous environment
• Sensorimotor feedbackSelf contained systems with sensor input, motor output
Chapter 1 – Section 3 (5/2/04) Page 1.3-7
CMOS Analog Circuit Design © P.E. Allen - 2004
What is the Future of Analog IC Design?• Technology will require more creative circuit solutions in order to achieve desired
performance• Analog circuits will continue to be a part of large VLSI digital systems• Interference and noise will become even more serious as the chip complexity increases• Packaging will be an important issue and offers some interesting solutions• Analog circuits will always be at the cutting edge of performance• Analog designer must also be both a circuit and systems designer and must know:
Technology and modelingAnalog circuit designVLSI digital designSystem application concepts
• There will be no significantly new and different technologies - innovation will combinenew applications with existing or improved technologies
• Semicustom methodology will eventually evolve with CAD tools that will allow:- Design capture and reuse- Quick extraction of model parameters from new technology- Test design- Automated design and layout of simple analog circuits
Chapter 1 – Section 4 (5/2/04) Page 1.4-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 1.4 - NOTATION, SYMBOLOGY, AND TERMINOLOGYDefinition of Symbols for Various Signals
Signal Definition Quantity Subscript ExampleTotal instantaneous value of the signal Lowercase Uppercase qA
DC value of the signal Uppercase Uppercase QA
AC value of the signal Lowercase Lowercase qa
Complex variable, phasor, or rms valueof the signal
Uppercase Lowercase Qa
Example:
t
ID iD
id
Idm
Fig. 1.4-1
Dra
in C
urre
nt
Chapter 1 – Section 4 (5/2/04) Page 1.4-2
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Transistor Symbols
G
S
D
G
S
D
G
S
D
G
S
D
B G
S
D
B
G
S
D
EnhancementNMOS withVBS = 0V.
EnhancementPMOS withVBS = 0V.
EnhancementNMOS withVBS ≠ 0V.
EnhancementPMOS withVBS ≠ 0V.
SimpleNMOSsymbol
SimplePMOSsymbol
Chapter 1 – Section 4 (5/2/04) Page 1.4-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Other Schematic Symbols
Differential amplifier,op amp, or comparator
+
-
+
-
V1 GmV1
I2
+-
+
-
V1 V2AvV1
+
-
+-
+
-
V2
I1
RmI1
I2I1
AiI1
Voltage-controlled,voltage source
Voltage-controlled, current source
Current-controlled, voltage source
Current-controlled, current source
Independent current source
Independentvoltage sources
+
-V
+
-V
+
-
V
Chapter 1 – Section 4 (5/2/04) Page 1.4-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Three-Terminal Notation (Data books)QABC
A = Terminal with the larger magnitude of potentialB = Terminal with the smaller magnitude of potentialC = Condition of the remaining terminal with respect to terminal B
C = 0 ⇒ There is an infinite resistance between terminal B and the 3rd terminalC = S ⇒ There is a zero resistance between terminal B and the 3rd terminalC = R ⇒ There is a finite resistance between terminal B and the 3rd terminalC = X ⇒ There is a voltage source in series with a resistor between terminal B
and the 3rd terminal in such a manner as to reverse bias a PN junction.Examples
(a.) Capacitance from drain to gate with the source shorted to the gate.(b.) Drain-source current when gate is shorted to source (depletion device)(c.) Breakdown voltage from drain to gate with the source is open- circuited to the gate.
+
-VGS
S D
G
CDGS
S
DG
IDSS
+
-
S D
G
IDS BVDGO
(a.) (b.) (c.)
Chapter 1 – Section 5 (5/2/04) Page 1.5-1
CMOS Analog Circuit Design © P.E. Allen - 2004
1.5 - SUMMARY• Analog IC design combines a function or application with IC technology for a successful
solution.• Analog IC design consists of three major steps:
1.) Electrical design ⇒ Topology, W/L values, and dc currents2.) Physical design (Layout)3.) Test design (Testing)
• Analog designers must be flexible and have a skill set that allows one to simplify andunderstand a complex problem
• Analog IC design is driven by improving technologies rather than new technologies.• Analog IC design has reached maturity and is here to stay.• The appropriate philosophy is “If it can be done economically by digital, don’t use
analog”.• As a result of the above, analog finds applications where speed, area, or power have
advantages over a digital approach.• Deep-submicron technologies will offer severe challenges to the creativity of the analog
designer.
Chapter 2 – Introduction (5/02/04) Page 2.0-1
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 2 – CMOS TECHNOLOGY
Chapter Outline2.1 Basic MOS Semiconductor Fabrication Processes2.2 CMOS Technology2.3 PN Junction2.4 MOS Transistor2.5 Passive Components2.6 Other Considerations of CMOS Technology2.7 Bipolar Transistor (optional)2.8 BiCMOS Technology (optional)Perspective
AnalogIntegrated
CircuitDesign
CMOSTransistor and Passive
Component Modeling
CMOSTechnology
andFabrication
Fig. 2.0-1
Chapter 2 – Introduction (5/02/04) Page 2.0-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Classification of Silicon Technology
Silicon IC Technologies
Bipolar Bipolar/CMOS MOS
JunctionIsolated
Dielectric Isolated
Oxideisolated
CMOSPMOS
(Aluminum Gate)
NMOS
Aluminum gate
Silicon gate
Aluminum gate
Silicon gate
Silicon-Germanium
Silicon Fig. 150-01
Chapter 2 – Introduction (5/02/04) Page 2.0-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Why CMOS Technology?Comparison of BJT and MOSFET technology from an analog viewpoint:
Feature BJT MOSFETCutoff Frequency(fT) 100 GHz 50 GHz (0.25µm)
Noise (thermal about the same) Less 1/f More 1/fDC Range of Operation 9 decades of exponential
current versus vBE2-3 decades of square lawbehavior
Small Signal Output Resistance Slightly larger Smaller for short channelSwitch Implementation Poor GoodCapacitor Implementation Voltage dependent Reasonably good
Therefore,• Almost every comparison favors the BJT, however a similar comparison made from a
digital viewpoint would come up on the side of CMOS.• Therefore, since large-volume technology will be driven by digital demands, CMOS is
an obvious result as the technology of availability.Other factors:• The potential for technology improvement for CMOS is greater than for BJT• Performance generally increases with decreasing channel length
Chapter 2 – Introduction (5/02/04) Page 2.0-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Components of a Modern CMOS TechnologyIllustration of a modern CMOS process:
n+
p-substrate
Metal Layers
NMOSTransistor
PMOSTransistor
031211-02
M1M2M3M4M5M6M7M80.8µm
0.3µm 7µm
Deep n-wellDeep p-well
n+
STIp+ p+
STI STI
Salicide
Polycide
Salicide
PolycideSidewall Spacers
Salicide
Source/drainextensions
Source/drainextensions
In addition to NMOS and PMOS transistors, the technology provides:1.) A deep n-well that can be utilized to reduce substrate noise coupling.2.) A MOS varactor that can serve in VCOs3.) At least 6 levels of metal that can form many useful structures such as inductors,
capacitors, and transmission lines.
Chapter 2 – Introduction (5/02/04) Page 2.0-5
CMOS Analog Circuit Design © P.E. Allen - 2004
CMOS Components – TransistorsfT as a function of gate-source overdrive, VGS-VT (0.13µm):
100 200 300 400 500
20
30
40
50
60
70
10
00
Typical, 25°C
Slow, 70°CPMOS
Typical, 25°C
Slow, 70°CNMOS
f T (
GH
z)
|VGS-VT| (mV) 030901-07
The upper frequency limit is probably around 40 GHz for NMOS with an fT in the vicinityof 60GHz with an overdrive of 0.5V and at the slow-high temperature corner.
Chapter 2 – Section 1 (5/02/04) Page 2.1-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 2.1 - BASIC CMOS TECHNOLOGYFUNDAMENTAL PROCESSING STEPS
Basic steps• Oxide growth• Thermal diffusion• Ion implantation• Deposition• Etching• Epitaxy
PhotolithographyPhotolithography is the means by which the above steps are applied to selected areas ofthe silicon wafer.
Silicon wafer
0.5-0.8mm
n-type: 3-5 Ω-cmp-type: 14-16 Ω-cm Fig. 2.1-1r
125-200 mm(5"-8")
Chapter 2 – Section 1 (5/02/04) Page 2.1-2
CMOS Analog Circuit Design © P.E. Allen - 2004
OxidationDescription:Oxidation is the process by which a layer of silicon dioxide is grown on the surface of asilicon wafer.
Original silicon surface
0.44 tox
tox
Silicon substrate
Silicon dioxide
Fig. 2.1-2
Uses:• Protect the underlying material from contamination• Provide isolation between two layers.Very thin oxides (100Å to 1000Å) are grown using dry oxidation techniques. Thickeroxides (>1000Å) are grown using wet oxidation techniques.
Chapter 2 – Section 1 (5/02/04) Page 2.1-3
CMOS Analog Circuit Design © P.E. Allen - 2004
DiffusionDiffusion is the movement of impurity atoms at the surface of the silicon into the bulk ofthe silicon. Always in the direction from higher concentration to lower concentration.
HighConcentration
LowConcentration
Fig. 150-04
Diffusion is typically done at high temperatures: 800 to 1400°C
Depth (x)
t1 < t2 < t3
t1t2
t3
N(x)
NB
Depth (x)
t1 < t2 < t3
Infinite source of impurities at the surface. Finite source of impurities at the surface.
N0
Fig. 150-05
ERFC Gaussian
t1 t2t3
N(x)
NB
N0
Chapter 2 – Section 1 (5/02/04) Page 2.1-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Ion ImplantationIon implantation is the process by whichimpurity ions are accelerated to a highvelocity and physically lodged into thetarget material.
• Annealing is required to activate theimpurity atoms and repair the physicaldamage to the crystal lattice. This stepis done at 500 to 800°C.
• Ion implantation is a lower temperatureprocess compared to diffusion.
• Can implant through surface layers, thus it isuseful for field-threshold adjustment.
• Can achieve unique doping profile such asburied concentration peak.
Path of impurity
atom
Fixed Atom
Fixed Atom
Fixed AtomImpurity Atomfinal resting place
Fig. 150-06
N(x)
NB
0 Depth (x)
Concentration peak
Fig. 150-07
Chapter 2 – Section 1 (5/02/04) Page 2.1-5
CMOS Analog Circuit Design © P.E. Allen - 2004
DepositionDeposition is the means by which various materials are deposited on the silicon wafer.Examples: • Silicon nitride (Si3N4)
• Silicon dioxide (SiO2)
• Aluminum • PolysiliconThere are various ways to deposit a material on a substrate: • Chemical-vapor deposition (CVD) • Low-pressure chemical-vapor deposition (LPCVD) • Plasma-assisted chemical-vapor deposition (PECVD) • Sputter depositionMaterial that is being deposited using these techniques covers the entire wafer.
Chapter 2 – Section 1 (5/02/04) Page 2.1-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Etching
Etching is the process of selectivelyremoving a layer of material.When etching is performed, the etchantmay remove portions or all of: • The desired material • The underlying layer • The masking layer
Important considerations: • Anisotropy of the etch is defined as,
A = 1-(lateral etch rate/vertical etch rate) • Selectivity of the etch (film to mask and film to substrate) is defined as,
Sfilm-mask = film etch rate
mask etch rate
A = 1 and Sfilm-mask = ∞ are desired.
There are basically two types of etches: • Wet etch which uses chemicals • Dry etch which uses chemically active ionized gases.
MaskFilm
bUnderlying layer
a
c
MaskFilm
Underlying layer
(a) Portion of the top layer ready for etching.
(b) Horizontal etching and etching of underlying layer.Fig. 150-08
Selectivity
AnisotropySelectivity
Chapter 2 – Section 1 (5/02/04) Page 2.1-7
CMOS Analog Circuit Design © P.E. Allen - 2004
EpitaxyEpitaxial growth consists of the formation of a layer of single-crystal silicon on thesurface of the silicon material so that the crystal structure of the silicon is continuousacross the interfaces.• It is done externally to the material as opposed to diffusion which is internal• The epitaxial layer (epi) can be doped differently, even oppositely, of the material on
which it grown• It accomplished at high temperatures using a chemical reaction at the surface• The epi layer can be any thickness, typically 1-20 microns
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
Si Si Si Si Si Si Si Si Si Si Si Si
+
-
-
-
- -
-
+
+
+
Gaseous cloud containing SiCL4 or SiH4
Si Si Si Si+
Fig. 150-09
Chapter 2 – Section 1 (5/02/04) Page 2.1-8
CMOS Analog Circuit Design © P.E. Allen - 2004
PhotolithographyComponents
• Photoresist material• Mask• Material to be patterned (e.g., oxide)
Positive photoresistAreas exposed to UV light are soluble in the developerNegative photoresistAreas not exposed to UV light are soluble in the developerSteps1. Apply photoresist2. Soft bake (drives off solvents in the photoresist)3. Expose the photoresist to UV light through a mask4. Develop (remove unwanted photoresist using solvents)5. Hard bake ( ≈ 100°C)6. Remove photoresist (solvents)
Chapter 2 – Section 1 (5/02/04) Page 2.1-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of Photolithography - ExposureThe process of exposingselective areas to lightthrough a photo-mask iscalled printing.Types of printing include:• Contact printing• Proximity printing• Projection printing
Photoresist
Photomask
UV Light
Photomask
Polysilicon
Fig. 150-10
Chapter 2 – Section 1 (5/02/04) Page 2.1-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of Photolithography - Positive Photoresist
Photoresist
Photoresist
Polysilicon
Polysilicon
Polysilicon
Etch
Removephotoresist
Develop
Fig. 150-11
Chapter 2 – Section 1 (5/02/04) Page 2.1-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of Photolithography - Negative Photoresist(Not used much any more)
Underlying Layer
Underlying Layer
Underlying Layer
SiO2
Photoresist
SiO2
SiO2
Fig. 150-12
Photoresist
Chapter 2 – Section 1 (5/02/04) Page 2.1-12
CMOS Analog Circuit Design © P.E. Allen - 2004
TYPICAL DSM CMOS FABRICATION PROCESSMajor Fabrication Steps for a DSM CMOS Process 1.) p and n wells 2.) Shallow trench isolation 3.) Threshold shift 4.) Thin oxide and gate polysilicon 5.) Lightly doped drains and sources 6.) Sidewall spacer 7.) Heavily doped drains and sources 8.) Siliciding (Salicide and Polycide) 9.) Bottom metal, tungsten plugs, and oxide10.) Higher level metals, tungsten plugs/vias, and oxide11.) Top level metal, vias and protective oxide
Chapter 2 – Section 1 (5/02/04) Page 2.1-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Step 1 – Starting MaterialThe substrate should be highly doped to act like a good conductor.
p+ p p- MetalSaliciden- n n+Oxide Poly
Substrate
031231-13Polycide
yyGate Ox
Chapter 2 – Section 1 (5/02/04) Page 2.1-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Step 2 - n and p wellsThese are the areas where the transistors will be fabricated - NMOS in the p-well andPMOS in the n-well.Done by implantation followed by a deep diffusion.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
Substrate
031231-12Polycide
yyGate Ox
n well implant and diffusion p well implant and diffusion
Chapter 2 – Section 1 (5/02/04) Page 2.1-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Step 3 – Shallow Trench IsolationThe shallow trench isolation (STI) electrically isolates one region/transistor from another.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
ShallowTrench
Isolation
ShallowTrench
Isolation
ShallowTrench
Isolation
Substrate
031231-11Polycide
yyGate Ox
Chapter 2 – Section 1 (5/02/04) Page 2.1-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Step 4 – Threshold Shift and Anti-Punch Through ImplantsThe natural thresholds of the NMOS is about 0V and of the PMOS is about –1.2V. An n-implant is used to make the NMOS harder to invert and the PMOS easier resulting inthreshold voltages balanced around zero volts.Also an implant can be applied to create a higher-doped region beneath the channels toprevent punch-through from the drain depletion region extending to source depletionregion.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
Substrate
031231-10Polycide
yyGate Ox
p threshold implant p threshold implant
n+ anti-punch through implant p+ anti-punch through implant
ShallowTrench
Isolation
ShallowTrench
Isolation
ShallowTrench
Isolation
Chapter 2 – Section 1 (5/02/04) Page 2.1-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Step 5 – Thin Oxide and Polysilicon GatesA thin oxide is deposited followed by polysilicon. These layers are removed where theyare not wanted.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
Substrate
031231-09Polycide
yyGate Ox
Thin Oxide ShallowTrench
Isolation
ShallowTrench
Isolation
ShallowTrench
Isolation
Chapter 2 – Section 1 (5/02/04) Page 2.1-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Step 6 – Lightly Doped Drains and SourcesA lightly-doped implant is used to create a lightly-doped source and drain next to thechannel of the MOSFETs.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
Substrate
031231-08Polycide
yyGate Ox
Shallow n-
ImplantShallow n-
ImplantShallow p-
ImplantShallow p-
Implant ShallowTrench
Isolation
ShallowTrench
Isolation
ShallowTrench
Isolation
Chapter 2 – Section 1 (5/02/04) Page 2.1-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Step 7 – Sidewall SpacersA layer of dielectric is deposited on the surface and removed in such a way as to leave“sidewall spacers” next to the thin-oxide-polysilicon-polycide sandwich. These sidewallspacers will prevent the part of the source and drain next to the channel from becomingheavily doped.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
SidewallSpacers
Substrate
031231-07Polycide
yyGate Ox
SidewallSpacers
ShallowTrench
Isolation
ShallowTrench
Isolation
ShallowTrench
Isolation
Chapter 2 – Section 1 (5/02/04) Page 2.1-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Step 8 – Implantation of the Heavily Doped Sources and DrainsNote that not only does this step provide the completed sources and drains but allows forohmic contact into the wells and substrate.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
Substrate
031231-06
p+
Polycide
yyGate Ox
p+
implantn+
implantn+
implantp+
implantp+
implantp+
implantn+
implant SidewallSpacers
n+ n+p+ p+
ShallowTrench
Isolation
ShallowTrench
Isolation
ShallowTrench
Isolation
p+n+
Chapter 2 – Section 1 (5/02/04) Page 2.1-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Step 9 – SilicidingSiliciding and polyciding is used to reduce interconnect resistivity by placing a low-resistance silicide such as TiSi2, WSi2, TaSi2, etc. on top of the diffusions.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
ShallowTrench
Isolation
Substrate
031231-05
p+
Polycide
yyGate Ox
SidewallSpacers
Salicide Salicide
Polycide
SalicideSalicide
n+ n+p+ p+
ShallowTrench
Isolation
ShallowTrench
Isolation
p+n+
Chapter 2 – Section 1 (5/02/04) Page 2.1-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Step 10 – Intermediate Oxide LayerAn oxide layer is used to cover the transistors and to planarize the surface.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
SidewallSpacers
Salicide Salicide
Polycide
Salicide
Substrate
Inter-mediateOxideLayer
031231-04
p+
Salicide
Polycide
yyGate Ox
n+ n+p+ p+
ShallowTrench
Isolation
ShallowTrench
Isolation
ShallowTrench
Isolation
p+n+
Chapter 2 – Section 1 (5/02/04) Page 2.1-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Step 11- First-Level MetalTungsten plugs are built through the lower intermediate oxide layer to provide contactbetween the devices, wells and substrate to the first-level metal.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
Substrate
031231-03
p+
Polycide
yyGate Ox
Salicide Salicide SalicideSalicide
FirstLevelMetal
Inter-mediateOxideLayers
TungstenPlugs
TungstenPlug
SidewallSpacers Polycide
n+ n+p+ p+
ShallowTrench
Isolation
ShallowTrench
Isolation
ShallowTrench
Isolation
p+n+
Chapter 2 – Section 1 (5/02/04) Page 2.1-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Step 12 – Second-Level MetalThe previous step is repeated to from the second-level metal.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
ShallowTrench
Isolation
Substrate
031231-02
p+
Polycide
yyGate Ox
Salicide Salicide SalicideSalicide
FirstLevelMetal
TungstenPlugs
TungstenPlug
SidewallSpacers Polycide
SecondLevel MetalTungsten Plugs
Inter-mediateOxideLayers
TungstenPlugs
n+ n+p+ p+
ShallowTrench
Isolation
ShallowTrench
Isolation
p+n+
Chapter 2 – Section 1 (5/02/04) Page 2.1-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Completed FabricationAfter multiple levels of metal are applied, the fabrication is completed with a thicker top-level metal and a protective layer to hermetically seal the circuit from the environment.Note that metal is used for the upper level metal vias. The chip is electrically connectedby removing the protective layer over large bonding pads.
p+ p p- MetalSaliciden- n n+Oxide
n-well p-well
Poly
ShallowTrench
Isolation
SidewallSpacers Polycide
Top Metal
SecondLevel Metal
FirstLevelMetal
Tungsten Plugs
Protective Insulator Layer
Substrate
Inter-mediateOxideLayers
031231-01
Metal Vias Metal Via
p+
Polycide
TungstenPlugs
yyGate Ox
Salicide Salicide SalicideSalicide
TungstenPlugs
TungstenPlug
n+ n+p+ p+
ShallowTrench
Isolation
ShallowTrench
Isolation
p+n+
Chapter 2 – Section 1 (5/02/04) Page 2.1-26
CMOS Analog Circuit Design © P.E. Allen - 2004
Scanning Electron Microscope of a MOSFET Cross-section
Fig. 2.8-20
TEOS
TEOS/BPSG
Tungsten Plug
SOG
Polycide
PolyGate
SidewallSpacer
Chapter 2 – Section 2 (5/02/04) Page 2.2-1
CMOS Analog Circuit Design © P.E. Allen - 2004
Scanning Electron Microscope Showing Metal Levels and Interconnect
Fig.180-11
Metal 1
Metal 2
Metal 3
TungstenPlugs
AluminumVias
Transistors
Chapter 2 – Section 2 (5/02/04) Page 2.2-2
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• Fabrication is the means by which the circuit components, both active and passive, are
built as an integrated circuit.• Basic process steps include:
1.) Oxide growth 2.) Thermal diffusion 3.) Ion implantation4.) Deposition 5.) Etching 6.) Epitaxy
• The complexity of a process can be measured in the terms of the number of maskingsteps or masks required to implement the process.
• Major CMOS Processing Steps: 1.) p and n wells 2.) Shallow trench isolation 3.) Threshold shift 4.) Thin oxide and gate polysilicon 5.) Lightly doped drains and sources 6.) Sidewall spacer 7.) Heavily doped drains and sources 8.) Siliciding (Salicide and Polycide) 9.) Bottom metal, tungsten plugs, and oxide10.) Higher level metals, tungsten plugs/vias, and oxide11.) Top level metal, vias and protective oxide
Chapter 2 – Section 2 (5/02/04) Page 2.2-3
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 2.2 - THE PN JUNCTIONAbrupt Junction
1. Doped atoms near the metallurgical junction lose their free carriers by diffusion.2. As these fixed atoms lose their free carriers, they build up an electric field, which
opposes the diffusion mechanism.3. Equilibrium conditions are reached when:
Current due to diffusion = Current due to electric field
Metallurgical Junction
p-type semiconductor n-type semiconductor
iD+ -vDDepletionregion
x
p-typesemicon-ductor
n-typesemicon-ductor
iD+
-W1 0
W
-Dv -
W2Fig. 06-01
Chapter 2 – Section 2 (5/02/04) Page 2.2-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Mathematical Characterization of the Abrupt PN JunctionAssume the pn junction is open-circuited.
Cross-section of an ideal pn junction:
Symbol for the pn junction:
Built-in potential, ψo:
ψo = Vt ln
NAND
ni2 ,
where Vt = kTq and ni2
is the intrinsic concentration of silicon.
ND
x0
Impurity concentration (cm-3)
x0
Depletion charge concentration (cm-3)
-W1
Electric Field (V/cm)
E0
x
x
Potential (V)
xd
ψ0
-NA
qND
-qNA
Fig. 06-04A
W2
iD
vD+ -
vD+ -
iD
Fig. 06-03
p-typesemicon-ductor
n-typesemicon-ductor
iD+
xp
-Dv -
xd
xn
Fig. 06-02
Chapter 2 – Section 2 (5/02/04) Page 2.2-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Physics of Abrupt PN JunctionsApply a forward bias voltage, vD, to the pn junction:1.) The voltage across the junction is ψo - vD.2.) Charge equality requires that W1NA = W2ND where
W1 (W2) = depletion region width on the p-side(n-side)3.) Poisson’s equation in one dimension is
d2vdx2 = -
ρε =
qNAε for -W1<x<0
where ρ = charge density q = charge of an electron (1.6x10-19 coulomb) ε = KSεo
KS = dielectric constant of silicon
εo = permittivity of free space (8.86x10-14F/cm)
4.) Integrating Poisson’s equation gives, dvdx =
qNAε x + C1
5.) The electric field, ε = - dvdx = -
qNA
ε x + C1
x0
Depletion charge concentration (cm-3)
-W1
qND
-qNA
W2
0-W1
Electric Field (V/cm)
E0
xW2
Chapter 2 – Section 2 (5/02/04) Page 2.2-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Physics of Abrupt PN Junctions - Continued6.) Since there is zero electric field outside the depletion region, a boundary condition is
ε = 0 for x = -W1This gives,
ε = - dvdx = -
qNAε x + W1 for -W1 < x< 0
Note that the maximum electric field occurs at x = 0which gives
εmax = -
qNAW1
ε7.) Integration of the electric field gives,
v = qNAε
x 2
2 + W1x + C2
8.) A second boundary condition is obtained by assuming that the potential of the neutralp-type region is zero. This boundary condition is,
v = 0 for x = -W1Substituting in the expression above gives,
v = qNAε
x 2
2 + W1x +W12
2
0-W1
Electric Field (V/cm)
Emax
xW2
0-W1
x
Potential (V)
xd
ψ0− vD
W2
V2
V1
Chapter 2 – Section 2 (5/02/04) Page 2.2-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Physics of Abrupt PN Junctions - Continued9.) At x =0, we define the potential v = V1 which gives
V1 = qNAε
W12
2If the potential difference from x = 0 to x = W2 is V2, then
V2 = qNDε
W22
210.) The total voltage across the pn junction is
ψo-vD = V1+V2 = q2ε
NAW12 + NDW22
11.) Substituting W1NA = W2ND into the above expression gives
ψo-vD = qNAW12
2ε
1+ NDNA
W2
W12
= qNAW12
2ε
1+ NA ND
12.) The depletion region width on the p-side of the pn junction is given as
W1 = 2ε(ψo -vD)
qNA
1 + NAND
and W2 =
2ε(ψo -vD)
qND
1 + NDNA
0-W1
x
Potential (V)
xd
ψ0− vD
W2
V2
V1
Chapter 2 – Section 2 (5/02/04) Page 2.2-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of the Abrupt PN Junction CharacterizationBarrier potential-
ψo = kTq ln
NAND
ni2 = Vt ln
NAND
ni2
Depletion region widths-
W1 =
2εsi(ψo-vD)NDqNA(NA+ND)
W2 = 2εsi(ψo-vD)NAqND(NA+ND)
W ∝ 1N
Depletion capacitance-
Cj =εsiA
d = εsiA
W1+W2 =
εsiA
2εsi(ψo-vD)q(ND+NA)
ND
NA+
NAND
= AεsiqNAND2(NA+ND)
1ψo-vD
= Cj0
1 - vDψo
Fig. 06-05vD0
Cj0
Cj
ψ0
Chapter 2 – Section 2 (5/02/04) Page 2.2-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 1An abrupt silicon pn junction has the doping densities of NA = 1015 atoms/cm3 and ND =1016 atoms/cm3. Calculate the junction built-in potential, the depletion-layer widths, themaximum field and the depletion capacitance with 10V reverse bias if Cj0 = 3pF.SolutionAt room temperature, kT/q = 26mV and the intrinsic concentration is ni = 1.5x1010 cm-3.
Therefore, the junction built-in potential is ψo = 0.026 ln
1015·1016
2.25x1026 = 0.637V
The depletion width on the p-side is,
W1 = 2·1.04x10-12·10.641.6x10-19·1015·1.1 = 3.55x10-4 cm = 3.55µm
The depletion width on the n-side is,
W2 = 2·1.04x10-12·10.641.6x10-19·1016·11 = 0.35x10-4 cm = 0.35µm
The maximum field occurs for x = 0 and is
Εmax = - qNAε W1 =
-1.6x10-19·1015·3.5x10-4
1.04x10-12 = -5.38x104 V/cm
The depletion capacitance can be found as Cj = 3pF
1 + (10/0.637) = 0.734pF
Chapter 2 – Section 2 (5/02/04) Page 2.2-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Reverse Breakdown and Leakage Current Characteristics of the PN JunctionBreakdown voltage
VR = εsi(NA+ND)
2qNAND E2
max ∝ 1N
where E2
max is the maximum electric field before breakdown occurs (usually due toavalanche breakdown).Reverse leakage currentThe reverse current, IR, increases by a multiplication factor M as the reverse voltageincreases and is
IRA = MIRwhere
M = 1
1 -
VR
BVn
ID (mA)
VD (V)
BV 5-5-10-15-20-25
1
2
3
-1
-2
-3 Fig. 6-06
Breakdown
VR
Chapter 2 – Section 2 (5/02/04) Page 2.2-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 2An abrupt pn junction has doping densities of NA = 3x1016 atoms/cm3 and ND = 4x1019
atoms/cm3. Calculate the breakdown voltage if Εcrit = 3x105 V/cm.
Solution
VR = εsi(NA+ND)
2qNAND E2
max ≈ εsi
2qNA E2
max = 1.04x10-12·9x1010
2·1.6x10-19·3x1016 = 9.7V
Chapter 2 – Section 2 (5/02/04) Page 2.2-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of a Graded PN Junction CharacterizationGraded junction:
ND
-NA
x0
Fig. 6-07
The previous expressions become:Depletion region widths-
W1 =
2εsi(ψo-vD)ND
qNA(NA+ND)m
W2 =
2εsi(ψo-vD)NA
qND(NA+ND)m W ∝
1
Nm
Depletion capacitance-
Cj = A
εsiqNAND
2(NA+ND)m
1
ψo-vD m = Cj0
1 - vDψo
m
where 0.33 ≤m ≤ 0.5.
Chapter 2 – Section 2 (5/02/04) Page 2.2-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Forward Bias Current-Voltage Relationship of the PN Junction
iD = Is
exp
vD
Vt - 1 where Is = qA
Dppno
Lp + Dnnpo
Ln ≈ qAD
L ni2
N = KT3exp
-VGO
Vt
-40 -30 -20 -10 0 10 20 30 40vD/Vt
iDIs
10
8
6
4
2
0
x1016
x1016
x1016
x1016
x1016
-5
0
5
10
15
20
25
-4 -3 -2 -1 0 1 2 3 4
iDIs
vD/Vt
Chapter 2 – Section 2 (5/02/04) Page 2.2-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Metal-Semiconductor JunctionsOhmic Junctions: A pn junction formed by a highly doped semiconductor and metal.
Energy band diagram IV Characteristics
ContactResistance
1
I
V
Vacuum Level
qφm qφsqφB EC
EF
EV
Thermionic or tunneling
n-type metal n-type semiconductor Fig. 2.3-4
Schottky Junctions: A pn junction formed by a lightly doped semiconductor and metal.Energy band diagram IV Characteristics
I
V
qφBECEF
EV
n-type metal
Forward Bias
Reverse Bias
Reverse Bias
Forward Bias
n-type semiconductor Fig. 2.3-5
Chapter 2 – Section 2 (5/02/04) Page 2.2-15
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARYCharacterized the reverse bias operation of the abrupt pn junction• pn junction has a barrier potential ψo
• Depletion region widths are proportional to N-0.5
• The pn junction depletion region acts like a voltage dependent capacitance
Applications of the reverse biased pn junction• Isolate transistors from the material they are built in• Variable capacitors - varactors
Chapter 2 – Section 3 (5/02/04) Page 2.3-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 2.3 - THE MOS TRANSISTORPhysical Structure of the n-channel and p-channel transistor in an n-well technology
L
W
L
W
sour
ce (n
+)
drai
n (n
+)
sour
ce (p
+)
drai
n (p
+)
n-well
SiO2Polysilicon
p- substrate
FOXn+ p+
p-channel transistor n-channel transistor
Substrate tieWell tie
FOX FOX FOX FOX
Fig. 2.4-1
How does the transistor work?Consider the enhancement n-channel MOSFET:
When the gate is positive with respect to the substrate a depletion region is formedbeneath the gate resulting in holes being pushed away from the Si-SiO2 interface.
When the gate voltage is sufficiently large (0.5-0.7V), the region beneath the gateinverts and a n-channel is formed between the source and drain.
Chapter 2 – Section 3 (5/02/04) Page 2.3-2
CMOS Analog Circuit Design © P.E. Allen - 2004
The MOSFET Threshold VoltageWhen the gate voltage reaches a value called the threshold voltage (VT), the substratebeneath the gate becomes inverted (it changes from p-type to n-type).
VT = φMS +
-2φF - QbCox
+
QSS
Cox
whereφMS = φF(substrate) - φF(gate)
φF = Equilibrium electrostatic potential (Femi potential)
φF(PMOS) = kTq ln(ND/ni) = Vt ln(ND/ni)
φF(NMOS) = kTq ln(ni/NA) = Vt ln(ni/NA)
Qb ≈ 2qNAεsi(|-2φF+vSB|)
QSS = undesired positive charge present between the oxide and the bulk silicon
Rewriting the threshold voltage expression gives,
VT = φMS -2φF - Qb0Cox
- QSSCox
- Qb - Qb0
Cox = VT0 + γ
|-2φF + vSB| - |-2φF|
where
VT0 = φMS - 2φF - Qb0Cox -
QSSCox
and γ = 2qεsiNA
Cox
Chapter 2 – Section 3 (5/02/04) Page 2.3-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Signs for the Quantities in the Threshold Voltage Expression
Parameter N-Channel P-ChannelSubstrate p-type n-typeφMS
Metal − −
n+ Si Gate − −
p+ Si Gate + +φF − +
Qb0,Qb − +Qss + +VSB + −γ + −
Chapter 2 – Section 3 (5/02/04) Page 2.3-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 2.3-1 - Calculation of the Threshold VoltageFind the threshold voltage and body factor γ for an n-channel transistor with an n+ silicongate if tox = 200Å, NA = 3 × 1016 cm-3, gate doping, ND = 4 × 1019 cm-3, and if thepositively-charged ions at the oxide-silicon interface per area is 1010 cm-2.SolutionThe intrinsic concentration is 1.45x1010 atoms/cm3. From above, φF(substrate) is givenas
φF(substrate) = -0.0259 ln
1.45×1010
3×1016 = -0.377 V
The equilibrium electrostatic potential for the n+ polysilicon gate is found from as
φF(gate) = 0.0259 ln
4×1019
1.45×1010 = 0.563 V
Therefore, the potential φMS is found to be
φF(substrate) -φF(gate) = -0.940 V.
The oxide capacitance is given as
Cox = εox/tox = 3.9 × 8.854 × 10-14
200 × 10-8 = 1.727×10-7 F/cm2
The fixed charge in the depletion region, Qb0, is given as
Qb0 = −[2×1.6×10-19×11.7×8.854×10-14×2×0.377×3×1016]1/2 = − 8.66×10-8 C/cm2.
Chapter 2 – Section 3 (5/02/04) Page 2.3-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 2.3-1 - ContinuedDividing Qb0 by Cox gives -0.501 V. Finally, Qss/Cox is given as
QssCox
= 1010×1.60×10-19
1.727×10-7 = 9.3×10-3 V
Substituting these values for VT0 gives
VT0 = - 0.940 + 0.754 + 0.501 - 9.3 x 10-3 = 0.306 VThe body factor is found as
γ =
2×1.6×10-19×11.7×8.854×10-14×3×1016 1/2
1.727×10-7 = 0.577 V1/2
Chapter 2 – Section 3 (5/02/04) Page 2.3-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Depletion Mode MOSFETThe channel is diffused into the substrate so that a channel exists between the source anddrain with no external gate potential.
Fig. 4.3-4n+ n+
p substrate (bulk)
Channel Length, L
n-channel
Polysilicon
Bulk Source Gate Drain
p+
Chann
el W
idth,
W
The threshold voltage for a depletion mode NMOS transistor will be negative (a negativegate potential is necessary to attract enough holes underneath the gate to cause thisregion to invert to p-type material).
Chapter 2 – Section 3 (5/02/04) Page 2.3-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Weak Inversion OperationWeak inversion operation occurs whenthe applied gate voltage is below VT andpertains to when the surface of thesubstrate beneath the gate is weaklyinverted.
Regions of operation according to the surface potential, φS.
φS < φF : Substrate not inverted
φF < φS < 2φF : Channel is weakly inverted (diffusion current)
2φF < φS : Strong inversion (drift current)
Drift current versusdiffusion current in aMOSFET:
yyyn+ n+
p-substrate/well
VGS
Diffusion Current
n-channel
log iD
10-6
10-120 VT
VGS
Drift CurrentDiffusion Current
Chapter 2 – Section 4 (5/02/04) Page 2.4-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 2.4 - PASSIVE COMPONENTSCAPACITORS
Types of Capacitors Considered• pn junction capacitors• Standard MOS capacitors• Accumulation mode MOS capacitors• Poly-poly capacitors• Metal-metal capacitors
Characterization of CapacitorsAssume C is the desired capacitance:1.) Dissipation (quality factor) of a capacitor is
Q = ωCRp
where Rp is the equivalent resistance in parallel with the capacitor, C.
2.) Cmax/Cmin ratio is the ratio of the largest value of capacitance to the smallest whenthe capacitor is used as a variable capacitor called varactor.
3.) Variation of capacitance with the control voltage.4.) Parasitic capacitors from both terminal of the desired capacitor to ac ground.
Chapter 2 – Section 4 (5/02/04) Page 2.4-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Desirable Characteristics of Varactors1.) A high quality factor2.) A control voltage range compatible with supply voltage3.) Good tunability over the available control voltage range4.) Small silicon area (reduces cost)5.) Reasonably uniform capacitance variation over the available control voltage range6.) A high Cmax/Cmin ratio
Some References for Further Information1.) P. Andreani and S. Mattisson, “On the Use of MOS Varactors in RF VCO’s,” IEEEJ. of Solid-State Circuits, vol. 35, no. 6, June 2000, pp. 905-910.2.) A-S Porret, T. Melly, C. Enz, and E. Vittoz, “Design of High-Q Varactors for Low-Power Wireless Applications Using a Standard CMOS Process,” IEEE J. of Solid-StateCircuits, vol. 35, no. 3, March 2000, pp. 337-345.3.) E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog IntegratedCircuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001
Chapter 2 – Section 4 (5/02/04) Page 2.4-3
CMOS Analog Circuit Design © P.E. Allen - 2004
PN Junction CapacitorsGenerally made by diffusion into the well.
Anode
n-well
p+
Substrate
Fig. 2.5-011
n+n+
p+
DepletionRegion
Cathode
p- substrate
CjCj
RwjRwj Rw
Cw
Rs
Anode Cathode
VA VBC
Rwj
rD
Layout:
Minimize the distance between the p+ and n+ diffusions.Two different versions have been tested.
1.) Large islands – 9µm on a side2.) Small islands – 1.2µm on a side n-well
n+ diffusion
p+ dif-fusion
Fig. 2.5-1A
Chapter 2 – Section 4 (5/02/04) Page 2.4-4
CMOS Analog Circuit Design © P.E. Allen - 2004
PN-Junction Capacitors – ContinuedThe anode should be the floating node and the cathode must be connected to ac ground.Experimental data (Q at 2GHz, 0.5µm CMOS):
00.5
1
1.52
2.5
3
3.54
0 0.5 1 1.5 2 2.5 3 3.5
CA
node
(pF
)
Cathode Voltage (V)
Large Islands
Small Islands
Cmax Cmin
0
20
40
60
80
100
120
0 0.5 1 1.5 2 2.5 3 3.5
QA
node
Qmin Qmax
Large Islands
Small Islands
Fig2.5-1BCathode Voltage (V)
Summary:
Small Islands (598 1.2µm x1.2µm) Large Islands (42 9µm x 9µm)TerminalUnder Test Cmax/Cmin Qmin Qmax Cmax/Cmin Qmin Qmax
Anode 1.23 94.5 109 1.32 19 22.6Cathode 1.21 8.4 9.2 1.29 8.6 9.5
Electrons as majority carriers lead to higher Q because of their higher mobility.The resistance, Rwj, is reduced in small islands compared with large islands ⇒ higher Q.
Chapter 2 – Section 4 (5/02/04) Page 2.4-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Single-Ended and Differential PN Junction CapacitorsDifferential configurations can reduce the bulk resistances and increase the effective Q.
VcontrolVS
n+ p+ n+ p+ p+ n+
n-well
VcontrolVS
-
n+ p+ p+ p+ p+ n+
n-well
VS+
VS
Vcontrol
VS+ VS
-
Vcontrol
Fig. 2.5-015
An examination of the electric field lines shows that because the symmetry inherent in thedifferential configuration, the path to the small-signal ground can be shortened if deviceswith opposite polarity alternate.
Chapter 2 – Section 4 (5/02/04) Page 2.4-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Standard MOS Capacitor (D = S = B)Conditions:• D = S = B• Operates from accumulation to
inversion• Nonmonotonic• Nonlinear p+
B
G D,S,B
p- substrate/bulk
p+p+
Fig. 2.5-012
n- well
n+
D S
VSG
Capacitance
StrongInversion
Accumulation
ModerateInversion
WeakInv.
Depletion
CoxCox
Charge carrier path
Chapter 2 – Section 4 (5/02/04) Page 2.4-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Inversion Mode MOS CapacitorsConditions:• D = S, B = VDD
• Accumulation region removedby connecting bulk to VDD
• Channel resistance:
Ron = L
12KP'(VBG-|VT|)
• LDD transistors will givelower Q because of theincreased series resistance
p+
B
G D,S
p- substrate/bulk
p+p+
Fig. 2.5-013
n- well
n+
D S
VSG
Capacitance
CoxCox
VDD
0
VT shift dueto VBS
p-channel
Charge carrier paths
B = D = S
InversionMode MOS
Chapter 2 – Section 4 (5/02/04) Page 2.4-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation Results for Standard and Inversion Mode 0.25µm CMOS Varactorsn-well:
Chapter 2 – Section 4 (5/02/04) Page 2.4-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Inversion Mode MOS Capacitors – ContinuedBulk tuning of the polysilicon-oxide-channel capacitor (0.35µm CMOS)
-0.65V
vBCG
1.0
0.8
0.6
0.4
0.20.0
-0.5-0.6-0.7-0.8-0.9-1.0-1.1-1.3-1.4-1.5 -1.2
CG
VT
vB (Volts)
Vol
ts o
r pF
Fig. 2.5-3
Cmax/Cmin ≈ 4
Interpretation:
Fig. 2.5-34
VSG
CapacitanceCox
0
InversionMode MOS
0.65V
Cmax
Cmin
VBS = -1.50VVBS = -1.05VVBS = -0.65V
Chapter 2 – Section 4 (5/02/04) Page 2.4-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Inversion Mode NMOS Varactor – ContinuedMore Detail - Includes the LDD transistor
Cox
p+
Bulk
G D,S
G
D,S
p- substrate/bulkn+n+
n- LDD
Rd RdCd CdCsi
CjRsj
Rsi
Cov Cov B
Fig. 2.5-2
Shown in inversion mode
Best results are obtained when the drain-source are on ac ground.Experimental Results (Q at 2GHz, 0.5µm CMOS):
1.5
2
2.5
3
3.5
4
4.5
0 0.5 1 1.5 2 2.5 3 3.5
CG
ate
(pF)
VG = 2.1V
VG = 1.8V
VG = 1.5V
Cmax Cmin
Drain/Source Voltage (V)
2224
26
2830
32
34
3638
0 0.5 1 1.5 2 2.5 3 3.5
VG = 2.1V
VG = 1.8V
VG = 1.5V
Qmax Qmin
Drain/Source Voltage (V) Fig. 2.5-1c
QG
ate
VG =1.8V: Cmax/Cmin ratio = 2.15 (1.91), Qmax = 34.3 (5.4), and Qmin = 25.8(4.9)
Chapter 2 – Section 4 (5/02/04) Page 2.4-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Accumulation Mode MOS CapacitorsConditions:• Remove p+ drain and source and put
n+ bulk contacts instead• Variable capacitor with a larger
transition region between themaximum and minimum values. p+
G B
p- substrate/bulk
n+
Fig. 2.5-014
n- well
n+
D S
VSG
Capacitance
CoxCox
0
Charge carrier paths
B=D=S
AccumulationMode MOS
Chapter 2 – Section 4 (5/02/04) Page 2.4-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Accumulation-Mode Capacitor – More Detail
Cox
p+Bulk
G D,S
G
D,S
p- substrate/bulk
n+n+
n- LDD
Rd RdCd Cd
Cw
Rs
Cov Cov B
Fig. 2.5-5
n- well
Rw
Shown in depletion mode.
Best results are obtained when the drain-source are on ac ground.Experimental Results (Q at 2GHz, 0.5µm CMOS):
2
2.4
2.8
3.2
3.6
4
0 0.5 1 1.5 2 2.5 3 3.5
CG
ate
(pF)
VG = 0.9V
VG = 0.6V
VG = 0.3V
Cmax Cmin
Drain/Source Voltage (V)
25
30
35
40
45
0 0.5 1 1.5 2 2.5 3 3.5
Qmax Qmin
Drain/Source Voltage (V)
QG
ate
VG = 0.9V
VG = 0.6V
VG = 0.3V
Fig. 2.5-6
VG = 0.6V: Cmax/Cmin ratio = 1.69 (1.61), Qmax = 38.3 (15.0), and Qmin = 33.2(13.6)
Chapter 2 – Section 4 (5/02/04) Page 2.4-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Differential Varactors†
Vcontrol
A B
Vcontrol
A B
VDD
Vcontrol
A B
Diode Varactor Inversion-PMOS Varactor Accumulation-PMOS VaractorFig. 040-01
† P. Andreani and S. Mattisson, “On the Use of MOS Varactors in RF VCO’s,” IEEE J. of Solid-State Circuits, Vol. 35, No. 6, June 2000, pp. 905-
910.
Varactor fL –fH(GHz)
fC(GHz)
TuningRange
Diode 1.73-1.93
1.83 10.9%
I-MOS 1.71-1.91
1.81 11.0%
A-MOS 1.70-1.89
1.80 10.6%
Chapter 2 – Section 4 (5/02/04) Page 2.4-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Compensated MOS-Capacitors in Depletion with Substrate Biasing†
Substrate biasing keeps the MOS capacitors in a broad depletion region and extends theusable voltage range and achieves a first-order cancellation of the nonlinearity effect.Principle:
† T. Tille, J. Sauerbrey and D. Schmitt-Landsiedel, “A 1.8V MOSFET-Only Σ∆ Modulator Using Substrate Biased Depletion-Mode MOS Capacitors
in Series Compensation,” IEEE J. of Solid-State Circuits, Vol. 36, No. 7, July 2001, pp. 1041-1047.
A BC
VSB1 VSB2
M1 M2
Fig. 040-02
Chapter 2 – Section 4 (5/02/04) Page 2.4-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Compensated MOS-Capacitors in Depletion – ContinuedMeasured CV plot of a series compensated MOS capacitor with different substrate biases(0.25µm CMOS, tox = 5nm, W1=W2=20µm and L1=L2=20µm):
Example of a realization of the seriescompensation without using floatingbatteries.
A BC
VS/D
M1 M2
Fig. 040-03
Keep the S/D at the lowestpotential to avoid forwardbiasing the bulk-source.
Chapter 2 – Section 4 (5/02/04) Page 2.4-16
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Capacitors - ContinuedPolysilicon-Oxide-Polysilicon (Poly-Poly):
substrate
IOXIOX
A B
IOX
FOX FOX
Polysilicon II
Polysilicon I
Best possible capacitor for analog circuitsLess parasiticsVoltage independentPossible approach for increasing the voltage linearity:
Top Plate
Bottom Plate
Top Plate
Bottom Plate
Chapter 2 – Section 4 (5/02/04) Page 2.4-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Implementation of Capacitors using Available Interconnect Layers
T
B
M3M2
M1T B
M3M2
M1PolyB
T
M2M1
PolyB T
M2M1
BT
Fig. 2.5-8
Chapter 2 – Section 4 (5/02/04) Page 2.4-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Horizontal Metal CapacitorsCapacitance between conductors on the same level and use lateral flux.
These capacitors are sometimes called fractal capacitors because the fractal patterns arestructures that enclose a finite area with a near-infinite perimeter.The capacitor/area can be increased by a factor of 10 over vertical flux capacitors.
+ - + -
+ - +-
Fringing field
Metal
Fig2.5-9
+ - + -Metal 3
Metal 2
Metal 1
Metal
Top view:
Side view:
Chapter 2 – Section 4 (5/02/04) Page 2.4-19
CMOS Analog Circuit Design © P.E. Allen - 2004
More Detail on Horizontal Metal Capacitors†
Some of the possible metal capacitor structures include:1.) Horizontal parallel plate (HPP).
2.) Parallel wires (PW):
† R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors, IEEE J. of Solid-State Circuits, vol. 37, no. 3,
March 2002, pp. 384-393.
030909-01
030909-02 Top ViewLateral View
Chapter 2 – Section 4 (5/02/04) Page 2.4-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Horizontal Metal Capacitors - Continued3.) Vertical parallel plates (VPP):
Vias
030909-03
4.) Vertical bars (VB):
Vias
030909-04
Top ViewLateral View
Chapter 2 – Section 4 (5/02/04) Page 2.4-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Horizontal Metal Capacitors - ContinuedExperimental results for a CMOS process with 3 layers of metal, Lmin =0.5µm, tox =0.95µm and tmetal = 0.63µm for the bottom 2 layers of metal.
StructureCap. Density
(aF/µm2)Caver.(pF)
Std. Dev.(fF)
σCaver.
fres.
(GHz)Q @
1 GHzRs (Ω) Break-
down (V)
VPP 158.3 18.99 103 0.0054 3.65 14.5 0.57 355PW 101.5 33.5 315 0.0094 1.1 8.6 0.55 380HPP 35.8 6.94 427 0.0615 6.0 21 1.1 690
Experimental results for a digital CMOS process with 7 layers of metal, Lmin =0.24µm, tox= 0.7µm and tmetal = 0.53µm for the bottom 5 layers of metal. All capacitors = 1pF.
Structure(1 pF)
Cap. Density(aF/µm2)
Caver.(pF)
Area(µm2)
Cap.Enhancement
Std.Dev.(fF)
σCaver.
fres.
(GHz)Q @
1 GHzBreak-down(V)
VPP 1512.2 1.01 670 7.4 5.06 0.0050 >40 83.2 128VB 1281.3 1.07 839.7 6.3 14.19 0.0132 37.1 48.7 124
HPP 203.6 1.09 5378 1.0 26.11 0.0239 21 63.8 500MIM 1100 1.05 960.9 5.4 - - 11 95 -
Chapter 2 – Section 4 (5/02/04) Page 2.4-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Horizontal Metal Capacitors - ContinuedHistogram of the capacitance distribution for the above case (1 pF):
0
2
4
6
8
10
12
94 96 98 100 102 104 106
HPPVPPPW
Num
ber
of d
ice
σcCaver
030909-05
Experimental results for a digital CMOS process with 7 layers of metal, Lmin =0.24µm, tox= 0.7µm and tmetal = 0.53µm for the bottom 5 layers of metal. All capacitors = 10pF.
Structure(10 pF)
Cap. Density(aF/µm2)
Caver.(pF)
Area(µm2)
Cap.Enhancement
Std.Dev.(fF)
σCaver.
fres.
(GHz)Q @
1 GHzBreak-down(V)
VPP 1480.0 11.46 7749 8.0 73.43 0.0064 11.3 26.6 125VB 1223.2 10.60 8666 6.6 73.21 0.0069 11.1 17.8 121
HPP 183.6 10.21 55615 1.0 182.1 0.0178 6.17 23.5 495MIM 1100 10.13 9216 6.0 - - 4.05 25.6 -
Chapter 2 – Section 4 (5/02/04) Page 2.4-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Capacitor Errors1.) Oxide gradients2.) Edge effects3.) Parasitics4.) Voltage dependence5.) Temperature dependence
Chapter 2 – Section 4 (5/02/04) Page 2.4-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Capacitor Errors - Oxide GradientsError due to a variation in oxide thickness across the wafer.
y
x1 x2 x1
A1 A2 B
A1 B A2
No common centroidlayout
Common centroidlayout
Only good for one-dimensional errors.An alternate approach is to layout numerous repetitions and connect them randomly toachieve a statistical error balanced over the entire area of interest.
A B C
A
A
B
B
C
C
A B C
A
A
B
B
C
C
A B C
A
A
B
B
C
C
0.2% matching of poly resistors was achieved using an array of 50 unit resistors.
Chapter 2 – Section 4 (5/02/04) Page 2.4-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Capacitor Errors - Edge EffectsThere will always be a randomness on the definition of the edge.However, etching can be influenced by the presence of adjacent structures.For example,
AC
A BC
B
Matching of A and B are disturbed by the presence of C.
Improved matching achieve by matching the surroundings of A and B.
Chapter 2 – Section 4 (5/02/04) Page 2.4-26
CMOS Analog Circuit Design © P.E. Allen - 2004
Capacitor Errors - Area/Periphery RatioThe best match between two structures occurs when their area-to-periphery ratios areidentical.Let C’1 = C1 ± ∆C1 and C’2 = C2 ± ∆C2
whereC’ = the actual capacitanceC = the desired capacitance (which is proportional to area)∆C = edge uncertainty (which is proportional to the periphery)
Solve for the ratio of C’2/C’1,
C’2C’1
= C2 ± ∆C2C1 ± ∆C1
= C2C1
1 ± ∆C2C2
1 ± ∆C1C1
≈ C2C1
1 ± ∆C2C2
1 -+ ∆C1C1
≈ C2C1
1 ± ∆C2C2
-+ ∆C1C1
If ∆C2C2
= ∆C1C1
, then C’2C’1
= C2C1
Therefore, the best matching results are obtained when the area/periphery ratio of C2 isequal to the area/periphery ratio of C1.
Chapter 2 – Section 4 (5/02/04) Page 2.4-27
CMOS Analog Circuit Design © P.E. Allen - 2004
Capacitor Errors - Relative AccuracyCapacitor relative accuracy is proportional to the area of the capacitors and inverselyproportional to the difference in values between the two capacitors.For example,
0.04
0.03
0.02
0.01
0.001 2 4 8 16 32 64
Unit Capacitance = 0.5pF
Unit Capacitance = 1pF
Unit Capacitance = 4pF
Rel
ativ
e A
ccur
acy
Ratio of Capacitors
Chapter 2 – Section 4 (5/02/04) Page 2.4-28
CMOS Analog Circuit Design © P.E. Allen - 2004
Capacitor Errors - ParasiticsParasitics are normally from the top and bottom plate to ac ground which is typically thesubstrate.
Top Plate
Bottom Plate
Desired Capacitor
Topplate
parasiticBottom
plateparasitic
Top plate parasitic is 0.01 to 0.001 of Cdesired
Bottom plate parasitic is 0.05 to 0.2 Cdesired
Chapter 2 – Section 4 (5/02/04) Page 2.4-29
CMOS Analog Circuit Design © P.E. Allen - 2004
Other Considerations on Capacitor AccuracyDecreasing Sensitivity to Edge Variation:
A A'
B B'
A A'
B B'
Sensitive to edge variation in both upper andlower plates
Sensitive to edge varation inupper plate only. Fig. 2.6-13
A structure that minimizes the ratio of perimeter to area (circle is best).
Top Plateof Capacitor
Fig. 2.6-14
Bottom plateof capacitor
Chapter 2 – Section 4 (5/02/04) Page 2.4-30
CMOS Analog Circuit Design © P.E. Allen - 2004
Definition of Temperature and Voltage CoefficientsIn general a variable y which is a function of x, y = f(x), can be expressed as a Taylorseries,
y(x = x0) ≈ y(x0) + a1(x- x0) + a2(x- x0)2+ a3(x- x0)3 + ···
where the coefficients, ai, are defined as,
a1 = df(x)dx
|x=x0 , a2 =
12
d2f(x)dx2
|x=x0 , ….
The coefficients, ai, are called the first-order, second-order, …. temperature or voltagecoefficients depending on whether x is temperature or voltage.Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a termcalled fractional temperature coefficient, TCF, which is defined as,
TCF(T=T0) = 1
f(T=T0) df(T)dT
|T=T0 parts per million/°C (ppm/°C)
or more simply,
TCF = 1
f(T) df(T)dT parts per million/°C (ppm/°C)
A similar definition holds for fractional voltage coefficient.
Chapter 2 – Section 4 (5/02/04) Page 2.4-31
CMOS Analog Circuit Design © P.E. Allen - 2004
Capacitor Errors - Temperature and Voltage Dependence
Polysilicon-Oxide-Semiconductor CapacitorsAbsolute accuracy ≈ ±10%Relative accuracy ≈ ±0.2%Temperature coefficient ≈ +25 ppm/C°Voltage coefficient ≈ -50ppm/V
Polysilicon-Oxide-Polysilicon CapacitorsAbsolute accuracy ≈ ±10%Relative accuracy ≈ ±0.2%Temperature coefficient ≈ +25 ppm/C°Voltage coefficient ≈ -20ppm/V
Accuracies depend upon the size of the capacitors.
Chapter 2 – Section 4 (5/02/04) Page 2.4-32
CMOS Analog Circuit Design © P.E. Allen - 2004
RESISTORSMOS Resistors - Source/Drain Resistor
p- substrate
FOX FOX
SiO2
Metal
n- well
p+
Fig. 2.5-16
Diffusion:10-100 ohms/squareAbsolute accuracy = ±35%Relative accuracy=2% (5µm), 0.2% (50µm)Temperature coefficient = +1500 ppm/°CVoltage coefficient ≈ 200 ppm/V
Ion Implanted:500-2000 ohms/squareAbsolute accuracy = ±15%Relative accuracy=2% (5µm), 0.15% (50µmTemperature coefficient = +400 ppm/°CVoltage coefficient ≈ 800 ppm/V
Comments:• Parasitic capacitance to substrate is voltage dependent.• Piezoresistance effects occur due to chip strain from mounting.
Chapter 2 – Section 4 (5/02/04) Page 2.4-33
CMOS Analog Circuit Design © P.E. Allen - 2004
Polysilicon Resistor
Fig. 2.5-17
p- substrate
FOX
Polysilicon resistorMetal
30-100 ohms/square (unshielded)100-500 ohms/square (shielded)Absolute accuracy = ±30%Relative accuracy = 2% (5 µm)Temperature coefficient = 500-1000 ppm/°CVoltage coefficient ≈ 100 ppm/VComments:• Used for fuzzes and laser trimming• Good general resistor with low parasitics
Chapter 2 – Section 4 (5/02/04) Page 2.4-34
CMOS Analog Circuit Design © P.E. Allen - 2004
N-well Resistor
Fig. 2.5-18
p- substrate
FOX FOX
Metal
n- well
n+
FOX
1000-5000 ohms/squareAbsolute accuracy = ±40%Relative accuracy ≈ 5%Temperature coefficient = 4000 ppm/°CVoltage coefficient is large ≈ 8000 ppm/VComments:• Good when large values of resistance are needed.• Parasitics are large and resistance is voltage dependent
Chapter 2 – Section 4 (5/02/04) Page 2.4-35
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Passive RC Component Performance Summary
Component Type Range ofValues
AbsoluteAccuracy
RelativeAccuracy
TemperatureCoefficient
VoltageCoefficient
Poly-oxide-semi-conductor Capacitor
0.35-0.5fF/µm2
10% 0.1% 20ppm/°C ±20ppm/V
Poly-Poly Capacitor 0.3-0.4fF/µm2
20% 0.1% 25ppm/°C ±50ppm/V
Diffused Resistor 10-100Ω/sq.
35% 2% 1500ppm/°C 200ppm/V
Ion ImplantedResistor
0.5-2kΩ/sq.
15% 2% 400ppm/°C 800ppm/V
Poly Resistor 30-200Ω/sq.
30% 2% 1500ppm/°C 100ppm/V
n-well Resistor 1-10 kΩ/sq. 40% 5% 8000ppm/°C 10kppm/V
Chapter 2 – Section 4 (5/02/04) Page 2.4-36
CMOS Analog Circuit Design © P.E. Allen - 2004
Future Technology Impact on Passive RC ComponentsWhat will be the impact of scaling down in CMOS technology?• Resistors – probably little impact• Capacitors – a different story
The capacitance can be divided into gate capacitance and overlap capacitance.Gate capacitance varies with external voltage changesOverlap capacitances are constant with respect to external voltage changes
∴ As the channel length decreases, the gate capacitance becomes less of the totalcapacitance and consequently the Cmax/Cmin will decrease. However, the Q of thecapacitor will increase because the physical dimensions are getting smaller.
Best capacitor for future scaled CMOS?The standard mode CMOS depeletion capacitor because Cmax/Cmin is larger thanthat for the accumulation mode and Q should be sufficient.
Chapter 2 – Section 4 (5/02/04) Page 2.4-37
CMOS Analog Circuit Design © P.E. Allen - 2004
INDUCTORSInductorsWhat is the range of values for on-chip inductors?
0 10 20 30 40 50
12
10
8
6
4
2
0Frequency (GHz)
Indu
ctan
ce (
nH)
ωL = 50Ω
Inductor area is too large
Interconnect parasiticsare too large
Fig. 6-5
Consider an inductor used to resonate with 5pF at 1000MHz.
L = 1
4π2fo2C =
1(2π·109)2·5x10-12 = 5nH
Note: Off-chip connections will result in inductance as well.
Chapter 2 – Section 4 (5/02/04) Page 2.4-38
CMOS Analog Circuit Design © P.E. Allen - 2004
Candidates for inductors in CMOS technology are:1.) Bond wires2.) Spiral inductors3.) Multi-level spiral4.) Solenoid
Bond wire Inductors:
β β
d Fig.6-6
• Function of the pad distance d and the bond angle β• Typical value is 1nH/mm which gives 2nH to 5nH in typical packages• Series loss is 0.2 Ω/mm for 1 mil diameter aluminum wire• Q ≈ 60 at 2 GHz
Chapter 2 – Section 4 (5/02/04) Page 2.4-39
CMOS Analog Circuit Design © P.E. Allen - 2004
Planar Spiral InductorsSpiral Inductors on a Lossy Substrate:
C1
L R
C2
R2R1
Fig. 16-7
• Design Parameters:Inductance,L = Σ(Lself + Lmutual)
Quality factor, Q = ωLR
Self-resonant frequency: fself = 1LC
• Trade-off exists between the Q and self-resonant frequency• Typical values are L = 1-8nH and Q = 3-6 at 2GHz
Chapter 2 – Section 4 (5/02/04) Page 2.4-40
CMOS Analog Circuit Design © P.E. Allen - 2004
Planar Spiral Inductors - ContinuedInductor Design
I
I
I
I
W
S
ID
Nturns = 2.5
SiO2
Silicon
Fig. 6-9
Typically: 3 < Nturns < 5 and S = Smin for the given current
Select the OD, Nturns, and W so that ID allows sufficient magnetic flux to flowthrough the center.Loss Mechanisms:• Skin effect• Capacitive substrate losses• Eddy currents in the silicon
Chapter 2 – Section 4 (5/02/04) Page 2.4-41
CMOS Analog Circuit Design © P.E. Allen - 2004
Planar Spiral Inductors - ContinuedInfluence of a Lossy Substrate
C1
L R
C2
R2R1
Fig. 12.2-13
CLoad
where:L is the desired inductanceR is the series resistanceC1 and C2 are the capacitance from the inductor to the ground plane
R1 and R2 are the eddy current losses in the silicon
Guidelines for using spiral inductors on chip:• Lossy substrate degrades Q at frequencies close to fself• To achieve an inductor, one must select frequencies less than fself• The Q of the capacitors associated with the inductor should be very high
Chapter 2 – Section 4 (5/02/04) Page 2.4-42
CMOS Analog Circuit Design © P.E. Allen - 2004
Planar Spiral Inductors - ContinuedComments concerning implementation:1.) Put a metal ground shield between the inductor and the silicon to reduce thecapacitance.
• Should be patterned so flux goes through but electric field is grounded• Metal strips should be orthogonal to the spiral to avoid induced loop current• The resistance of the shield should be low to terminate the electric field
2.) Avoid contact resistance wherever possible to keep the series resistance low.3.) Use the metal with the lowest resistanceand furtherest away from the substrate.4.) Parallel metal strips if other metal levelsare available to reduce the resistance.Example:
Fig. 2.5-12
Chapter 2 – Section 4 (5/02/04) Page 2.4-43
CMOS Analog Circuit Design © P.E. Allen - 2004
Multi-Level Spiral InductorsUse of more than one level of metal to make the inductor.• Can get more inductance per area• Can increase the interwire capacitance so the different levels are often offset to get
minimum overlap.• Multi-level spiral inductors suffer from contact resistance (must have many parallel
contacts to reduce the contact resistance).• Metal especially designed for inductors is top level approximately 4µm thick.
Q = 5-6, fSR = 30-40GHz. Q = 10-11, fSR = 15-30GHz1. Good for high L in small area.
1 The skin effect and substrate loss appear to be the limiting factor at higher frequencies of self-resonance.
Chapter 2 – Section 4 (5/02/04) Page 2.4-44
CMOS Analog Circuit Design © P.E. Allen - 2004
Inductors - ContinuedSelf-resonance as a function of inductance. Outer dimension of inductors.
Chapter 2 – Section 4 (5/02/04) Page 2.4-45
CMOS Analog Circuit Design © P.E. Allen - 2004
Solenoid InductorsExample:
Coil Current
Magnetic Flux
Coil CurrentUpper Metal
Lower Metal
ContactVias
Silicon
SiO2
Fig. 6-11
Comments:• Magnetic flux is small due to planar structure• Capacitive coupling to substrate is still present• Potentially best with a ferromagnetic core
Chapter 2 – Section 4 (5/02/04) Page 2.4-46
CMOS Analog Circuit Design © P.E. Allen - 2004
TransformersTransformer structures are easily obtained using stacked inductors as shown below for a1:2 transformer.
Method of reducing theinter-winding capacitances.
4 turns 8 turns 3 turns
Measured 1:2 transformer voltage gains:
Chapter 2 – Section 4 (5/02/04) Page 2.4-47
CMOS Analog Circuit Design © P.E. Allen - 2004
Transformers – ContinuedA 1:4 transformer:Structure- Measured voltage gain-
(CL = 0, 50fF, 100fF, 500fF and 1pF.CL is the capacitive loading on thesecondary.)
Secondary
Chapter 2 – Section 5 (5/02/04) Page 2.5-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 2.5 - OTHER CONSIDERATIONS OF CMOS TECHNOLOGYLateral Bipolar Junction TransistorP-Well Process, NPN Lateral:
Emitter Collector
p+ n+ n+
p-well
Base
n+
n-substrate
VDD
Chapter 2 – Section 5 (5/02/04) Page 2.5-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Lateral Bipolar Junction Transistor - ContinuedField-aided Lateral-ßF ≈ 50 to 100 depending on the process
Emitter Collector
p+ n+ n+
p-well
Base
n+
n-substrate
VDD VGate
Keep channelfrom forming
• Good geometry matching• Low 1/f noise (if channel doesn’t form)• Acts like a photodetector with good efficiency
Chapter 2 – Section 5 (5/02/04) Page 2.5-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Geometry of the Lateral PNP BJTMinimum Size layout of a single 40 emitter dot LPNP transistor (total device area
emitter dot lateral PNP BJT: is 0.006mm2 in a 1.2µm CMOS process):
n-well
p-substrate diffusion
n-wellcontact
Base
LateralCollector
EmitterGate(poly)
31.2 µm
33.0 µm
p-diffusion contact
VSS
84.0 µm
Emitter
Gate
LateralCollector
Base
71.4 µm
V SS
Chapter 2 – Section 5 (5/02/04) Page 2.5-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Performance of the Lateral PNP BJTSchematic:
Emitter
Gate
Base
LateralCollector
VerticalCollector
VSS( )
ßL vs ICL for the 40 emitter Lateral efficiency versus IE for the 40
dot LPNP BJT: emitter dot LPNP BJT:
100 nA 1 µA 10 µA 100 µA 10 nA
Lateral Collector Current
1 nA 1 mA
150
110
90
70
Lat
eral
ß
130
50
VCE =− 4.0 V
VCE =− 0.4 V
VCE =− 0 .4V
VCE
=− 4.0 V
100 nA 1 µA 10 µA 100 µA 10 nA
Emitter Current
1 nA 1 mA
1.0
0.8
0.6
0.4
0.2
0
Lat
eral
Eff
icie
ncy
Chapter 2 – Section 5 (5/02/04) Page 2.5-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Performance of the Lateral PNP BJT - ContinuedTypical Performance for the 40 emitter dot LPNP BJT:
Transistor area 0.006 mm2
Lateral ß 90Lateral efficiency 0.70Base resistance 150 ΩEn @ 5 Hz 2.46 nV / Hz En (midband) 1.92 nV / Hz fc (En) 3.2 HzIn @ 5 Hz 3.53 pA / Hz In (midband) 0.61 pA / Hz fc (In) 162 Hz
fT 85 MHzEarly voltage 16 V
Chapter 2 – Section 5 (5/02/04) Page 2.5-6
CMOS Analog Circuit Design © P.E. Allen - 2004
High Voltage MOS TransistorThe well can be substituted for the drain giving a lower conductivity drain and thereforehigher breakdown voltage.NMOS in n-well example:
Polysilicon
Source
Oxide
ChannelDrainSource
n-well
n+n+ p+
Substrate
Fig. 190-07
p-substrate
Gate
Drain-substrate/channel can be as large as 20V or more.Need to make the channel longer to avoid breakdowns via the channel.
Chapter 2 – Section 5 (5/02/04) Page 2.5-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Latch-up in CMOS TechnologyLatch-up Mechanisms:1. SCR regenerative switching action.2. Secondary breakdown.3. Sustaining voltage breakdown.Parasitic lateral PNP and vertical NPN BJTs in a p-well CMOS technology:
p+
n+
n+
p+
n+
yyVDD D DG S S G VSS
p-well
n- substrate
RN-RP-
AB
p+
Fig. 190-08
Equivalent circuit of the SCRformed from the parasitic BJTs:
VDD
VSS
RN-
RP-
A
B
VDD
VSS
Vin ≈ Vout
A
B
Fig. 190-09
VSS
+
-
Chapter 2 – Section 5 (5/02/04) Page 2.5-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Preventing Latch-Up in a P-Well Technology1.) Keep the source/drain of the MOS device not in the well as far away from the well as
possible. This will lower the value of the BJT betas.2.) Reduce the values of RN- and RP-. This requires more current before latch-up can
occur.3.) Make a p- diffusion around the p-well. This shorts the collector of Q1 to ground.
Figure 190-10
p-welln- substrate
FOX
n+ guard barsn-channel transistor
p+ guard barsp-channel transistor
VDD VSS
FOX FOX FOXFOXFOXFOX
For more information see R. Troutman, “CMOS Latchup”, Kluwer Academic Publishers.
Chapter 2 – Section 5 (5/02/04) Page 2.5-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Electrostatic Discharge Protection (ESD)Objective: To prevent large external voltages from destroying the gate oxide.
p-substrate
FOX
Metal
n-well
FOXn+ p+
Electrical equivalent circuitVDD
VSS
To internal gates BondingPad
Implementation in CMOS technology
p+ to n-welldiode
n+ to p-substratediode
p+ resistor
FOX
Fig. 190-11
Chapter 2 – Section 5 (5/02/04) Page 2.5-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Temperature Characteristics of TransistorsFractional Temperature Coefficient
TCF =1x·∂x∂T Typically in ppm/°C
MOS Transistor
VT = V(T0) + α(T-T0) + ···, where α ≈ -2.3mV/°C (200°K to 400°K)
µ = KµT-1.5
BJT TransistorReverse Current, IS:
1IS
·∂IS∂T =
3T +
1T
VG0kT/q
Empirically, IS doubles approximately every 5°C increase
Forward Voltage, vD:
∂vD∂Τ = -
VG0 - vDT -
3kT/qT ≈ -2mV/°C at vD = 0.6V
Chapter 2 – Section 5 (5/02/04) Page 2.5-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Noise in TransistorsShot Noise
i2 = 2qID∆f (amperes2) where
q = charge of an electronID = dc value of iD∆f = bandwidth in Hz
Noise current spectral density = i2
∆f (amperes2/Hz)
Thermal NoiseResistor:
v2 = 4kTR∆f (volts2) MOSFET:
iD2 = 8kTgm∆f
3 (ignoring bottom gate)
wherek = Boltzmann’s constantR = resistor or equivalent resistor in which the thermal noise is occurring.gm = transconductance of the MOSFET
Chapter 2 – Section 5 (5/02/04) Page 2.5-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Noise in Transistors - ContinuedFlicker (1/f) Noise
iD2 = Kf
Ia
fb ∆f
whereKf = constant (10-28 Farad·amperes)
a = constant (0.5 to 2)b = constant (≈1)
Noise powerspectral density
log(f)
1/f
Fig. 190-12
Chapter 2 – Section 6 (5/02/04) Page 2.6-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 2.6 – INTEGRATED CIRCUIT LAYOUTMatching Concepts1.) Unit matching principle – Always implement two unequal components by an integernumber of unit components.
1.0 1.5 0.5 0.5 0.5 0.5 0.5
1.0
1.5 Fig. 2.6-01
2.) Common-centroid layout (illustrated above).3.) Elimination of mismatch due tosurrounding material
A BC
A BC
Fig. 2.6-02
4.) Minimize the ratio of the perimeter to the area (a circle is optimum).5.) For parallel plates make one larger than the other to eliminate alignment problems.
Chapter 2 – Section 6 (5/02/04) Page 2.6-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Matching Concepts - Continued6.) Maintain a constant area-to-perimeter ratio between matching elements.
Yiannoulos path – A serpentine structure that maintains a constant area-to-perimeterratio and allows efficient use of area.
Total area is12.5 units
Total area is18 units.
One unit
Etch compensation
Fig. 2.6-03
Total perimeteris 25 units
Total perimeteris 36 units
Both structures have a periphery/area ratio of 2.
Chapter 2 – Section 6 (5/02/04) Page 2.6-3
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Transistor LayoutExample of the layout of a single MOS transistor:
Contact
Polysilicongate
Active areadrain/source
Metal 1
W
L
Cut
FOX FOX
Metal
Active areadrain/source
Fig. 2.6-04
Comments:• Make sure to contact the source and drain with multiple contacts to evenly distribute
the current flow under the gate.• Minimize the area of the source and drain to reduce bulk-source/drain capacitance.
Chapter 2 – Section 6 (5/02/04) Page 2.6-4
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Transistor Layout - ContinuedFor best matching, the transistor “stripes” should be oriented in the same direction (notorthogonal).Photolithographic invariance (PLI) are transistors that exhibit identical orientation.Examples of the layout of matched MOS transistors:1.) Examples of mirror symmetry and photolithographic invariance.
Mirror Symmetry
Photolithographic Invariance
Fig. 2.6-05
Chapter 2 – Section 6 (5/02/04) Page 2.6-5
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Transistor Layout - Continued2.) Two transistors sharing a common source and laid out to achieve both
photolithographic invariance and common centroid.
Metal 2
Via 1
Metal 1
Fig. 2.6-06
Chapter 2 – Section 6 (5/02/04) Page 2.6-6
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Transistor Layout - Continued3.) Compact layout of the previous example.
Fig. 2.6-07
Metal 2
Metal 2
Via 1
Metal 1
Chapter 2 – Section 6 (5/02/04) Page 2.6-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Resistor Layout
L
W
T
Direction of current flow
Area, AFig. 2.6-15
Resistance of a conductive sheet is expressed in terms of
R = ρLA =
ρLWT (Ω)
whereρ = resistivity in Ω-m
Ohms/square:
R =
ρ
T LW = ρS
LW (Ω)
whereρS is a sheet resistivity and has the units of ohms/square
Chapter 2 – Section 6 (5/02/04) Page 2.6-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Example of Resistor Layouts
Metal 1
Active area or PolysiliconContact
Diffusion or polysilicon resistor
L
W
Metal 1
Well diffusionContact
Well resistor
L
WActive area
FOX FOXFOX
Metal
Active area (diffusion)
FOX FOX
Metal
Active area (diffusion) Well diffusion
CutCut
Substrate Substrate
Fig. 2.6-16
Corner corrections:
0.51.45 1.25
Fig. 2.6-16B
Chapter 2 – Section 6 (5/02/04) Page 2.6-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 2.6-1 Resistance CalculationGiven a polysilicon resistor like that drawn above with W=0.8µm and L=20µm, calculate
ρs (in Ω/), the number of squares of resistance, and the resistance value. Assume thatρ for polysilicon is 9 × 10-4 Ω-cm and polysilicon is 3000 Å thick. Ignore any contactresistance.SolutionFirst calculate ρs.
ρs = ρT =
9 × 10-4 Ω-cm 3000 × 10-8 cm = 30 Ω/
The number of squares of resistance, N, is
N = LW =
20µm0.8µm = 25
giving the total resistance asR = ρs × Ν = 30 × 25 = 750 Ω
Chapter 2 – Section 6 (5/02/04) Page 2.6-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Capacitor Layout
Polysilicon gate
FOX
Metal Polysilicon 2
Cut
Polysilicon gatePolysilicon 2
FOX
Metal 3 Metal 2 Metal 1
Metal 3 Metal 1 Metal 3
Metal 2
Metal 1
Via 2
Via 2
Via 1
Cut
Double-polysilicon capacitor Triple-level metal capacitor.
Metal 1
Substrate
Substrate
Metal 2
Fig. 2.6-17
Chapter 2 – Section 6 (5/02/04) Page 2.6-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Design RulesDesign rules are geometrical constraints that guarantee the proper operation of a circuitimplemented by a given CMOS process.These rules are necessary to avoid problems such as device misalignment, metalfracturing, lack of continuity, etc.Design rules are expressed in terms of minimum dimensions such as minimum values of:
- Widths- Separations- Extensions- Overlaps
• Design rules typically use a minimum feature dimension called “lambda”. Lambda isusually equal to the minimum channel length.
• Minimum resolution of the design rules is typically half lambda.• In most processes, lambda can be scaled or reduced as the process matures.
Chapter 2 – Section 7 (5/02/04) Page 2.7-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 2.7 - BIPOLAR TRANSISTOR (OPTIONAL)
Major Processing Steps for a Junction Isolated BJT TechnologyStart with a p substrate.
1. Implantation of the buried n+ layer2. Growth of the epitaxial layer
3. p+ isolation diffusion4. Base p-type diffusion
5. Emitter n+ diffusion
6. p+ ohmic contact7. Contact etching8. Metal deposition and etching9. Passivation and bond pad opening
Chapter 2 – Section 7 (5/02/04) Page 2.7-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Implantation of the Buried Layer (Mask Step 1)Objective of the buried layer is to reduce the collector resistance.
Fig.2.7-1
p substrate
p+ p p- ni n- n n+ Metal
n++ implantation for buried layer
TOPVIEW
SIDEVIEW
Chapter 2 – Section 7 (5/02/04) Page 2.7-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Epitaxial Layer (No Mask Required)The objective is to provide the proper n-type doping in which to build the npn BJT.
Fig.2.7-2
p substrate
n+ buried layer
n collector
p+ p p- ni n- n n+ Metal
Assume the n+ buried layer can be seen underneath the epitaxial collector
TOPVIEW
SIDEVIEW
EpitaxialRegion
Chapter 2 – Section 7 (5/02/04) Page 2.7-4
CMOS Analog Circuit Design © P.E. Allen - 2004
p+ isolation diffusion (Mask Step 2)
The objective of this step is to surround (isolate) the npn BJT by a p+ diffusion. Theseregions also permit contact to the substrate from the surface.
Fig.2.7-3
p substrate
p+ isolation
n+ buried layer
n collector
p+ isolation
p+ p p- ni n- n n+ Metal
TOPVIEW
SIDEVIEW
p+ isolation
n collector
Assume that the n+ buried region can be seen
Chapter 2 – Section 7 (5/02/04) Page 2.7-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Base p-type diffusion (Mask Step 3)The step provides the p-type base for the npn BJT.
Fig.2.7-4
p substrate
p+ isolation p base
n+ buried layer
n collector
p- isolation
p+ p p- ni n- n n+ Metal
TOPVIEW
SIDEVIEW
p basen collector
Chapter 2 – Section 7 (5/02/04) Page 2.7-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Emitter n+ diffusion (Mask Step 4)
This step implements the n+ emitter of the npn BJT and the collector ohmic contact.
Fig.2.7-5
p substrate
p+ isolation p base
n+ emitter
n+ buried layer
n collector
n+ p+ isolation
p+ p p- ni n- n n+ Metal
TOPVIEW
SIDEVIEW
Chapter 2 – Section 7 (5/02/04) Page 2.7-7
CMOS Analog Circuit Design © P.E. Allen - 2004
p+ ohmic contact (Mask Step 5)This step permits ohmic contact to the base region if it is not doped sufficiently high.
Fig.2.7-6
p substrate
p+ isolation p base
n+ emitter
n+ buried layer
n collector
n+ p+ p+ isolation
p+ p p- ni n- n n+ Metal
TOPVIEW
SIDEVIEW
Chapter 2 – Section 7 (5/02/04) Page 2.7-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Contact etching (Mask Step 6)This step opens up the areas in the dielectric area which metal will contact.
Fig.2.7-7
p substrate
p+ isolation p base
n+ emitter
n+ buried layer
n collector
n+ p+ p+ isolation
p+ p p- ni n- n n+ Metal
TOPVIEW
SIDEVIEW
Dielectric Layer
Chapter 2 – Section 7 (5/02/04) Page 2.7-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Metal deposition and etching (Mask Step 7)In this step, metal is deposited over the entire wafer and removed where it is not wanted.
Fig.2.7-8
p substrate
p+ isolation p base
n+ emitter
n+ buried layer
n collector
n+ p+ p+ isolation
TOPVIEW
SIDEVIEW
Chapter 2 – Section 7 (5/02/04) Page 2.7-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Passivation (Mask Step 8)Cover the entire wafer with glass and open the area over bond pads (requires anothermask).
Fig.2.7-9
p substrate
p+ isolation p base
n+ emitter
n+ buried layer
n collector
n+ p+ p+ isolation
TOPVIEW
SIDEVIEW
Passivation
x
Chapter 2 – Section 7 (5/02/04) Page 2.7-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Typical Impurity Concentration Profile for the npn BJTTaken along the line from the surface indicated in the last slide.
Fig. 2.7-10
1021
1020
1019
1018
1017
1016
1015
1014
1013
1012
1 2 3 4 5 6 7 8 9 10 11 12Impu
rity
Con
cent
ratio
n (c
m- 3
)
x, Depth from thesurface (microns)
Em
itter
Base Collector Buried Layer Substrate
n+ p n n+ p
Substrate Doping Level
Epitaxialcollector
doping level
Chapter 2 – Section 7 (5/02/04) Page 2.7-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Substrate pnp BJTCollector is always connected to the substrate potential which is the most negative DCpotential.
Fig.2.7-11
p collector/substrate
p+ isolation/collector
p emitter
n base
n+ p+ p+ isolation/collector
p+ p p- ni n- n n+ Metal
TOPVIEW
SIDEVIEW
Chapter 2 – Section 7 (5/02/04) Page 2.7-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Lateral pnp BJTCollector is not constrained to a fixed dc potential.
Fig.2.7-12
p substrate
p+ isolation
n+ buried layer
n base
n+ p+ isolation
p+ p p- ni n- n n+ Metal
TOPVIEW
SIDEVIEW
p collector p emitter
p+ p+
Chapter 2 – Section 7 (5/02/04) Page 2.7-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Types of Modifications to the Standard npn Technology1.) Dielectric isolation - Isolation of the transistor from the substrate using an oxide
layer.
2.) Double diffusion - A second, deeper n+ emitter diffusion is used to create JFETs.3.) Ion implanted JFETs - Use of an ion implantation to create the upper gate of a p-
channel JFET4.) Superbeta transistors - Use of a very thin base width to achieve higher values of βF.
5.) Double diffused pnp BJT - Double diffusion is used to build a vertical pnp transistorwhose performance more closely approaches that of the npn BJT.
Chapter 2 – Section 8 (5/02/04) Page 2.8-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 2.8 - BiCMOS TECHNOLOGY (OPTIONAL)Typical 0.5µm BiCMOS TechnologyMasking Sequence:
1. Buried n+ layer 13. PMOS lightly doped drain
2. Buried p+ layer 14. n+ source/drain 3. Collector tub 15. p+ source/drain 4. Active area 16. Silicide protection 5. Collector sinker 17. Contacts 6. n-well 18. Metal 1 7. p-well 19. Via 1 8. Emitter window 20. Metal 2 9. Base oxide/implant 21. Via 210. Emitter implant 22. Metal 311. Poly 1 23. Nitride passivation12. NMOS lightly doped drain
Notation:BSPG = Boron and Phosphorus doped Silicate Glass (oxide)Kooi Nitride = A thin layer of silicon nitride on the silicon surface as a result of the
reaction of silicon with the HN3 generated, during the field oxidation.TEOS = Tetro-Ethyl-Ortho-Silicate. A chemical compound used to deposit conformaloxide films.
Chapter 2 – Section 8 (5/02/04) Page 2.8-2
CMOS Analog Circuit Design © P.E. Allen - 2004
n+ and p+ Buried Layers
Starting Substrate:
p-substrate 1µm
5µmBiCMOS-01
n+ and p+ Buried Layers:
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
1µm
5µm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-02
Chapter 2 – Section 8 (5/02/04) Page 2.8-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Epitaxial Growth
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layerp+ buried layer
p-typeEpitaxialSilicon
p-well n-well p-well
1µm
5µm
NMOS TransistorPMOS TransistorNPN Transistor
n-well
BiCMOS-03
Comment:• As the epi layer grows vertically, it assumes the doping level of the substrate beneath it.• In addition, the high temperature of the epitaxial process causes the buried layers to
diffuse upward and downward.
Chapter 2 – Section 8 (5/02/04) Page 2.8-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Collector Tub
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-welln-well
p-well
1µm
5µm
Collector Tub
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-04
Original Area of CollectorTub Implant
Comment:• The collector area is developed by an initial implant followed by a drive-in diffusion to
form the collector tub.
Chapter 2 – Section 8 (5/02/04) Page 2.8-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Active Area Definition
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-welln-well
p-well
1µm
5µm
Collector Tub
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-05
Nitrideα-Silicon
Comment:• The silicon nitride is use to impede the growth of the thick oxide which allows contact
to the substrate• α-silicon is used for stress relief and to minimize the bird’s beak encroachment
Chapter 2 – Section 8 (5/02/04) Page 2.8-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Field Oxide
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
FOX
p-welln-well
p-well
1µm
5µm
Collector Tub
Field Oxide Field Oxide
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-06
FOX Field Oxide
Comments:• The field oxide is used to isolate surface structures (i.e. metal) from the substrate
Chapter 2 – Section 8 (5/02/04) Page 2.8-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Collector Sink and n-Well and p-Well Definitions
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µm
Collector Tub
Field Oxide
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-07
FOX
Field Oxide
Collector Sink Anti-Punch ThroughThreshold Adjust
Anti-Punch ThroughThreshold Adjust
n-well
FOX Field Oxide
Chapter 2 – Section 8 (5/02/04) Page 2.8-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Base Definition
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
FOX
p-well p-well
1µm
5µm
Collector Tub
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-08
Field Oxide Field Oxide
n-well
FOX Field Oxide
Chapter 2 – Section 8 (5/02/04) Page 2.8-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Definition of the Emitter Window and Sub-Collector Implant
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-09
Field Oxide
n-well
Sub-Collector
FOX
Field Oxide
Sacrifical Oxide
FOX Field Oxide
Chapter 2 – Section 8 (5/02/04) Page 2.8-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Emitter Implant
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µm
Collector Tub
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-10
Field Oxide
n-well
Sub-CollectorFO
X
Field Oxide
Emitter Implant
FOX Field Oxide
Comments:• The polysilicon above the base is implanted with n-type carriers
Chapter 2 – Section 8 (5/02/04) Page 2.8-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Emitter Diffusion
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-11
Field Oxide
n-well
FOX
Field Oxide
Emitter
FOX Field Oxide
Comments:• The polysilicon not over the emitter window is removed and the n-type carriers diffuse
into the base forming the emitter
Chapter 2 – Section 8 (5/02/04) Page 2.8-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Formation of the MOS Gates and LD Drains/Sources
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-12
Field Oxide
n-wellFO
X
Field OxideFOX Field Oxide
Comments:• The surface of the region where the MOSFETs are to be built is cleared and a thin gate
oxide is deposited with a polysilicon layer on top of the thin oxide• The polysilicon is removed over the source and drain areas• A light source/drain diffusion is done for the NMOS and PMOS (separately)
Chapter 2 – Section 8 (5/02/04) Page 2.8-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Heavily Doped Source/Drain
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-13
Field Oxide
n-well
FOX
Field OxideFOX Field Oxide
Comments:• The sidewall spacers prevent the heavy source/drain doping from being near the
channel of the MOSFET
Chapter 2 – Section 8 (5/02/04) Page 2.8-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Siliciding
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µm
NMOS TransistorPMOS TransistorNPN Transistor
BiCMOS-14
Field Oxide
n-wellFO
X
Field Oxide
Silicide TiSi2 Silicide TiSi2 Silicide TiSi2
FOX Field Oxide
Comments:• Siliciding is used to reduce the resistance of the polysilicon and to provide ohmic
contacts to the base, emitter, collector, sources and drains
Chapter 2 – Section 8 (5/02/04) Page 2.8-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Contacts
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µmBiCMOS-15
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
Tungsten Plugs Tungsten PlugsTungsten PlugsTEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
FOX
Comments:• A dielectric is deposited over the entire wafer• One of the purposes of the dielectric is to smooth out the surface• Tungsten plugs are used to make electrical contact between the transistors and metal1
Chapter 2 – Section 8 (5/02/04) Page 2.8-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Metal1
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µmBiCMOS-16
Field Oxide Field Oxide
n-wellFO
XField Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
Metal1 Metal1Metal1
FOX
Chapter 2 – Section 8 (5/02/04) Page 2.8-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Metal1-Metal2 Vias
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µmBiCMOS-17
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
Tungsten Plugs Oxide/SOG/Oxide
FOX
Chapter 2 – Section 8 (5/02/04) Page 2.8-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Metal2
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µmBiCMOS-18
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
Metal 2
FOX
Oxide/SOG/Oxide
Chapter 2 – Section 8 (5/02/04) Page 2.8-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Metal2-Metal3 Vias
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µmBiCMOS-19
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
FOX
TEOS/BPSG/SOG
Oxide/SOG/Oxide
Comments:• The metal2-metal3 vias will be filled with metal3 as opposed to tungsten plugs
Chapter 2 – Section 8 (5/02/04) Page 2.8-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Completed Wafer
p-substrate
n+ buried layer p+ buriedlayer
n+ buried layer p+ buried layer
p-typeEpitaxialSilicon
p-well p-well
1µm
5µmBiCMOS-20
Field Oxide Field Oxide
n-well
FOX
Field Oxide Field Oxide
TEOS/BPSG/SOG TEOS/BPSG/SOG TEOS/BPSG/SOG
Nitride (Hermetically seals the wafer)
FOX
TEOS/BPSG/SOG
Metal3
Oxide/SOG/Oxide
Oxide/SOG/Oxide
Metal3Vias
Chapter 2 – Section 8 (5/02/04) Page 2.8-21
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• This section has illustrated the major process steps for a 0.5micron BiCMOS
technology.• The performance of the active devices are:
npn bipolar junction transistor:fT = 12GHz, βF = 100-140 BVCEO = 7V
n-channel FET:
K’ = 127µA/V2 VT = 0.64V λN ≈ 0.060
p-channel FET:
K’ = 34µA/V2 VT = -0.63V λP ≈ 0.072
• Although today’s state of the art is 0.25µm or 0.18µm BiCMOS, the processing stepsillustrated above approximate that which is done in a smaller geometry.
Chapter 2 – Section 9 (5/02/04) Page 2.9-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 2.9 - SUMMARY• Basic process steps include:
1.) Oxide growth 2.) Thermal diffusion 3.) Ion implantation4.) Deposition 5.) Etching 6.) Epitaxy
• PN junctions are used to electrically isolate regions in CMOS• A simple CMOS technology requires about 8 masks• Bipolar technology provides a good vertical NPN and lateral and substrate PNPs• BiCMOS combines the best of both BJT and CMOS technologies• Passive component compatible with CMOS technology include:
Capacitors - MOS, poly-poly, metal-metal, etc.Resistors - Diffused, implanted, well, etc.Inductors - Planar good only at very high frequencies
• CMOS technology has a reasonably good lateral BJT• Other considerations in CMOS technology include:
Latch-upESD protectionTemperature influenceNoise influence
• Design rules are used to preserve the integrity of the technology
Chapter 3 – Introduction (5/02/04) Page 3.0-1
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 3 - CMOS MODELS
Chapter Outline3.1 MOS Structure and Operation3.2 Large signal MOS models suitable for hand calculations3.3 Extensions of the large signal MOS model3.4 Capacitances of the MOSFET3.5 Small Signal MOS models3.6 Temperature and noise models for MOS transistors3.7 BJT models3.8 SPICE level 2 model3.9 Models for simulation of MOS circuits3.10 Extraction of a large signal model for hand calculations from the BSIM3 model3.11 SummaryPerspective
AnalogIntegrated
CircuitDesign
CMOSTransistor and Passive
Component Modeling
CMOSTechnology
andFabrication
Fig.3.0-1
Chapter 3 – Introduction (5/02/04) Page 3.0-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Philosophy for Models Suitable for Analog DesignThe model required for analog design with CMOS technology is one that leads tounderstanding and insight as distinguished from accuracy.
TechnologyUnderstanding
and Usage
Thinking ModelSimple,
±10% to ±50% accuracy
Design Decisions-"What can I change to
accomplish ....?"
Computer Simulation
Expectations"Ballpark"
Extraction of SimpleModel Parameters
from Computer Models
Comparison ofsimulation with
expectations
Refined andoptimized
design
Updating Model Updating Technology
Fig.3.0-02
This chapter is devoted to the simple model suitable for design not using simulation.
Chapter 3 – Introduction (5/02/04) Page 3.0-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Categorization of Electrical Models
Time Dependence
Time Independent Time Dependent
Linearity
Linear Small-signal, midband Rin, Av, Rout
(.TF)
Small-signal frequencyresponse-poles and zeros(.AC)
Nonlinear DC operating pointiD = f(vD,vG,vS,vB)
(.OP)
Large-signal transientresponse - Slew rate
(.TRAN)
Based on the simulation capabilities of SPICE.
Chapter 3 – Section 1 (5/2/04) Page 3.1-1
CMOS Analog Circuit Design © P.E. Allen - 2004
3.1 - MOS STRUCTURE AND OPERATIONMetal-Oxide-Semiconductor Structure
n+ n+
Polysilicon
p+
p- substrate
LightlyDoped p
HeavilyDoped n
HeavilyDoped p
LightlyDoped n
IntrinsicDoping Fig.3.1-01
Bulk/Substrate Source Gate DrainThin Oxide(10-100nm
100Å-1000Å)
Metal
Terminals:• Bulk - Used to make an ohmic contact to the substrate• Gate - The gate voltage is applied in such a manner as to invert the doping of the
material directly beneath the gate to form a channel between the source and drain.• Source - Source of the carriers flowing in the channel• Drain - Collects the carriers flowing in the channel
Chapter 3 – Section 1 (5/2/04) Page 3.1-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Formation of the Channel for an Enhancement MOS Transistor
Polysilicon
p+
p- substrate
Fig.3.1-02
VB = 0 VG =VTVS = 0 VD = 0
p+
p- substrate
VB = 0 VG < VTVS = 0 VD = 0
Polysilicon
p+
p- substrate
VB = 0 VG >VTVS = 0 VD = 0
Subthreshold (VG<VT)
Threshold (VG=VT)
Strong Threshold (VG>VT)
Inverted Region
Inverted Region
Polysilicon
n+
n+ n+
n+ n+
n+
Depletion Region
Chapter 3 – Section 1 (5/2/04) Page 3.1-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Transconductance Characteristics of an Enhancement NMOS FET when VDS = 0.1V
Polysilicon
p+
p- substrate
Fig.3.1-03
VB = 0 VG = 2VTVS = 0 VD = 0.1V
p+
p- substrate
VB = 0 vG =VTVS = 0 VD = 0.1V
Polysilicon
p+
p- substrate
VB = 0 VG = 3VTVS = 0 VD = 0.1V
VGS≤VT:
Inverted Region
Inverted Region
PolysiliconiD
iD
vGSVT 2VT 3VT0
0
iD
iD
vGSVT 2VT 3VT0
0
iD
vGSVT 2VT 3VT0
0
VGS=2VT:
VGS=3VT:
n+ n+
n+ n+
Depletion Region
n+ n+
Chapter 3 – Section 1 (5/2/04) Page 3.1-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Output Characteristics of the Enhancement NMOS Transistor for VGS = 2VT
Fig.3.1-04
VB = 0 VG = 2VTVS = 0 VD = 0.5VT
vG =2VT VD = 0V
VB = 0 VS = 0 VD =VT
VDS=0:iD
vDSVT0.5VT0
0
VDS=0.5VT:
VDS=VT:VG = 2VT
Polysilicon
p+
p- substrate
VB = 0 VS = 0
Inverted Region
iD
iD
vDSVT0.5VT0
0
iD
vDSVT0.5VT0
0
Polysilicon
p+
p- substrate Channel current
iD
Polysilicon
p+
p- substrateA depletion region
forms between the drain and channel
iD
n+
n+ n+
n+
n+ n+
VGS = 2VT
VGS = 2VT
VGS = 2VT
Chapter 3 – Section 1 (5/2/04) Page 3.1-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Output Characteristics of the Enhanced NMOS when vDS = 2VT
Fig.3.1-05
VB = 0 VG = 2VTVS = 0 VD = 2VT
vG =VT
VB = 0 VS = 0
VGS=VT:iD
vDSVT 2VT0
0
VGS=2VT:
VGS=3VT:VG = 3VT
Polysilicon
p+
p- substrate
VB = 0 VS = 0iD
Polysilicon
p+
p- substrate
iD
n+n+
n+ n+
VD = 2VT
VD = 2VT
iD
vDS0
0
iD
vDS0
0
3VT
VT 2VT 3VT
VT 2VT 3VT
Polysilicon
p+
p- substrate
iD
n+n+
Further increase in VG will cause the FET to become active
VGS =2VT
VGS =3VT
VGS =VT
Chapter 3 – Section 1 (5/2/04) Page 3.1-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Output Characteristics of an Enhancement NMOS Transistor
0 1 2 3 4 5vDS (Volts)
0
500
1000
1500
2000
i D(µ
A)
VGS = 3.0
VGS = 2.5
VGS = 2.0
VGS = 1.5
VGS = 1.0
Fig. 3.1-6
SPICE Input File:Output Characteristics for NMOSM1 6 1 0 0 MOS1 w=5u l=1.0uVGS1 1 0 1.0M2 6 2 0 0 MOS1 w=5u l=1.0uVGS2 2 0 1.5M3 6 3 0 0 MOS1 w=5u l=1.0uVGS3 3 0 2.0M4 6 4 0 0 MOS1 w=5u l=1.0uVGS4 4 0 2.5
M5 6 5 0 0 MOS1 w=5u l=1.0uVGS5 5 0 3.0VDS 6 0 5.model mos1 nmos (vto=0.7 kp=110u+gamma=0.4 +lambda=.04 phi=.7).dc vds 0 5 .2.print dc ID(M1), ID(M2), ID(M3), ID(M4),ID(M5).end
Chapter 3 – Section 1 (5/2/04) Page 3.1-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Transconductance Characteristics of an Enhancement NMOS Transistor
0
1000
2000
3000
4000
5000
6000
0 1 2 3 4 5vGS (Volts)
i D(µ
A)
VDS = 5V
VDS = 1V
VDS = 2V
VDS = 4VVDS = 3V
Fig. 3.1-7
SPICE Input File:Transconductance Characteristics for NMOSM1 1 6 0 0 MOS1 w=5u l=1.0uVDS1 1 0 1.0M2 2 6 0 0 MOS1 w=5u l=1.0uVDS2 2 0 2.0M3 3 6 0 0 MOS1 w=5u l=1.0uVDS3 3 0 3.0M4 4 6 0 0 MOS1 w=5u l=1.0uVDS4 4 0 4.0
M5 5 6 0 0 MOS1 w=5u l=1.0uVDS5 5 0 5.0VGS 6 0 5.model mos1 nmos (vto=0.7 kp=110u+gamma=0.4 lambda=.04 phi=.7).dc vgs 0 5 .2.print dc ID(M1), ID(M2), ID(M3), ID(M4),ID(M5).probe.end
Chapter 3 – Section 2 (5/2/04) Page 3.2-1
CMOS Analog Circuit Design © P.E. Allen - 2004
3.2 - LARGE SIGNAL FET MODEL FOR HAND CALCULATIONSLarge Signal Model DerivationDerivation-1.) Let the charge per unit area in the channelinversion layer be
QI(y) = -Cox[vGS-v(y)-VT] (coul./cm2)2.) Define sheet conductivity of the inversionlayer per square as
σS = µoQI(y)
cm2
v·s
coulombs
cm2 = ampsvolt =
1Ω/sq.
3.) Ohm's Law for current in a sheet is
JS = iDW = -σSEy = -σS
dvdy → dv =
-iDσSW dy =
-iDdyµoQI(y)W → iD dy = -WµoQI(y)dv
4.) Integrating along the channel for 0 to L gives
⌡⌠
0
L
iDdy = - ⌡⌠
0
vDS
WµoQI(y)dv = ⌡⌠
0
vDS
WµoCox[vGS-v(y)-VT] dv
5.) Evaluating the limits gives
iD = WµoCox
L
(vGS-VT)v(y) - v2(y)
2vDS
0
→ iD = WµoCox
L
(vGS-VT)vDS - vDS2
2
n+ n+
yv(y)
dy
0 Ly y+dyp-Source Drain
+
--
+vGSvDSiD
Fig.110-03
Chapter 3 – Section 2 (5/2/04) Page 3.2-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Saturation Voltage - VDS(sat)Interpretation of the largesignal model:
The saturation voltage for MOSFETs is the value of drain-source voltage at the peak ofthe inverted parabolas.
diDdvDS
= µoCoxW
L [(vGS-VT) - vDS] = 0
vDS(sat) = vGS - VT
Useful definitions:µoCoxW
L = K’W
L = β
Increasingvalues of
Saturation RegionActive Region
vDS
iDvDS = vGS-VT
vGS
Fig. 110-04
vDS
vGSVT
v DS = v GS
- VT
Cutoff Saturation Active
00 Fig. 3.2-4
Chapter 3 – Section 2 (5/2/04) Page 3.2-3
CMOS Analog Circuit Design © P.E. Allen - 2004
The Simple Large Signal MOSFET ModelRegions of Operation of the MOS Transistor:1.) Cutoff Region:
vGS - VT < 0iD = 0
(Ignores subthreshold currents) 2.) Active Region
0 < vDS < vGS - VT
iD = µoCoxW
2L 2(vGS - VT) - vDS vDS
3.) Saturation Region0 < vGS - VT < vDS
iD = µoCoxW
2L vGS - VT 2
Output Characteristics of the MOSFET:
0.75
1.0
0.5
0.25
00 0.5 1.0 1.5 2.0 2.5
= 0
= 0.5
= 0.707
= 0.867
= 1.0
Channel modulation effects
ActiveRegion Saturation Region
Cutoff Region
iD/ID0vDS = vGS-VT
vDSVGS0-VT
vGS-VTVGS0-VT
vGS-VTVGS0-VTvGS-VT
VGS0-VTvGS-VT
VGS0-VTvGS-VT
VGS0-VT
Fig. 110-05
Chapter 3 – Section 2 (5/2/04) Page 3.2-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of the Need to Account for the Influence of v D S on the Simple Sah ModelCompare the Simple Sah model to SPICE level 2:
0 0.2 0.4 0.6 0.8 1
25µA
20µA
15µA
10µA
5µA
0µA
K' = 44.8µA/Vk = 0, v (sat) = 1.0V
2
DS
K' = 29.6µA/Vk = 0, v (sat) = 1.0V
2
DS
K' = 44.8µA/Vk=0.5, v (sat) = 1.0V
2
DS
SPICE Level 2
vDS (volts)
i D
VGS = 2.0V, W/L = 100µm/100µm, and no mobility effects.
Chapter 3 – Section 2 (5/2/04) Page 3.2-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Modification of the Previous Model to Include the Effects of vDS on VTFrom the previous derivation:
⌡⌠
0
L
iD dy = - ⌡⌠
0
vDS
WµoQI(y)dv = ⌡⌠
0
vDS
WµoCox[vGS - v(y) -VT]dv
Assume that the threshold voltage varies across the channel in the following way:VT(y) = VT + kv(y)
where VT is the value of VT the at the source end of the channel and k is a constant.Integrating the above gives,
iD = WµoCox
L
(vGS-VT)v(y) - (1+k) v2(y)
2
vDS
0
or
iD = WµoCox
L
(vGS-VT)vDS - (1+k) v2DS
2
To find vDS(sat), set the diD/dvDS equal to zero and solve for vDS = vDS(sat),
vDS(sat) = vGS - VT
1 + k
Therefore, in the saturation region, the drain current is
iD = WµoCox
2(1+k)L (vGS - VT)2
For k = 0.5 and K’ = 44.8µA/V2, excellent correlation is achieved with SPICE 2.
Chapter 3 – Section 2 (5/2/04) Page 3.2-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of VDS on the Output CharacteristicsChannel modulation effect:
As the value of vDS increases, theeffective L decreases causing thecurrent to increase.
Illustration:
Note that Leff = L - Xd
Therefore the model in saturationbecomes,
iD = K’W2Leff (vGS-VT)2 →
diDdvDS
= - K’W2Leff2
(vGS - VT)2 dLeffdvDS
= iD
Leff dXddvDS
≡ λiD
Therefore, a good approximation to the influence of vDS on iD is
iD ≈ iD(λ = 0) + diD
dvDS vDS = iD(λ = 0)(1 + λvDS) =
K’W2L (vGS-VT)2(1+λvDS)
Polysilicon
p+
p- substrateFig110-06
VG > VT VD > VDS(sat)
n+n+
DepletionRegion
Xd
B S
Leff
Chapter 3 – Section 2 (5/2/04) Page 3.2-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Channel Length Modulation Parameter, λλλλAssume the MOS is transistor is saturated-
∴ iD = µCoxW
2L (vGS - VT)2(1 + λvDS)Define iD(0) = iD when vDS = 0V.
∴ iD(0) = µCoxW
2L (vGS- VT)2
Now, iD = iD(0)[1 + λvDS] = iD(0) + λiD(0) vDS
Matching with y = mx + b gives the value of λ
vDS
iD
-1λ
iD1(0)iD2(0)iD3(0 VGS3
VGS2
VGS1
)
Chapter 3 – Section 2 (5/2/04) Page 3.2-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of the Bulk Voltage on the Large Signal MOSFET ModelIllustration of the influence of the bulk:
VSB0 = 0V:
VSB1>0V:
VSB2 > VSB1:
VBS0 = 0VVG > VTVS = 0 VD > 0
Polysilicon
p+
p- substrate Channel current
iD
n+n+
Fig.110-07AVSB1 > 0V
VG > VTVS = 0 VD > 0
Polysilicon
p+
p- substrate Channel current
iD
n+
Fig.110-07B
n+
VSB2 >VSB1 VG > VTVS = 0 VD > 0
Polysilicon
p+
p- substrate
iD = 0
n+
Fig.110-07C
n+
Chapter 3 – Section 2 (5/2/04) Page 3.2-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of the Bulk Voltage on the Large Signal MOSFET Model - ContinuedBulk-Source (vBS) influence on the transconductance characteristics-
VBS = 0
Decreasing valuesof bulk-source voltage
iD
vDS ≥ vGS-VT
VT0 VT1 VT2 VT2vGS
ID
Fig. 110-08
In general, the simple model incorporates the bulk effect into VT by the previouslydeveloped relationship:
VT(vBS) = VT0 + γ 2|φf| + |vBS| - γ 2|φf|
Chapter 3 – Section 2 (5/2/04) Page 3.2-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of the Simple Large Signal MOSFET ModelN-channel reference convention:
Non-saturation-
iD = WµoCox
L
(vGS - VT)vDS - vDS2
2 (1 + λvDS)
Saturation-
iD = WµoCox
L
(vGS-VT)vDS(sat) - vDS(sat)2
2 (1+λvDS) = WµoCox
2L (vGS-VT) 2(1+λvDS)
where:µo = zero field mobility (cm2/volt·sec)Cox = gate oxide capacitance per unit area (F/cm2)λ = channel-length modulation parameter (volts-1)
VT = VT0 + γ
2|φf| + |vBS| - 2|φf|
VT0 = zero bias threshold voltageγ = bulk threshold parameter (volts-0.5)2|φf| = strong inversion surface potential (volts)
For p-channel MOSFETs, use n-channel equations with p-channel parameters and invertcurrent.
G
D
B
S
vDS
vGS
iD
+
-
+
-
+vBS
Fig. 110-10
Chapter 3 – Section 2 (5/2/04) Page 3.2-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Silicon Constants
ConstantSymbol
Constant Description Value Units
VGkni
ε0εsiεox
Silicon bandgap (27°C)Boltzmann’s constantIntrinsic carrierconcentration (27°C)Permittivity of free spacePermittivity of siliconPermittivity of SiO2
1.2051.381x10-23
1.45x1010
8.854x10-1411.7 ε03.9 ε0
VJ/K
cm-3
F/cmF/cmF/cm
Chapter 3 – Section 2 (5/2/04) Page 3.2-12
CMOS Analog Circuit Design © P.E. Allen - 2004
MOSFET ParametersModel Parameters for a Typical CMOS Bulk Process (0.8µm CMOS n-well):
Parameter Parameter Typical Parameter ValueSymbol Description N-Channel P-Channel Units
VT0 Threshold Voltage(VBS = 0)
0.7± 0.15 -0.7 ± 0.15 V
K' Transconductance Para-meter (in saturation)
110.0 ± 10% 50.0 ± 10% µA/V2
γ Bulk thresholdparameter
0.4 0.57 (V)1/2
λ Channel lengthmodulation parameter
0.04 (L=1 µm)0.01 (L=2 µm)
0.05 (L=1 µm)0.01 (L=2 µm)
(V)-1
2|φF| Surface potential atstrong inversion
0.7 0.8 V
Chapter 3 – Section 2 (5/2/04) Page 3.2-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Large Signal Model of the MOS TransistorSchematic:
where,rG, rS, rB, and rD are ohmic and contactresistancesand
iBD = Is
exp
vBD
Vt - 1
and
iBS = Is
exp
vBS
Vt - 1
S
rSCGB
CGS CBS
iBS
iBD
vBD
vBS
+ -
+ - BrBiD
CBDCGD
rD
D
rGG
Fig. 3.2-10
All modeling so farhas been focused onthis dependent currentsource.
Chapter 3 – Section 3 (5/2/04) Page 3.3-1
CMOS Analog Circuit Design © P.E. Allen - 2004
3.3 - LARGE SIGNAL MODEL EXTENSIONSTO SHORT-CHANNEL MOSFETS
Extensions• Velocity saturation• Weak inversion (subthreshold)• Substrate currentsSubstrate Interference• Problems of mixed signal circuits on the same substrate• Modeling and potential solutions
Chapter 3 – Section 3 (5/2/04) Page 3.3-2
CMOS Analog Circuit Design © P.E. Allen - 2004
VELOCITY SATURATIONWhat is Velocity Saturation?
The most important short-channeleffect in MOSFETs is the velocitysaturation of carriers in the channel.A plot of electron drift velocityversus electric field is shown below.
An expression for the electron driftvelocity as a function of the electricfield is,
vd ≈ µnE
1 + E/Ec
wherevd = electron drift velocity (m/s)
µn = low-field mobility (≈ 0.07m2/V·s)
Ec = critical electrical field at which velocity saturation occurs
5x104
105
2x104
104
5x103
105 106 107
Electric Field (V/m)
Ele
ctro
n D
rift
Vel
ocity
(m
/s)
Fig130-1
Chapter 3 – Section 3 (5/2/04) Page 3.3-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Short-Channel Model DerivationAs before,
JD = JS = iDW = QI(y)vd(y) → iD = WQI(y)vd(y) =
WQI(y)µnE1 + E/Ec
→ iD
1+ EEc
= WQI(y)µnE
Replacing E by dv/dy gives,
iD
1 + 1
Ec dvdy = WQI(y)µn
dvdy
Integrating along the channel gives,
⌡⌠
0
L
iD
1 + 1
Ec dvdy dy = ⌡⌠
0
vDS
WQI(y)µndv
The result of this integration is,
iD = µnCox
2
1 + 1
Ec vDSL
WL [2(vGS-VT)vDS-vDS2] =
K’2[1+θ(vGS-VT)]
WL [2(vGS-VT)vDS-vDS2]
where θ = 1/LEc with dimensions of V-1.
Chapter 3 – Section 3 (5/2/04) Page 3.3-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Saturation VoltageDifferentiating iD with respect to vDS and setting equal to zero gives,
θ vDS2 + 2vDS – 2(VGS-VT) = 0
Solving for vDS gives,
V’DS(sat) = 1θ
1 + 2θ(VGS-VT -1 ≈ (VGS-VT)
1 - θ (VGS-VT)
2 + ···
or
V’DS(sat) ≈ VDS(sat)
1 - θ (VGS-VT)
2 + ···
Note that the transistor will enter the saturation region for vDS < vGS - VT in thepresence of velocity saturation.Therefore the large signal model in the saturation region is,
iD = K’
2[1 + θ(vGS-VT)] WL [ vGS - VT]2, vDS ≥ (VGS-VT)
1 - θ (VGS-VT)
2 + ···
Chapter 3 – Section 3 (5/2/04) Page 3.3-5
CMOS Analog Circuit Design © P.E. Allen - 2004
The Influence of Velocity Saturation on the Transconductance Characteristics
The following plot was made for K’ = 110µA/V2 and W/L = 1:
0
200
400
600
800
1000
0.5 1 1.5 2 2.5 3
i D/W
(µ
A/µ
m)
vGS (V)
θ = 0
θ = 0.2
θ = 0.4
θ = 0.6
θ = 0.8θ = 1.0
Fig130-2
Note as the velocity saturation effect becomes stronger, that the drain current-gatevoltage relationship becomes linear.
Chapter 3 – Section 3 (5/2/04) Page 3.3-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Circuit Model for Velocity SaturationA simple circuit model to include the influence of velocity saturationis the following:We know that
iD = K’W2L (vGS’ -VT)2 and vGS = vGS’ + iD RSX
orvGS’ = vGS - iDRXS
Substituting vGS’ into the current relationship gives,
iD = K’W2L (vGS - iDRSX -VT)2
Solving for iD results in,
iD = K’
2
1 + K’ WL RSX(vGS-VT)
WL (vGS - VT)2
Comparing with the previous result, we see that
θ = K’ WL RSX → RSX =
θLK’W =
1EcK’W
Therefore for K’ = 110µA/V2, W = 1µm and Ec = 1.5x106V/m, we get RSX = 6.06kΩ.
G
D
S
RSX
+
vGS
-
vGS'+
-
iD
Fig130-3
Chapter 3 – Section 3 (5/2/04) Page 3.3-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Output Characteristics of Short-Channel MOSFETs†
IBM, 1998, tox = 3.5nm
800
700
600
500
400
300
200
100
0-1.8 -1.2 -0.6 0.0 0.6 1.2 1.8
NFETLeff = 0.08µm
VGS=1.8V
VGS=1.4V
VGS=1.0V
VGS=0.6V
PFETLeff = 0.11µm
VGS=-1.8V
VGS=-1.4V
VGS=-1.0V
VGS=-0.6V
Drain Voltage (V)
Dra
in C
urre
nt (
µA
/µm
)
Fig130-4
† Su, L., et.al., “A High Performance Sub-0.25µm CMOS Technology with Multiple Thresholds and Copper Interconnects,” 1998 Symposium onVLSI Technology Digest of Technical Papers, pp. 18-19.
Chapter 3 – Section 3 (5/2/04) Page 3.3-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Velocity Saturation Effects
Velocity Saturation Insignificant Velocity Saturation Significant
gm = K’W2L (VGS-VT) gm = WCoxuoEc
1+ 2θ (VGS-VT)-11+ 2θ (VGS-VT)
fT = 1
2π gmCgs ∝ L-2 fT =
12π
gmCgs ∝ L-1
Chapter 3 – Section 3 (5/2/04) Page 3.3-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Important Short Channel Effects1.) An approximate plot of the n as a function
of channel length is shown below where
iD ∝ (vGS – VT)n
2.) Note that the value of λ varies with channel length, L. The data below is from a0.25µm CMOS technology.
0
0.1
0.2
0.3
0.4
0.5
0.6
0 0.5 1 1.5 2 2.5Cha
nnel
Len
gth
Mod
ulat
ion
(V-1
)
Channel Length (microns)
PMOS
NMOS
Fig.130-6
0 1 2 3 4 50
1
2
n
LLmin
Fig.130-5
Chapter 3 – Section 3 (5/2/04) Page 3.3-10
CMOS Analog Circuit Design © P.E. Allen - 2004
SUBTHRESHOLD MOSFET MODELWhat is Weak Inversion Operation?
Weak inversion operation occurs when the applied gate voltage is below VT andpertains to when the surface of the substrate beneath the gate is weakly inverted.
yyyn+ n+
p-substrate/well
VGS
Diffusion Current
n-channel
Fig. 140-01
Regions of operation according to the surface potential, φS (or ψS)
φS < φF : Substrate not invertedφF < φS < 2φF : Channel is weakly inverted (diffusion current)2φF < φS : Strong inversion (drift current)
Chapter 3 – Section 3 (5/2/04) Page 3.3-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Drift versus Diffusion Current1.) For strong inversion, the gate voltage controls the charge in the inverted region but
not in the depletion region. The concentration of charge across the channel isapproximately constant and the current is drift caused by electric field.
2.) For weak inversion, the charge in channel is much less that that in the depletion regionand drift current decreases. However, there is a concentration gradient in the channel,that causes diffusion current.The n-channel MOSFET acts like a NPN BJT: the emitter is the source, the base isthe substrate and the collector is the drain.
Illustration:
log iD
10-6
10-120 VT
VGS
Drift CurrentDiffusion Current
Fig. 140-02
Chapter 3 – Section 3 (5/2/04) Page 3.3-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Large-Signal Model for Weak InversionThe electrons in the substrate at the source side can be expressed as,
np(0) = npoexp
φs
Vt
The electrons in the substrate at the drain side can be expressed as,
np(L) = npoexp
φs-vDS
Vt
Therefore, the drain current due to diffusion is,
iD = qADn
np(L)- np(0)
L = WL qXDnnpoexp
φs
Vt
1 - exp
- vDSVt
where X is the thickness of the region in which iD flows.
In weak inversion, the changes in the surface potential, ∆φs are controlled by changes inthe gate-source voltage, ∆vGS, through a voltage divider consisting of Cox and Cjs, thedepletion region capacitance.
∴dφs
dvGS =
CoxCox+ Cjs
= 1n → φs =
vGSn + k1 =
vGS-VTn + k2
where
k2 = k1 + VTn
Chapter 3 – Section 3 (5/2/04) Page 3.3-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Large-Signal Model for Weak Inversion – ContinuedSubstituting the above relationships back into the expression for iD gives,
iD = WL qXDnnpo exp
k2
Vtexp
vGS-VT
nVt
1 - exp
- vDSVt
Define It as
It = qXDnnpo exp
k2
Vt
to get,
iD = WL It exp
vGS-VT
nVt
1 - exp
- vDSVt
where n ≈ 1.5 – 3If vDS > 0, then
iD = It WL exp
vGS-VT
nVt
1 + vDS VA
VGS=VT
VGS<VT
iD
vDS00 1V
Fig. 140-03
1µA
Chapter 3 – Section 3 (5/2/04) Page 3.3-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Model for Weak InversionSmall-signal model:
gm = diD
dvGS |
Q = It WL
ItnVt
exp
vGS-VT
nVt
1 + vDS VA
= IDnVt
= qIDnkT =
IDVt
Cox
Cox+Cjs
gds = diD
dvDS |
Q ≈ IDVA
The boundary between nonsaturated and saturated is found as,
Vov = VDS(sat) = VON = VGS – VT = 2nVt
Chapter 3 – Section 3 (5/2/04) Page 3.3-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation of an n-channel MOSFET in both Weak and Strong InversionUses the BSIM model.†
0V 0.4V 0.8V 1.2V
ID(M
1)
1.6V 2VVGS
100µA
1µA
10nA
100pA
1nA
100nA
10µA
vGSiD
Fig. 140-05
† Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User’s Guide, Kluwer Academic Publishers, Boston, 1999.
Chapter 3 – Section 3 (5/2/04) Page 3.3-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 3-1 – The NMOS in Weak InversionCalculate Vov and fT for an NMOS transistor with ID = 1µA, It = 0.1µA, and vDS>>VT.Assume that W = 10µm, L = 1µm, n = 1.5, K’N = 200µA/V2, tox = 100Å, and thetemperature is 27°C.SolutionFirst we find the
Vov = VDS(sat) = VON = VGS – VT = 2nVt = 2(1.5)(25.9mV) ≈ 78mV
Next, we need to find gm and Cgs.
gm = IDnVt
= 1µA
1.5·25.9mV = 25.75µS
Previously, we found that n = 1 + CjsCox
. ∴ Cjs = (n-1)Cox = 0.5 Cox
It can be shown that
Cgs = WL
CoxCjs
Cox + Cjs = 0.33WLCox =
10µm2
3 3.9×8.854×10-14(F/cm)×(100cm/106µm)
100Å × (106µm/1010Å)
Cgs = 11.5fF → fT = |1
2π ωT = 1
2π 25.75µS11.5fF ≈ 360MHz
(Equivalent transistor operating in strong inversion has an fT = 3.4GHz)
Chapter 3 – Section 3 (5/2/04) Page 3.3-17
CMOS Analog Circuit Design © P.E. Allen - 2004
SUBSTRATE CURRENT FLOW IN MOSFETSImpact IonizationImpact Ionization:
Occurs because high electric fields cause an impact which generates a hole-electronpair. The electrons flow out the drain and the holes flow into the substrate causing asubstrate current flow.Illustration:
Polysilicon
p+
p- substrate
Fig130-7
VG > VTVD > VDS(sat)
n+
DepletionRegion
B S
FixedAtom
Freehole
Freeelectron
A n+
Chapter 3 – Section 3 (5/2/04) Page 3.3-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Model of Substrate Current FlowSubstrate current:
iDB = K1(vDS - vDS(sat))iDe-[K2/(vDS-vDS(sat))]
where
K1 and K2 are process-dependent parameters (typical values: K1 = 5V-1 and K2 = 30V)
Schematic model:D
G
S
B
iDB
Fig130-8Small-signal model:
gdb = ∂iDB∂vDB
= K2 IDB
VDS - VDS(sat)
This conductance will have a negative influence on high-output resistance currentsinks/sources.
Chapter 3 – Section 3 (5/2/04) Page 3.3-19
CMOS Analog Circuit Design © P.E. Allen - 2004
SUBSTRATE INTERFERENCE IN CMOS CIRCUITSHow Do Carriers Get Injected into the Substrate?1.) Hot carriers (substrate current)2.) Electrostatic coupling (across depletion regions and other dielectrics)3.) Electromagnetic coupling (parallel conductors)
Why is this a Problem?With decreasing channel lengths, more circuitry is being integrated on the samesubstrate. The result is that noisy circuits (circuits with rapid transitions) are beginningto adversely influence sensitive circuits (such as analog circuits).
Present SolutionKeep circuit separate by using multiple substrates and put the multiple substrates in thesame package.
Chapter 3 – Section 3 (5/2/04) Page 3.3-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Hot Carrier Injection in CMOS Technology without an Epitaxial Region
p- substrate (10 Ω-cm)
LightlyDoped p
HeavilyDoped n
HeavilyDoped p
LightlyDoped n
IntrinsicDoping
Metal
p+
n- wellVDD(Digital)vin vout
n+ n+
VDD
vin vout
HotCarrier
p+n+ n+
VGS
VDD(Analog)
vout
vin
RL
VGSvin
vout
RL
VDD(Analog)
Substrate Noise
Back-gating due to a momentary change in reverse bias
VGS
iD
ID
vGS
∆iD
∆iD
Digital Ground Analog Ground
Noisy Circuits Quiet Circuits
Fig. SI-01
Put substrate connectionsas close to the noise sourceas possible
"AC ground"
"AC ground"
p+ channel stop (1Ω-cm)
p+p+ n+
n+ channelstop (1 Ω-cm)
Chapter 3 – Section 3 (5/2/04) Page 3.3-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Hot Carrier Injection in CMOS Technology with an Epitaxial Region
p+ substrate (0.05 Ω-cm)
LightlyDoped p
HeavilyDoped n
HeavilyDoped p
LightlyDoped n
IntrinsicDoping
Metal
p+
n- wellVDD(Digital)vin vout
n+ n+
VDD
vin vout
HotCarrier
p+n+ n+
VGS
VDD(Analog)
vout
vin
RL
VGSvin
vout
RL
VDD(Analog)
Substrate Noise
Digital Ground Analog Ground
Noisy Circuits Quiet Circuits
Fig. SI-02
Put substrate connectionsas close to the noise sourceas possible
"AC ground"
"AC ground"
Reduced backgating due tosmaller resistance
p-epitaxiallayer (15 Ω-cm)
n+
p+p+
Chapter 3 – Section 3 (5/2/04) Page 3.3-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Computer Model for Substrate Interference Using SPICE PrimitivesNoise Injection Model:
p- substrate
LightlyDoped p
HeavilyDoped n
HeavilyDoped p
LightlyDoped n
IntrinsicDoping
Metal
p+
n- wellVDD(Digital)
vin vout
n+ n+
VDD
vin vout
HotCarrier
Digital Ground
Fig. SI-06
p+p+ n+
Coupling
HotCarrier Coupling
Coupling
VDD
L1 Cs1
Cs2
Cs4Cs5
Cs3 Rs1
Rs2Rs3
L2 L3
Substratevin
n- well
vout
Cs1 = Capacitance between n-well and substrate
Cs2,Cs3 and Cs4 = Capacitances between interconnect lines(including bond pads) and substrate
Cs5 = All capacitance between the substrate and ac ground
Rs1,Rs2 and Rs3 = Bulk resistances in n-well and substrate
L1,L2 and L3 = Inductance of the bond wires and package leads
Chapter 3 – Section 3 (5/2/04) Page 3.3-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Computer Model for Substrate Interference Using SPICE PrimitivesNoise Detection Model:
p- substrate
LightlyDoped p
HeavilyDoped n
HeavilyDoped p
LightlyDoped n
IntrinsicDoping
Metal
p+n+ n+
VGS
VDD(Analog)
vout
vin RL
VGSvin
vout
RL
VDD(Analog)
Substrate Noise
Analog Ground
Fig. SI-07
VDD
VGS
Substrate
L6
L5
L4
Cs5
Cs6Cs7
CL
Rs4
voutRL
Cs5,Cs6 and Cs7 = Capacitances between interconnect lines(including bond pads) and substrate
Rs4 = Bulk resistance in the substrate
L4,L5 and L6 = Inductance of the bond wires and package leads
Chapter 3 – Section 3 (5/2/04) Page 3.3-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Other Sources of Substrate Injection(We do it to ourselves and can’t blame the digital circuits.)
LightlyDoped p
HeavilyDoped n
HeavilyDoped p
LightlyDoped n
IntrinsicDoping
Metal
p- well
p+ n+ n+ n+
Collector Base Emitter Collector
Fig. SI-04
Substrate BJTInductor
Also, there is coupling from power supplies and clock lines to other adjacent signal lines.
Chapter 3 – Section 3 (5/2/04) Page 3.3-25
CMOS Analog Circuit Design © P.E. Allen - 2004
What is a Good Ground?• On-chip, it is a region with very low bulk resistance.
It is best accomplished by connecting metal to the region at as many points aspossible.
• Off-chip, it is all determined by the connections orbond wires.The inductance of the bond wires is large enoughto create significant ground potential changes forfast current transients.
v = L didt
Use multiple bonding wires to reduce the groundnoise caused by inductance.
• Fast changing signals have part oftheir path (circuit through groundand power supplies. Thereforebypass the off-chip power suppliesto ground as close to the chip aspossible.
1 2 3 4 5 6 7 800
4
8
20
12
16
Number of Substrate Contact Package Pins
Settling Time to within 0.5mV (ns)
Peak-to-Peak Noise (mV)
Fig. SI-08
VDD
VSS
+-
Vin C1
C2
Vout
t = 0
Fig. SI-05
Chapter 3 – Section 3 (5/2/04) Page 3.3-26
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Substrate Interference• Methods to reduce substrate noise
1.) Physical separation2.) Guard rings placed close to the sensitive circuits with dedicated package pins.3.) Reduce the inductance in power supply and ground leads (best method)4.) Connect regions of constant potential (wells and substrate) to metal with as
many contacts as possible.• Noise Insensitive Circuit Design Techniques
1.) Design for a high power supply rejection ratio (PSRR)2.) Use multiple devices spatially distinct and average the signal and noise.3.) Use “quiet” digital logic (power supply current remains constant)4.) Use differential signal processing techniques.
• Some references1.) D.K. Su, M.J. Loinaz, S. Masui and B.A. Wooley, “Experimental Results and Modeling Techniques forSubstrate Noise in Mixed-Signal IC’s,” J. of Solid-State Circuits, vol. 28, No. 4, April 1993, pp. 420-430.2.) K.M. Fukuda, T. Anbo, T. Tsukada, T. Matsuura and M. Hotta, “Voltage-Comparator-BasedMeasurement of Equivalently Sampled Substrate Noise Waveforms in Mixed-Signal ICs,” J. of Solid-StateCircuits, vol. 31, No. 5, May 1996, pp. 726-731.3.) X. Aragones, J. Gonzalez and A. Rubio, Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs, Kluwer Acadmic Publishers, Boston, MA, 1999.
Chapter 3 – Section 4 (5/2/04) Page 3.4-1
CMOS Analog Circuit Design © P.E. Allen - 2004
3.4 - CAPACITANCES OF THE MOSFETTypes of CapacitancePhysical Picture:
SiO2
Bulk
Source DrainGate
CBS CBD
C4
C1 C2 C3
Fig120-06
FOX FOX
MOSFET capacitors consist of:• Depletion capacitances• Charge storage or parallel plate capacitances
Chapter 3 – Section 4 (5/2/04) Page 3.4-2
CMOS Analog Circuit Design © P.E. Allen - 2004
MOSFET Depletion CapacitorsModel:1.) vBS ≤ FC·PB
CBS = CJ·AS
1 - vBSPB
MJ
+ CJSW·PS
1 - vBSPB
MJSW
,
and2.) vBS> FC·PB
CBS = CJ·AS
1- FC1+MJ
1 - (1+MJ)FC + MJ VBSPB
+ CJSW·PS
1 - FC1+MJSW
1 - (1+MJSW)FC + MJSW VBSPB
whereAS = area of the sourcePS = perimeter of the sourceCJSW = zero bias, bulk source sidewall capacitanceMJSW = bulk-source sidewall grading coefficient
For the bulk-drain depletion capacitance replace "S" by "D" in the above.
SiO2
Polysilicon gate
Bulk
A B
CD
EF
GH
Drain bottom = ABCDDrain sidewall = ABFE + BCGF + DCGH + ADHE
Source Drain
Fig. 120-07
FC·PB
PB
vBS
CBS
vBS ≤ FC·PBvBS ≥ FC·PB
Fig. 120-08
Chapter 3 – Section 4 (5/2/04) Page 3.4-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Charge Storage (Parallel Plate) MOSFET Capacitances - C1, C2, C3 and C4
Overlap capacitances:C1 = C3 = LD·Weff·Cox = CGSO or CGDO(LD ≈ 0.015 µm for LDD structures)
Channel capacitances:C2 = gate-to-channel = CoxWeff·(L-2LD) =CoxWeff·LeffC4 = voltage dependent channel-bulk/substrate capacitance
Bulk
LDMask
W
Oxide encroachment
ActualL (Leff)
Gate
Mask L
Source-gate overlapcapacitance CGS (C1)
Drain-gate overlapcapacitance CGD (C3)
ActualW (Weff)
Fig. 120-09
Source
Gate
Drain
Gate-ChannelCapacitance (C2)
Channel-BulkCapacitance (C4)
FOX FOX
Chapter 3 – Section 4 (5/2/04) Page 3.4-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Charge Storage (Parallel Plate) MOSFET Capacitances - C5View looking down the channel from source to drain
Bulk
Overlap Overlap
Source/DrainGate
FOX FOXC5 C5
Fig120-10
C5 = CGBOCapacitance values based on an oxide thickness of 140 Å or Cox=24.7 × 10-4 F/m2:
Type P-Channel N-Channel Units
CGSO 220 ×10-12 220 × 10-12 F/m
CGDO 220 × 10-12 220 × 10-12 F/m
CGBO 700 × 10-12 700 × 10-12 F/m
CJ 560 × 10-6 770 × 10-6 F/m2
CJSW 350 × 10-12 380 × 10-12 F/m
MJ 0.5 0.5MJSW 0.35 0.38
Chapter 3 – Section 4 (5/2/04) Page 3.4-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Expressions for CGD, CGS and CGBCutoff Region:
CGB = C2+2C5 = Cox(Weff)(Leff)
+ 2CGBO(Leff)
CGS = C1 ≈ Cox(LD)Weff = CGSO(Weff)
CGD = C3 ≈ Cox(LD)Weff = CGDO(Weff)
Saturation Region:CGB = 2C5 = CGBO(Leff)
CGS = C1+(2/3)C2 = Cox(LD+0.67Leff)(Weff)
= CGSO(Weff) + 0.67Cox(Weff)(Leff)
CGD = C3 ≈ Cox(LD)Weff) = CGDO(Weff)
Nonsaturated Region:CGB = 2 C 5 = 2CGBO(Leff)
CGS = C1 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGSO + 0.5CoxLeff)WeffCGD = C3 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGDO + 0.5CoxLeff)Weff
p+
p- substrate
Fig120-1
VB = 0 VG >VTVS = 0 VD >VG -VT
n+ n+p+
p- substrate
VB = 0 VG < VTVS = 0 VD > 0
Polysilicon
p+
p- substrate
VB = 0 VG >VTVS = 0 VD <VG -VT
Cutoff
Saturated
Active
Inverted Region
Inverted Region
Polysilicon
n+ n+
Polysilicon
n+ n+
CGD
CGB
CGS
CGS CGD
CGDCGS
Chapter 3 – Section 4 (5/2/04) Page 3.4-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of CGD, CGS and CGB
Comments on the variation of CBG in the cutoff region:
CBG = 1
1C2 +
1C4
+ 2C5
1.) For vGS ≈ 0, CGB ≈ C2 + 2C5
(C4 is large because of the thin
inversion layer in weak inversion
where VGS is slightly less than VT))
2.) For 0 < vGS ≤ VT, CGB ≈ 2C5
(C4 is small because of the thickerinversion layer in strong inversion)
0 vGS
CGS
CGS, CGD
CGDCGB
CGS, CGD
C2 + 2C5
C1+ 0.67C2
C1, C32C5
VT vDS +VT
Off Saturation Non-Saturation
vDS = constant vBS = 0
Capacitance
C1+ 0.5C2
Fig120-12
C4 Large
C4 Small
Chapter 3 – Section 4 (5/2/04) Page 3.5-1
CMOS Analog Circuit Design © P.E. Allen - 2004
3.5 – SMALL SIGNAL MODELS FOR THE MOSFETSmall-Signal Model for the Saturation RegionThe small-signal model is a linearization of the large signal model about a quiescent oroperating point.Consider the large-signal MOSFET in the saturation region (vDS ≥ vGS – VT) :
iD = WµoCox
2L (vGS - VT) 2 (1 + λvDS)
The small-signal model is the linear dependence of id on vgs, vbs, and vds. Written as,
id ≈ gmvgs + gmbsvbs + gds vdswhere
gm ≡ diD
dvGS |Q = β(VGS-VT) = 2βID
gds ≡ diD
dvDS |Q =
λID1 + λVDS
≈ λID
and
gmbs ≡ dιDdvBS
Q =
diD
dvGS
dvGS
dvBS
Q
=
- diDdVT
dVT
dvBS
Q
= gmγ
2 2|φF| - VBS = ηgm
Chapter 3 – Section 4 (5/2/04) Page 3.5-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Model – ContinuedComplete schematicmodel:
where
gm ≡ diD
dvGS |Q =
β(VGS-VT) = 2βID gds ≡ diD
dvDS |Q =
λiD1 + λvDS
≈ λiD
and
gmbs = ∂ιD∂vBS
Q =
∂iD
∂vGS
∂vGS
∂vBS
Q
=
- ∂iD∂vT
∂vT
∂vBS
Q
= gmγ
2 2|φF| - VBS = ηgm
Simplified schematic model:
An extremely importantassumption:
gm ≈ 10gmbs ≈ 100gds
rds
G
S
gmvgsvgs
+
-gmbsvbs
vds
+
-
id
Fig. 120-01
B
vbs
+
-
G
S
B
D
G
S
B
D
S
D
rdsG
D
S
G
D
S
G
S
gmvgsvgs
+
-
vds
+
-
id
Fig. 120-02
D
S
Chapter 3 – Section 4 (5/2/04) Page 3.5-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of the Small-Signal Model ApplicationAssume that the gate is connected to the drain.DC resistor:
DC resistance = vi
Q
= VI = RDC
Useful for biasing - creating current fromvoltage and vice versa
Small-Signal Load (AC resistance):
rds
G
S
gmvgsvgs
+
-gmbsvbs
vds
+
-
id
Fig. 120-01
B
vbs
+
-
G
S
B
D
G
S
B
D
S
D
Assume that vbs = 0,
AC resistance = vdsid =
vgsid =
1gm + gds ≈
1gm = Rac
VT
i
vFig. 120-03
ID
VDS
AC Resistance
DC Resistance
Chapter 3 – Section 4 (5/2/04) Page 3.5-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Model for the Nonsaturated Region
gm = ∂iD∂vGS
|Q =
K’WVDSL (1+λVDS) ≈
K’W
L VDS
gmbs = ∂iD∂vBS
|Q =
K’Wγ VDS
2L 2φF - VBS
gds = ∂iD∂vDS
|Q =
K’WL ( VGS - VT - VDS)(1+λVDS) +
IDλ1+λVDS ≈
K’WL (VGS - VT - VDS)
Note:While the small-signal model analysis is independent of the region of operation, theevaluation of the small-signal performance is not.
Chapter 3 – Section 4 (5/2/04) Page 3.5-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Small Signal Model for the Subthreshold RegionIf vDS > 0, then
iD = Kx WL evGS/nVt (1 + λvDS)
Small-signal model:
gm = diDdvGS
|Q =
qIDnkT
gds = diD
dvDS |Q ≈
IDVA
Chapter 3 – Section 4 (5/2/04) Page 3.5-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Frequency Dependent ModelThe depletion capacitorsare found by evaluating thelarge signal capacitors atthe DC operating point.
The charge storagecapacitors are constant fora specific region ofoperation.
Gain-bandwidth of the MOSFET:Assume VSB = 0 and the MOSFET is in saturation,
fT = 12π
gmCgs + Cgd
≈ 12π
gmCgs
Recalling that
Cgs ≈ 23 CoxWL and gm = µoCox
WL (VGS-VT) → fT =
34π
µo
L2 (VGS-VT)
rds
G
S
gmvgsvgs
+
-gmbsvbs
vds
+
-
id
Fig120-13B
vbs
+
- S
D
Cgd
Cgb
Cgs
Cbs
Cbd
Chapter 3 – Section 6 (5/2/04) Page 3.6-1
CMOS Analog Circuit Design © P.E. Allen - 2004
3.6 - TEMPERATURE AND NOISE MODELS FOR THE MOSFETLarge Signal Temperature ModelTransconductance parameter:
K’(T) = K’(T0) (T/T0)-1.5 (Exponent becomes +1.5 below 77°K)
Threshold Voltage:VT(T) = VT(T0) + α(T-T0) + ···
Typically αNMOS = -2mV/°C to –3mV/°C from 200°K to 400°K (PMOS has a + sign)
ExampleFind the value of ID for a NMOS transistor at 27°C and 100°C if VGS = 2V and W/L =
5µm/1µm if K’(T0) = 110µA/V2 and VT(T0) = 0.7V and T0 = 27°C and αNMOS = -2mV/°C.
SolutionAt room temperature, the value of drain current is,
ID(27°C) = 110µA/V2·5µm
2·1µm (2-0.7)2 = 465µA
At T = 100°C (373°K), K’(100°C)=K’(27°C) (373/300)-1.5=110µA/V2·0.72=79.3µA/V2
and VT(100°C) = 0.7 – (.002)(73°C) = 0.554V
∴ ID(100°C) = 79.3µA/V2·5µm
2·1µm (2-0.554)2 = 415µA (Repeat with VGS = 1.5V)
Chapter 3 – Section 6 (5/2/04) Page 3.6-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Experimental Verification of the MOSFET Temperature DependenceNMOS Threshold:
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0 50 100 150 200 250 300
VT(V)
Temperature (°C)
Theorymatchedat 25°C
Fig. 3.6-1
Symbol Min. L NA (cm-3) tox (A° ) α (mV/°C)
O 6µm 2x1016 1000 -3.5 5µm 1x1016 650 -2.5∆ 4µm 2x1016 500 -2.3∇ 2µm 3.3x1016 275 -1.8
Chapter 3 – Section 6 (5/2/04) Page 3.6-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Experimental Verification of the MOSFET Temperature DependencePMOS Threshold:
Fig. 3.6-2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
VT(V)
Temperature (°C)
Theorymatchedat 25°C
0 50 100 150 200 250 300
Symbol Min. L NA (cm-3) Tox (A° ) α (mV/°C)
O 6µm 2x1015 1000 +3.5 5µm 2x1015 650 +2.5∆ 4µm 2x1016 500 +2.3∇ 2µm 1.1x1016 275 +2.0
Chapter 3 – Section 6 (5/2/04) Page 3.6-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Experimental Verification of the MOSFET Temperature DependenceNMOS K’:
µ(T)
0
200
400
600
800
1000
0 50 100 150 200 250 300Fig. 3.6-3Temperature (°C)
Theorymatchedat 25°C
Symbol Min. LData
6 µm5 µm4 µm2 µm
(cm2/V·s)
Chapter 3 – Section 6 (5/2/04) Page 3.6-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Experimental Verification of the MOSFET Temperature DependencePMOS K’:
µ(T)
0
200
400
600
800
1000
0 50 100 150 200 250 300Fig. 3.6-4Temperature (°C)
Theorymatchedat 25°C
Symbol Min. LData
6 µm5 µm4 µm2 µm
(cm2/V·s)
Chapter 3 – Section 6 (5/2/04) Page 3.6-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Zero Temperature Coefficient (ZTC) Point for MOSFETsFor a given value of gate-source voltage, the drain current of the MOSFET will beindependent of temperature. Consider the following circuit:
Assume that the transistor is saturated and that:
µ = µo
T
To-1.5 and VT(T) = VT(To) + α(T-To)
where α = -0.0023V/°C and To = 27°C
∴ ID(T) = µoCoxW
2L
T
To-1.5[VGS – VT0 - α(T-To)]2
dIDdT =
-1.5µoCox2To
T
To-2.5[VGS-VT0-α(T-To)]2+αµoCox
T
To-1.5[VGS-VT0-α(T-To)] = 0
∴ VGS – VT0 - α(T-To) = -4Tα
3 ⇒ VGS(ZTC) = VT0 - αTo - αΤ3
Let K’ = 10µA/V2, W/L = 5 and VT0 = 0.71V.
At T=27°C (300°K), VGS(ZTC)=0.71-(-0.0023)(300°K)-(0.333)(-0.0023)(300°K) = 1.63V
At T = 27°C (300°K), ID = (10µA/V2)(5/2)(1.63-0.71)2 = 21.2µA
At T=200°C (473°K), VGS(ZTC)=0.71-(-0.0023)(300°K)-(0.333)(-0.0023)(473°K)=1.76V
ID
VGS
Fig. 4.5-12
Chapter 3 – Section 6 (5/2/04) Page 3.6-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Experimental Verification of the ZTC Point
The data below is for a 5µm n-channel MOSFET with W/L=50µm/10µm, NA=1016 cm-3,
tox = 650Å, uoCox = 10µA/V2, and VT0 = 0.71V.
0
20
40
60
80
100
0 0.6 1.2 1.8 2.4 3
25°C100°C
150°C200°C250°C275°C
300°C
VDS = 6V
Zero TC Point
25°C100°C
150°C200°C
250°C
275°C
VGS (V)
I D (
µA
)
Fig. 3.6-065
Chapter 3 – Section 6 (5/2/04) Page 3.6-8
CMOS Analog Circuit Design © P.E. Allen - 2004
ZTC Point for PMOS
The data is for a 5µm p-channel MOSFET with W/L=50µm/10µm, ND=2x10-15cm-3, and
tox = 650Å.
0
10
20
30
40
0 -0.6 -1.2 -1.8 -2.4 -3.0
VDS = -6V
300°C
275°C
250°C
VSG(ZTC) ≈ -1.95V
150°C100°C25°C
25°C100°C
150°C
VGS (V)
I D (µ
A)
Fig. 3.6-066
Zero temperature coefficient will occur for every MOSFET up to about 200°C.
Chapter 3 – Section 6 (5/2/04) Page 3.6-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Bulk-Drain (Bulk-Source) Leakage Currents (V G S >V T )Cross-section of a NMOS in a p-well:
Polysilicon
p+
n- substrate
Fig.3.6-5
VG > VT VD > VDS(sat)
n+n+
DepletionRegion
B S
p-well
Chapter 3 – Section 6 (5/2/04) Page 3.6-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Bulk-Drain (Bulk-Source) Leakage Currents (V G S <V T )Cross-section of a NMOS in a p-well:
Polysilicon
p+
n- substrate
Fig.3.6-6
VG <VT VD > VDS(sat)
n+n+
DepletionRegion
B S
p-well
Chapter 3 – Section 6 (5/2/04) Page 3.6-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Temperature Modeling of the PN JunctionPN Junctions (Reverse-biased only):
−iD ≅ Is = qA
Dppno
Lp +
DnnpoLn
≅ qAD
L n
2i
N = KT 3exp
−VGo
Vt
Differentiating with respect to temperature gives,dIs
dT = 3KT 3
T exp
−VGo
Vt +
qKT 3VGo
KT 2 exp
−VGo
Vt =
3Is
T + Is
T VGo
Vt
TCF = dIsIsdT =
3T +
1T
VGoVt
ExampleAssume that the temperature is 300°Κ (room temperature) and calculate the reversediode current change and the TCF for a 5°Κ increase.SolutionThe TCF can be calculated from the above expression as
TCF = 0.01 + 0.155 = 0.165Since the TCF is change per degree, the reverse current will increase by a factor of 1.165for every degree Κ (or °C) change in temperature. Multiplying by 1.165 five times givesan increase of approximately 2. Thus, the reverse saturation current approximatelydoubles for every 5°C temperature increase. Experimentally, the reverse current doublesfor every 8 °C increase in temperature because the reverse current is part leakage current.
Chapter 3 – Section 6 (5/2/04) Page 3.6-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Experimental Verification of the PN Junction Temperature Dependence
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
1.8 2 2.2 2.4 2.6 2.81000/T (°K-1) Fig. 3.6-7
Theorymatchedat 150°C
Symbol Min. LData
6 µm5 µm4 µm2 µm
Generation-Recombination
Leakage Dominant
DiffusionLeakage
Dominant
Lea
kage
Cur
rent
(A
) 250°C
200°C
100°C
IR
1V
50µmLmin
Theory:
Is(T) ∝ T 3 exp
VG(T)
kT
Chapter 3 – Section 6 (5/2/04) Page 3.6-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Temperature Modeling of the PN Junction – ContinuedPN Junctions (Forward biased – vD constant):
iD ≅ Is exp
vD
VtDifferentiating this expression with respect to temperature and assuming that the diodevoltage is a constant (vD = VD) gives
diDdT =
iDIs
dIsdT -
1T
VDVt
iD
The fractional temperature coefficient for iD is
1iD
diDdT =
1Is
dIsdT -
VDTVt
= 3T +
VGo - VD
TVt
If VD is assumed to be 0.6 volts, then the fractional temperature coefficient is equal to 0.01+ (0.155 - 0.077) = 0.0879. The forward diode current will double for a 10°C.PN Junctions (Forward biased – iD constant):
VD = Vt ln(ID/Is)Differentiating with respect to temperature gives
dvDdT =
vDT - Vt
1
Is dIsdT =
vDT -
3VtT -
VGoT = -
VGo - vD
T - 3VtT
Assuming that vD = VD = 0.6 V the temperature dependence of the forward diode voltageat room temperature is approximately -2.3 mV/°C.
Chapter 3 – Section 6 (5/2/04) Page 3.6-14
CMOS Analog Circuit Design © P.E. Allen - 2004
MOSFET NOISEMOS Device Noise at Low Frequencies
D
B
S
G
D
S
in2
B
G
NoiseFreeMOSFET
D
S
BG
NoiseFreeMOSFET
eN2
*
where
in2 =
8kTgm(1+η)
3 + KF ID
fSCoxL2 ∆f (amperes2)
∆f = bandwidth at a frequency, f
η = gmbs
gm
k = Boltzmann’s constantKF = Flicker noise coefficientS = Slope factor of the 1/f noise
Chapter 3 – Section 6 (5/2/04) Page 3.6-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Reflecting the MOSFET Noise to the GateDividing in
2 by gm2 gives
en2 =
in2
gm2 =
8kT(1+η)
3gm +
KF 2fCoxWL K’ ∆f (volts2)
It will be convenient to use B = KF
2CoxK’ for model simplification.
in2
1/f noise Thermal noiselog10(f)
Chapter 3 – Section 6 (5/2/04) Page 3.6-16
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Experimental Noise Data
W/L ID(µA) Noise Voltage at100Hz (nV/ Hz )
Thermal NoiseVoltage (nV/ Hz )
25/25 90 360 4025/25 50 360 3525/25 20 360 25
1.2/1.2 90 10,000 3501.2/1.2 50 10,000 2001.2/1.2 20 10,000 1800.8/0.8 90 70,000 18000.8/0.8 50 60,000 15000.8/0.8 20 50,000 120025/2 90 900 3025/2 50 850 2825/2 20 - -25/1 90 1000 3825/1 50 850 3325/1 20 1000 30
25/0.6 90 950 5025/0.6 50 750 4225/0.6 20 700 35
Chapter 3 – Section 6 (5/2/04) Page 3.6-17
CMOS Analog Circuit Design © P.E. Allen - 2004
MOSFET Noise Model at High FrequenciesAt high frequencies, the source resistance can no longer be assumed to be small.
Therefore, a noise current generator at the input results.MOSFET Noise Models:
G D
S S
gmvgs
Cgs
Cgd
rds in2 io2vin
Circuit 1: Frequency Dependent Noise Model
G D
S S
gmvgs
Cgs
Cgd
rdsii2 io2vin
Circuit 2: Input-referenced Noise Model
ei2
vgs
vgs
*
Chapter 3 – Section 6 (5/2/04) Page 3.6-18
CMOS Analog Circuit Design © P.E. Allen - 2004
MOSFET Noise Model at High Frequencies – ContinuedTo find ei
2 and ii2, we will perform the following calculations:
ei2:
Short-circuit the input and find io2 of both models and equate to get ei
2 .
Ckt. 1: io2 = in
2
Ckt. 2: io2 = gm
2 ei2+ (ωCgd)2ei
2
ii2:
Open-circuit the input and find io2 of both models and equate to get ii
2 .
Ckt. 1: io2 = in
2
Ckt. 2: io2 =
(1/Cgs)
(1/Cds) + (1/Cgs) 2 ii2 +
gm2ii
2
ω2(Cgs+Cds)2
≈ gm
2
ω2Cgs2 in
2 if Cgd < Cgs ⇒ ii2 =
ω2Cgs2
gm2 in
2
ei2 =
in2
gm2 + (ωCgd)2
Chapter 3 – Section 7 (5/2/04) Page 3.7-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SEC. 3.7 – BJT MODELSBipolar Transistor Symbol and Sign Convention
The bipolar junction transistor (BJT) is athree-terminal device whose symbol and signconvention (according to the text) is given asshown:Description of the three terminals:
• Emitter - The emitter is the source of majoritycarriers that result in the gain mechanism ofthe BJT. These carriers which are “emitted”into the base are electrons for the npntransistor and holes for the pnp transistor.
• Base - The base is a region which physically separates the emitter and collector andhas an opposite doping (holes for the npn and electrons for the pnp BJTs). The word“base” comes from the way that the first transistors were constructed. The base wasthe physical support for the whole transistor.
• Collector - The collector serves to “collect” those carries injected from the emitter intothe base and which reach the collector without recombination.
Fig.07-02
C
B
E
+
-vBCiB
+
-vBE
+
-
vCE
iC
iE
C
B
E
+
-vBCiB
+
-vBE
+
-
vCE
iC
iE
npn pnp
Chapter 3 – Section 7 (5/2/04) Page 3.7-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Physical Aspects of an npn BJTA cross-section of an npn BJT is shown below:
Fig.070-03
n
E B C
CE
B
n+ p nA A'
DepletionRegion
DepletionRegion
pn+
DepletionRegion
DepletionRegion
Comments:• The emitter-base depeletion region is generally smaller in width because the doping
level is higher and base-emitter junction is generally forward-biased.• The next slide will examine the carrier concentrations see looking into the above A-A’
cross-section.
Chapter 3 – Section 7 (5/2/04) Page 3.7-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Carrier Concentrations of the npn BJTThe carrier concentrations (not to scale) for the npn BJT are shown below.
Fig.070-04
xA'A
NA
pp(x)
np(x)
np(0)
x = 0 x =WB
np(WB)pnE(0)pnE
nnE
CarrierConcentration
DepletionRegion
DepletionRegion
ND
pnC
nnC
Emitter Base Collector
Comments:• The above carrier concentrations assume that the base-emitter junction is forward
biased and the base-collector junction is reverse biased.• The above carrier concentration will be used to derive the large signal model on the
next slide.
Chapter 3 – Section 7 (5/2/04) Page 3.7-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Derivation of the BJT Large Signal Model in the Foward Active Region1.) Carrier concentrations in the base on the emitter side. The concentration of electrons
in the base on the emitter side (x = 0) isnp(0) = npo exp(vBE/Vt)
The concentration of electrons in the base on the collector side (x = WB) isnp(WB) = npo exp(vBC/Vt) ≈ 0 because vBC is negative and large.
2.) If the recombination of electrons in the base is small, then the minority-carrierconcentrations, np(x), are straight lines and shown on the previous page. Fromcharge-neutrality requirements for the base,
NA + np(x) = pp(x) → np(x) - pp(x) = NA
3.) The collector current is produced by minority-carrier electrons in the base diffusing inthe direction of the concentration gradient and being swept across the collector-basedepletion region by the field existing there. Therefore, the diffusion current densitydue to electrons in the base is
Jn = qDn
dnp(x)
dx
where Dn is the diffusion constant for electrons. The derivative is the slope of theconcentration profile in the base which gives,
Jn = -qDn
np(0)
WB
Chapter 3 – Section 7 (5/2/04) Page 3.7-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Derivation of the BJT Large Signal Model in the Foward Active Region - Continued3.) Continued
If the collector current is defined as positive flowing into the collector terminal, then
iC = qADn
np(0)
WB =
qADnnpoWB
exp
vBE
Vt
where A is the cross-sectional area of the emitter. The desired result is
iC = IS exp
vBE
Vt
where the saturation current, IS, is defined as
IS = qADnnpo
WB
Since, ni2 = npoNA, we can rewrite IS as
IS = qADnni2
WBNA =
qADnni2
QB
where QB is the number of doping atoms in the base per unit area of the emitter.
Chapter 3 – Section 7 (5/2/04) Page 3.7-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Derivation of the Forward Current Gain of the BJT, ββββF1.) The base current, iB, consists of two major components. These components are due
to the recombination of holes and electrons in the base, iB1, and the injection of holesfrom the base into the emitter, iB2. It can be shown that,
iB1 = 12
npoWBqAτb exp
vBE
Vt and iB2 =
qADpLp
ni2
ND exp
vBE
Vt
2.) Therefore the total base current is
iB = iB1 + iB2 =
1
2 npoWBqA
τb + qADp
Lp ni2
ND exp
vBE
Vt
3.) Define the forward active current gain, βF, as
βF = iCiB =
qADnnpoWB
12
npoWBqAτb +
qADpLp
ni2
ND
= 1
WB2
2τbDn +
DpDn
WBLp
NAND
≈ 50 to 150
Note that βF is increased by decreasing WB and increasing ND/NA.
Chapter 3 – Section 7 (5/2/04) Page 3.7-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Derivation of the Current Gain from Emitter to Collector in Forward Active Region
1.) Emitter to collector current gain is designated as, αF = iCiE .
2.) Since sum of all currents flowing into the transistor must be zero, we can write that
iE = -(iC+iB) = -
iC + iCβF =- iC
1+ 1βF = -
iCαF
∴ αF = βF
1 + βF =
1
1 + 1βF
= 1
1 + WB2
2τbDn +
DpDn
WBLp
NAND
≈ αTγ
where
αT ≡ Base Transport factor ≈ 1
1 + WB2
2τbDn
→ 1
and
γ ≡ Emitter injection efficiency ≈ 1
1 + DpDn
WBLp
NAND
→ 1
Chapter 3 – Section 7 (5/2/04) Page 3.7-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Large Signal Model for the BJT in the Forward Active RegionLarge-signal model for a npn transistor:
Fig.070-05
βFiB
iB
+
-
vBE
B C
E E
iB = Is exp VtβF
vBE
βFiB
+
-VBE(on)
B C
E EAssumes vBE is aconstant and iB is
determined externally
Large-signal model for a pnp transistor:
Fig.070-06
βFiB
iB
+
-
vBE
B C
E E
iB = - Is exp VtβF
vBE
βFiB
iB
+
-
VBE(on)
B C
E EAssumes vBE is aconstant and iB is
determined externally-
Chapter 3 – Section 7 (5/2/04) Page 3.7-9
CMOS Analog Circuit Design © P.E. Allen - 2004
COLLECTOR VOLTAGE INFLUENCE ON THE LARGE SIGNAL MODELBase Width Dependence on the Collector-Emitter VoltageThe large signal model so far has the collector current as a function of only the base-emitter voltage. However, there is a weak dependence of the collector current on thecollector-emitter voltage that is developed here.Influence of the base-collector depletion region width:
Fig.070-07
x
np(0) = npo exp
CarrierConcentration
InitialDepletion
Region
EmitterBase
Collector
Collector depletionregion widens due to achange in vCE, ∆VCE
WB
∆WB
Vt
vBE
iC
iC+∆iC
Note that the change of the collector-emitter voltage causes the amount of charge in thebase to change slightly influencing the collector current.
Chapter 3 – Section 7 (5/2/04) Page 3.7-10
CMOS Analog Circuit Design © P.E. Allen - 2004
The Early Voltage of BJTsPreviously we saw that,
iC = qADnni2
QB exp
vBE
Vt
Differentiation of iC with respect to vCE gives,
∂iC∂vCE
= - qADnni2
QB2
expVBEVt
∂QB∂vCE
= - ICQB
∂QB∂vCE
For a uniform-base transistor, QB = WBNA so that the derivative becomes
∂iC∂vCE
= -IC
WB ∂WB∂vCE
≡ -ICVA
⇒ VA = -WB ∂vCE∂WB
where VA is called the Early voltage.
Chapter 3 – Section 7 (5/2/04) Page 3.7-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of the Early VoltageThe output characteristics of an npn BJT:
Fig.070-08VA
iC
vCE
VBE1
VBE2
VBE3
VBE4
Modified large signal model now becomes,
iC = IS
1 + vCEVA
exp
vBE
Vt
Chapter 3 – Section 7 (5/2/04) Page 3.7-12
CMOS Analog Circuit Design © P.E. Allen - 2004
SATURATION AND INVERSE ACTIVE REGIONSRegions of Operation of the BJTIf we consider the transistor as back-to-back diodes, we can clearly see the four regionsof operation.
Fig.080-01
vBE
vBC
Saturation RegionBE forward biasedBC forward biased
Forward Active RegionBE forward biasedBC reverse biased
Inverse Active RegionBE reverse biasedBC forward biased
Cutoff RegionBE reverse biasedBC reverse biased
≈
C
B
E
C
B
E
Note: While the back-to-back diode model is appropriate here, it is not a suitable modelfor the BJT in general because it does not model the current gain mechanism of the BJT.Essentially, the back-to-back diode model has a very wide base region and all the injectedcarriers from the emitter recombine in the base (βF = 0).
Chapter 3 – Section 7 (5/2/04) Page 3.7-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Saturation RegionIn the saturation region, both the base-emitter and base-collector pn junctions areforward biased.Consequently, there is injection of electrons into the base from both the emitter andcollector.The carrier concentrations in saturation are:
Fig.080-02
x
pp(x)
np(x)
np(0)
WB
np(WB)
pnE(0)pnE
nnE
CarrierConcentration
pnC
nnC
Emitter Base Collector
np1(x)np2(x)
iCElectrons
Electrons
Chapter 3 – Section 7 (5/2/04) Page 3.7-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Typical Output Characteristics for an npn BJT
Fig.080-04
iC(mA)
5
4
3
2
1
-0.02
-0.04
-0.06
-0.08
-0.10
10 20 30 40-8 -6 -4 -2VCE(V)
BVCEOIB=0.01mA
IB=0 0.02mA
0.03mA
0.04mA
IB=0.04mA
IB=0
0.02mA
0.03mA
0.01mA
Forwardactiveregion
Inverseactiveregion
Saturation
Saturation
Cutoff
Cutoff
Chapter 3 – Section 7 (5/2/04) Page 3.7-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Large Signal Model in SaturationIn saturation, both junctions are forward biased and the impedance levels looking into theemitter or collector is very low.Simplified model:
VBE(on)
B C
E E
VCE(sat)
Fig.1.3-11
VBE(on)
B C
E E
VCE(sat)
npn pnp
where VBE(on) ≈ 0.6 to 0.7V and VCE(sat) ≈ 0.2V
Chapter 3 – Section 7 (5/2/04) Page 3.7-16
CMOS Analog Circuit Design © P.E. Allen - 2004
The Ebers-Moll Large Signal ModelConsider the saturation condition with both pn junctions forward biased.1.) The emitter injected current in the base resulting
from np1(x) is,
iEF = -IES
expvBEVt
- 1
where IES is a constant called “saturation current”
2.) The collector injected current in the base resultingfrom np2(x) is,
iCR = -ICS
expvBCVt
- 1
where ICS is a constant called “saturation current”
3.) The total collector current, iC, given as
iC = iCR + αFiEF = αFIES
expvBEVt
- 1 -ICS
expvBCVt
- 1
Also, we can write,
iE = iEF + αRiCR = IES
expvBEVt
- 1 +αRICS
expvBCVt
- 1
where αR is the collector efficiency (as an emitter) and βR = αR/(1-αR).
Fig.080-06
x
np(x)
np(0)
WB
np(WB)
Base
np1(x)np2(x)
iC
iEFiCR
Chapter 3 – Section 7 (5/2/04) Page 3.7-17
CMOS Analog Circuit Design © P.E. Allen - 2004
The Ebers-Moll Equations - ContinuedThe reciprocity condition allows us to write,
αFIEF = αRICR = ISSubstituting into the previous form of the Ebers-Moll equations gives,
iC = IS
expvBEVt
- 1 -ISαR
expvBCVt
- 1
and
iE =-ISαF
expvBEVt
- 1 +IS
expvBCVt
- 1
These equations are valid for all four regions of operation of the BJT.
Chapter 3 – Section 7 (5/2/04) Page 3.7-18
CMOS Analog Circuit Design © P.E. Allen - 2004
TRANSISTOR BREAKDOWN VOLTAGESCommon-Base Transistor Breakdown Characteristics
Fig.080-08
IE
iC
VCB
iC(mA)
VCB(V)20 40 60 80 100
1.5
1.0
0.5
0
IE=0
IE=0.5mA
IE=1.0mA
IE=1.5mA
BVCBO
As the collector-base voltage becomes large, the collector current can be written as,iC = -αFiEM
where
M = 1
1 -
vCB
BVCBO
n
Chapter 3 – Section 7 (5/2/04) Page 3.7-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Common-Emitter Transistor Breakdown CharacteristicsAssume that a constant base current, iB, is applied. Using the previous result gives
iC = -αFiEM ⇒ iE = iC
-αFM
∴ iC = -(iE + iB) ⇒ iC
1- 1
αFM = -iB ⇒ iC = αFM
1-αFM iB
where,
M = 1
1 -
vCB
BVCBO
n
Breakdown occurs when αFM = 1.
Assuming that vCE ≈ vCB gives,
αF
1 -
BVCEO
BVCBO
n = 1 ⇒ BVCEOBVCBO
= 1-αF 1/n ≈ BVCBOβF1/n
Note that BVCEO is less than BVCBO. For βF = 100 and n = 4, BVCEO ≈ 0.5BVCBO.
Chapter 3 – Section 7 (5/2/04) Page 3.7-20
CMOS Analog Circuit Design © P.E. Allen - 2004
DEPENDENCE OF ββββF ON OPERATING CONDITIONS
Transistor ββββF Dependence on Collector Current and Temperature
Plot of βF as a function of iC:
Region I: Low current region where βFdecreases as iC decreases.
Region II: Midcurrent region where βFis approximately constant.
Region III: High current region whereβF decreases as iC increases.
The temperature coefficient of βF is,
TCF = 1βF
∂βF∂Τ ≈ +7000ppm/°C (ppm = parts per million)
Fig.080-09
βF
400
300
200
100
00.1µA 1µA 10µA 100µA 1mA 10mA
iC
Region I Region II Region III
T=125°C
T=25°C
T=-55°C
Chapter 3 – Section 7 (5/2/04) Page 3.7-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Variation of Forward Beta with Collector CurrentRegion II:
iC = IS exp
vBE
Vt and iB ≈
ISβFM exp
vBE
Vt
where βFM = the maximum value of βF.
Region I:
iC = IS exp
vBE
Vt and iBX = ISX exp
vBE
mVt
due to recombination, m ≈ 2
βFL = iC
iBX =
ISISX
exp
vBE
Vt
1 - 1m
≈ ISISX
iC
Is[1-(1/m)]
for m = 2, βFL ∝ iC
Region III:
iC = ISH exp
vBE
2Vt due to the high level injection and iB ≈
ISβFM exp
vBE
Vt
βFH ≈ ISHIS βF exp
- vBE2Vt
≈ ISH2
IS βFM 1iC
Fig.080-10
ln i
ln Is
vBE(linear scale)
Region I RegionII
Region III
ln βFM
ln βFL
ln βFH
iC
iB
Chapter 3 – Section 7 (5/2/04) Page 3.7-22
CMOS Analog Circuit Design © P.E. Allen - 2004
BJT, Common-Emitter, Forward-Active RegionEffect of a small-signal input voltage applied to a BJT.
Fig.090-02
x
np(0) = npo exp
CarrierConcentration
CollectorDepletion
Region
EmitterBase
CollectorWB
Vt
VBE+vbe
IC
IC+ic
np(0) = npo exp
Vt
VBE
∆Qh
∆Qe
EmitterDepletion
RegioniB = IB + ib
iC = IC + ic
vi
VBE
VCC
An increase in vBE (vi) causes more electrons to be injected in the base increasing thebase current iB by an amount ib. The increased base current causes the collector currentiC to increase by an amount ic.
vi ⇒ ib ⇒ ic
Chapter 3 – Section 7 (5/2/04) Page 3.7-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Transconductance of the Small Signal BJT ModelThe small signal transconductance is defined as
gm ≡ diC
dvBE |Q =
∆iC∆vBE
= ic
vbe =
icvi
⇒ ic = gmvi
The large signal model for iC is
iC = IS expvBEVt
⇒ gm =
d
dvBE IS exp
vBEVt
|Q
= ISVt
expVBEVt
= ICVt
∴ gm = ICVt
Another way to develop the small signal transconductance
iC = IS exp
VBE+vi
Vt = IS exp
VBE
Vt exp
vi
Vt = IC exp
vi
Vt ≈ IC
1 + viVt
+ 12
vi
Vt2 +
16
vi
Vt3 + ···
ButiC = IC + ic
∴ ic ≈ IC viVt
+ IC2
vi
Vt2 +
IC6
vi
Vt3 + ··· ≈
ICVt
vi = gmvi
Chapter 3 – Section 7 (5/2/04) Page 3.7-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Input Resistance of the Small Signal BJT ModelIn the forward-active region, we can write that
iB = iCβF
Small changes in iB and iC can be related as
∆iB = d
diC
iC
βF ∆iC
The small signal current gain, βo, can be written as
βo = ∆iC∆iB =
1d
diC
iC
βF
= icib
Therefore, we define the small signal input resistance as
rπ ≡ viib =
βoviic =
βogm
rπ = βogm
Chapter 3 – Section 7 (5/2/04) Page 3.7-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Output Resistance of the Small Signal BJT ModelIn the forward-active region, we can write that the small signal output conductance, go(ro = 1/go) as
go ≡ diC
dvCE |Q =
∆iC∆vCE
= ic
vce ⇒ ic = govce
The large signal model for iC , including the influence of vCE, is
iC = IS
1 + vCEVA
expvBEVt
go ≡ diC
dvCE |Q = IS
1
VA exp
VBEVt
≈ ICVA
∴ ro = VAIC
Chapter 3 – Section 7 (5/2/04) Page 3.7-26
CMOS Analog Circuit Design © P.E. Allen - 2004
Simple Small Signal BJT ModelImplementing the above relationships, ic = gmvi, ic = govce, and vi = rπib, into a schematicmodel gives,
gmvirπ ro
ib ic
+
-
vi
+
-
vce
B C
E E
C
B
E
C
B
EFig. 090-03
Note that the small signal model is the same for either a npn or a pnp BJT.Example:
Find the small signal input resistance, Rin, the output resistance, Rout, and the voltagegain of the common emitter BJT if the BJT is unloaded (RL = ∞), vout/vin, the dc collectorcurrent is 1mA, the Early voltage is 100V, and βο at room temperature.
gm = ICVt
= 1mA26mV =
126 mhos Rin = rπ =
βogm
= 100·26 = 2.6kΩ
Rout = ro = VAIC =
100V1mA = 100kΩ
voutvin
= -gm ro = - 26mS·100kΩ = -2600V/V
Chapter 3 – Section 7 (5/2/04) Page 3.7-27
CMOS Analog Circuit Design © P.E. Allen - 2004
EXTENSIONS OF THE SMALL SIGNAL BJT MODELCollector-Base Resistance of the Small Signal BJT ModelRecall the influence of V on the base width:
Fig.3.7-6
x
np(0) = npo exp
CarrierConcentration
InitialDepletion
Region
EmitterBase
Collector
Collector depletionregion widens due to achange in vCE, ∆VCE
WB
∆WB
Vt
vBE
iC
iC+∆iC
We noted that an increase in vCE causes and increase in the depletion width and adecrease in the total minority-carrier charge stored in the base and therefore a decrease inthe base recombination current, iB1.
This influence is modeled by a collector-base resistor, rµ, defined as
rµ = ∆vCE∆iΒ1 =
∆vCE∆iC
∆iC ∆iΒ1 = ro
∆iC∆iΒ1 ≈ βoro (if base current is primarily recomb.)
In general, rµ ≥ 10 βoro for the npn BJT and about 2-5 βoro for the lateral pnp BJT.
Chapter 3 – Section 7 (5/2/04) Page 3.7-28
CMOS Analog Circuit Design © P.E. Allen - 2004
Base-Charging Capacitance of the Small Signal BJT ModelConsider changes in base-carrier concentrations once again.
Fig.3.7-16
x
np(0) = npo exp
CarrierConcentration
CollectorDepletion
Region
EmitterBase
CollectorWB
Vt
VBE+vbe
IC
IC+ic
np(0) = npo exp
Vt
VBE
∆Qh
∆Qe
EmitterDepletion
RegioniB = IB + ib
iC = IC + ic
vi
VBE
VCC
The ∆vBE change causes a change in the minority carriers, ∆Qe = qe, which must be equalto the change in majority carriers, ∆Qh = qh. This charge can be related to the voltageacross the base, vi, as
qh = Cbvi
where Cb is the base-charging capacitor and is given as
Cb = qhvi
= τF ic
vi = τF gm = τF
ICVt
The base transit time τF is defined as WB2
2Dn
Chapter 3 – Section 7 (5/2/04) Page 3.7-29
CMOS Analog Circuit Design © P.E. Allen - 2004
Parasitic Elements of the BJT Small Signal ModelTypical cross-section of the npn BJT:
Fig.3.7-18
p- substrate
p- isolation p- isolation
p base
n+ emitter
n+ buried layer
n collector
n+ p+
Collector Base Emitter
Ccs CcsCµ Cµ
Cje Cje
rc1
rc3
rc2
rex
p+ p p- ni n- n n+ Metal
rb
Cje = base-emitter depletion capacitance (forward biased)
Cµ = Cµ0
1 - vCBψ0
m = collector-base depletion capacitance (reverse biased)
Resistances are all bulk ohmic resistances. rb, rc, and rex are important. Also, rb = f(IC).
Chapter 3 – Section 7 (5/2/04) Page 3.7-30
CMOS Analog Circuit Design © P.E. Allen - 2004
Complete Small Signal BJT Model
Fig. 3.7-19
rµ
Cµ
gmv1
+
-
v1rπCπ
B'
ro Ccs
rc C
Erex
B rb
E
The capacitance, Cπ, consists of the sum of Cje and Cb.
Cπ = Cje +Cb
Chapter 3 – Section 7 (5/2/04) Page 3.7-31
CMOS Analog Circuit Design © P.E. Allen - 2004
ExampleDerive the complete small signal equivalent circuit for a BJT at IC = 1mA, VCB = 3V, andVCS = 5V. The device parameters are Cje0 = 10fF, ne = 0.5, ψ0e = 0.9V, Cµ0 = 10fF, nc =0.3, ψ0c = 0.5V, Ccs0 = 20fF, ns = 0.3, ψ0s = 0.65V, βo = 100, τF = 10ps, VA = 20V, rb =300Ω, rc = 50Ω, rex = 5Ω, and rµ = 10βoro.
SolutionBecause Cje is difficult to determine and usually an insignificant part of Cπ, let usapproximate it as 2Cje0.
Cje = 20fF
Cµ = Cµ0
1+ VCBψ0c
ne =
10fF
1+ 3
0.50.3
= 5.6fF and Ccs = Ccs0
1+ VCSψ0s
ns =
20F
1+ 5
0.650.3
= 10.5fF
gm = ICVt
= 1mA26mV = 38mA/V Cb = τF gm = (10ps)(38mA/V) = 0.38pF
Cπ = Cb + Cje = 0.38pF+0.02pF = 0.4pF
rπ =βogm
=100·26Ω=2.6kΩ, ro=VAIC =
20V1mA =20kΩ, and rµ=10βοro=10·100·20kΩ =20MΩ
Chapter 3 – Section 7 (5/2/04) Page 3.7-32
CMOS Analog Circuit Design © P.E. Allen - 2004
FREQUENCY RESPONSE OF THE BJTTransition Frequency, fTfT is the frequency where the magnitude of the short-circuit, common-emitter currentequal unity.Circuit and model:
Assume that rc ≈ 0. As a result, ro and Ccs have no effect.
∴ V1≈rπ
1+ rπ(Cπ+Cb)s Ii and Io≈gmV1 ⇒ Io(jω)Ii(jω) =
gmrπ
1+ gmrπ(Cπ+Cb)s
gm
=βo
1+ βo(Cπ+Cb)s
gm
Now, β(jω) = Io(jω)Ii(jω) =
βo
1+ βo(Cπ+Cb)jω
gm
At high frequencies,
β(jω) ≈ gm
jω (Cπ+Cb) ⇒ When | β(jω)| =1 then ωT = gm
Cπ+Cb or fT =
12π
gm Cπ+Cb
Fig.3.7-20
io
ii
ii
Cµ
gmv1
+
-
v1rπCπ ro Ccs
rcrb
io
Chapter 3 – Section 7 (5/2/04) Page 3.7-33
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of the BJT Transition Frequencyβ as a function of frequency:
Fig.3.7-21
|β(jω)|
1000
100
10
1
βo
-6dB/octave
ωβ 0.1ωT ωTω (log scale)
Note that the product of the magnitude and frequency at any point on the –6dB/octavecurve is equal to ωT.
For example,0.1 ωT x10 = ωT
In measuring ωT, the value of |β(jω)| is measured at some frequency less than ωT (sayωx) and ωT is calculated by taking the product of |β(jωx)| and ωx to get ωT.
Chapter 3 – Section 7 (5/2/04) Page 3.7-34
CMOS Analog Circuit Design © P.E. Allen - 2004
Current Dependence of fT
Note that τT = 1ωΤ =
Cπgm
+ Cµgm
= Cbgm
+ Cjegm
+ Cµgm
= τF + Cjegm
+ Cµgm
At low currents, the Cje and Cµ terms dominate causing τT to rise and ωT to fall.
At high currents, τT approaches τF which is the maximum value of ωT.
For further increases in collector current, ωT decreases because of high-level injectioneffects and the Kirk effect.
Typical frequency dependence of fT:
Fig.3.7-22
fT (GHz)
10
8
6
4
2
010µA 100µA 1mA 10mA
IC
Chapter 3 – Section 7 (5/2/04) Page 3.7-35
CMOS Analog Circuit Design © P.E. Allen - 2004
NOISE MODEL FOR THE BJTModel DevelopmentConsider the BJT in the following mode of operation:
Add all internal noise sources to the BJT small signal model to get:
B
E
C
E
io
ic2 = 2qIC∆fib2 = 2qIB∆f + K1
IBf∆f
vb2 = 4kTrb∆frb
rπ Cπ vπ
+
-
gmvπ ro
B'
Noise-free BJT
*
wherevb2 = thermal noise of the base resistance
ib2 = base shot and flicker noise currentsand
ic2 = collector shot and flicker noise currents
+
-
vin
io
Chapter 3 – Section 7 (5/2/04) Page 3.7-36
CMOS Analog Circuit Design © P.E. Allen - 2004
Equivalent BJT Noise Model
Find an equivalent input noise current, ii2 , and input noise voltage, vi2 , given as:
B C
E E
gmvπCπ roii2 io2vin
eeq2 =vi2
vπ
*ieq2 = rπ
rb B'
Fig. 3.7-25Noise-free BJT
To find ii2 and vi2 , perform the following steps:
1.) Short circuit the input and find io2 of both models and equate to get vi2 .
2,) Open circuit the input and find io2 of both models and equate to get ii2 .
Calculations:1,) Short circuit the input (assume rb << rπ)
Ckt 1: io2 = g m 2 vb2 + ic2
Ckt 2: io2 = g m 2 vi2 veq2 = vi2 = vb2 +
ic2
gm2
Chapter 3 – Section 7 (5/2/04) Page 3.7-37
CMOS Analog Circuit Design © P.E. Allen - 2004
Equivalent BJT Noise Model – Continued2.) Open circuit the input (assume rb << rπ)
Circuit 1:
io2 = ic2 + gm2
rπ
sCπ
rπ + 1
sCπ
2
ib2 = ic2 + gm2rπ2
1
srπCπ+12 ib2
io2 = ic2 + ßo2
1
sωß + 1
2 ib2 = ic2 + |ß(jω)|2 ib2
Circuit 2:
io2 = |ß(jω)|2 ii2
Equating the above results gives
ieq2 = ii2 = ib2 + ic2
|ß(jω)|2 = 2qIB∆f + K1IB∆f
f + 2qIC∆f|ß(jω)|2
Chapter 3 – Section 7 (5/2/04) Page 3.7-38
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Dependence of the BJT Noise Model
Frequency response of ii1 or ieq2 ,
1/f
Thermal Influence of a decreasing ß
fβ log f
10-23
10-24
10-25
ieq2 = ii
2 AHz
100 1k 10k 100k 1M 10M 100M1G
Chapter 3 – Section 7 (5/2/04) Page 3.7-39
CMOS Analog Circuit Design © P.E. Allen - 2004
Thermal Noise due to Parasitic Resistances
vc2 = 4kTrc/Area
ve2 = 4kTrc/Area
and
vb2 = 4kTrb/Area (already included)
Modified BJT noise model:
B
E
C
ic2 = 2qIC∆f
ib2 = 2qIB∆f + K1
IB
f∆f
vb2 = 4kTrb∆frb
rπ Cπ vπ
+
-
gmvπ ro
B'
CCS
rc
re
rµ
Cµ
ve2 = 4kTre∆f
vc2 = 4kTrc∆f
* *
*
Chapter 3 – Section 7 (5/2/04) Page 3.7-40
CMOS Analog Circuit Design © P.E. Allen - 2004
COMPARISON OF THE MOS AND BIPOLAR TRANSISTORSQuantity MOS Transistor Bipolar Transistor
Intrinsic Gain 2K’Wλ2LID
∝ 1
ID
VAVt
ωT gmCgs
= 3
2Cox
2K’IDWL3
1τF
Input Noise Voltage(V2/Hz)
8kT3gm
+ K’
WLCoxf 4kTrb + 2qICgm2
Input Noise Current(A2/Hz)
02q
IB + K1 IBa
f + IC
|β(jω)|2
Input Offset Voltage∆VT +
VGS-VT2
-∆RR -
∆(W/L)W/L
kTq
-∆RR -
∆AEAE
- ∆QBQB
Rout1
λΙD VAIC
Rin ∞ rπ
gm 2K’WIDL
ICVt
Chapter 3 – Section 8 (5/2/04) Page 3.8-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SEC. 3.8 – SPICE LEVEL 2 MODELSECOND-ORDER EFFECTS IN THE LARGE SIGNAL MODEL
Derivation of the Second-Order ModelConsider the following illustration of aMOSFET in the active region:
Assume, the charge in the depletion region between the channel and bulk is no longerconstant and is dependent on v(y). Therefore, we model the dependence of thresholdvoltage, VT, on y as
VT(y) = VT0 + γ
2|φF| + vCB - 2φF
where vCB is the voltage across the depletion region at y and is expressed as
vCB = vS + v(y) – vB = v(y) + vSB
∴ VT(y) = VT0 + γ
2|φF| + v(y) + vSB - 2φF
Polysilicon
p+
p- substrateFig.3.8-1
VG > VT VD < VDS(sat)
n+n+
DepletionRegion
B S
dy
0 Ly
v(y)
VSB
Chapter 3 – Section 8 (5/2/04) Page 3.8-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Derivation of the Second-Order Model – ContinuedNow we repeat the previous analysis using this expression for VT.
The charge in the inversion layer was written as,
QI(y) = Cox vGS -v(y) -VT (y) = Cox
vGS -v(y) -VT0 -γ 2|φF| +v(y) +vSB + 2φF
Using Ohm’s law for an increment, dy, of channel, we can write
dv(y) = iDdR = iDdy
µnQI(y)W ⇒ iDdy = µnWQI(y)dv(y)
Integrating this result over the channel from source to drain gives,
iD = ⌡⌠0
Ldy = µnWCox ⌡
⌠
0
vDS
vGS -v(y) -VT0 -γ 2|φF| +v(y) +vSB + 2φF dv
Evaluating the limits gives,
iDL = µnWCox
vGS-VT0+γ 2|φF|-vDS2 vDS-
23γ 2|φF| +vSB+vDS 1.5+
23γ 2|φF|+vSB 1.5
or iD = µnWCox
L
vGS-VT0+γ 2|φF|-vDS2 vDS-
23γ 2|φF|+vSB+vDS 1.5+
23γ 2|φF|+vSB 1.5
These results agree with the first edition of the text if the following definitions are made:
VBIN ≈ VT0 - γ 2|φF| , θ ≈ 1 andπεsi
4CoxW ≈ 1
Chapter 3 – Section 8 (5/2/04) Page 3.8-3
CMOS Analog Circuit Design © P.E. Allen - 2004
SECOND-ORDER EFFECTS DUE TO SMALL GEOMETRIESSecond-Order Effects1.) Mobility degradation, µs
2.) Corrected threshold voltage, VBIN
3.) Corrected bulk threshold parameter, γs
4.) Effective channel length, Lmod
New model:
iD = µsWCox
Lmod
vGS -VBIN -θvDS
2 vDS - 23γγγγs
2|φF| +vSB+vDS 1.5+ 2|φF| +vSB 1.5
Chapter 3 – Section 8 (5/2/04) Page 3.8-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Mobility DegradationThe degradation of the surface mobility µo can be written as
µs = µo
UCRIT·εsi
Cox [vGS-VT-UTRA·vDS] UEXP
whereUCRIT = Critical field for mobility degradation (Volts/cm)UTRA = Transverse field coefficient for mobility degradationUEXP = Critical field exponent for mobility degradation
Normally, µs ≤ µo
Chapter 3 – Section 8 (5/2/04) Page 3.8-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Corrected Threshold VoltageThe corrected built-in threshold voltage for short channel transistors can be expressed as
VBIN = VFB + 2φF + ∆ πεsi
4CoxW (2φF - |vBS|)
where∆ = an empirical channel width factor which adjusts the threshold voltage
θ = 1 + πεsi
4CoxW
Chapter 3 – Section 8 (5/2/04) Page 3.8-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Corrected Bulk Threshold ParameterConsider the following geometricalsituation for short channels:
Define the corrected bulk thresholdparameter as
γs = γ(1-αS - αD)where
αS = XJ2L
1+ 2WSXJ - 1
αD = XJ2L
1+ 2WDXJ - 1
whereXJ = metallurgical junction depth (meters)
WS = source depletion width = 2εsi
q·NSUB (2φF + |vSB|) )
WD = Drain depletion width = 2εsi
q·NSUB (2φF + |vSB| + vDS) )
Fig.3.8-2
XJ
WS
XJ
WDXJ+WS XJ+WD
Bulk charge depletedby the gate field
Polysilicon Gate Gate oxide
Source Drain
Bulk/Substrate
WSWD
Chapter 3 – Section 8 (5/2/04) Page 3.8-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Effective Channel LengthEffective channel length, Lmod can be expressed as,
Lmod = Leff(1-λvDS)
whereLeff = L –2·XJ·LD
LD = lateral diffusion
λ = 1
LeffvDS
2εsiq·NSUB
vDS-vDS(sat)4 + 1 +
vDS-vDS(sat)
42
and
vDS(sat) = vGS-VBIN
θ + γs2
2θ2
1- 1+ θ2
γs2
vGS-VBIN
θ + 2φF + |vBS|
Other short channel effects not considered here:• Saturation due to scattering-limited velocity• Hot electron effects
Chapter 3 – Section 9 (5/2/04) Page 3.9-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SEC. 3.9 – MODELS FOR SIMULATION OF MOS CIRCUITSFET Model Generations• First Generation – Physically based analytical model including all geometry
dependence.• Second Generation – Model equations became subject to mathematical conditioning for
circuit simulation. Use of empirical relationships and parameter extraction.• Third Generation – A return to simpler model structure with reduced number of
parameters which are physically based rather than empirical. Uses better methods ofmathematical conditioning for simulation including more specialized smoothingfunctions.
Performance Comparison of Models (from Cheng and Hu, MOSFET Modeling & BSIM3Users Guide)
Model MinimumL (µm)
MinimumTox (nm)
ModelContinuity
iD Accuracy inStrong Inversion
iD Accuracy inSubthreshold
Small signalparameter
Scalability
MOS1 5 50 Poor Poor Not Modeled Poor Poor
MOS2 2 25 Poor Poor Poor Poor Fair
MOS3 1 20 Poor Fair Poor Poor Poor
BSIM1 0.8 15 Fair Good Fair Poor Fair
BSIM2 0.35 7.5 Fair Good Good Fair Fair
BSIM3v2 0.25 5 Fair Good Good Good Good
BSIM3v3 0.15 4 Good Good Good Good Good
Chapter 3 – Section 9 (5/2/04) Page 3.9-2
CMOS Analog Circuit Design © P.E. Allen - 2004
First Generation ModelsLevel 1 (MOS1)• Basic square law model based on the gradual channel approximation and the square law
for saturated drain current.• Good for hand analysis.• Needs improvement for deep-submicron technology (must incorporate the square law to
linear shift)Level 2 (MOS2)• First attempt to include small geometry effects• Inclusion of the channel-bulk depletion charge results in the familiar 3/2 power terms• Introduced a simple subthreshold model which was not continuous with the strong
inversion model.• Model became quite complicated and probably is best known as a “developing ground”
for better modeling techniques.Level 3 (MOS3)• Used to overcome the limitations of Level 2. Made use of a semi-empirical approach. • Added DIBL and the reduction of mobility by the lateral field.• Similar to Level 2 but considerably more efficient.• Used binning but was poorly implemented.
Chapter 3 – Section 9 (5/2/04) Page 3.9-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Second Generation ModelsBSIM (Berkeley Short-Channel IGFET Model)• Emphasis is on mathematical conditioning for circuit simulation• Short channel models are mostly empirical and shifts the modeling to the parameter
extraction capability• Introduced a more detailed subthreshold current model with good continuity• Poor modeling of channel conductanceHSPICE Level 28• Based on BSIM but has been extensively modified.• More suitable for analog circuit design• Uses model binning• Model parameter set is almost entirely empirical• User is locked into HSPICE• Model is proprietaryBSIM2• Closely based on BSIM• Employs several expressions developed from two dimensional analysis• Makes extensive modifications to the BSIM model for mobility and the drain current• Uses a new subthreshold model• Output conductance model makes the model very suitable for analog circuit design• The drain current model is more accurate and provides better convergence• Becomes more complex with a large number of parameters• No provisions for variations in the operating temperature
Chapter 3 – Section 9 (5/2/04) Page 3.9-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Third Generation ModelsBSIM3• This model has achieved stability and is being widely used in industry for deep
submicron technology.• Initial focus of simplicity was not realized.MOS Model 9• Developed at Philips Laboratory• Has extensive heritage of industrial use• Model equations are clean and simple – should be efficientOther Candidates• EKV (Enz-Krummenacher-Vittoz) – fresh approach well suited to the needs of analog
circuit design
Chapter 3 – Section 9 (5/2/04) Page 3.9-5
CMOS Analog Circuit Design © P.E. Allen - 2004
BSIM2 ModelGeneric composite expression for the model parameters:
X = Xo + LXLeff +
WXWeff
whereXo = parameter for a given W and LLX (WX) = first-order dependence of X on L (W)
Modeling features of BSIM2:Mobility• Mobility reduction by the vertical field• Mobility reduction by the lateral fieldDrain Current• Velocity saturation• Linear region drain current• Saturation region drain current• Subthreshold current
iDS = µoCoxWeff
Leff ·
kT
q evGS-Vt-Voff
n ·
1 - eqVDS/kT
where
Voff = VOF + VOFB ·vBS + VOFD ·vDS and n = NO + NB
PHI - vBS + ND ·vDS
Chapter 3 – Section 9 (5/2/04) Page 3.9-6
CMOS Analog Circuit Design © P.E. Allen - 2004
BSIM2 Output Conductance Model
Rout
vDSvDS(sat)00
LinearRegion(Triode)
Channellength
modulation(CLM)
Saturation(DIBL) Substrate
currentinduced
bodyeffect
(SCBE)
Draincurrent
5V(3.1-2)
• Drain-Induced Barrier Lowering (DIBL) – Lowering of the potential barrier at thesource-bulk junction allowing carriers to traverse the channel at a lower gate biasthan would otherwise be expected.
• Substrate Current-Induced Body Effect (SCBE) – The high field near the drainaccelerates carriers to high energies resulting in impact ionization which generates ahole-electron pair (hot carrier generation). The opposite carriers are swept into thesubstrate and have the effect of slightly forward-biasing the source-substrate junction.This reduces the threshold voltage and increases the drain current.
Charge Model• Eliminates the partitioning choice (50%/50% is used)• BSIM charge model better documented with more options
Chapter 3 – Section 9 (5/2/04) Page 3.9-7
CMOS Analog Circuit Design © P.E. Allen - 2004
BSIM2 Basic Parameter Extraction• A number of devices with different W/L are fabricated and measured
Weff,3
Weff,2
Weff,1
Weff
Leff,2Leff,1 Leff,3 Leff,4Leff
3 4
8
1211
7
109
5 6
1 2
• A long, wide device is used as the base to add geometry effects as corrections.• Procedure:
1.) Oxide thickness and the differences between the drawn and effective channeldimensions are provided as process input.2.) A long, wide device is used to determine some base parameters which are used asthe starting point for each individual device extraction in the second phase.3.) In the second phase, a set of parameters is extracted independently for each device.This phase represents the fitting of the data for each independent device to the intrinsicequation structure of the model
1.) In the third phase, the compiled parameters from the second phase are used todetermine the geometry parameters. This represents the imposition of the extrinsicstructure onto the model.
Chapter 3 – Section 9 (5/2/04) Page 3.9-8
CMOS Analog Circuit Design © P.E. Allen - 2004
BSIM2 Model used in SubthresholdBSIM Model Parameters used in SubthresholdVDS 1 0 DC 3.0M1 1 1 0 0 CMOSN W=5UM L=2UM.MODEL CMOSN NMOS LEVEL=4+VFB=-7.92628E-01 LVFB= 1.22972E-02 WVFB=-1.00233E-01+PHI= 7.59099E-01 LPHI= 0.00000E+00 WPHI= 0.00000E+00+K1= 1.06705E+00 LK1= 5.08430E-02 WK1= 4.72787E-01+K2=-4.23365E-03 LK2= 6.76974E-02 WK2= 6.27415E-02+ETA=-4.30579E-03 LETA= 9.05179E-03 WETA= 7.33154E-03+MUZ= 5.58459E+02 DL=6.86137E-001 DW=-1.04701E-001+U0= 5.52698E-02 LU0= 6.09430E-02 WU0=-6.91423E-02+U1= 5.38133E-03 LU1= 5.43387E-01 WU1=-8.63357E-02+X2MZ= 1.45214E+01 LX2MZ=-3.08694E+01 WX2MZ= 4.75033E+01+X2E=-1.67104E-04 LX2E=-4.75323E-03 WX2E=-2.74841E-03+X3E= 5.33407E-04 LX3E=-4.69455E-04 WX3E=-5.26199E-03+X2U0= 2.45645E-03 LX2U0=-1.46188E-02 WX2U0= 2.63555E-02+X2U1=-3.80979E-04 LX2U1=-1.71488E-03 WX2U1= 2.23520E-02+MUS= 5.48735E+02 LMUS= 3.28720E+02 WMUS= 1.35360E+02+X2MS= 6.72261E+00 LX2MS=-3.48094E+01 WX2MS= 9.84809E+01+X3MS=-2.79427E+00 LX3MS= 6.31555E+01 WX3MS=-1.99720E-01+X3U1= 1.18671E-03 LX3U1= 6.13936E-02 WX3U1=-3.49351E-03+TOX=4.03000E-002 TEMP= 2.70000E+01 VDD= 5.00000E+00+CGDO=4.40942E-010 CGSO=4.40942E-010 CGBO=6.34142E-010+XPART=-1.00000E+000+N0=1.00000E+000 LN0=0.00000E+000 WN0=0.00000E+000+NB=0.00000E+000 LNB=0.00000E+000 WNB=0.00000E+000+ND=0.00000E+000 LND=0.00000E+000 WND=0.00000E+000+RSH=0 CJ=4.141500e-04 CJSW=4.617400e-10 JS=0 PB=0.8+PBSW=0.8 MJ=0.4726 MJSW=0.3597 WDF=0 DELL=0.DC VDS 5.0 0 0.01.PRINT DC ID(M1).PROBE.END
Chapter 3 – Section 9 (5/2/04) Page 3.9-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Results of the BSIM2 Model Simulation in Subthreshold
0V 0.4V 0.8V 1.2V
ID(M
1)
1.6V 2VVGS
100µA
1µA
10nA
100pA
1nA
100nA
10µAvGS
iD +
-
Chapter 3 – Section 9 (5/2/04) Page 3.9-10
CMOS Analog Circuit Design © P.E. Allen - 2004
BSIM3 ModelThe background for the BSIM3 model and the equations are given in detail in the textMOSFET Modeling & BSIM3 User’s Guide, by Y. Cheng and C. Hu, Kluwer AcademicPublishers, 1999.The short channel effects included in the BSIM3 model are:• Normal and reverse short-channel and narrow-width effects on the threshold.• Channel length modulation (CLM).• Drain induced barrier lowering (DIBL).• Velocity saturation.• Mobility degradation due to the vertical electric field.• Impact ionization.• Band-to-band tunnelling.• Velocity overshoot.• Self-heating.1.) Channel quantiztion.2.) Polysilicon depletion.
Chapter 3 – Section 9 (5/2/04) Page 3.9-11
CMOS Analog Circuit Design © P.E. Allen - 2004
BSIM3v3 Model Equations for Hand CalculationsIn strong inversion, approximate hand equations are:
iDS = µeffCox Weff
Leff
1
1+ vDS
EsatLeff
vGS -Vth - AbulkvDS
2 vDS , vDS < VDS(sat)
iDS = WeffvsatCox[vGS – Vth – AbulkVDS(sat)]
1+ vDS - VDS(sat)
VA , vDS > VDS(sat)
where
VDS(sat) = EsatLeff(vGS-Vth)
AbulkEsatLeff + (vGS-Vth)
Leff = Ldrawn – 2dL
Weff = Wdrawn – 2dW
Esat = Electric field where the drift velocity (v) saturates
vsat = saturation velocity of carriers in the channel
µ = µeff
1+(Ey/Esat) ⇒ µeff = 2vsat
Esat
Note: Assume Abulk ≈ 1 and extract Vth and VA.
Chapter 3 – Section 9 (5/2/04) Page 3.9-12
CMOS Analog Circuit Design © P.E. Allen - 2004
MOSIS Parametric Test Results
http://www.mosis.org/ RUN: T02D VENDOR: TSMC TECHNOLOGY: SCN025 FEATURE SIZE: 0.25 microns
INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of MOSIStest structures on each wafer of this fabrication lot. SPICE parameters obtained from similar measurements on aselected wafer are also attached.
COMMENTS: TSMC 0251P5M.
TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS
MINIMUM 0.36/0.24 Vth 0.54 -0.50 voltsSHORT 20.0/0.24 Idss 557 -256 uA/um Vth 0.56 -0.56 volts Vpt 7.6 -7.2 voltsWIDE 20.0/0.24 Ids0 6.6 -1.5 pA/umLARGE 50.0/50.0 Vth 0.47 -0.60 volts Vjbkd 5.8 -7.0 volts Ijlk -25.0 -1.1 pA Gamma 0.44 0.61 V0.5
K’ (Uo*Cox/2) 112.0 -23.0 uA/V2
Chapter 3 – Section 9 (5/2/04) Page 3.9-13
CMOS Analog Circuit Design © P.E. Allen - 2004
0.25µm BSIM3v3.1 NMOS Parameters.MODEL CMOSN NMOS ( LEVEL = 49+VERSION = 3.1 TNOM = 27 TOX = 5.7E-9+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.4273342+K1 = 0.3922983 K2 = 0.0185825 K3 = 1E-3+K3B = 2.0947677 W0 = 2.171779E-7 NLX = 1.919758E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 7.137212E-3 DVT1 = 6.066487E-3 DVT2 = -0.3025397+U0 = 403.1776038 UA = -3.60743E-12 UB = 1.323051E-18+UC = 2.575123E-11 VSAT = 1.616298E5 A0 = 1.4626549+AGS = 0.3136349 B0 = 3.080869E-8 B1 = -1E-7+KETA = 5.462411E-3 A1 = 4.653219E-4 A2 = 0.6191129+RDSW = 345.624986 PRWG = 0.3183394 PRWB = -0.1441065+WR = 1 WINT = 8.107812E-9 LINT = 3.375523E-9+XL = 3E-8 XW = 0 DWG = 6.420502E-10+DWB = 1.042094E-8 VOFF = -0.1083577 NFACTOR = 1.1884386+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 4.914545E-3 ETAB = 4.215338E-4+DSUB = 0.0313287 PCLM = 1.2088426 PDIBLC1 = 0.7240447+PDIBLC2 = 5.120303E-3 PDIBLCB = -0.0443076 DROUT = 0.7752992+PSCBE1 = 4.451333E8 PSCBE2 = 5E-10 PVAG = 0.2068286+DELTA = 0.01 MOBMOD = 1 PRT = 0+UTE = -1.5 KT1 = -0.11 KT1L = 0+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18+UC1 = -5.6E-11 AT = 3.3E4 WL = 0+WLN = 1 WW = -1.22182E-16 WWN = 1.2127+WWL = 0 LL = 0 LLN = 1+LW = 0 LWN = 1 LWL = 0+CAPMOD = 2 XPART = 0.4 CGDO = 6.33E-10+CGSO = 6.33E-10 CGBO = 1E-11 CJ = 1.766171E-3+PB = 0.9577677 MJ = 0.4579102 CJSW = 3.931544E-10+PBSW = 0.99 MJSW = 0.2722644 CF = 0+PVTH0 = -2.126483E-3 PRDSW = -24.2435379 PK2 = -4.788094E-4+WKETA = 1.430792E-3 LKETA = -6.548592E-3 )
Chapter 3 – Section 9 (5/2/04) Page 3.9-14
CMOS Analog Circuit Design © P.E. Allen - 2004
0.25µm BSIM3v3.1 PMOS ParametersMODEL CMOSP PMOS ( LEVEL = 49+VERSION = 3.1 TNOM = 27 TOX = 5.7E-9+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.6193382+K1 = 0.5275326 K2 = 0.0281819 K3 = 0+K3B = 11.249555 W0 = 1E-6 NLX = 1E-9+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 3.1920483 DVT1 = 0.4901788 DVT2 = -0.0295257+U0 = 185.1288894 UA = 3.40616E-9 UB = 3.640498E-20+UC = -6.35238E-11 VSAT = 1.975064E5 A0 = 0.4156696+AGS = 0.0702036 B0 = 3.111154E-6 B1 = 5E-6+KETA = 0.0253118 A1 = 2.421043E-4 A2 = 0.6754231+RDSW = 866.896668 PRWG = 0.0362726 PRWB = -0.293946+WR = 1 WINT = 6.519911E-9 LINT = 2.210804E-8+XL = 3E-8 XW = 0 DWG = -2.423118E-8+DWB = 3.052612E-8 VOFF = -0.1161062 NFACTOR = 1.2546896+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 0.7241245 ETAB = -0.3675267+DSUB = 1.1734643 PCLM = 1.0837457 PDIBLC1 = 9.608442E-4+PDIBLC2 = 0.0176785 PDIBLCB = -9.605935E-4 DROUT = 0.0735541+PSCBE1 = 1.579442E10 PSCBE2 = 6.707105E-9 PVAG = 0.0409261+DELTA = 0.01 MOBMOD = 1 PRT = 0+UTE = -1.5 KT1 = -0.11 KT1L = 0+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18+UC1 = -5.6E-11 AT = 3.3E4 WL = 0+WLN = 1 WW = 0 WWN = 1+WWL = 0 LL = 0 LLN = 1+LW = 0 LWN = 1 LWL = 0+CAPMOD = 2 XPART = 0.4 CGDO = 5.11E-10+CGSO = 5.11E-10 CGBO = 1E-11 CJ = 1.882953E-3+PB = 0.99 MJ = 0.4690946 CJSW = 3.018356E-10+PBSW = 0.8137064 MJSW = 0.3299497 CF = 0+PVTH0 = 5.268963E-3 PRDSW = -2.2622317 PK2 = 3.952008E-3+WKETA = -7.69819E-3 LKETA = -0.0119828 )
Chapter 3 – Section 9 (5/2/04) Page 3.9-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Adjustable Precision Analog Models – Table Lookupy
x1
x2
x3
HighLevel
Simulators
CircuitLevel
Simulators
"Extraction" Methodology I-V characterisitcs Capacitances Transconductances
ProcessSimulators Measurement
Methods
• ObjectiveDevelop models having adjustable precision in ac and dc perfomrance using tablelookup models.
• AdvantagesUsable at any level – device, circuit, or behavioralQuickly developed from experiment or process simulatorsFaster than analytical device models (BSIM)
• DisadvantagesRequires approximately 10kbytes for a typical MOS modelCan’t be parameterized easily
Chapter 3 – Section 9 (5/2/04) Page 3.9-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of MOSFET Models for Simulation• Models are much improved for efficient computer simulation• Output conductance model is greatly improved• Poor results for narrow channel transistors• Can have discontinuities at bin boundaries• Fairly complex model, difficult to understand in detail
Chapter 3 – Section 10 (5/2/04) Page 3.10-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SEC. 3.10 – EXTRACTION OF A LARGE SIGNAL MODEL FOR HANDCALCULATIONS
ObjectiveExtract a simple model that is useful for design from the computer models such as
BSIM3.
Extraction for Short Channel Models
Procedure for extracting short channel models:
1.) Extract the square-law model parameters for a transistor with length at least 10times Lmin.
2.) Using the values of K’, VT , λ, and γ extract the model parameters for the followingmodel:
iD = K’
2[1 + θ(vGS-VT)] WL [ vGS – VT]2(1+λvDS)
Adjust the values of K’, VT , and λ as needed.
Chapter 3 – Section 10 (5/2/04) Page 3.10-2
CMOS Analog Circuit Design © P.E. Allen - 2004
EXTRACTION OF THE SIMPLE, SQUARE-LAW MODEL
Characterization of the Simple Square-Law ModelEquations for the MOSFET in strong inversion:
iD = K
Weff
2Leff(vGS - VT) 2(1 + λvDS) (1)
iD = K
Weff
Leff
(vGS - VT)vDS - v
2DS2 (1 + λvDS) (2)
where
VT = VT0 + γ [ 2|φF| + vSB − 2|φF| ] (3)
Chapter 3 – Section 10 (5/2/04) Page 3.10-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Extraction of Model Parameters:
First assume that vDS is chosen such that the λvDS term in Eq. (1) is much less than oneand vSB is zero, so that VT = VT0.
Therefore, Eq. (1) simplifies to
iD = K’
Weff
2Leff (vGS - VT0) 2 (4)
This equation can be manipulated algebraically to obtain the following
i1/2D =
K' Weff
2Leff1/2
vGS =
K' Weff
2Leff1/2
VT0 (5)
which has the formy = mx + b (6)
This equation is easily recognized as the equation for a straight line with m as the slopeand b as the y-intercept. Comparing Eq. (5) to Eq. (6) gives
y = i1/2D (7)
x = vGS (8)
m =
K' Weff
2Leff1/2
(9)
and
b = -
K' Weff
2Leff1/2
VT0 (10)
Chapter 3 – Section 10 (5/2/04) Page 3.10-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of K’ and VT Extraction
iD( )1/2
vDS>VDSAT
m=′ K Weff
2Leff
1/2
vGS′ b =VT0
Weak inversionregion
Mobility degradationregion
00 AppB-01
Comments:• Stay away from the extreme regions of mobility degradation and weak inversion• Use channel lengths greater than Lmin
Chapter 3 – Section 10 (5/2/04) Page 3.10-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 3.10-1 – Extraction of K’ and VT Using Linear RegressionGiven the following transistor data shown in Table 3.10-1 and linear regression formulasbased on the form,
y = mx + b (11)
and
m = ∑xi yi - (∑ xi∑ yi)/n
∑x2i - (∑xi)2/n
(12)
determine VT0 and K W/2L. The data in Table B-1 also give I1/2D as a function of VGS.
Table 3.10-1 Data for Example 3.10-1
VGS (V) ID (µA) ID (µA)1/2 VSB (V)1.000 0.700 0.837 0.0001.200 2.00 1.414 0.0001.500 8.00 2.828 0.0001.700 13.95 3.735 0.0001.900 22.1 4.701 0.000
Chapter 3 – Section 10 (5/2/04) Page 3.10-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 3.10-1 – ContinuedSolution
The data must be checked for linearity before linear regression is applied. Checkingslopes between data points is a simple numerical technique for determining linearity.Using the formula that
Slope = m = ∆y∆x =
ID2 - ID1
VGS2 - VGS1
Gives
m1 = 1.414 - 0.837
0.2 = 2.885 m2 = 2.828 - 1.414
0.3 = 4.713
m3 = 3.735 - 2.828
0.2 = 4.535 m4 = 4.701 - 3.735
0.2 = 4.830
These results indicate that the first (lowest value of VGS) data point is either bad, or at apoint where the transistor is in weak inversion. This data point will not be included insubsequent analysis. Performing the linear regression yields the following results.
VT0 = 0.898 V and K'Weff2Leff
= 21.92 µA/V2
Chapter 3 – Section 10 (5/2/04) Page 3.10-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Extraction of the Bulk-Threshold Parameter γγγγUsing the same techniques as before, the following equation
VT = VT0 + γ [ 2|φF| + vSB − 2|φF| ] is written in the linear form where
y = VT
x = 2|φF| + vSB − 2|φF| (13)m = γ
b = VT0
The term 2|φF| is unknown but is normally in the range of 0.6 to 0.7 volts.Procedure:
1.) Pick a value for 2|φF|.2.) Extract a value for γ.
3.) Calculate NSUB using the relationship, γ = 2εsi q NSUB
Cox
4.) Calculate φF using the relationship, φF = − kTq ln
NSUB
ni
5.) Iterative procedures can be used to achieve the desired accuracy of γ and 2|φF|.Generally, an approximate value for 2|φF| gives adequate results.
Chapter 3 – Section 10 (5/2/04) Page 3.10-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of the Procedure for Extracting γγγγ
A plot of iD versus vGS for different values of vSB used to determine γ is shown below.
iD( )1/2
vGSVT0 VT1 VT2 VT3 FigAppB-02
By plotting VT versus x of Eq. (13) one can measure the slope of the best fit line fromwhich the parameter γ can be extracted. In order to do this, VT must be determined atvarious values of vSB using the technique previously described.
Chapter 3 – Section 10 (5/2/04) Page 3.10-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of the Procedure for Extracting γγγγ - ContinuedEach VT determined above must be plotted against the vSB term. The result is shownbelow. The slope m, measured from the best fit line, is the parameter γ.
VT VSB=1V m= γ
VSB =2VVSB =3V
VSB =0V
vSB +2 φF( )0.5− 2 φF( )
0.5FigAppB-03
Chapter 3 – Section 10 (5/2/04) Page 3.10-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 3.10-2 – Extraction of the Bulk Threshold ParameterUsing the results from Ex. 3.10-1 and the following transistor data, determine the value ofγ using linear regression techniques. Assume that 2|φF| is 0.6 volts.
Table 3.10-2 Data for Example 3.10-2.VSB (V) VGS (V) ID (µA)1.000 1.400 1.4311.000 1.600 4.551.000 1.800 9.441.000 2.000 15.952.000 1.700 3.152.000 1.900 7.432.000 2.10 13.412.000 2.30 21.2
SolutionTable 3.10-2 shows data for VSB = 1 volt and VSB = 2 volts. A quick check of the data inthis table reveals that ID versus VGS is linear and thus may be used in the linearregression analysis. Using the same procedure as in Ex. 3.10-1, the following thresholdsare determined: VT0 = 0.898 volts (from Ex. 3.10-1), VT = 1.143 volts (@VSB = 1 V), and VT
= 1.322 V (@VSB = 2 V). Table 3.10-3 gives the value of VT as a function of [(2|φF| + VSB)1/2 − (2|φF|)1/2 ] for the three values of VSB.
Chapter 3 – Section 10 (5/2/04) Page 3.10-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 3.10-2 - ContinuedTable 3.10-3 Data for Example 3.10-2.
VSB (V) VT (V) [ 2|φF| + VSB - 2|φF| ] (V1/2)0.000 0.898 0.0001.000 1.143 0.4902.000 1.322 0.838
With these data, linear regression must be performed on the data of VT versus [(2|φF| +VSB)0.5 − (2|φF |)0.5]. The regression parameters of Eq. (12) are
Σxiyi = 1.668
Σxiyi = 4.466
Σx2i = 0.9423
(Σxi)2 = 1.764
These values give m = 0.506 = γ.
Chapter 3 – Section 10 (5/2/04) Page 3.10-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Extraction of the Channel Length Modulation Parameter, λλλλThe channel length modulation parameter λ should be determined for all device lengthsthat might be used. For the sake of simplicity, Eq. (1) is rewritten as
iD = i’D=λ’ vDS + i’D
which is in the familiar linear form wherey = iD (Eq. (1))
x = vDS
m = λi'Db = i'D (Eq. (1) with λ = 0)
By plotting iD versus vDS, measuring the slopeof the data in the saturation region, anddividing that value by the y-intercept, λ can bedetermined. The procedure is illustrated in thefigure shown. i'Dm= λ
vDS
iD
i'D
Nonsaturationregion
Saturation region
AppB-03
Chapter 3 – Section 10 (5/2/04) Page 3.10-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 3.10-3 – Extraction of the Channel Length Modulation ParameterGiven the data of ID versus VDS in Table 3.10-4, determine the parameter λ.
Table 3.10-4 Data for Example 3.10-3.
ID (µA) 39.2 68.2 86.8 94.2 95.7 97.2 98.8 100.3VDS (V) 0.500 1.000 1.500 2.000 2.50 3.00 3.50 4.00
SolutionWe note that the data of Table 3.10-4 covers both the saturation and nonsaturationregions of operation. A quick check shows that saturation is reached near VDS = 2.0 V. Tocalculate λ, we shall use the data for VDS greater than or equal to 2.5 V. The parameters ofthe linear regression are
xiyi = 1277.85 ∑xi∑yi = 5096.00
∑x2i = 43.5 (∑xi)2 = 169These values result in m = λI'D = 3.08 and b = I'D = 88, giving λ = 0.035 V-1.The slope in the saturation region is typically very small, making it necessary to be carefulthat two data points taken with low resolution are not subtracted (to obtain the slope)resulting in a number that is of the same order of magnitude as the resolution of the datapoint measured. If this occurs, then the value obtained will have significant andunacceptable error.
Chapter 3 – Section 10 (5/2/04) Page 3.10-14
CMOS Analog Circuit Design © P.E. Allen - 2004
EXTRACTION OF THE SIMPLE MODEL FOR SHORT CHANNEL MOSFETSExtraction for Short Channel MOSFETS
The model proposed is the following one which is the square-law model modified bythe velocity saturation influence.
iD = K’
2[1 + θ(vGS-VT)] WL [ vGS - VT]2(1+λvDS)
Using the values of K’, VT , λ, and γ extracted previously, use an appropriate extractionprocedure to find the value of θ adjusting the values of K’, VT , and λ as needed.
Comments:
• We will assume that the bulk will be connected to the source or the standardrelationship between VT and VBS can be used.
• The saturation voltage is still given by
VDS( sat) = VGS - VT
Chapter 3 – Section 10 (5/2/04) Page 3.10-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Example of a Genetic Algorithm†
1.) To use this algorithm or any other, use the simulator and an appropriate short-channel model (BSIM3) to generate a set of data for the transconductance (iD vs. vGS)and output characteristics (iD vs. vDS) of the transistor with the desired W and Lvalues.
2.) The best fit to the data is found using a genetic algorithm. The constraints on theparameters are obtained from experience with prior transistor parameters and are:
10E-6 < β< 610E-6, 1 < θ < 5, 0 < VT < 1, and 0 < λ < 0.53,) The details of the genetic algorithm are:
Gene structure is A = [β, θ, VT, fitness]. A mutation was done by varying all fourparameters. A weighted sum of the least square errors of the data curves was used asthe error function. The fitness of a gene was chosen as 1/error.
4.) The results for an extraction run of 8000 iterations for an NMOS transistor is shownbelow.
β(A/V2) θ VT(V) λ(V-1)294.1x10-6 1.4564 0.4190 0.1437
5.) The results for a NMOS and PMOS transistor are shown on the following pages.
† Anurag Kaplish, “Parameter Optimization of Deep Submicron MOSFETS Using a Genetic Algorithm,” May 4, 2000, Special Project Report, School
of ECE, Georgia Tech.
Chapter 3 – Section 10 (5/2/04) Page 3.10-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Extraction Results for an NMOS Transistor with W = 0.32µm and L = 0.18µmTransconductance:
Chapter 3 – Section 10 (5/2/04) Page 3.10-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Extraction Results for an NMOS Transistor with W = 0.32µm and L = 0.18µmOutput:
Chapter 3 – Section 10 (5/2/04) Page 3.10-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Extraction Results for an PMOS Transistor with W = 0.32µm and L = 0.18µmTransconductance:
Chapter 3 – Section 10 (5/2/04) Page 3.10-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Extraction Results for an PMOS Transistor with W = 0.32µm and L = 0.18µmOutput:
Chapter 3 – Section 11 (5/2/04) Page 3.11-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SEC. 3.11 - SUMMARY• Model philosophy for analog IC design
Use simple models for design and sophisticated models for verification• Models have several parts
Large signal static (dc variables)Small signal static (midband gains, resistances)Small signal dynamic (frequency response, noise)Large signal dynamic (slew rate)
• In addition models may include:TemperatureNoiseProcess variations (Monte Carlo methods)
• Computer modelsMust be numerically efficientQuickly derived from new technology
• Analog Design “Tricks”Stay away from minimum channel length if possible
- Larger rds → larger gains- Better agreement
Don’t use the computer models for design, rather verification of design
Chapter 4 – Introduction (5/2/04) Page 4.0-1
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 4 – CMOS SUBCIRCUITSChapter Outline4.1 MOS Switch4.2 MOS Diode/Active Resistor4.3 Current Sinks and Sources4.4 Current Mirrors4.5 Current and Voltage References4.6 Bandgap Reference
GoalTo develop an understanding of the sub-blocks and subcircuits used in CMOS analog
circuit design.
Design Hierarchy
Blocks or circuits(Combination of primitives, independent)
Sub-blocks or subcircuits(A primitive, not independent)
Functional blocks or circuits(Perform a complex function)
Fig. 4.0-1
Chapter 4
Chapter 4 – Introduction (5/2/04) Page 4.0-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of Hierarchy in Analog Circuits for an Op Amp
Operational Amplifier
BiasingCircuits
InputDifferentialAmplifier
SecondGainStage
OutputStage
CurrentSource
CurrentMirrors
CurrentSink
CurrentMirror Load
Inverter CurrentSink Load
SourceFollower
CurrentSink Load
SourceCoupled Pair
Fig. 4.0-2
Chapter 4 – Section 1 (5/2/04) Page 4.1-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 4.1 - MOS SWITCHModel for a Switch• An ideal switch is a short-circuitwhen ON and an open-circuit whenOFF.
• Actual switch:VC = controlling terminal for the switch (VC high ⇒ switch ON, VC low ⇒ switch OFF)
ron = resistance of the switch when ON roff = resistance of the switch when OFF
VOS = offset voltage when the switch is ON Ioff = offset current when the switch is OFF
IA and IB are leakage currents to ground CA and CB are capacitances to ground
CAC and CBC = parasitic capacitors between the control terminal and switch terminals
CAC CBC
CA CBVC
IA
rOFF
IOFF
rON
CAB
VOS
A B
C IB
Fig. 4.1-1
Chapter 4 – Section 1 (5/2/04) Page 4.1-2
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Transistor as a SwitchBulk
A B
(S/D) (D/S)
C (G)
A B
Fig4.1-2
On Characteristics of a MOS SwitchAssume operation in active region (vDS < vGS - VT) and vDS small.
iD = µCoxW
L
(vGS - VT) - vDS
2 vDS ≈ µCoxW
L (vGS - VT)vDS
Thus, RON ≈ vDS
iD =
1µCoxW
L (vGS - VT)
OFF Characteristics of a MOS SwitchIf vGS < VT, then iD = IOFF = 0 when vDS ≈ 0V.If vDS > 0, then
ROFF ≈ 1
iDλ = 1
IOFFλ ≈ ∞
Chapter 4 – Section 1 (5/2/04) Page 4.1-3
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Switch Voltage RangesIf a MOS switch is used to connect two circuits that can have analog signal that vary
from 0 to 1V, what must be the value of the bulk and gate voltages for the switch to workproperly?
Circuit1
Circuit2
(0 to 1V)
(S/D)
(0 to 1V)
(D/S)
Bulk
GateFig.4.1-3
• To insure that the bulk-source and bulk-drain pn junctions are reverse biased, the bulkvoltage must be less than the minimum analog signal for a NMOS switch.
• To insure that the switch is on, the gate voltage must be greater than the maximumanalog signal plus the threshold for a NMOS switch.
Therefore:VBulk ≤ 0V
and VGate(on) > 1V + VT
Also, VGate(off) ≤ 0V
Unfortunately, the large value of reverse bias bulk voltage causes the threshold voltage toincrease.
Chapter 4 – Section 1 (5/2/04) Page 4.1-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Current-Voltage Characteristics of a NMOS SwitchThe following simulated output characteristics correspond to triode operation of theMOSFET.
-1V -0.5V 0V 0.5V 1V
100µA
50µA
0µA
-50µA
-100µA
VGS=1.0V
VGS=1.5V
VGS=2.0VVGS=5.0V
VGS=2.5VVGS=3.0VVGS=3.5VVGS=4.0VVGS=4.5V
Fig. 4.1-4vDS
iD
SPICE Input File:MOS Switch On CharacteristicsM1 1 2 0 3 MNMOS W=1U L=1U.MODEL MNMOS NMOS VTO=0.7, KP=110U,+LAMBDA=0.04, GAMMA=0.4 PHI=0.7VDS 1 0 DC 0.0
VGS 2 0 DC 0.0VBS 3 0 DC -5.0.DC VDS -1 1 0.1 VGS 1 5 0.5.PRINT DC ID(M1).PROBE.END
Chapter 4 – Section 1 (5/2/04) Page 4.1-5
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Switch ON Resistance as a Function of Gate-Source Voltage
1V 1.5V 2V 2.5V 3V 3.5V 4V 4.5V 5V
100kΩ
10kΩ
1kΩ
100Ω
10Ω
W/L = 1µm/1µm
W/L = 5µm/1µm
W/L = 10µm/1µm
W/L = 50µm/1µm
MO
SFE
ET
On
Res
ista
nce
VGS Fig. 4.1-5
SPICE Input File:MOS Switch On Resistance as a f(W/L)M1 1 2 0 0 MNMOS W=1U L=1UM2 1 2 0 0 MNMOS W=5U L=1UM3 1 2 0 0 MNMOS W=10U L=1UM4 1 2 0 0 MNMOS W=50U L=1U.MODEL MNMOS NMOS VTO=0.7, KP=110U,
+LAMBDA=0.04, GAMMA=0.4, PHI=0.7VDS 1 0 DC 0.001VVGS 2 0 DC 0.0.DC VGS 1 5 0.1.PRINT DC ID(M1) ID(M2) ID(M3)ID(M4).PROBE.END
Chapter 4 – Section 1 (5/2/04) Page 4.1-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of the ON Resistance on MOS SwitchesFinite ON Resistance:
ExampleInitially assume the capacitor is uncharged. If VGate(ON) is 5V and is high for 0.1µs,find the W/L of the MOSFET switch that will charge a capacitance of 10pF in five timeconstants.
SolutionThe time constant must be 100ns/5 = 20ns. Therefore RON must be less than20ns/10pF = 2kΩ. The ON resistance of the MOSFET (for small vDS) is
RON = 1
KN’(W/L)(VGS-VT) ⇒WL =
1RON·KN’(VGS-VT) =
12kΩ·110µA/V2·4.3
=1.06
Comments:• It is relatively easy to charge on-chip capacitors with minimum size switches.• Switch resistance is really not constant during switching and the problem is more
complex than above.
vin=2.5VVGateC
vC(0) = 0-+
vin>0C
vC -+
RON
Fig. 4.1-6
Chapter 4 – Section 1 (5/2/04) Page 4.1-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Including the Influence of the Varying On ResistanceGate-source Constant
gON(t) = K’W
L (vGS(t)-VT) -0.5vDS(t)
gON(aver.) = 1
rON(aver.) ≈ gON(0) + gON(∞)
2
= K’W2L (VGS-VT) -
K’WVDS(0)4L +
K’W2L (VGS-VT)
= K’W
L (VGS-VT) - K’WVDS(0)
4LGate-source Varying
VGS=5V
VGS=5V-vIN
VDS
ID t=0
t=∞
gON(0)
gON(∞)
Fig. 4.1-8vDS(0)vDS(∞)
VGate
C vC(0) = 0-
+
+
-vGS(t)
vIN
gON = K’W2L [VGS(0)-VT] -
K’WVDS(0)4L +
K’W2L [VGS(∞)-vIN-VT]
VGS=5V
VDS
ID t=0
t=∞
gON(0)
gON(∞)
Fig. 4.1-7vDS(0)vDS(∞)
Chapter 4 – Section 1 (5/2/04) Page 4.1-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 4.1-1 - Switch ON ResistanceAssume that at t = 0, the gate of the switch shown is
taken to 5V. Design the W/L value of the switch todischarge the C1 capacitor to within 1% of its initialcharge in 10ns. Use the MOSFET parameters of Table3.1-2.
SolutionNote that the source of the NMOS is on the right and is always at ground potential so
there is no bulk effect as long as the voltage across C1 is positive. The voltage across C1can be expressed as
vC1(t) = 5exp
-t
RONC1
At 10ns, vC1 is 5/100 or 0.05V. Therefore,
0.05=5exp
-10-8
RON10-11 = 5exp
-103
RON ⇒ exp(GON103)=100 ⇒ GON = ln(100)
103 =0.0046S
∴ 0.0046 = K’W
L (VGS-VT) - K’WVDS(0)
4L =
110x10-6·4.3-110x10-6·5
4WL = 356x10-6
WL
Thus, WL =
0.0046356x10-6 = 13.71 ≈ 14
+-+
5V-
0V
5V
C1 =10pF
C2 = 10pF
+ -0V
Fig.4.1-9
vout(t)
Chapter 4 – Section 1 (5/2/04) Page 4.1-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of the OFF State on MOS SwitchesThe OFF state influence is primarily in any current that flows from the terminals of theswitch to ground.An example might be:
vin vout
CH
+-RBulk
+
-vCH
Fig. 4.1-10
Typically, no problems occur unless capacitance voltages are held for a long time. Forexample,
vout(t) = vCH e-t/(RBulkCH)
If RBulk ≈ 109Ω and CH = 10pF, the time constant is 109·10-11 = 0.01seconds
Chapter 4 – Section 1 (5/2/04) Page 4.1-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of Parasitic CapacitancesThe parasitic capacitors have two influences:• Parasitics to ground at the switch terminals (CBD and CBS) add to the value of the
desired capacitors.This problem is solved by the use of stray-insensitive switched capacitor circuits
• Parasitics from gate to source and drain cause charge injection onto or off the desiredcapacitors.This problem can be minimized but not eliminated.
Model for studying charge injection:
1
VS
+
-
CLvCL VS
+
-
CLvCL
Cchannel
CGS0 CGD0
Rchannel
VS
+
-
CLvCL
Cchannel
CGS0 CGD0
Rchannel
2
Cchannel
2
1 1
Fig. 4.1-11
A simple switch circuit usefulfor studying charge injection.
A distributed model ofthe transistor switch.
A lumped model ofthe transistor switch.
Chapter 4 – Section 1 (5/2/04) Page 4.1-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Charge Injection (Clock feedthrough, Charge feedthrough)Charge injection is a complex analysis which is better suited for computer analysis.
Here we will attempt to develop an understanding sufficient to show ways of reducing theeffect of charge injection.What is Charge Injection?1.) When the voltages change across the gate-drainand gate-source capacitors, a current will flow
because i = C dvdt .
2.) When the switch is off, charge injection willappear on the external capacitors (CL) connected tothe switch terminals causing their voltages to change.
There are two cases of charge injection depending upon the transition rate when theswitch turns off.1.) Slow transition time.2.) Fast transition time.
Fig. 4.1-12
Chapter 4 – Section 1 (5/2/04) Page 4.1-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Slow Transition TimeConsider the following switch circuit:
vin+VT
Switch ONA
B
C
CLvin
Fig. 4.1-13
vin+VTSwitch OFF
A
B
C
CLvin
Chargeinjection
1.) During the on-to-off transition time from A to B, the charge injection is absorbed bythe low impedance source, vin.
2.) The switch turns off when the gate voltage is vin+VT (point B).
3.) From B to C the switch is off but the gate voltage is changing. As a result chargeinjection occurs to CL.
Chapter 4 – Section 1 (5/2/04) Page 4.1-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Fast Transition TimeFor the fast transition time, the rate of transition is faster than the channel time constantso that some of the charge during the region from point A to point B is injected onto CLeven though the transistor switch has not yet turned off.
vin+VT
Switch ONA
B
C
CLvin
Fig. 4.1-14
vin+VTSwitch OFF
A
B
C
CLvin
Chargeinjection
Chargeinjection
Chapter 4 – Section 1 (5/2/04) Page 4.1-14
CMOS Analog Circuit Design © P.E. Allen - 2004
A Quantized Model of Charge Injection†
Approximate the gate transition as a stair case and discretize in voltage as follows:
Voltage
vin+VT
vCL
vGATE
Discretized Gate Voltage
tSlow Transition
Voltage
vin+VT
vCL
vGATE
Discretized Gate Voltage
tFast Transition
Chargeinjectiondue to fasttransition
Fig 4.1-15
vin vin
The time constant of the channel, Rchannel·Cchannel, determines whether or not thecapacitance, CL, fully charges during each voltage step.
† B.J. Sheu and C. Hu, “Switched-Induced Error Voltage on A Switched Capacitor,” IEEE J. Solid-State Circuits, Vol. SC-19, No. 4, pp. 519-525,August 1984.
Chapter 4 – Section 1 (5/2/04) Page 4.1-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Analytical Expressions to Approximate Charge InjectionAssume the gate voltage is making a transition from high, VH, to low, VL.∴ vGate = vG(t) = VH - Ut
where U = magnitude of the slope of vG(t)
Define VHT = VH - VS - VT and β = K’W
L .
The error in voltage across CL, Verror, is given below in two terms. The first termcorrsponds to the feedthrough that occurs while the switch is still on and the second termcorresponds to feedthrough when the switch is off.
1.) Slow transition occurs when βV
2HT
2CL >> U.
Verror = -
W·CGD0 + Cchannel
2CL
πUCL2β -
W·CGD0CL (VS+2VT -VL)
2.) Fast transition occurs when βV
2HT
2CL << U.
Verror = -
W·CGD0 + Cchannel
2CL
VHT - βV
3HT
6U·CL - W·CGD0
CL (VS+2VT -VL)
Chapter 4 – Section 1 (5/2/04) Page 4.1-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Expression for Feedthrough when the Switch is OFFThe model for this case is given as:
Fig. 4.1-16
VS +VTSwitch OFF
A
B
C
CLvin ≈VS ≈VD
Chargeinjection
COLCOL
VS +VT
COL
CL
+
-
vCL
VL
VS
VT
VLCircuit at theinstant gate
reaches VS +VT
The switch decrease from B to C is modeled as a negative step of magnitude VS +VT - VL.
The output voltage on the capacitor after opening the switch is,
vCL =
CL
COL+CL VS-
COL
COL+CL VT -(VS+VT -VL)
COL
COL+CL ≈ VS-(VS+2VT -VL)
COL
CL
if COL < CL.
Therefore, the error voltage is
Verror ≈ -(VS + 2VT - VL)
COL
CL = -(vin + 2VT - VL)
COL
CL
Chapter 4 – Section 1 (5/2/04) Page 4.1-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 4.1-2 - Calculation of Charge Feedthrough ErrorCalculate the effect of charge feedthroughon the previous circuit where VS = 1V, CL= 200fF, W/L = 0.8µm/0.8µm, and VG isgiven below for the two cases. Use modelparameters from Tables 3.1-2 and 3.2-1.Neglect ∆L and ∆W effects.SolutionCase 1:
The value of U is equal to 5V/0.2nS or 25x109. Next we must test to see if the slowor fast transition time is appropriate. First calculate the value of VT as
VT = VT0 + γ 2|φF| -VBS - γ 2|φF| = 0.7 + 0.4 0.7+1 - 0.4 0.7 = 0.887VTherefore,
VHT =VH-VS-VT = 5-1-0.887=3.113V ⇒ βV
2HT
2CL = 110x10-6·3.1132
2·200fF = 2.66x109 < 25x109
which corresponds to the fast transition case. Using the previous expression gives,Verror =
-
176x10-18+0.5(1.58x10-15)
200x10-15
3.113-3.32x10-3
30x10-3 - 176x10-18
200x10-15(1+1.774-0) = -16.94mV
vG
t0.2ns 10ns
5V
0V
Case 2
Case 1
Fig. 4.1-17
Chapter 4 – Section 1 (5/2/04) Page 4.1-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 4.1-2- ContinuedCase 2:
In this case U is equal to 5V/10ns or 5x108 which means that the slow transition caseis valid (5x108 < 2.66x109).Using the previous expression gives,
Verror = -
176x10-18+0.5(1.58x10-15)
200x10-15
314x10-6
220x10-6 -176x10-18
200x10-15(1+1.774-0) = -8.21mV
Comment:These results are not expected to give precise answers regarding the amount of
charge feedthrough one should expect in an actual circuit. Rather, they are a guide tounderstand the effects of various circuit elements and terminal conditions in order tominimize unwanted behavior by design techniques.
Chapter 4 – Section 1 (5/2/04) Page 4.1-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Solutions to Charge Injection1.) Use minimum size switches to reduce the overlap capacitances and/or increaseCL.
2.) Use a dummy compensating transistor.
φ1 φ1
M1 MD
W1L1
WDLD
= W12L1
Fig. 4.1-19
• Requires complementary clocks• Complete cancellation is difficult and may in fact may make the feedthrough worse
3.) Use complementary switches (transmission gates)4.) Use differential implementation of switched capacitor circuits (probably the best
solution)
Chapter 4 – Section 1 (5/2/04) Page 4.1-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Input-Dependent Charge InjectionExamination of the error voltage reveals that,
Error voltage = Component independent of input + Component dependent on inputThis only occurs for switches that are floating and is due to the fact that the inputinfluences the voltage at which the transistor switches (vin ≈ VS ≈ VD). Leads tospurious responses and other undesired results.Solution:
Use delayed clocks toremove the input-depend-ence by breaking thecurrent path for injectionfrom the floating switches.
Assume that Cs is chargedto Vin (both φ1 and φ1dare high):1.) φ1 opens, no input-dependent feedthrough because switch terminals (S3) are atground potential.2.) φ1d opens, no feedthrough occurs because there is no current path (except throughsmall parasitic capacitors).
Ci
φ1
φ2φ1d
φ2
C sVin
LC
VoutS1S2 S3
S4
φ1
φ2
φ1d
Clock Delay
t
t
t
Fig. 4.1-20
Chapter 4 – Section 1 (5/2/04) Page 4.1-21
CMOS Analog Circuit Design © P.E. Allen - 2004
CMOS Switches (Transmission Gate)
VDD
Clock
Clock
A B
Fig. 4.1-21
BAClock
Clock
Advantages:• Feedthrough somewhat diminished• Larger dynamic range• Lower ON resistanceDisadvantages:• Requires a complementary clock• Requires more area
Chapter 4 – Section 1 (5/2/04) Page 4.1-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 4.1-3 - Charge Injection for a CMOS SwitchCalculate the effect of charge feedthrough on thecircuit shown below. Assume that U = 5V/50ns =108V/s, vin = 2.5V and ignore the bulk effect. Usethe model parameters from Tables 3.1-2 and 3.2-1.SolutionFirst we must identify the transition behavior. Forthe NMOS transistor we have
βNV 2
HTN2CL =
110x10-6·(5-2.5-0.7)2
2·10-12 = 1.78x108
For the PMOS transistor, noting thatVHTP = VS - |VTP| - VL = 2.5-0.7-0 = 1.8
we haveβPV
2HTP
2CL = 50x10-6·(1.8)2
2·10-12 = 8.10x107 . Thus, the NMOS transistor is in the
slow transition and the PMOS transistor is in the fast transition regimes.Error due to NMOS:
Verror(NMOS) = -
176x10-18 + 0.5(1.58x10-15)
10-12 π·108·10-12
2·110x10-6 - 176x10-18
10-12 (2.5+1.4-0)
= -1.840mV
vin
M2
M1
0.8µm0.8µm
0.8µm0.8µm
+
-
vCL
CL =1pF
5V
0Vvin-|VTP|
5V
0Vvin+VTN
Fig. 4.1-18
Chapter 4 – Section 1 (5/2/04) Page 4.1-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 4.1-3 - ContinuedError due to PMOS:
Verror(PMOS) =
176x10-18+0.5(1.58x10-15)
10-12
1.8-50x10-6(1.8)3
6·108·10-12 +176x10-18
10-12 (5+1.4-2.5)
= 1.956mVNet error voltage due to charge injection is 116µV. This will vary with VS.
Chapter 4 – Section 1 (5/2/04) Page 4.1-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Dynamic Range of the CMOS SwitchThe dynamic range of a switch is therange of voltages at the switchterminals (VA≈VB=VA,B) over whichthe ON resistance stays reasonablysmall.
VDD
A B
VDD
M1
M21µAVA,B
Fig. 4.1-22
Spice File:Simulation CMOS transmission switch resistanceM1 1 3 2 0 MNMOS L=1U W=10UM2 1 0 2 3 MPMOS L=1U W=10U.MODEL MNMOS NMOS VTO=0.7, KP=110U,+LAMBDA=0.04, GAMMA=0.4, PHI=0.7.MODEL MPMOS PMOS VTO=-0.7, KP=50U,+ LAMBDA=0.05, GAMMA=0.5, PHI=0.8
VDD 3 0VAB 1 0IA 2 0 DC 1U.DC VAB 0 3 0.02 VDD 1 3 0.5.PRINT DC V(1,2).END
Result: Low ON resistance over a wide voltage range is difficult as the power supply decreases.
0
10kΩ
0V 0.5V 1V 1.5V 2V 2.5V 3V
8kΩ
6kΩ
4kΩ
2kΩ
VDD=1V
VDD=1.5V
VDD=2V
VDD=2.5VVDD=3V
VDD=1V
VDD=1.5V
VDD=2V
Switc
h O
n R
esis
tanc
e
VA,B (Common mode voltage) Fig. 4.1-22A
Chapter 4 – Section 1 (5/2/04) Page 4.1-25
CMOS Analog Circuit Design © P.E. Allen - 2004
CMOS Switch with Twin-Well Switching
VDD
VSS
M1
M2
M3
M4 M5
AnalogSignalInput
Analog Signal Output
VControl
VControl
Circuit when VControl is in its high state. Circuit when VControl is in its low state.
M1
M2
High State
Low State
Analog Signal Output
AnalogSignalInput
M1
M2
High State
Low State
Analog Signal Output
AnalogSignalInput
VDD
VSS
Chapter 4 – Section 1 (5/2/04) Page 4.1-26
CMOS Analog Circuit Design © P.E. Allen - 2004
Charge Pumps for Switches with Low Power Supply VoltagesAs power supply voltages decrease below 3V, it becomes difficult to keep the switch
on at a low value of on-resistance over the range of the power supply. Consequently,charge pumps are used.
Charge pump circuit:
0V
3.3V
C1 C2
VDD = 3.3V
Vsub_hi
CL
0V
0V
Vhi
To a single NMOS switch
M1
(Prevents latchup)
≈ 5V
Vhi = 2VDD·C2
Cgate,NMOS switch + C2 + CL
Chapter 4 – Section 1 (5/2/04) Page 4.1-27
CMOS Analog Circuit Design © P.E. Allen - 2004
Charge Pump - ContinuedHigh voltage generator for the well of M1:
C1 C23.3V
0V
Vsub_hi
6.6V
CStorageCBulk
VDD=3.3V
Fig. 4.1-225
Prevents latch-up of M1 by providing a high bulk bias (6.6V).
Use a separate clock driver for each switch to avoid crosstalk through the gate clocklines. Area for layout can be small.
Chapter 4 – Section 1 (5/2/04) Page 4.1-28
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation of the Charge Pump Circuit†
Circuit:VDD
C1
VSS
M1 CLK_out
CLK_in
M2M3
M4
Fig. 4.1-23
CLK_outM5
M6
C1
Simulation:3.0
2.0
1.0
0.0
-1.00.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
Vol
ts
Time (µs)
Input
Output
Fig. 4.1-24
† T.B. Cho and R.R. Gray, “A 10b, 20 Msample/s, 35mW Pipeline A/D Converter,” IEEE J. of Solid-State Circuits, Vol. 30, No. 3m March 1995, pp.166-172.
Chapter 4 – Section 1 (5/2/04) Page 4.1-29
CMOS Analog Circuit Design © P.E. Allen - 2004
Bootstrapped Switches with High Reliability†
In the previous charge pump switch driver, the amount of gate-source drive dependsupon the input signal and can easily causereliability problems because it becomes too largefor low values of input signal.
The solution to this problem is a →bootstrapped switch as shown.
Actual bootstrap switch:VDD
φ
φ
φ
φ
C1 C2C3
M1 M2 M3 M4
M5
M12
M8
M13
M9
M7 M10
M11S D
VDD
vg
vg
t
Input Signal
Boosted Clock
VDD
Fig. 4.1-26
φ low: M7 and M10 make vg=0 and C3 charges to VDD, φ high: C3 connected to vGS11.M7 reduces the vDS and vGS of M10 when φ = 0. M13 ensures that vGS8 ≤ VDD.The parasitics at the source of M11 require this node to be driven from a low impedance. † A.M. Abo and P.R. Gray, “A 1.5V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, IEEE J. of Solid-State Circuits, Vol. 34, No. 5,May 1999, pp. 599-605.
VDD
OFF ON Fig. 4.1-25
Chapter 4 – Section 1 (5/2/04) Page 4.1-30
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of MOSFET Switches
• Symmetrical switching characteristics• High OFF resistance• Moderate ON resistance (OK for most applications)• Clock feedthrough is proportional to size of switch (W) and inversely proportional to
switching capacitors.• Output offset due to clock feedthrough has 2 components:
Input dependentInput independent
• Complementary switches help increase dynamic range.• Fully differential operation should minimize the clock feedthrough.• As power supply reduces, switches become more difficult to fully turn on.• Switches contribute a kT/C noise which can get folded back into the baseband.
Chapter 4 – Section 2 (5/2/04) Page 4.2-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 4.2 - MOS DIODE/ACTIVE RESISTOR
MOS Diode
When the MOSFET has the gate connected to the drain, it acts like a diode withcharacteristics similar to a pn-junction diode.
+
vGS = v
-
i
+
vSG = v
-i
VT
i
vFig. 4-2-1
Note that when the gate is connected to the drain of an enhancement MOSFET, theMOSFET is always in the saturation region.
vDS ≥ vGS - VT ⇒ vD - vS ≥ vG - vS - VT ⇒ vD - vG ≥ -VT ⇒ vDG ≥ -VT
Since VT is always greater than zero for an enhancement device, then vDG = 0 satisfiesthe conditions for saturation.• Works for NMOS or PMOS• Note that the drain could be VT less than the gate and still be in saturation
Chapter 4 – Section 2 (5/2/04) Page 4.2-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Large-Signal and Small-Signal Characteristics of the MOS DiodeLarge-Signal Characteristics:
Ignore channel modulation-
i = iD = K’W2L (vGS - VT)2 =
β2 (vGS - VT)2 and v = vGS = vDS = VT +
2iDβ
Small-Signal Characteristics:The small signal model is a linearization of the large signal model at an operating point.
iD = β2 (vGS-VT)2(1+λvDS) → ιd + ID =
β2 [vgs+(VGS-VT)]2[1+λ(vds+VDS)]
id+ID = β2 vgs2 + ββββ(VGS-VT)vgs +
ββββ2 (VGS-VT)2 +
β2 vgs2λvds + β(VGS-VT)vgsλvds
+ ββββ2 (VGS-VT)2λλλλvds +
β2 vgs2λVDS + β(VGS-VT)vgsλVDS +
ββββ2 (VGS-VT)2λλλλVDS
Assume that vgs < VGS-VT, vds < VDS and λ <<1. Therefore we write:
id+ID ≈ β(VGS-VT)vgs + β2 (VGS-VT)2λvds +
β2 (VGS-VT)2(1+λVDS)
∴ id = β(VGS-VT)vgs+β2 (VGS-VT)2λvds = gmvgs+gdsvds and ID =
β2 (VGS-VT)2(1+λVDS)
Chapter 4 – Section 2 (5/2/04) Page 4.2-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Application of the MOS DiodeDC resistor:
DC resistance = vi
Q
= VI
• Useful for biasing - creating current from voltageand vice versa
Small-Signal Load (AC resistance):
rds
G
S
gmvgsvgs
+
-gmbsvbs
vds
+
-
id
Fig. 4.2-4
B
vbs
+
-
G
S
B
D
G
S
B
D
S
D
AC resistance = vdsid =
1gm + gds ≈
1gm
where
gm = β(VGS-VT) = 2βID and gds ≈ β2 (VGS-VT)2λ = IDλ
VT
i
vFig. 4-2-2B
ID
VDS
AC Resistance
DC Resistance
Chapter 4 – Section 2 (5/2/04) Page 4.2-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of the Back Gate (Bulk)It can be shown that the small signal model for the MOSFET with the bulk not connectedto the source is,
rds
G
S
gmvgsvgs
+
-gmbsvbs
vds
+
-
id
Fig. 4.2-4
B
vbs
+
-
G
S
B
D
G
S
B
D
S
D
where
gmbs is defined as ∂ιD∂vBS
Q =
∂iD
∂vGS
∂vGS
∂vBS
Q
=
- ∂iD∂vT
∂vT
∂vBS
Q
gmbs = gmγ
2 2|φF| - VBS = ηgm
It is very useful to simplify the small signal model when possible. The following arereasonable guidelines for this simplification:
gm ≈ 10gmbs ≈ 100gds
Chapter 4 – Section 2 (5/2/04) Page 4.2-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 4.2-1 - Small-Signal Load ResistanceFind the small signal resistance of the MOS diodeshown using the parameters of Table 3.2-1.Assume that the W/L ratio is 10µm/1µm.Solution
If we are going to include the bulk effect, we must first findthe dc value of the bulk-source voltage. Unfortunately, we do notknow the threshold voltage because the bulk-source voltage isunknown. The best approach is to ignore the bulk-source voltage,find the gate-source voltage and then iterate if necessary.
∴ VGS = 2Iβ + VT0 =
2·100110·10 + 0.7 = 1.126V
Thus let us guess at a gate-source voltage of 1.3V (to account for the bulk effect) andcalculate the resulting gate-source voltage.
VT = VT0+γ 2|φF|-(-3.7)-γ 2|φF| = 0.7+0.4 0.7+3.7-0.4 0.7 = 1.20V ⇒ VGS = 1.63V
Now refine our guess at VGS as 1.6V and repeat the above to get VT = 1.175V whichgives VGS = 1.60V.
Therefore, VBS = -3.4V.
VDD = 5V
100µA
rac
Fig. 4.2-5
Chapter 4 – Section 2 (5/2/04) Page 4.2-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 4.2-1 - ContinuedThe small signal model for this example is shown.The ac input resistance is found by,
iac = gdsvac - gmvgs - gmbsvbs= gdsvac + gmvs + gmbsvs = vac(gm+gmbs+gds)
∴ rac = vaciac =
1gm+gmbs+gds
Now we must find the parameters which are,
gm = 2βID = 2·110·10·100 µS = 469µS, gds = 0.04V-1·100µA = 4µS,
and gmbs = 469µS·0.42 0.7+3.4 = 0.0987·469µS = 46.33µS
Finally, rac = 106
469 + 46.33 + 4 = 1926Ω
If we had used the previous approximations of gm ≈ 10gmbs ≈ 100gds, then we could havesimply let
rac ≈ 1/gm = 1/469µS = 2132Ω
Probably the most important result of this approximation is that we would not have tofind VBS which took a lot of effort for little return.
rds
G,D,B
S
gmvgs gmbsvbsvds = vgs
+
-
id
Fig. 4.2-6
rac
vac
iac
Chapter 4 – Section 2 (5/2/04) Page 4.2-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Applications of the MOS Diode for Biasing1.) Deriving a bias voltage from power supply.
ID1 = ID2 ⇒ βN(VBias-VTN)2 = βP(VDD-VBias-|VTP|)2
Solving for VBias gives
VBias = VTN +
βPβN (VDD-|VTP|)
1 + βPβN
and ID = βN(VBias-VTN)2
Use the ratio of βP/βN to design VBias and the value of βN to designthe current ID.
2.) Deriving a bias voltage from a bias current.VBias = VGS1+ VGS2
= 2IBiasβ1 + VT1 +
2IBiasβ2 + VT2
Design β1 and β2 to yield the desired value of VBias. Try to keep
the values of W/L as close to unity as possible to minimize area.
M2
M1
VBias
VDD
+
-
ID
Fig. 4.2-7
VBias
VDD
+
-
IBias
M2
M1
Fig. 4.2-8
Chapter 4 – Section 2 (5/2/04) Page 4.2-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Use of the MOSFET to Implement a Floating ResistorIn many applications, it is useful to implement a
resistance using a MOSFET. First, consider thesimple, single MOSFET implementation.
RAB = L
K’W(VGS - VT)
100µA
60µA
20µA
-20µA
-60µA
-100µA-1V -0.6V -0.2V 0.2V 0.6V 1V
VGS=2V
VGS=3V
VGS=4V
VGS=5V
VGS=10V
VGS=9V
VGS=8VVGS=7V
VGS=6V
Fig. 4.2-95
VBias
A B A B
Fig. 4.2-9
RAB
Chapter 4 – Section 2 (5/2/04) Page 4.2-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Cancellation of Second-Order Voltage Dependence – Parallel MOSFETsCircuit:
Assume both devices are non-saturated
iD1 = ß1
(vAB + VC - VT)vAB - vAB2
2
iD2 = ß2
(VC - VT)vAB - vAB2
2
iAB = iD1 + iD2 = ß
vAB2 + (VC - VT)vAB - vAB2
2 + (VC - VT)vAB - vAB2
2 iAB = 2ß(VC - VT)vAB
RAB = 1
2ß(VC - VT)
M1
M2
VC VC
A B A B
Fig. 4.2-10
RAB
+ -
vAB
iAB
+
-
+
-
IBias IBias
VDD VDD
iAB
+ -vAB
Chapter 4 – Section 2 (5/2/04) Page 4.2-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Parallel MOSFET PerformanceVoltage-Current Characteristic:
Vc=7V
VDS
0
I(VS
EN
SE
)
-2 -1 0 1 2
2mA
1mA
-1mA
-2mA
W=15u L=3uVBS=-5.0V
6V
5V
4V
3V
Fig. 4.1-11
SPICE Input File:NMOS parallel transistor realizationM1 2 1 0 5 MNMOS W=15U L=3UM2 2 4 0 5 MNMOS W=15U L=3U.MODEL MNMOS NMOS VTO=0.75, KP=25U,+LAMBDA=0.01, GAMMA=0.8 PHI=0.6VC 1 2E1 4 0 1 2 1.0VSENSE 10 2 DC 0
VDS 10 0VSS 5 0 DC -5.DC VDS -2.0 2.0 .2 VC 3 7 1.PRINT DC I(VSENSE).PROBE.END
Still have the influence of the bulk on the threshold voltage.
Chapter 4 – Section 2 (5/2/04) Page 4.2-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Double MOSFET Differential ResistorCancels the bulk effect.
+
-v1
v2
i1
i2
R
R
VSS
VSS
VC2
v1
v2
i1
i2
VC1
VC1
+
-v
v
iD1
iD2
iD3
iD4
M1
M2
M3
M4Fig. 4.2-12
iD1 = β [(VC1-v-VT)(v1-v) - 0.5(v1-v)2] iD2 = β [(VC2-v-VT)(v1-v) - 0.5(v1-v)2]iD3 = β [(VC2-v-VT)(v2-v) - 0.5(v2-v)2] iD4 = β [(VC1-v-VT)(v2-v) - 0.5(v2-v)2]i1 = iD1+iD3 = β [(VC1-v-VT)V1-v) - 0.5(v1-v)2 + (VC2-v-VT)(v2-v) - 0.5(v2-v)2]
i2 = iD2+iD4 = β [(VC2-v-VT)(v1-v) - 0.5(v1-v)2 + (VC1-v-VT)(v2-v) - 0.5(v2-v)2]
i1 - i2 = β [(VC1-v-VT)(v1-v) + (VC2-v-VT)(v2-v) + (VC2-v-VT)(v1-v) + (VC1-v-VT)(v2-v)]
= β [v1(VC1-VC2) + v2(VC2-VC1)] = β (VC1-VC2)(v1-v2)
Differential input resistance is
Rin = v1-v2
i1-i2 =
v1-v2
β (VC1-VC2)(v1-v2) = 1
β (VC1-VC2) , v1,v2 ≤ min(VC1-VT),(VC2-VT)
Chapter 4 – Section 2 (5/2/04) Page 4.2-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Double-MOSFET, Differential Resistor Performance
SPICE Input File:
Double MOSFET Differential Resistor RealizationM1 1 2 3 4 MNMOS1 W=3U L=3UM2 1 5 8 4 MNMOS1 W=3U L=3UM3 6 5 3 4 MNMOS1 W=3U L=3UM4 6 2 8 4 MNMOS1 W=3U L=3UVSENSE 3 8 DC 0VC1 2 0 DC 7VVC2 5 0VSS 4 0 DC -5VV12 1 6.MODEL MNMOS1 NMOS VTO=0.75 KP=25U+LAMBDA=0.01 GAMMA=0.8 PHI=0.6.DC V12 -3 3 0.2 VC2 2 6 1.PRINT DC I(VSENSE)).PROBE.END
Comments:• Good linearity and tunability.• Can be used as a multiplier.
V1-V2
-3 -2 -1 0 1 2
VC2 = 6V
5V
4V
3V
2V
VBC =-5VV3 =0V
VC1 =7V
I(VS
EN
SE
)
150uA
100uA
50uA
0
50uA-
100uA-
150uA-
Chapter 4 – Section 2 (5/2/04) Page 4.2-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Active Resistor Realizations
AC ResistanceRealization
Linearity HowControlled
Restrictions
Single MOSFET Poor VGS orW/L
vBULK < Min (vS, vD)
Parallel MOSFET Good VC or W/L v ≤ (VC - VT)
Double-MOSFET,differential resistor
VeryGood
VC1 - VC2
orW/L
v1, v2 < min(VC1-VT,VC2-VT)vBULK < min(v1,v2)
Transresistance only
Chapter 4 – Section 3 (5/2/04) Page 4.3-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 4.3 - CURRENT SINKS AND SOURCES
Characterization of MOS Sinks and SourcesA sink/source is characterized by two quantities:• rout - a measure of the “flatness” of the current sink/source (its independence of
voltage)• VMIN - the min. across the sink or source for which the current is no longer constant
CMOS Current Sink:
VDD
VGG
iOUT
vOUT
+
-
VMINVGG
VGG-VT00
0
Slope = 1/rout
iOUT
vOUTVDD
Fig. 4.3-1
rout = 1
diD/dvDS = 1+λVDS
λΙD ≈ 1
λIDand
VMIN = VDS(sat) = VGS - VT0 = VGG - VT0
Chapter 4 – Section 3 (5/2/04) Page 4.3-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Simple MOS Current Source
VDD
VGG
iOUTvOUT
+
-
VMINVGG
VGG+|VT0|0
0
Slope = 1/rout
iOUT
vOUTVDD
Fig. 280-02
VDD-VGG
This current source only works when vOUT ≤ VGG + |VT0|
Chapter 4 – Section 3 (5/2/04) Page 4.3-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Gate-Source Voltage ComponentsIt is important to note that the gate-source voltage consists of two parts as illustratedbelow:
Fig. 280-03VT
ID
VGSvGS
iD
00
EnhanceChannel
W/L10W/L 0.1W/L
ProvideCurrent
VGS = VT0 + VON = Part to enhance the channel + Part to cause current flow
where VON = VDS(sat) = VGS - VT0
∴ VMIN = VON = VDS(sat) = 2ID
K’(W/L) for the simple current sink.
Note that VMIN can be reduced by using large values of W/L.
Chapter 4 – Section 3 (5/2/04) Page 4.3-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation of a Simple MOS Current Sink
0
20
40
60
80
100
120
0 1 2 3 4 5
i OU
T (
µA
)
vOUT (Volts)
Slope = 1/Rout
Vmin
VGS1 =1.126V
iOUT
vOUT
+
-
10µm1µm
Comments:VMIN is too large - desire VMIN to approach zero, at least approach VCE(sat)
Slope too high - desire the characteristic to be flat implying very large output resistance
(KN’ = 110µA/V2, VT = 0.7Vand λ = 0.04V-1) ⇒ rds = 250kΩ
Chapter 4 – Section 3 (5/2/04) Page 4.3-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Increasing the Output Resistance of a Current Sink/SourcePrinciple:
In order to increase the output resistance, use negative series feedback because,rout (with feedback) = rout(without feedback) x [1 + Loop gain]
Circuit:How does it work?1.) Assume iout increases.2.) As a result, vS increases.3.) Since the gate is held constant at VGG, then vGS decreases.4.) The decrease in vGS causes iOUT to decrease opposing the
original increaseLoop Gain?
iOUT’ = gmvS = gmRiOUT
∴ Loop gain = iOUT’iOUT = gmR
rout(w.fb.) = rout(w/o fb.)x [1+gmR] = rds(1+gmR)
If gmR >>1, then rout(w. fb.) ≈ gmrdsR
VGG R
iOUT
+
vOUT
-Fig. 280-08
++
-
-vS
vGSM2
iOUT
+
vOUT
-
Fig. 280-09
iOUT'
M2
VGG R
+
-
vS
iOUTM2'
Chapter 4 – Section 3 (5/2/04) Page 4.3-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Increasing the Output Resistance of a Simple MOS Current SinkSmall signal model for calculating theoutput resistance for the cascodecurrent sink:
Loop equation:vout = (iout-gm2vgs2-gmbs2vbs2)rds2
+ ioutR
= iout(rds2+R) - gm2rds2vgs2 - gmbs2rds2vbs2But,
vgs2 = 0 - vs2 = -ioutR and vbs2 = 0 - vs2 = -ioutR
Therefore,vout = iout[rds2 + R + gm2rds2R + gmbs2rds2R]
or
rout = voutiout = rds2 + R + gm2rds2R + gmbs2rds2R ≈ gm2rds2R = µ2R (µ = gmrds)
A general principle emerges:The output resistance of a cascode circuit ≈ R x (Common source voltage gain of thecascoding transistor)
VGGR
iOUT
+
vOUT
-
rds2
R
iout
+
vout
-
gmvgs2 gmbsvbs2
M2
+
-
vs2
Fig. 280-10
vg2 = vb2 = 0
Chapter 4 – Section 3 (5/2/04) Page 4.3-7
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Cascode Current Sink
+
vOUT
-
iOUT
M2
M1VGG2
VGG1
rds2
iout
+
vout
-
gm2vgs2 gmbs2vbs2
+
-
vs2
Fig. 280-11vgs1 =vg2 = vb2 = 0
gm1vgs1 rds1
Small signal output resistance:Noting that vgs1 = vg2 = vb2 = 0 and writing a loop equation we get,
vout = (iout - gm2vgs2 - gmbs2vbs2)rds2 + rds1ioutHowever,
vgs2 = 0 - vs2 = -ioutrds1 and vbs2 = 0 - vs2 = -ioutrds1Therefore,
vout = iout[rds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2]or
rout = voutiout = rds1 + rds2 + gm2rds1rds2 + gmbs2rds1rds2 ≈ gm2rds1rds2 = µ2rds1
Comments:1.) Same as before if R = rds1 2.) Bulk effects have little influence.
Chapter 4 – Section 3 (5/2/04) Page 4.3-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation of the Cascode CMOS Current Sink
ExampleUse the model parameters
KN’=110µA/V2, VT = 0.7 and λN =0.04V-1 to calculate (a) the small-signal output resistance for the simplecurrent sink if IOUT = 100µA and (b)the small-signal output resistance forthe cascode current sink with IOUT =100µA. Assume that all W/L valuesare 1.
Solution
(a) Using λ = 0.04 V-1 and IOUT = 100µA gives rds1 = 250kΩ = rds2. (b) Ignoring thebulk effect, we find that gm1 = gm2 = 469µS which gives rout = (250kΩ)(469µS)(250kΩ)= 29.32MΩ.
0
20
40
60
80
100
120
0 1 2 3 4 5
i OU
T (
µA
)
vOUT (Volts)
Slope = 1/Rout
Vmin
VGG1 =1.126V
iOUT
vOUT
+
-
VGG2 =1.552V
All W/Ls are10µm/1µm
Fig. 280-12
Chapter 4 – Section 3 (5/2/04) Page 4.3-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Gate-Source Matching PrincipleA. If the gate-source voltages of two or more transistors
are equal and the transistors are matched and operatingin the saturation region, then the currents are related bythe W/L ratios of the individual transistors. The gate-source voltages may be directly connected or implied.
iD1 = K’W12L1 (vGS1-VT1)2 → (vGS1-VT1)2 =
2K’iD1(W1/L1)
iD2 = K’W22L2 (vGS2-VT2)2 → (vGS2-VT2)2 =
2K’iD2(W2/L2)
If vGS1 = vGS2, then
W2
L2 iD1 =
W1
L1 iD2 or iD1 =
W1/L1
W2/L2 iD2
B. If the drain currents of two or more transistors are equal and the trans-istors are matched and operating in the saturation region, then the gate-source voltages are related by the W/L ratios (ignoring bulk effects).
If iD1 = iD2, then vGS1 = VT1 + W2/L2W1/L1 (vGS2 - VT2)
or
if W2/L2 = W1/L1, then vGS1 = vGS2 (Note: VDS1must equal VDS2 for ideal results)
+
-
vGS1
iD1M1
iD2M2
+
-
vGS2
W1L1
W2L2
Fig. 290-02
+
-vGS1
iD1
iD2M2
+
-vGS2
W1L1
W2L2
Fig. 290-03
Chapter 4 – Section 3 (5/2/04) Page 4.3-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Practical Cascode Current Sink ImplementationDoes not require any batteries and uses the gate-source matching principle.
VDD
IREF
+
vOUT
-
M4
M3
M2
M1
iOUT
-
+
-
+VT+VON
2VT+2VON
-
+
-
+
-
+vDS2
Fig. 4.3-10VT+2VON0vOUT
iOUT
VT+VON
VT+VON
VT+VON
However, VMIN is now equal to VT +VON + vDS2(min) = VT + VON + VON = VT + 2VONAssuming that IOUT = 100µA and W2/L2 = W1/L1 = 10 gives VON = 0.426V.
Thus VMIN = 0.7V + 2·0.426V = 1.55V (this is way too much)
Chapter 4 – Section 3 (5/2/04) Page 4.3-11
CMOS Analog Circuit Design © P.E. Allen - 2004
High-Swing Cascode Current Sink
Since
VON = 2ID
K’(W/L) ,then if L/W isquadrupled, thenVON is doubled.∴ VMIN = 2VON.
ExampleUse the cascode current sink configuration above to design a current sink of 100µA
and a VMIN = 1V. Assume the device parameters of Table 3.1-2.
SolutionWith VMIN = 1V, choose VON = 0.5V. Assuming M1 and M2 are identical gives
WL =
2·IOUT
K’·VON2 = 2·100x10-6
110x10-6x0.25 = 7.27 ⇒
W1L1 =
W2L2 =
W3L3 = 7.27 and
W4L4 = 1.82
+
-
M2
M1
1/1
1/1
M31/1
1/4
M4
VDD VDD
IREF IREFiOUT
vOUT
+
-VON
+
-VON
+
-
VT+2VON
VT+VON+
-
VT+VON+
-
2VON0 vOUT
iOUT
VMIN
Fig. 290-04
Chapter 4 – Section 3 (5/2/04) Page 4.3-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Improved High-Swing Cascode Current SinkBecause the drain-source voltages ofthe matching transistors, M1 and M3are not equal, iOUT ≠ IREF.
To circumvent this problem the cascodecurrent sink shown is utilized:
Note that the drain-source voltage ofM1 and M3 are identical causing iOUTto be a replication of IREF.
Design Procedure1.) Since VMIN = 2VON = 2VDS(sat), let VON = 0.5VMIN.
2.) VON = 2IREF
K’(W/L) ⇒W1L1 =
W2L2 =
W3L3 =
W5L5 =
2IREF
K’VON2 = 8IREF
K’VMIN2
3.) W4L4 =
2IREF
K’(VGS4-VT)2 =
2IREF
K’(2VON)2 =
IREF
2K’VON2
+
-
M2
M1
1/1
1/1
M3
1/1
1/4
M4
VDD VDD
IREF IREFiOUT
vOUT
+
-
VON
+
-
VON
+
-
VT+2VON
VT+VON+
-
VT+VON+
-+
-
VON
M5
1/1
-
Fig. 290-05
+
-
VT
Chapter 4 – Section 3 (5/2/04) Page 4.3-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Signal Flow in TransistorsThe last example brings up an interesting and important point. This point is illustrated
by the following question, “How does IREF flow into the M3-M5 combination oftransistors since there is no path to the gate of M5?”Consider how signals flow in transistors:
D
G
S
+-
+
+
++
C
B
E
+-
+
+
++
Fig. 4.3-12B
Output Only
InputOnly
Output Only
InputOnly
Answer to the above question:As VDD increases (i.e. the circuit begins to operate),
IREF cannot flow into the drain of M5, so it flows throughthe path indicated by the arrow to the gate of M3. Itcharges the stray capacitance and causes the gate-sourcevoltage of M3 to increase to the exact value necessary tocause IREF to flow through the M3-M5 combination.
M3
VDD
+
-
IREF
M5
Fig. 4.3-12A
VT +2VON
VGS3
Chapter 4 – Section 3 (5/2/04) Page 4.3-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 4.3-1 - Design of a Minimum VMIN Current SinkAssume IREF = 100µA and design a cascode current sink with a VMIN = 0.3V using thefollowing parameters: VTO=0.7, KP=110U, LAMBDA=0.04, GAMMA=0.4, PHI=0.7
SolutionFrom the previous equations, we get
W1L1 =
W2L2 =
W3L3 =
W5L5 =
8IREFK’VMIN 2
= 8·100
110·(0.3V)2 = 80.8 and
W4L4 =
IREF2K’VON 2
= 100
2·110·0.152 = 20.2
Simulation Results:Low Vmin Cascade Current Sink - Method No. 2M1 5 1 0 0 MNMOS W=81U L=1UM2 2 3 5 5 MNMOS W=81U L=1UM3 4 1 0 0 MNMOS W=81U L=1UM4 3 3 0 0 MNMOS W=20U L=1UM5 1 3 4 4 MNMOS W=81U L=1U.MODEL MNMOS NMOS VTO=0.7 KP=110U+LAMBDA=0.04 GAMMA=0.4 PHI=0.7VDD 6 0 DC 5VIIN1 6 1 DC 100UIIN2 6 3 DC 100UVOUT 2 0 DC 5.0.OP.DC VOUT 5 0 0.05.PRINT DC ID(M2)
.END
0
20
40
60
80
100
120
0 1 2 3 4 5vOUT(V)
i OU
T(µ
A)
VMIN
Fig. 290-06
Chapter 4 – Section 3 (5/2/04) Page 4.3-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Self-Biased Cascode Current Sink†
The VT + 2VON bias voltage is developed through a seriesresistor.
Design procedure:Same as the previous except
R = VONIREF =
VMIN2IREF
For the previous example,
R = 0.3V
2·100µA = 1.5kΩ
Observation:Note that the last several slides have been devoted to just getting the MOS cascode
current sink/source to have the same minimum voltage as the BJT!
† T.L. Brooks and A.L. Westwick, “A Low-Power Differential CMOS Bandgap Reference,” Proc. of IEEE Inter. Solid-State Circuits Conf., Feb.1994, pp. 248-249.
IREF
VDD
VT+2VON
R
iOU
M1 M2
M3 M4+
-VT
+
-
VON
+
-
VON
+
-
VONVT+VON
Fig. 290-0
Chapter 4 – Section 3 (5/2/04) Page 4.3-16
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Regulated Cascode Sink†
vOUT
VDD
M1 M2
M3
M4
M5M6M7
IREF
iOUT
VO1
+
-
IREF
IREF
Fig. 290-08
A
Increasing vGS3VGS3(max)
VGS3(norm)
VDS3(sat)vDS3
VDS3(min)
iD3
Comments:• Achieves very high output resistance by increasing the loop gain due to the M4-M5inverting amplifier.
Loop gain = gm3rds2
gm4
gds4+gds5 ≈
gm3rds2gm4rds42 if rds4 ≈ rds5 ∴ rout ≈
rds3gm3rds2gm4rds42
• M3 maintains “constant” current even though it is no longer in the saturation region.Assume an iOUT increase → vS3 increase → vGS4 increase→ vG3 decrease → Large decrease in vGS3 → Large decrease in iOUT
† E. Sackinger and W. Guggenbuhl, “A Versatile Building Block: The CMOS Differential Difference Amplifier,” IEEE J. of Solid-State Circuits, vol.SC-22, no. 2, pp. 287-294, April 1987.
Chapter 4 – Section 3 (5/2/04) Page 4.3-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Regulated Cascode Current Sink - ContinuedSmall signal model:
Solving for the output resistance:iout = gm3vgs3 + gds3(vout-vgs4)
Butvgs4 = ioutrds2
andvgs3 = vg3 - vs3 = -gm4(rds4||rds5)vgs4 - vgs4 = -rds2[1 + gm4(rds4||rds5)]iout
∴ iout = -gm3rds2[1 + gm4(rds4||rds5)]iout + gds3vout - gds3rds2ioutvout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||rds5)]iout
∴ rout = voutiout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(rds4||rds5)]
≈ rds3gm3rds2gm4(rds4||rds5)
If IREF = 100µA, all W/Ls are 10µm/1µm we get rds = 0.25MΩ and gm = 469µS whichgives
rout ≈ (0.25MΩ)(469µS)(0.25MΩ)(469µS)(0.125MΩ) = 1.72GΩ
gm4vgs4
gm3vgs3
rds4rds5 rds2rds3
vgs4
vgs3G3=D4=D5
D2=S3=G4
+
-
+ -D3
S2 = G2= S4
vout
+
-
iout
Fig. 290-09
Chapter 4 – Section 3 (5/2/04) Page 4.3-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Regulated Cascode Current Sink - ContinuedVMIN:
Without the use of the VO1 battery shown, VMIN is pretty bad. It is,
VMIN = VGS4 + VDS3(sat) = VT + 2VONMinimizing VMIN:
If VO1 = VT , then VMIN = 2VON. This is accomplished by the following circuit:
If VGS4A - VGS4B = VDS2(sat) = VON,
then VMIN = 2VON
∴2ID4
KN’(W4A/L4A) - 2IB
KN’(W4B/L4B) = 2IB+2IRE
KN’(W2/L
orID4
W4A/L4A - IB
W4B/L4B = IB+IREFW2/L2
A number of solutions exist. For example, let IB = IREF. This gives ID4A = 5.824IREFassuming all W/L ratios are identical.
VDDVDDVDD
M1 M2
M3
M4A M4B
+
-
vOUT
IBID4AIREF+IB
+ +
- -VGS4AVGS4B
+
-VDS2
+
-VDS2
IB
iOUT
IREF+IB
Fig. 290-10
Chapter 4 – Section 3 (5/2/04) Page 4.3-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 4.3-4 - Design of a Minimum VMIN Regulated Cascode Current SinkDesign a regulated cascode current sink for 100µA and minimum voltage of VMIN = 0.3V.SolutionLet the W/L ratios of M1 through M5 be equal and let IB = 10µA. Therefore,
VMIN = 0.3V = VON3 + VON2 = 2·100µA
110µA/V2(W/L) +2·110µA
110µA/V2(W/L)
= 2·100µA
110µA/V2(W/L)
1 + 1.1
Therefore,
0.3V = 2·100µA
110µA/V2(W/L)(2.049)
WL =
2·100µA·2.0492
110µA/V20.32 = 84.8 ≈ 85.
With IB = 10µA, then ID4A =
10 + 110 2 = 186µA
M1 M2
M3
M4A M4B
+
-
vOUT
iOUT
Fig. 290-11
110µA 186µA 10µA
10µA
110µA
85/1
85/185/1
85/185/1
+5V +5V +5V
Chapter 4 – Section 3 (5/2/04) Page 4.3-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Comparison of the MOS Cascode Current Sink and Regulated Cascode CurrentSinkClose examination in the knee area reveals interesting differences.Simulation results:
80
85
90
95
100
105
110
0 0.1 0.2 0.3 0.4 0.5vOUT (V)
i OU
T (µ
A)
MOS Cascode
RegulatedMOS Cascode
Fig. 290-12
BJT Cascode
Comments: • The regulated cascode current is smaller than the cascode current because the drain-
source voltages of M1 and M2 are not equal. • The regulated cascode current sink has a smaller VMIN due to the fact that M3 can
have a drain-source voltage smaller than VDS(sat).
Chapter 4 – Section 3 (5/2/04) Page 4.3-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Current Sinks and Sources
Current Sink/Source rOUT VMINSimple MOS Current Sink
rds = 1λΙD VDS(sat) =
VONSimple BJT Current Sink
ro = VAΙC
VCE(sat)≈ 0.2V
Cascode MOS ≈ gm2rds2rds1 VT + 2VONCascode BJT ≈ βFro 2VCE(sat)Minimum VMIN Cascode CurrentSink
≈ gm2rds2rds1 2VON
Regulated Cascode Current Sink* ≈ rds3gm3rds2gm4(rds4||rds5) ≈ VT +VONMinimum VMIN RegulatedCascode Current Sink*
≈ rds3gm3rds2gm4(rds4||rds5) ≈VON
* Unfortunately, the regulated cascode current sink has a dominant pole in the feedbackloop which can cause a pole-zero doublet which leads to a combination of fast and slowtime constants. For this reason, the regulated cascode circuit should only be used inbiasing applications unless the impact of this dynamic is understood.
Chapter 4 – Section 4 (5/2/04) Page 4.4-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 4.4 - CURRENT MIRRORS
Characterization of Current MirrorsA current mirror is basically nothing more than a current amplifier. The idealcharacteristics of a current amplifier are:
• Output current linearly related to the input current, iout = Aiiin• Input resistance is zero• Output resistance is infinity
Also, the characteristic VMIN applies not only to the output but also the input.
• VMIN(in) is the range of vin over which the input resistance is not small
• VMIN(out) is the range of vout over which the output resistance is not large
Graphically:
CurrentMirror
+
-vin
iin+
-vout
iout
vin
iin
VMIN (in)
Slope= 1/Rin
iin vout
iout
VMIN (out)
Slope = 1/Rout
iout
1Ai
Fig. 300-01Input Characteristics Transfer Characteristics Output Characteristics
Therefore, Rout, Rin, VMIN(out), VMIN(in), and Ai will characterize the current mirror.
Chapter 4 – Section 4 (5/2/04) Page 4.4-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Simple MOS Current Mirror
M1 M2
iI iO
+
-
vDS1
+
-
vDS2
Fig. 300-02
+-vGS-
Assume that vDS2 > vGS - VT2, then
iOiI =
L1W2
W1L2
VGS-VT2
VGS-VT12
1 + λvDS2
1 + λvDS1
K2’
K1’
If the transistors are matched, then K1’ = K2’ and VT1 = VT2 to give,
iOiI =
L1W2
W1L2
1 + λvDS2
1 + λvDS1
If vDS1 = vDS2, then
iOiI =
L1W2
W1L2
Therefore the sources of error are 1.) vDS1≠ vDS2 and 2.) M1 and M2 are not matched.
Chapter 4 – Section 4 (5/2/04) Page 4.4-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of the Channel Modulation Parameter, λλλλIf the transistors are matched and the W/L ratios are equal, then
iOiI =
1 + λvDS21 + λvDS1
if the channel modulation parameter is the same for both transistors (L1 = L2).
Ratio error (%) versus drain voltage difference:
Note that one could use this effect tomeasure λ.
Measure VDS1,VDS2, iI and iO andsolve the above equation for the channelmodulation parameter, λ.
4.0
8.0
5.0
6.0
7.0
0.0
3.0
2.0
1.0
0.0 5.0 vDS2 - vDS1 (volts)
λ = 0.01
1.0 2.0
λ = 0.015
λ = 0.02
Ratio Error vDS2 - vDS1 (volts)
v DS2
v DS1
1 11
100
+ +−
×λ λ
%R
atio
Err
or
vDS1 = 2.0 volt
Fig. 300-033.0 4.0
Chapter 4 – Section 4 (5/2/04) Page 4.4-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of Mismatched TransistorsAssume that vDS1 = vDS2 and that K1’ ≠ K2’ and VT1 ≠ VT2. Therefore we have
iOiI =
K2’(vGS - VT2)2
K1’(vGS - VT1)2
How do you analyze the mismatch? Use plus and minus worst case approach. Define ∆K’ = K’2-K’1 and K’ = 0.5(K2’+K1’) ⇒ K1’= K’-0.5∆K’ and K2’= K’+0.5∆K’
∆VT = VT2-VT1 and VT = 0.5(VT1+VT2) ⇒ VT1 =VT -0.5∆VT and VT2=VT+0.5∆VTSubstituting these terms into the above equation gives,
iOiI =
(K’+0.5∆K’)(vGS - VT - 0.5∆VT )2
(K’-0.5∆K’)(vGS - VT + 0.5∆VT)2 =
1 + ∆K’2K’
1 - ∆VT
2(vGS-VT)2
1 - ∆K’2K’
1 + ∆VT
2(vGS-VT)2
Assuming that the terms added to or subtracted from “1” are smaller than unity givesiOiI ≈
1 + ∆K’2K’
1 + ∆K’2K’
1 - ∆VT
2(vGS-VT)2
1 - ∆VT
2(vGS-VT)2
≈ 1 + ∆K’K’ -
2∆VT(vGS-VT)
Assume ∆K’/K’ = ±5% and ∆VT/(vGS-VT) = ±10%.
∴ iO/iI ≈ 1 ± 0.05 ±(-0.20) = 1 ± (0.25) ⇒ ±15% error if tolerances are correlated.
Chapter 4 – Section 4 (5/2/04) Page 4.4-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of the Offset Voltage Error Influence
Assume that VT1 = 0.7V and K’W/L = 110µA/V2.
8.0
16.0
10.0
12.0
14.0
0.0
6.0
4.0
2.0
0.0 10
∆VT (mV)
1.0 2.0
i O i i
100
×%
Rat
io E
rror
1−
iI = 1µA
3.0 4.0 5.0 6.0 7.0 8.0 9.0
iI = 3µA
iI = 5µA
iI = 10µA
iI = 100µA
Fig. 300-4
Key: Make the part of VGS causing the current to flow, VON, more significant than VT.
Chapter 4 – Section 4 (5/2/04) Page 4.4-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of Error in Aspect Ratio of the TransistorsExample 1 - Aspect Ratio Errors in Current MirrorsFigure 4.4-4 shows the layout of a one-to-four current amplifier. Assume that the lengthsare identical (L1 = L2) and find the ratio error if W1 = 5 ± 0.1 µm. The actual widths of thetwo transistors are
W1 = 5 ± 0.1 µm and W2 = 20 ± 0.1 µmiO
M1 M2
+
-
+
-
+
-
VDS1VDS2
iI
VGS
M1M2iO iI
GND
Fig. 300-5
SolutionWe note that the tolerance is not multiplied by the nominal gain factor of 4. The ratio ofW2 to W1 and consequently the gain of the current amplifier is
iOiI =
W2W1
= 20 ± 0.15 ± 0.1 = 4
1 ± (0.1/20)
1 ± (0.1/5) ≈ 4
1 ± 0.120
1 -±0.1
5 ≈ 4
1 ± 0.120 -
±0.420 = 4 - (±0.03)
where we have assumed that the variations would both have the same sign (correlated). Itis seen that this ratio error is 0.75% of the desired current ratio or gain.
Chapter 4 – Section 4 (5/2/04) Page 4.4-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of Error in Aspect Ratio of the Transistors-ContinuedExample 2 - Reduction of the Aspect Ratio Errors in Current MirrorsUse the layout technique illustrated in Fig. 4.4-5 and calculate the ratio error of a currentamplifier having the specifications of the previous example.SolutionsThe actual widths of M1 and M2 are
W1 = 5 ± 0.1 µm and W2 = 4(5 ± 0.1) µm
The ratio of W2 to W1 and consequently the current gain is given below and is for allpractical purposes independent of layout error.
iOiI =
4(5 ± 0.1)5 ± 0.1 = 4
M1M2bM2a M2dM2c iO
M1 M2
iI
iI
GND
GND
iO
Fig. 300-6
Chapter 4 – Section 4 (5/2/04) Page 4.4-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of the Simple MOS Current Mirror/Amplifier• Minimum input voltage is VMIN(in) = VT+VON
Okay, but could be reduced to VON.
Principle:
M1M2
VTiI iO
VT+VON+-
+
-VON
M1 M2VT
Fig. 300-7
iI iO
VT+VON
+
-
+
-
VON
Ib
IbIb
VDD
Ib
M3 M4
M5 M6 M7
Will deal with later in low voltage op amps.• Minimum output voltage is VMIN(out) = VON
• Output resistance is Rout = 1
λID
• Input resistance is Rin ≈ 1
gm• Current gain accuracy is poor because vDS1 ≠ vDS2
Chapter 4 – Section 4 (5/2/04) Page 4.4-9
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Cascode Current MirrorImproving the output resistance:
iI iO
M3
M1 M2
M4
Fig. 310-018
gm3v3 rds3
+
-
v3
gm1v1 rds1
+
-
v1
D3=G3=G4
S3=G2
D1=G1
S1
gm4vgs4rds4
rds2
D4
S4
D2
S2gm2vgs2
+
-
viniin
+
-
vout iout
• Rout:
vout = rds4(iout-gm4vgs4) + rds2(iout-gm2vgs2)But, iin = 0 so that v1 = v3 = 0 ⇒ vgs4 = -vs4 = -ioutrds2 and vgs2 = 0∴ vout = iout[rds4 + rds2 + gm4rds2rds4] ≈ rds2gm4rds4
• Rin:
Rin = 1
gm3 ||rds3 + 1
gm1 ||rds1 ≈ 1
gm1 + 1
gm3 ≈ 2
gm• VMIN(out) = VT + 2VON• VMIN(in) = 2(VT +VON)
• Current gain match: Excellent since vDS1 = vDS2
Chapter 4 – Section 4 (5/2/04) Page 4.4-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Large Output Swing Cascode Current Mirror
M2
M1M3
1/4
M4
VDD
IREF II IO
M5
Fig. 310-02
ii
1/1
1/1
1/1
1/1
gm5vgs5rds5
gm3vgs3 rds3
+
-
vs5
D5=G3
D3=S5
S3=G5
+
-
viniin
= gm3vin
VDD VDD
io
• Rout ≈ gm2rds2rds1• Rin = ?vin = rds5(iin-gm5vgs5)+vs5 = rds5(iin +gm5vs5)+vs5 = rds5iin+(1+gm5rds5)vs5
But, vs5 = rds3(iin - gm3vin)
∴ vin = rds5iin + (1+gm5rds5)rds3iin - gm3rds3(1+gm5rds5)vin
Rin = viniin =
rds5 + rds3 + rds3gm5rds5 gm3rds3(1+gm5rds5) ≈
1gm3
• VMIN(out) = 2VON• VMIN(in) = VT + VON• Current gain is excellent because vDS1 = vDS3.
Chapter 4 – Section 4 (5/2/04) Page 4.4-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Self-Biased Cascode Current Mirror
• Rin = ?
vin = iinR + rds3(iin-gm3vgs3)
+ rds1(iin-gm1vgs1)
But,vgs1 = vin-iinR
andvgs3 = vin-rds1(iin-gm1vgs1) = vin-rds1iin+gm1rds1(vin-iinR)
∴ vin = iinR+rds3iin-gm3rds3[vin-rds1iin+gm1rds1(vin-iinR)]+rds1[iin-gm1(vin+iinR)]
vin[1+gm3rds3+gm1rds1gm3rds3+gm1rds1]
= iin[R+rds1+rds3+gm3rds3rds1+ gm1rds1gm3rds3R]
Rin = R + rds1 + rds3 + gm3rds3rds1 + gm1rds1gm3rds3R
1 + gm3rds3 + gm1rds1gm3rds3 + gm1rds1 ≈ 1
gm1 + R
• Rout ≈ gm4rds4rds2• VMIN(in) = VT + 2VON •VMIN(out) = 2VON • Current gain matching is excellent
VDD VDD
I1 I2iin iout
R
M1 M2
M3 M4
gm3vgs3
rds3
R
gm1vgs1 rds1
+
-
vin
+
-
v2v1
+
-
+
-
vin
Small-signal model to calculate Rin.Self-biased, cascode current mirrorFig. 310-03
iin
Chapter 4 – Section 4 (5/2/04) Page 4.4-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Wilson MOS Current Mirror
iI iOM3
M2M1
gm3vgs3 rds3
gm2vgs2 rds2gm1vgs1 rds1
+
-
vout
iout
Fig. 310-09
+ -vgs3+
-
vgs2=vgs1
+
-
vin
iin
Uses negative series feedback to achieve higher output resistance.
• Rout = ? (iin=0) vout = rds2(iout - gm3vgs3) + vgs2
vgs2 = iout
gm2+gds2 = rds2iout
1+gm2rds2 and vgs3 = -gm1rds1vgs2 - vgs2= -(1+gm1rds1)vgs2
∴ vout = rds2iout + gm3rds2(1+gm1rds1)vgs2 = iout
rds3+rds21+gm3rds2+gm1rds1gm3rds3
1 + gm2rds2
Rout = rds3+rds2
1+gm3rds2+gm1rds1gm3rds3
1 + gm2rds2 ≈ gm1rds1gm3rds3
gm2
Chapter 4 – Section 4 (5/2/04) Page 4.4-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Wilson Current Mirror - Continued• Rin = ? (vout = 0)
iin ≈ gm1vgs1 = gm1gm3vgs3
gm2+gds2+gds3 ≈ gm1gm3vgs3
gm2
vgs3 = vin - vgs1= vin - gm1gm3vgs3
gm2 ⇒ vgs3 = vin
1 + gm1gm3
gm2
∴ iin ≈ gm1gm3 vingm2 +gm3 ⇒ Rin =
gm2 +gm3 gm1gm3
• VMIN(in) = 2(VT+VON)
• VMIN(out) = VT + 2VON• Current gain matching - poor, vDS1 ≠ vDS2
Chapter 4 – Section 4 (5/2/04) Page 4.4-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Evolution of the Regulated Cascode Current Mirror from the Wilson CurrentMirror
iI iOM3
M2
M1
Wilson Current Mirror Redrawn
iI iOM3
M2
M1
VBias2
Regulated Cascode Current Sink
Fig. 310-10
Chapter 4 – Section 4 (5/2/04) Page 4.4-15
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Regulated Cascode Current Mirror
IBiasIO
M3
M2
M1
ii
M4
FIG. 310-11
VDD
io
VDD
II
VDD
• Rout ≈ gm2rds3
• Rin ≈ 1
gm4
• VMIN(out) = VT+2VON (Can be reduced to 2VON)
• VMIN(in) = VT+VON (Can be reduced to VON)
• Current gain matching - good as long as vDS4 = vDS2
Chapter 4 – Section 4 (5/2/04) Page 4.4-16
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARYSummary of MOS Current Mirrors
CurrentMirror
Accuracy OutputResistance
InputResistance
MinimumOutputVoltage
MinimumInput
Voltage
Simple Poor rds 1gm
VON VT+VON
Cascode Excellent gmrds2 2gm
VT+2VON 2(VT+VON)
Wide OutputSwing
Cascode
Excellent gmrds2 1gm
2VON VT+VON
Self-biasedCascode
Excellent gmrds2 R + 1
gm2VON VT+2VON
Wilson Poor gmrds2 2gm
2(VT+VON) VT+2VON
RegulatedCascode
Good-Excellent
gm2rds3 1gm
VT+2VON(min. is2VON)
VT+VON(min. isVON)
Chapter 4 – Section 5 (5/2/04) Page 4.5-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 4.5 - CURRENT AND VOLTAGE REFERENCES
Characteristics of a Voltage or Current ReferenceWhat is a Voltage or Current Reference?
A voltage or current reference is an independent voltage or current source that has ahigh degree of precision and stability.Requirements of a Reference Circuit:• Should be independent of power supply• Should be independent of temperature• Should be independent of processing variations• Should be independent of noise and other interference
Reference
Noise
Temperature
Power Supply
NominalValue
Fig. 4.5-1
Chapter 4 – Section 5 (5/2/04) Page 4.5-2
CMOS Analog Circuit Design © P.E. Allen - 2004
REFERENCES WITH POWER SUPPLY INDEPENDENCEPower Supply IndependenceHow do you characterize power supply independence?Use the concept of:
SIREF
VDD =
∂IREF/IREF∂VDD/VDD
= VDDIREF
∂IREF
∂VDD
Application of sensitivity to determining power supply dependence:
∂IREFIREF =
SIREF
VDD ∂VDDVDD
Thus, the fractional change in the reference voltage is equal to the sensitivity times thefractional change in the power supply voltage.For example, if the sensitivity is 1, then a 10% change in VDD will cause a 10% change inIREF.
Ideally, we want SIREF
VDD to be zero for power supply independence.
Chapter 4 – Section 5 (5/2/04) Page 4.5-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Simple Current Reference
VDDVCC
RIIN
IOUTIC1 IB1 IB2Q1 Q2
RIIN
IOUTID1
M1 M2
Fig. 360-02
IOUT ≈ VCC-VBE
R
1
1+ 2βF
IOUT ≈ VDD-VGS
R = VDD -
2IINβ1 - VT
R
SIREF
VCC = 1 S
IREF
VDD = 1
Temperature and process dependence?
Chapter 4 – Section 5 (5/2/04) Page 4.5-4
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Widlar Current ReferenceOperation:
VGS1 – VGS2 – IOUTR2 = 0
IOUTR2 + VON2 – VON1 = 0
Assuming strong inversion and λ → 0,
IOUTR2 + 2IOUT
K'(W2/L2) – VON1 = 0
Solving for IOUT gives,
IOUT = -
2 K'(W2/L2) +
2 K'(W2/L2) + 4R2VON1
2R2
where VON1 = 2IIN
K'(W1/L1)
Differentiating IOUT with respect to VDD gives,1
2 IOUT dIOUTdVDD
= 1
2/(K' W2/L2)+ 4R2VON1 dVON1dVDD
, dVON1dVDD
= VON12IIN
dIIN
dVDD
∴ SIREF
VDD =S
IOUT
VDD =
VON1
VON22+4 IOUTR2VON1 S
IIN
VDD ≈
VON1
4VON12 SIIN
VDD = 0.5S
IIN
VDD
VDD
R1IIN
IOUTID1
M1 M2
Fig. 360-04
R2
Chapter 4 – Section 5 (5/2/04) Page 4.5-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 4.5-1For the MOS Widlar current reference, find IOUT if IIN = 100µA, R2 = 4kΩ, K’ =200µA/V2, and W2/L2 = W1/L1 = 25. Assume the temperature is 27°C and that n = 1.5.Find the sensitivity of IOUT with respect to VDD.
Solution
VON1 = 2IIN
K'(W1/L1) = 2·100
200·25 = 0.2V
IOUT = -
2200·25 +
2 200·25 + 4(0.004)0.2
20.004 µA = 5 µA ⇒ IOUT = 25µA
Note that VON2 = VON1 - IOUTR2 = 0.2-(25)(0.004) = 0.1V > 2nVt = 78mV so bothtransistors are in strong inversion.
For the sensitivity calculations, assume that VDD >> VGS1. Therefore IIN ≈ VDD/R1.
SIREF
VDD =
VON1
4VON22 SIIN
VDD ≈
VON1
4VON22 = 0.5
Therefore, a 10% variation in VDD causes a 5% variation in IOUT.
Chapter 4 – Section 5 (5/2/04) Page 4.5-6
CMOS Analog Circuit Design © P.E. Allen - 2004
MOS Peaking Current ReferenceStrong Inversion Operation: Circuit:
VGS1 – IINR – VGS2 = 0
VON2 = VON1 – IINR
IOUT = K'(W2/L2)
2 VON22
= K'(W2/L2)
2 (VON1 – IINR)2
where Transfer Characteristics:
VON1 = 2IIN
K'(W1/L1)
Weak Inversion Operation:
VGS2 – VT ≈ nVt ln
IIN
(W1/L1)IT – IINR
If the transistors are identical and VDS2 > 3VT,
IOUT = W1L1
IT exp
VGS2 – VT
nVt ≈ IIN exp
-IINR
nVt
VDD
IIN
IOUTR
M1 M2
Fig. 360-7
2 4 6 8 1000
0.2
0.4
0.6
0.8
1.0
IIN(µA)
IOUT(µA)
Fig. 360-8
1.2
1.4
1.6
Weak Inversion
Strong Inversion
Chapter 4 – Section 5 (5/2/04) Page 4.5-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Threshold Referenced Current ReferenceCircuit:
Operation:
IOUT = VGS1 R2
= VT +
2IINK'(W1/L1)
R2
≈ VT R2
if VT > VON1
The sensitivity of IOUT with respect to VDD is
SIOUT
VDD =
VON1
IOUTR2 S
IIN
VDD =
VON1
2VGS1 S
IIN
VDD
For example, if VT = 1V, VON1 = 0.1V and SIIN
VDD ≈ 1, then
SIOUT
VDD =
0.1
2·1.1 = 0.045
Therefore, if VDD changes by 10%, IREF or IOUT changes by 0.45%.
VDD
R1IIN
IOUT
ID1
M1
M2
Fig. 360-10
R2
Chapter 4 – Section 5 (5/2/04) Page 4.5-8
CMOS Analog Circuit Design © P.E. Allen - 2004
SIMPLE BIAS/REFERENCE CIRCUITSVoltage References using Voltage Division
M2
M1
VDDVDD
R1
R2
+
-
VREF
+
-
VREF
Resistor voltage divider. Active device voltage divider. Fig. 370-01
VREF = R2
R1+R2 VDD VREF = VTN + (βP/βN) (VDD-|VTP|)
1 + (βP/βN)
SVREF
VDD=1 S
VREF
VDD=
VDDVREF
(βP/βN)
1+ (βP/βN) = VDD (βP/βN)
VTN + (βP/βN) (VDD-|VTP|)
= VDD (βP/βN)
VTN + (βP/βN) (VDD-|VTP|)
Assume βN = βP and VTN = |VTP| ⇒ SVREF
VDD = 1
Chapter 4 – Section 5 (5/2/04) Page 4.5-9
CMOS Analog Circuit Design © P.E. Allen - 2004
References with Sensitivity Less than OneIn order to get sensitivities less than one, the upper and lower circuits must be differentwith the lower circuit less dependent on VDD.
In otherwords, the upper circuit should act like a current source and the lower circuit likea voltage source.
Principle:
VREF
VDD
IBias
Fig. 370-02
Chapter 4 – Section 5 (5/2/04) Page 4.5-10
CMOS Analog Circuit Design © P.E. Allen - 2004
MOSFET-Resistance Voltage References
vout
VDD
+
-
R
VREF
VDD
+
-
R
VREF
R1
R2
Fig. 370-03
VREF = VGS = VT + 2(VDD-VREF)
βR
or VREF = VT - 1βR +
2(VDD-VT)βR +
1(βR)2
SVREF
VDD =
1
1 + β(VREF-VT)R
VDD
VREF
Assume that VDD = 5V, W/L = 2 and R =100kΩ,
Thus, VREF ≈ 1.281V and SVDD
VREF = 0.283
This circuit allows VREF to be larger.
If the current in R1 (and R2) is smallcompared to the current flowingthrough the transistor, then
VREF ≈
R1 + R2
R2 VGS
Chapter 4 – Section 5 (5/2/04) Page 4.5-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Bipolar-Resistance Voltage References
vout
VCC
+
-
R
VREF
VCC
+
-
R
VREF
R1
R2
Fig. 370-04
VREF = VEB = kTq ln
I
Is
I = VCC − VEB
R ≅ VCCR
VREF ≅ kTq ln
VCC
RIs
SVREFVCC =
1ln[VCC/(RIs)] =
1ln(I/Is)
If VCC=5V, R = 4.3kΩ and Is = 1fA,then VREF = 0.719V.
Also, SVREF
VCC = 0.0362
If the current in R1 (and R2) is smallcompared to the current flowingthrough the transistor, then
VREF ≈
R1 + R2
R2 VEB
Chapter 4 – Section 5 (5/2/04) Page 4.5-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 1 - Design of a Higher-Voltage Bipolar Voltage ReferenceUse the circuit on the previous slide to design a voltage reference having VREF = 2.5Vwhen VCC = 5V. Assume Is = 1fA and βF = 100. Evaluate the sensitivity of VREF withrespect to VCC.
SolutionChoose I (the current flowing through R) to be 100µA.
Therefore R = VCC-VREF
100µA = 2.5V
100µA = 25kΩ.
Choose I1(the current flowing through R1) to be 50µA. Therefore the current flowing in
the emitter is 50µA. The value of VEB = Vt ln
50µA
1fA = 0.638V.
∴ R1 = 0.638V50µA = 12.76kΩ
With 50µA in the emitter, the base current is approximately 5µA. Therefore, the current through R2 is 55µA.
Since VREF = IR2R2 + 0.638V = 2.5V, we get R2 =
2.5V-0.638V
55µA = 33.85kΩ.The sensitivity of VREF with respect to VCC is
SVREF
VCC =
R1+ R2
R1S
VEB
VCC =
12.76kΩ+33.85kΩ
12.76kΩ
1
ln(IQ/Is) = 3.652(0.0406) = 0.148
Chapter 4 – Section 5 (5/2/04) Page 4.5-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Breakdown Diode Voltage ReferencesIf the power supply voltage is high enough, i.e. VDD ≈ 10V, the breakdown diode can beused as a voltage reference.
V-I characteristics of a breakdown diode.
i
vVBV VDD
VDD
R
IQ
i +
-
v
Q
Variation of the temperature coefficient of the breakdown diode as afunction of the breakdown voltage, BV.
2 4 6 8 10
1
2
3
4
5
6
-3
-2
-1
VBV
Tem
pera
ture
coe
ffic
ient
of
VB
V (
mV
/°C
)
Fig. 370-05
VDD
R
VREF = VBV
SVREFVDD =
∂VREF
∂VDD
VDD
VREF ≅
vref
vdd
VDD
VBV =
rZ
rZ + R
VDD
VBV
where rz is the small-signal impedance of the breakdown diode at IQ (30 to 100Ω).
Typical sensitivities are 0.02 to 0.05.Note that the temperature dependence could be zero if VB was a variable.
Chapter 4 – Section 5 (5/2/04) Page 4.5-14
CMOS Analog Circuit Design © P.E. Allen - 2004
BOOTSTRAPPED BIAS/REFERENCE CIRCUITSBootstrapped Current SourceSo far, none of the previous references except the base-emitter and threshold-referencedsources have shown very good independence from power supply. Let us now examine atechnique which does achieve the desired independence.Circuit:
i
v
IQ
VQ
RI2 =
WL
I1 = (VGS1 - VT)2
M2
+
-
M1
I5
M8
VGS1
M3M4
R
I6
M5
M6
I1 I2
Startup
VDD
VGS1M7
Fig. 370-06
Desiredoperatingpoint
Undesiredoperatingpoint
0V
K'N2RB
Principle:
If M3 = M4, then I1 ≈ I2. However, the M1-R loop gives VGS1 = VT1 + 2I1
KN’(W1/L1)
Solving these two equations gives I2 = VGS1
R = VT1R +
1
R 2I1
KN’(W1/L1)
The output current, Iout = I1 = I2 can be solved as Iout = VT1R +
1β1R2 +
1R
2VT1β1R +
1(β1R)2
Chapter 4 – Section 5 (5/2/04) Page 4.5-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation Results for the Bootstrapped Current Source
The current ID2 appears to be okay, why isID1 increasing?Apparently, the channel modulation on thecurrent mirror M3-M4 is large.At VDD = 5V, VSD3 = 2.83V and VSD4 =1.09V which gives ID3 = 1.067ID4≈ 107µANeed to cascode the upper current mirror.
SPICE Input File:Simple, Bootstrap Current ReferenceVDD 1 0 DC 5.0VSS 9 0 DC 0.0M1 5 7 9 9 N W=20U L=1UM2 3 5 7 9 N W=20U L=1UM3 5 3 1 1 P W=25U L=1UM4 3 3 1 1 P W=25U L=1UM5 9 3 1 1 P W=25U L=1UR 7 9 10KILOHMM8 6 6 9 9 N W=1U L=1UM7 6 6 5 9 N W=20U L=1U
RB 1 6 100KILOHM.OP.DC VDD 0 5 0.1.MODEL N NMOS VTO=0.7 KP=110UGAMMA=0.4 +PHI=0.7 LAMBDA=0.04.MODEL P PMOS VTO=-0.7 KP=50UGAMMA=0.57 +PHI=0.8 LAMBDA=0.05.PRINT DC ID(M1) ID(M2) ID(M5).PROBE.END
0 1 2 3 4 5VDD
120µA
100µA
80µA
60µA
40µA
20µA
0
ID1
ID2
Fig. 370-07
Chapter 4 – Section 5 (5/2/04) Page 4.5-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Cascoded Bootstrapped Current Source
SPICE Input File:Cascode, Bootstrap Current ReferenceVDD 1 0 DC 5.0VSS 9 0 DC 0.0M1 5 7 9 9 N W=20U L=1UM2 4 5 7 9 N W=20U L=1UM3 2 3 1 1 P W=25U L=1UM4 8 3 1 1 P W=25U L=1UM3C 5 4 2 1 P W=25U L=1UMC4 3 4 8 1 P W=25U L=1URON 3 4 4KILOHMM5 9 3 1 1 P W=25U L=1UR 7 9 10KILOHMM8 6 6 9 9 N W=1U L=1U
M7 6 6 5 9 N W=20U L=1URB 1 6 100KILOHM.OP.DC VDD 0 5 0.1.MODEL N NMOS VTO=0.7KP=110U GAMMA=0.4 PHI=0.7LAMBDA=0.04.MODEL P PMOS VTO=-0.7KP=50U GAMMA=0.57 PHI=0.8LAMBDA=0.05.PRINT DC ID(M1) ID(M2) ID(M5).PROBE.END
0 1 2 3 4 5VDD
120µA
100µA
80µA
60µA
40µA
20µA
0
ID1
ID2
Fig. 370-
M2
+
-
M1
I5
M8
VGS1
M3 M4
R
M5
I1 I2
Startup
VDD
M7
0V
RB
M3C MC4
MC5
RON
Chapter 4 – Section 5 (5/2/04) Page 4.5-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Base-Emitter Referenced Circuit
M2
+
-
+
-
M1
I5
M7
-
VEB1
VR
M3 M4
R
M5
I1
I2
Startup
Q1
VDD
Fig. 370-09
i2
i1
Desiredoperating
point
Undesiredoperating
point
i2=VTln(i1/Is)/R
i2=i1M6
Iout = I2 = VEB1
R
BJT can be a MOSFET in weak inversion.
Chapter 4 – Section 5 (5/2/04) Page 4.5-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Low Voltage Bootstrap MOS CircuitThe previous bootstrap circuits required at least 2 volts across the power supply beforeoperating.A low-voltage bootstrap circuit:
VSS
M3 M4
VDD
R
M1 M2
VT
VTI1
I2
VT+VON
VON
VR
VT+VON
VON
Fig. 4.5-8A
Without the batteries, VT, the minimum power supply is VT+2VON+VR.
With the batteries, VT, the minimum power supply is 2VON+VR ≈ 0.5V
Chapter 4 – Section 5 (5/2/04) Page 4.5-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Power-Supply Independent References• Reasonably good, simple references are possible• Best power supply sensitivity is approximately 0.01
(10% change in power supply causes a 0.1% change in reference)• Typical simple reference temperature dependence is ≈ 1000 ppm/°C• Can obtain zero temperature coefficient over a limited range of operation
Type of ReferenceSVREFVPP
Voltage division 1MOSFET-R <1BJT-R <<1ThresholdReferenced
<<1
Base-emitterReferenced
<<1
Chapter 4 – Section 5 (5/2/04) Page 4.5-20
CMOS Analog Circuit Design © P.E. Allen - 2004
REFERENCES WITH TEMPERATURE INDEPENDENCECharacterization of Temperature DependenceThe objective is to minimize the fractional temperature coefficient defined as,
TCF = 1
VREF
∂VREF
∂T = 1T S
VREF
T parts per million per °C or ppm/°C
Temperature dependence of PN junctions:
i ≈ Isexp
v
Vt
Is = KT3exp
-VGO
Vt
1Is
∂Is
∂T = ∂(ln Is)∂T =
3T +
VGOTVt ≈
VGOTVt
dvBEdT ≈
VBE - VGOT = -2mV/°C at room temperature
(VGO = 1.205 V at room temperature and is called the bandgap voltage)Temperature dependence of MOSFET in strong inversion:
dvGS
dT = dVTdT +
2LWCox
ddT
iD
µo
µo = KT-1.5
VT(T) = VT(To) - α(T-To)
dvGSdT ≈ -α ≈ -2.3
mV°C
Resistors:(1/R)(dR/dT) ppm/°C
Chapter 4 – Section 5 (5/2/04) Page 4.5-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Bipolar-Resistance Voltage ReferencesFrom previous work we know that,
VREF = kTq ln
VDD - VREF
RIs
However, not only is VREF a function of T, but R and Is are alsofunctions of T.
∴ dVREF
dT = kq ln
VDD-VREF
RIs +
kTq
RIs
VDD-VREF
-1
RIs dVREF
dT -
VDD-VREF
RIs
dR
RdT + dIs
IsdT
= VREF
T - Vt
VDD-VREF dVREF
dT - Vt
dR
RdT + dIs
IsdT = VREF-VGO
T - Vt
VDD-VREF dVREF
dT - 3Vt
T - Vt
R dRdT
∴dVREF
dT =
VREF-VGO
T - Vt dR
RdT - 3Vt
T
1 + Vt
VDD-VREF
≈ VREF-VGO
T - Vt dR
RdT - 3Vt
T
TCF = 1
VREF dVREF
dT = VREF-VGO
VREF·T - Vt
VREF dR
RdT - 3Vt
VREF·T
If VREF = 0.6V, Vt = 0.026V, and the R is polysilicon, then at 27°K the TCF is
TCF =0.6-1.2050.6·300 -
0.026·0.00150.6 -
3·0.0260.6·300 = 33110-6-65x10-6-433x10-6 =-3859ppm/°C
VDD
+
-
R
VREF
Fig. 380-1
Chapter 4 – Section 5 (5/2/04) Page 4.5-22
CMOS Analog Circuit Design © P.E. Allen - 2004
MOSFET Resistor Voltage ReferenceFrom previous results we know that
VREF = VGS = VT + 2(VDD-VREF)
βR
or VREF = VT - 1βR +
2(VDD-VT)βR +
1(βR)2
Note that VREF, VT, β, and R are all functions of temperature.
It can be shown that the TCF of this reference is
dVREFdT =
−α + VDD − VREF
2βR
1.5
T − 1R
dRdT
1 + 1
2βR (VDD − VREF)
∴ TCF = −α +
VDD − VREF2βR
1.5
T − 1R
dRdT
VREF(1 + 1
2βR (VDD − VREF))
VDD
+
-
R
VREF
Fig. 380-02
Chapter 4 – Section 5 (5/2/04) Page 4.5-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 4.5-1 - Calculation of MOSFET-Resistor Voltage Reference TCFCalculate the temperature coefficient of the MOSFET-Resistor voltage reference whereW/L=2, VDD=5V, R=100kΩ using the parameters of Table 3.1-2. The resistor, R, ispolysilicon and has a temperature coefficient of 1500 ppm/°C.Solution
First, calculate VREF . Note that βR = 220 × 10-6 × 105 = 22 and dR
RdT = 1500ppm/°C
∴ VREF = 0.7 − 1
22 + 2(5 − 0.7)
22 +
1
222 = 1.281V
Now, dVREF
dT = −2.3×10-3 +
5 − 1.2812 22
1.5
300 − 1500 × 10-6
1 + 1
2 22 (5 - 1.281)
= -1.189x10-3V/°C
The fractional temperature coefficient is given by
TCF = −1.189 × 10-3
1
1.281 = −928 ppm/°C
Chapter 4 – Section 5 (5/2/04) Page 4.5-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Bootstrapped Current Source/SinkGate-source referenced source:
The output current was given as, Iout = VT1R +
1β1R2 +
1R
2VT1β1R +
1(β1R)2
Although we could grind out the derivative of Iout with respect to T, the temperatureperformance of this circuit is not that good to spend the time to do so. Therefore, let usassume that VGS1 ≈ VT1 which gives
Iout ≈ VT1R ⇒
dIoutdT =
1R
dVT1dT -
1R2
dRdT
In the resistor is polysilicon, then
TCF = 1
Iout dIoutdT =
1VT1
dVT1dT -
1R
dRdT =
-αVT1
- 1R
dRdT =
-2.3x10-3
0.7 -1.5x10-3 = -4786ppm/°C
Base-emitter referenced source:
The output current was given as, Iout = I2 = VBE1
R
The TCF = 1
VBE1 dVBE1
dT - 1R
dRdT
If VBE1 = 0.6V and R is poly, then the TCF = 1
0.6 (-2x10-3) - 1.5x10-3 = -4833ppm/°C.
Chapter 4 – Section 5 (5/2/04) Page 4.5-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Technique to Make gm Dependent on a ResistorConsider the following circuit with all transistors having aW/L = 10. This is a bootstrapped reference which creates aVbias independent of VDD. The two key equations are:
I3 = I4 ⇒ I1 = I2and
VGS1 = VGS2 + I2RSolving for I2 gives:
I2 = VGS1-VGS2
R = 1R
2I1
ß1 -
2I2ß2
= 2I1
R ß1
1 - 12
∴ I2 = 1
R 2ß1 ⇒ I2 = I1 =
1
2ß1R2 = 1
2·110x10-6·10·25x106 = 18.18µA
Now, Vbias can be written as
Vbias=VGS1=2I2ß1
+VTN = 1
ß1R+VTN = 1
110x10-6·10·5x103 + 0.7 = 0.1818+0.7 = 0.8818V
Any transistor with VGS = Vbias will have a current flow that is given by 1/2ßR2.
Therefore, gm = 2Iß = 2ß
2ßR2 = 1R ⇒ gm =
1R
(This means that the temperature dependence of gm will be that of 1/R which can be usedto achieve temperature controlled performance.)
M3 M4
M1M2A
M2B M2C
M2D
R=5kΩ
VDD
+
-VBias
Fig. 4.5-11
Chapter 4 – Section 5 (5/2/04) Page 4.5-26
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Reference Performance
Type of ReferenceS
VREF
VDD
TCF Comments
MOSFET-R <1 >1000ppm/°CBJT-R <<1 >1000ppm/°CBreakdown Diode <<1 Can be very small BV too largeBootstrap Gate-Source Referenced
Good if currentsare matched
>1000ppm/°C Requires start-up circuit
Bootstrap Base-emitter Referenced
Good if currentsare matched
>1000ppm/°C Requires start-up circuit
• A MOSFET can have zero temperature dependence of iD for a certain vGS
• If one is careful, very good independence of power supply can be achieved• None of the above references have really good temperature independenceConsider the following example:
A 10 bit ADC has a reference voltage of 1V. The LSB is approximately 0.001V.Therefore, the voltage reference must be stable to within 0.1%. If a 100°C change intemperature is experienced, then the TCF must be 0.001%/C or multiplying by 104 gives aTCF = 10ppm/°C.
Chapter 4 – Section 6 (5/2/04) Page 4.6-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 4.6 - BANDGAP REFERENCESTemperature Stable References• The previous reference circuits failed to provide small values of temperature coefficientalthough sufficient power supply independence was achieved.• This lecture introduces the bandgap voltage concept combined with power supplyindependence to create a very stable voltage reference in regard to both temperature andpower supply variations.Bandgap Voltage Reference Principle
The principle of the bandgap voltage reference is to balance the negative temperaturecoefficient of a pn junction with the positive temperature coefficient of the thermalvoltage, Vt = kT/q.
Concept:
Result: References with TCF’sapproaching 10 ppm/°C.
VDD
Σ
-2mV/°CVBE
I1
VBE+
-
T
Vt =kTq K
KVt
+0.085mV/°C
T
Vt
VREF = VBE + KVt
Fig. 390-01
Chapter 4 – Section 6 (5/2/04) Page 4.6-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Derivation of the Temperature Coefficient of the Base-Emitter VoltageFor small TCF's the dependence VBE must be known more precisely than ≈ -2mV/°C.1.) Start with the collector current density, JC:
JC = q Dn npo
WB exp
VBE
Vt
where, JC = IC/Area = collector current density
Dn = average diffusion constant for electrons
WB = base widthVBE = base-emitter voltageVt = kT/q
k = Boltzmann's constant (1.38x10-23J/°K)T = Absolute temperature
npo = ni2/NA = equilibrium concentration of electrons in the base
ni2 = DT3 exp
-VGO
Vt = intrinsic concentration of carriers
D = temperature independent constantVGO = bandgap voltage of silicon (1.205V)
NA = acceptor impurity concentration
Chapter 4 – Section 6 (5/2/04) Page 4.6-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Derivation of the Temperature Coefficient of the Base-Emitter Voltage - Continued2.) Combine the above relationships into one:
JC = q Dn
NAWB DT3 exp
VBE - VGO
Vt = ATγ exp
VBE - VGO
Vt where, γ = 3
3.) The value of JC at a reference temperature of T = T0 is
JC0 = AT0γ exp
q
kT0 (VBE - VGO)
while the value of JC at a general temperature, T, is
JC = ATγ exp
q
kT (VBE - VGO)
4.) The ratio of JC/JC0 can be expressed as,JC
JC0 =
T
T0 γ exp
q
k
VBE - VG0
T - VBE0 - VG0
T0
or
ln
JC
JC0 = γ ln
T
T0 +
qkT
VBE - VGO - TT0
(VBE0 - VGO)
where VBE0 is the value of VBE at T = T0.5.) Solving for VBE from the above results gives,
VBE(T) = VGO
1 - TT0
+ VBE0
T
T0 +
γkTq ln
T0
T + kTq ln
JC
JC0
Chapter 4 – Section 6 (5/2/04) Page 4.6-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Derivation of the Temperature Coefficient of the Base-Emitter Voltage - Continued6.) Next, assume JC ∝ Tα and find ∂VBE/∂T.
∂VBE∂T =
∂VGO∂T
1-TT0
-VGOT0 +
VBE0T0 +
γkTq
∂ ln(T0/T)∂T +ln
T0
T ∂(γkT/q)
∂T +kTq
∂ln
JC
JC0∂Τ +
kq ln
JC
JC0
7.) Assume that T = T0 which means JC = JC0. Since, ∂VGO/∂T = 0,
∂VBE∂T
|T=T0 = -
VGOT0 +
VBE0T0 +
γkTq ·
∂ ln(T0/T)∂T +
kTq
∂ln(JC/JC0)
∂T
8.) Note that,
∂ln(T0/T)
∂T = TT0
∂(T0/T)∂T =
TT0
-T0
T2 = -1T and
∂ln(JC/JC0)∂Τ =
JC0JC
∂(JC/JC0)∂T =
JC0JC
α
T JCJC0 =
αT
Therefore,
∂VBE∂T |
T=T0= - VGOT0 +
VBE0T0 -
γkq +
αkq or
∂VBE∂T |
T=T0 = VBE0 - VGO
T0 + (α - γ)
k
q
Typical values of α and γ are 1 and 3.2. If VBE0 = 0.6V, then at room temperature:
∂VBE∂T
|T=T0 =
0.6-1.205300 + (1-3.2)
0.026
300 = 0.6-1.205-0.1092
300 = -1.826mV/°C
Chapter 4 – Section 6 (5/2/04) Page 4.6-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Derivation of the Temperature Coefficient of the Thermal Voltage (kT/q)1.) Consider two identical pn junctions having different current densities,
VDD VDD
IC1 IC2
AE1 AE2
+ -∆VBE
Q1 Q2
Fig. 390-02
∆VBE = VBE1- VBE2 = kTq ln
JC1
JC2
- Find ∂(∆VBE)/∂T,
∂ (∆VBE)
∂T = VtT ln
JC1
JC2 = kq ln
JC1
JC2
Chapter 4 – Section 6 (5/2/04) Page 4.6-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Derivation of the Gain, K, for the Bandgap Voltage Reference1.) In order to achieve a zero temperature coefficient at T = T0, the following equationmust be satisfied:
0 = ∂VBE
∂T |
T=T0 + K" ∂(∆VBE)∂Τ where K" is a constant that satisfies the equation.
2.) Therefore, we get
0 = K"
Vt0
T0 ln
JC1
JC2 +
VBE0 - VGO
T0 +
(α - γ)Vt0
T0
3.) Define K = K" ln
JC1
JC2 , therefore
0 = K
Vt0
T0 +
VBE0 - VGO
T0 +
(α - γ)Vt0
T0
4.) Solving for K gives K = VGO - VBE0 - Vt0(α-γ)
Vt0
Assuming that JC1/JC2 = AE1/AE2 = 10 and VBE0 = 0.6V gives,
K = 1.205 - 0.6 + (2.2)(0.026)
0.026 = 25.4695.) The output voltage of the bandgap voltage reference is found as,
VREF|
T=T0 = VBE0 + KVt0 = VBE0 + VGO - VBE0 + (γ-α)Vt0 or VREF = VGO + (γ-α)Vt0
For the previous values, VREF = 1.205 + 0.026(2.2) = 1.262V.
Chapter 4 – Section 6 (5/2/04) Page 4.6-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Variation of the Bandgap Reference Voltage with respect to TemperatureThe previous derivation is only valid at a given temperature, T0. As the temperature
changes away from T0, the value of ∂VREF/∂T is no longer zero.Illustration:
-60 -40 -20 0 20 40 60 80 100 120
1.240
1.250
1.260
1.270
1.280
1.290 ∂V = 0
V = 0
VREF = 0
T0 = 400°K
T0 = 300°K
T0 = 200°K
V (V)
T°C
Fig. 4.6-3
REF
REF
REF
∂T
∂∂T
∂∂T
Bandgap curvature correction will be necessary for low ppm/C bandgap references.
Chapter 4 – Section 6 (5/2/04) Page 4.6-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Classical Widlar Bandgap Voltage Reference†
Operation:VBE1 = VBE2 + I2R3
gives∆VBE = VBE1 - VBE2 = I2R3
But,
∆VBE = Vt ln
I1
Is1 - Vt ln
I2
Is2 = Vt ln
I1Is2
I2Is1
Assume VBE1 ≈ VBE3, we get I1R1 = I2R2
Therefore,
I2 = ∆VBE
R3 =
Vt
R3 ln
I1Is2
I2Is1 =
Vt
R3 ln
R2Is2
R1Is1
Now we can express VREF as
VREF = I2R2 + VBE3 = R2
R3 Vt ln
R2Is2
R1Is1 + VBE3 = KVt + VBE
Design R1, R2, Is1, and Is2 to get the desired K.Let K = 25 and Is2 = 10Is1 and design R1, R2, and R3. Choose R2 = 10R1 = 10kΩ.Therefore, ln(100) = 4.602. Therefore R2/R3 = 25/4.602 or R3 = R2/5.4287 = 1.842kΩ.
† R.J. Widlar, “New Developments in IC Voltage Regulators,” IEEE J. of Solid-State Circuits, Vol. SC-6, pp. 2-7, February 1971.
VREF
VCC
I1 I2
I
R2R1
R3
Q1 Q2
Q3
Q4
+
-
Fig. 390-04
Chapter 4 – Section 6 (5/2/04) Page 4.6-9
CMOS Analog Circuit Design © P.E. Allen - 2004
A CMOS Bandgap Reference using PNP Lateral BJTsBootstrapped Voltage Reference using PNP Laterals-
M1 M2
M3
VDD
VSS
R3
R4
R1
R2
VREF
+
-
Q1 Q2
IREFI1 I2
Fig. 390-05
I2 = VBE1 - VBE2
R2 =
Vt
R2
ln
I1
Is1 - ln
I2
Is2 =
Vt
R2 ln
Is2
Is1 =
Vt
R2 ln
AE2
AE1
if I1 = I2 which is forced by the current mirror consisting of M1 and M2.
∴ VREF = VBE1 + I1R1 = VBE1 +
R1
R2 ln
AE2
AE1 Vt = VBE1 + KVt
While an op amp could be used to make I1 = I2 it suffers from offset and noise and leads todeterioration of the bandgap temperature performance.VREF is with respect to VDD and therefore is susceptible to changes on VDD.
Chapter 4 – Section 6 (5/2/04) Page 4.6-10
CMOS Analog Circuit Design © P.E. Allen - 2004
A CMOS Bandgap Reference using Substrate PNP BJTs
Operation:The cascode mirror (M5-M8) keeps the currents
in Q1, Q2, and Q3 identical. Thus,
VBE1 = I2R + VBE2
or
I2 = VtR ln(n)
Therefore,VREF = VBE3 + I2(kR) = VBE3 + kVt·ln(n)
Use k and n to design the desired value of K (n isan integer greater than 1).
M1 M2
M7 M8
M5 M6
VDD
VSS
R
M3 M4
VREF
+
-Q1
I1
M9
M10
I2
kR
Q2 Q3x1 xn xn
Fig. 390-06
Chapter 4 – Section 6 (5/2/04) Page 4.6-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Weak Inversion Bandgap Voltage ReferenceCircuit:
Analysis:
For the p-channel transistors:
ID = IDO(W/L) exp
VBG
nVt
exp
-VBS
Vt - exp
-VBD
Vt
where Vt = kT/q.
If VBD >> Vt, then ID = IDO(W/L) exp
VBG
nVt -
VBS
Vt .
The various transistor currents can be expressed as:
ID1 = ID2 = IDO(W2/L2) exp
VBG2
nVt and ID3 = ID4 = IDO(W4/L4) exp
VBG4
nVt -
VBS4
Vt
Note that VBG2 = VBG4 and VBS4 = VR1.Therefore,
ID1
ID3 =
W2/L2
W4/L4 exp
VR1
Vt
where
VR1 = Vt ln
W1W4L2L3
L1L4W2W3 and IR1 =
VR1
R1
M1
M2
M3
M4
M6
R2
R1
Q5
VDD
VR1
+
-
VR2
+
-
+
-
VREF
ID1=ID2 ID3=ID4
ID6
Fig. 390-07
Chapter 4 – Section 6 (5/2/04) Page 4.6-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Weak Inversion Bandgap Voltage Reference - ContinuedThe reference voltage can be expressed as,
VREF = R2I6 + VBE5
However,
I6 = W6L3
L6W3 IR1 =
W6L3
L6W3 Vt
R1 ln
W1W4L2L3
L1L4W2W3 .
Substituting I6 and the previously derived expression for VBE(T) in VREF gives,
VREF = W6L3
L6W3 R2
R1 Vt ln
W1W4L2L3
L1L4W2W3 + VGO
1 - TT0 + VBE0
T
T0 + 3Vt ln
T0
T
To achieve ∂VREF/∂T = 0 at T = T0, we get∂VREF
∂T =
k
q
R2
R1
W6L3
L6W3 ln
W1W4L2L3
L1L4W2W3 -
VGO
T0 +
VBE0
T0 +
3kq
Therefore,
R2W6L3
R1L6W3 ln
W1W4L2L3
L1L4W2W3 =
qkT0
(VGO - VBE0) - 3
Under the above constraint, VREF has an ≈ zero TCF at T = T0 and has a value of
VREF = VGO + 3kTq
1 + ln
T0
T = VGO + 3kTq
Practical values of ∂VREF/∂T for the weak inversion bandgap are less than 100 ppm/°C.
Chapter 4 – Section 6 (5/2/04) Page 4.6-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Curvature Correction Techniques:
• Squared PTAT Correction:Temperature coefficient ≈ 1-20 ppm/°C
• VBE loop
M. Gunaway, et. al., “A Curvature-Corrected Low-Voltage BandgapReference,” IEEE Journal of Solid-StateCircuits, vol. 28, no. 6, pp. 667-670, June1993.
• ß compensationI. Lee et. al., “Exponential Curvature-Compensated BiCMOS BandgapReferences,” IEEE Journal of Solid-State Circuits, vol. 29, no. 11, pp. 1396-1403,Nov. 1994.
• Nonlinear cancellationG.M. Meijer et. al., “A New Curvature-Corrected Bandgap Reference,” IEEEJournal of Solid-State Circuits, vol. 17, no. 6, pp. 1139-1143, December 1982.
VBE VPTAT
VRef = VBE + VPTAT + VPTAT2
Temperature
Vol
tage
Fig. 400-01
VPTAT2
Chapter 4 – Section 6 (5/2/04) Page 4.6-14
CMOS Analog Circuit Design © P.E. Allen - 2004
VBE Loop Curvature Correction Technique
Circuit:Operation:
INL = VBE1-VBE2
R3 = VtR3 ln
Ic1A2
A1Ic2
= VtR3 ln
2IPTAT
INL+IConstantwhere
Iconstant = INL + IPTAT + IVBE
≈ INL + VtRx +
VBER2
(a quasi-temperature independent current subject to the TCF of the resistors)where
Vt = kT/q
Ic1 and Ic2 are the collector currents of Qn1 and Qn2, respectively
Rx = a resistor used to define IPTAT
∴ VREF =
VBER2 +
VtR3 ln
2IPTAT
INL + Iconstant + IPTAT R1
Temperature coefficient ≈ 3 ppm/°C with a total quiescent current of 95µA..
VDD VDD VDDIPTAT IPTAT
IPTAT
INL
IVBE+INL
IVBE
IConstantQn1x1
Qn2x2R2
R3 VREF
3-Output Current Mirror (IVBE+INL)
VDD
Fig. 400-02
R1
Chapter 4 – Section 6 (5/2/04) Page 4.6-15
CMOS Analog Circuit Design © P.E. Allen - 2004
ß Compensation Curvature Correction TechniqueCircuit: Operation:
VREF = VBE +
AT + BT
(1+ß) R ≈ VBE +
AT + BTß R
whereA and B are constantT = temperature
The temperature dependence of ß is
ß(T) ∝ e-1/T ⇒ ß(T) = Ce-1/T
∴ VREF = VBE(T) +
AT + BTe1/T
C
Not good for small values of Vin.
Vin ≥ VREF + Vsat. = VGO + Vsat. = 1.4V
I=AT I=BT
RVREF
Vin
BT1+ß
Fig. 400-03
Chapter 4 – Section 6 (5/2/04) Page 4.6-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Nonlinear Cancellation Curvature Correction TechniqueObjective: Eliminate nonlinear term from the BE.Result: 0.5 ppm/°C from -25°C to 85°C.Operation: From above, VREF = VPTAT + 4VBE(IPTAT) - 3VBE(IConstant)
Note that, IPTAT ⇒ Ic ∝ T 1 ⇒ α = 1and Iconstant ⇒ Ic ∝ T 0 ⇒ α = 0,Previously we found,
VBE(T) ≈ VGO - TT0 VGO-VBE(T0) -(γ -α)Vt ln
T
T0
so that
VBE(IPTAT) =VGO-TT0 VGO-VBE(T0) -(γ-1)Vt ln
T
T0
and
VBE(IConstant) =VGO - TT0 VGO -VBE(T0) -γVt ln
T
T0
Combining the above relationships gives, VREF(T) = VPTAT + VGO - (T/T0)[VGO - VBE(T0)] - [γ - 4] Vt ln (T/T0)
If γ ≈ 4, then VREF(T) ≈ VPTAT + VGO 1 - (T/T0) + VBE(T0)(T/T0)
Q1
Q2
Q3
Q4
Q5
Q6
Q7Q8
IPTAT
VPTAT R1R2
VBE
VREF
VCC
IConstantVREF
R2=
VREF
VPTATR1
VBE
IPTAT
VCC
ConventionalBandgap Reference
Curvature CorrectedBandgap Reference
Fig. 400-04
Chapter 4 – Section 6 (5/2/04) Page 4.6-17
CMOS Analog Circuit Design © P.E. Allen - 2004
A Practical Version of the Nonlinear Curvature Correction TechniqueThe last idea was good in concept but not appropriate for CMOS implementation. Thefollowing is a possible implementation.
Iconst
VDD
VDDVDD
IPTAT
R1 R2R0
Q1 Q2
+
-
VREF
IVBE(PTAT)IVBE(Const)
040629-01
IVBE
VDD
KIPTAT
VDD
Iconst
VGS(ZTC)
+
-
Constant CurrentGenerator
VREF = R0[IVBE(PTAT) - IVBE(Const)] = R0 VBE(PTAT)
R1 - R0
VBE(Const)R2
= R0R1
VGO-TT0 VGO-VBE(T0) -(γ-1)Vt ln
T
T0 - R0R2
VGO-TT0 VGO-VBE(T0) -γVt ln
T
T0
Let R0R1
- R0R2
= 1 and R0R1
(γ-1) = R0R2
γ → R1R2
= γ-1γ to cancel the nonlinear curvature term.
Chapter 4 – Section 6 (5/2/04) Page 4.6-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Other Characteristics of Bandgap Voltage ReferencesNoise
Voltage references for high-resolution ADCs are particularly sensitive to noise.Noise sources: Op amp, resistors, switches, etc.
PSRRMaximize the PSRR of the op amp.
Offset VoltagesBecomes a problem when op amps are used.VBE2 = VBE1 + VR1 + VOS
∆VBE = VBE2 - VBE1 = VR1 + VOS = Vt ln
iC2AE1
iC1AE2
Since iC2R3 = iC1R2 - VOS
then iC2
iC1 =
R2
R3 -
VOS
iC1R3 =
R2
R3
1 + VOS
iC1R2
Therefore,
VR1 = -VOS + Vt ln
R2AE1
R3AE2
1 + VOS
iC1R2
VREF = VBE2 - VOS + iC1R2 = VBE2 - VOS +
VR1
R1R2 = VBE2 - VOS +
R2
R1 VR1
VREF = VBE2 - VOS
1+ R2
R1 +
R2
R1 Vt ln
R2AE1
R3AE2
1 - VOS
iC1R2
Fig. 400-05
iC1iC2
VCC
Q1Q2
+-
+
VREF
-
VEE
VOS
R3 R2
R1
+
-VR1
Chapter 4 – Section 6 (5/2/04) Page 4.6-19
CMOS Analog Circuit Design © P.E. Allen - 2004
How do you get a Stable Reference Current from the Bandgap?Assume that a temperature stable reference voltage is available (i.e. bandgap
reference) and use the zero TC NMOS current sink.The problem is that VREF may not be equal to the value of VGS that gives zero TC.
IREFR1
R2
+
-
VGS
VREF
Fig. 400-06
1:1 Current Mirror
1:1 Current Mirror
VDD
IR1 IR2
VGS = IR2R2 = R2
VREF
R1 =
R2
R1VREF
∴dVGS
dT =
R2
R1 dVREF
dT + VREF
R1 dR2
dT - R2
R12
dR1
dT = R2
R1
dVREF
dT + dR2
dT - dR1
dT
If the temperature coefficients of R1 and R2 are equal
dR1
dT = dR2
dT , then
dVGS
dT = R2
R1 dVREF
dT and VGS is proportional to the temperature dependence of VREF.
If the MOSFET is biased at the zero TC point, then the current should have the samedependence on temperature as VREF.
Chapter 4 – Section 6 (5/2/04) Page 4.6-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Practical Aspects of Temperature-Independent and Supply-Independent BiasingA temperature-independent and supply-independent current source and its distribution:
+-
Rext
To SlaveBias Ckt.
To SlaveBias Ckt.
VDD
BandgapVoltage,
VBG
M7
M5
M4
M1
Q1 Q2
M2
M3
M6
M8M9
M10
M11
M12
Q3
IPTAT R1 R2
M13
M14
M15
M16
M17
M18
M19
M20
Fig. 400-07xn
IREF
R3
R4
Constant current:
IREF = VBG
Rext where VBG = VBE3 + IPTATR2 = VBE3 +
VT
R1 ln(n)·R2
Chapter 4 – Section 6 (5/2/04) Page 4.6-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Practical Aspects of Bias Distribution Circuits - Continued
Distribution of the current avoids change in bias voltage due to IR drop in bias lines.
Slave bias circuit:
From Master Bias
Ib Ib
VDD
VPBias1
VPBias2
VNBias2
VNBias1
Fig. 400-08
Chapter 4 – Section 6 (5/2/04) Page 4.6-22
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY OF VOLTAGE AND CURRENT REFERENCES• Reasonably good, simple references are possible• Best power supply sensitivity is approximately 0.01
(10% change in power supply causes a 0.1% change in reference)• Typical simple reference temperature dependence is ≈ 1000 ppm/°C• Can obtain zero temperature coefficient over a limited range of operation• Bandgap voltage references can achieve temperature dependence less than 50 ppm/°C• Correction of second-order effects in the bandgap voltage reference can achieve very
stable (1 ppm/°C) voltage references.• Watch out for second-order effects such as noise when using the bandgap voltage
reference in sensitive applications.
We will examine bandgap voltage references once again when we consider lowvoltage circuits in Section 6 of Chapter 7.
Chapter 4 – Section 7 (5/2/04) Page 4.7-1
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 4 - SUMMARY• This chapter covered the analysis and design of sub-blocks or subcircuits including:
- Switches - MOS diode and floating resistor realizations- Current sinks and sources - Current mirrors (amplifiers)- Current and voltage references - Bandgap reference
• Subcircuits represent primitives of circuit design and do not stand alone• The current sink/source is an important subcircuit which is used for biases and ac loads• A current sink/source is characterized by
1.) The independence of the current on the voltage across it (rout)2.) The voltage range over which the current is not independent of the voltage (VMIN )
• A current mirror is characterized by1.) The independence of the output current on the voltage across it (rout → large)2.) The output voltage range over which output current is dependent (VMIN (out))3.) The independence of the input voltage on the input current (rin → small)4.) The range of input voltage over which the input current is independent (VMIN(in))5.) The accuracy of the current out as a function of the current in ratio.
• A voltage or current reference is independent of power supply and temperature• The bandgap reference is the best realization of a voltage reference
Chapter 5 – Introduction (5/2/04) Page 5.0-1
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 5 – CMOS AMPLIFIERSChapter Outline5.1 Inverters5.2 Differential Amplifiers5.3 Cascode Amplifiers5.4 Current Amplifiers5.5 Output Amplifiers5.6 High-Gain Architectures
GoalTo develop an understanding of the amplifier building blocks used in CMOS analog
circuit design.
Design Hierarchy
Blocks or circuits(Combination of primitives, independent)
Sub-blocks or subcircuits(A primitive, not independent)
Functional blocks or circuits(Perform a complex function)
Fig. 5.0-1
Chapter 5
Chapter 5 – Introduction (5/2/04) Page 5.0-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of Hierarchy in Analog Circuits for an Op Amp
Operational Amplifier
BiasingCircuits
InputDifferentialAmplifier
SecondGainStage
OutputStage
CurrentSource
CurrentMirrors
CurrentSink
CurrentMirror Load
Inverter CurrentSink Load
SourceFollower
CurrentSink Load
SourceCoupled Pair
Fig. 5.0-2
Chapter 5 – Introduction (5/2/04) Page 5.0-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Active Load AmplifiersWhat is an active load amplifier?
VDD
Fig320-01
VCC
IBias
+
-
VT+2VON
VT+VON+
-
VT+VON+
-
+
-
VT+2VON
IBias
+-
VEBVEB +VEC(sat)
+
-
+
-VBE
VBE +VCE(sat)
+
-
MOS Loads BJT Loads
MOS Transconductors BJT Transconductors
IBias IBias
It is a combination of any of the above transconductors and loads to form an amplifier.(Remember that the above are only some of the examples of transconductors and loads.)
Chapter 5 – Section 1 (5/2/04) Page 5.1-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 5.1 - CMOS INVERTING AMPLIFIERS
Characterization of AmplifiersAmplifiers will be characterized by the following properties:• Large-signal voltage transfer characteristics• Large-signal voltage swing limitations• Small-signal, frequency independent performance
- Gain- Input resistance- Output resistance
• Small-signal, frequency response• Other properties
- Noise- Power dissipation- Etc.
Chapter 5 – Section 1 (5/2/04) Page 5.1-2
CMOS Analog Circuit Design © P.E. Allen - 2004
InvertersThe inverting amplifier is an amplifier which amplifies and inverts the input signal.
The inverting amplifier generally has the source on ac ground or the common-sourceconfiguration.Various types of inverting CMOS amplifiers:
VDD
M2
M1vIN
vOUTID
M2
M1vIN
vOUTID
M1vIN
vOUTID
M2M2
M1
vIN vOUTID
M2
M1vIN
vOUTID
VGG2
ActivePMOS Load
Inverter
ActiveNMOS Load
Inverter
DepletionNMOS Load
Inverter
CurrentSource Load
Inverter
Push-pull
InverterFig. 5.1-1
We will consider:• Active PMOS Load Inverter (active load inverter)• Current Source Load Inverter• Push-pull Inverter
Chapter 5 – Section 1 (5/2/04) Page 5.1-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Voltage Transfer Characteristic of the Active Load Inverter
0 1 2 3 4 5
I D (
mA
)
0
4
5
0 1 2 3 4 5
v OU
T
3
vIN
A B
C
D
E
H I K
F
M2
M1
vIN
vOUT
ID
5V
+
-
+
-
W2L2
=1µm1µm
W1L1
=2µm1µm
Fig. 320-02
vIN=5.0VvIN=4.0V
vIN=4.5V
vIN=1.0V
vIN=1.5V
vIN=2.0V
vIN=2.5V
A,BCD
E
F
M2
2
1J
HI
JK
G
M1 saturat
ed
M1 activ
e
0.0
0.1
0.2
0.3
0.4
0.5vIN=3.5VvIN=3.0V
G
vOUTM2 cutoff
M2 saturated
The boundary between active and saturation operation for M1 isvDS1 ≥ vGS1 - VTN → vOUT ≥ vIN - 0.7V
Chapter 5 – Section 1 (5/2/04) Page 5.1-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Large-Signal Voltage Swing Limits of the Active Load InverterMaximum output voltage, vOUT(max):
vOUT(max) ≅ VDD - |VTP|
(ignores subthreshold current influence on the MOSFET)Minimum output voltage, vOUT(min):
Assume that M1 is nonsaturated and that VT1 = |VT2| = VT.
vDS1 ≥ vGS1 - VTN → vOUT ≥ vIN - 0.7V
The current through M1 is
iD = β1
(vGS1 − VT)vDS1 − v 2DS12 = β1
(VDD − VT)(vOUT ) − (vOUT)2
2
and the current through M2 is
iD = β22 (vSG2 − VT)2 =
β22 (VDD − vOUT − VT)2 =
β22 (vOUT + VT − VDD)2
Equating these currents gives the minimum vOUT as,
vOUT(min) = VDD − VT − VDD − VT
1 + (β2/β1)
Chapter 5 – Section 1 (5/2/04) Page 5.1-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Midband Performance of the Active Load InverterThe development of the small-signal model for the active load inverter is shown below:
M2
M1vIN
vOUTID
VDD
gm2vgs2
gm1vgs1
rds2
rds1
+
-
vin
G1D1=D2=G2
S1=B1
S2=B2
+
-
vout gm1vin rds1
+
-
vin
+
-
voutgm2vout rds2
Rout
Fig. 320-03
Sum the currents at the output node to get,gm1vin + gds1vout + gm2vout + gds2vout = 0
Solving for the voltage gain, vout/vin, gives
voutvin
= −gm1
gds1 + gds2 + gm2 ≅ −
gm1gm2
= −
K'NW1L2
K'PL1W21/2
The small-signal output resistance can also be found from the above by letting vin = 0 toget,
Rout = 1
gds1 + gds2 + gm2 ≅
1gm2
Chapter 5 – Section 1 (5/2/04) Page 5.1-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Response of the MOS Diode Load InverterIncorporation of the parasiticcapacitors into the small-signalmodel:If we assume the input voltage has asmall source resistance, then we canwrite the following:
sCM(Vout-Vin) + gmVin
+ GoutVout + sCoutVout = 0
∴ Vout(Gout + sCM + sCout) = - (gm – sCM)Vin
VoutVin =
-(gm – sCM)Gout+ sCM + sCout
= -gmRout
1-sCMgm
1+ sRout(CM + Cout) = −gmRout
1 - sz1
1 - sp1
where
gm = gm1, p1 = −1
Rout(Cout+CM) , and z1 = gm1CM
and
Rout = [gds1+gds2+gm2]-1 ≅ 1
gm2 , CM = Cgd1 , and Cout = Cbd1+Cbd2+Cgs2+CL
Fig. 320-04Cgs1
Cgd1
Cgs2
Cbd2
Cbd1
VDD
Vin
Vout
CL
M2
M1
CM
CoutRoutVout
+
-
Vin gmVin
+
-
Chapter 5 – Section 1 (5/2/04) Page 5.1-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Response of the MOS Diode Load Inverter - ContinuedIf |p1| < z1, then the -3dB frequency is approximately equal to [Rout(Cout+CM)]-1.
dB
20log10(gmRout)
0dB |p1| ≈ ω-3dBlog10f
z1
Fig. 5.1-4A
Observation:The poles in a MOSFET circuit can be found by summing the capacitance connected
to a node and multiplying this capacitance times the equivalent resistance from this nodeto ground and inverting the product.
Chapter 5 – Section 1 (5/2/04) Page 5.1-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 5.1-1 - Performance of an Active Resistor-Load InverterCalculate the output-voltage swing limits for VDD = 5 volts, the small-signal gain, the
output resistance, and the -3 dB frequency of active load inverter if (W1/L1) is 2 µm/1 µmand W2/L2 = 1 µm/1 µm, Cgd1 = 100fF, Cbd1 = 200fF, Cbd2 = 100fF, Cgs2 = 200fF, CL = 1pF, and ID1 = ID2 = 100µA, using the parameters in Table 3.1-2.
SolutionFrom the above results we find that:
vOUT(max) = 4.3 volts
vOUT(min) = 0.418 volts
Small-signal voltage gain = -1.92V/VRout = 9.17 kΩ including gds1 and gds2 and 10 kΩ ignoring gds1 and gds2
z1 = 2.10x109 rads/sec
p1 = -64.1x106 rads/sec. Thus, the -3 dB frequency is 10.2 MHz.
Chapter 5 – Section 1 (5/2/04) Page 5.1-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Voltage Transfer Characteristic of the Current Source Inverter
0 1 2 3 4 5
I D (
mA
)
vOUT
0 1 2 3 4 5
v OU
T
vIN
M2
M1
vIN
vOUT
ID
5V
+
-
+
-
W2L2
=2µm1µm
W1L1
= 2µm1µm
Fig. 5.1-5
C
M2
2.5V
A B C
D
E
G H I KF
J1
0
2
3
4
5
M2 saturated
EHIKJ
G
F
M2 active
M1 activ
eM1 sa
turated
vIN=5.0VvIN=4.0V
vIN=4.5V
vIN=1.0V
vIN=1.5V
vIN=2.0V
vIN=2.5V
0.0
0.1
0.2
0.3
0.4
0.5vIN=3.5VvIN=3.0V
D
A,B
Regions of operation for the transistors:M1: vDS1 ≥ vGS1 -VTn → vOUT ≥vIN - 0.7VM2: vSD2 ≥ vSG2 - |VTp| → VDD - vOUT ≥VDD -VGG2 - |VTp| → vOUT ≤ 3.2V
Chapter 5 – Section 1 (5/2/04) Page 5.1-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Large-Signal Voltage Swing Limits of the Current Source Load InverterMaximum output voltage, vOUT(max):
vOUT (max) ≅ VDD
Minimum output voltage, vOUT(min):
Assume that M1 is nonsaturated. The minimum output voltage is,
vOUT(min) = vOUT(min) = (VDD - VT1)
1 - 1 -
β2
β1
VDD - VGG - |VT2|
VDD - VT12
This result assumes that vIN is taken to VDD.
Chapter 5 – Section 1 (5/2/04) Page 5.1-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Midband Performance of the Current Source Load InverterSmall-Signal Model:
M2
M1vIN
vOUTID
VDD
gm1vgs1
rds2
rds1
+
-
vin
G1 D1=D2
S1=B1=G2
S2=B2
+
-
vout gm1vin rds1
+
-
vin
+
-
voutrds2
Rout
Fig. 5.1-5B
VGG2
Midband Performance:
voutvin
= −gm1
gds1 + gds2 =
2K'NW1
L1ID
1/2
−1
λ1 + λ2 ∝
1ΙD
!!! and Rout = 1
gds1 + gds2 ≅
1ID(λ1 + λ2)
0.1µA 1µA 10µA 100µA 1mA 10mA
10
Amax
log|Av|
Weakinversion
Stronginversion
ID
Fig. 5.1-6
Amax
100Amax
1000Amax
Chapter 5 – Section 1 (5/2/04) Page 5.1-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Response of the Current Source Load InverterIncorporation of the parasiticcapacitors into the small-signalmodel (x is connected to VGG2):
If we assume the input voltagehas a small source resistance,then we can write the following:
Vout(s)Vin(s) =
−gmRout
1 - sz1
1 - sp1
where gm = gm1, p1 = −1
Rout(Cout+CM) , and z1 = gmCM
and Rout = 1
gds1 + gds2 and Cout = Cgd2 + Cbd1 + Cbd2 + CL CM = Cgd1
Therefore, if |p1|<|z1|, then the −3 dB frequency response can be expressed as
ω-3dB ≈ ω1 = gds1 + gds2
Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL
Cgd2
Cgd1
Cgs2
Cbd2
Cbd1
VDD
Vin
Vout
CL
M2
M1
CM
CoutRoutVout
+
-
Vin gmVin
+
-
Fig. 5.1-4
x
Chapter 5 – Section 1 (5/2/04) Page 5.1-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 5.1-2 - Performance of a Current-Sink InverterA current-sink inverter is shown in Fig. 5.1-7. Assume
that W1 = 2 µm, L1 = 1 µm, W2 = 1 µm, L2 = 1µm, VDD = 5volts, VGG1 = 3 volts, and the parameters of Table 3.1-2describe M1 and M2. Use the capacitor values of Example5.1-1 (Cgd1 = Cgd2). Calculate the output-swing limits andthe small-signal performance.Solution
To attain the output signal-swing limitations, we treatFig. 5.1-7 as a current source CMOS inverter with PMOS parameters for the NMOS andNMOS parameters for the PMOS and use NMOS equations. Using a prime notation todesignate the results of the current source CMOS inverter that exchanges the PMOS andNMOS model parameters,
vOUT(max)’ = 5V and vOUT(min)’ = (5-0.7)
1 - 1 -
110·1
50·2
3-0.7
5-0-0.72 = 0.74V
In terms of the current sink CMOS inverter, these limits are subtracted from 5V to getvOUT(max) = 4.26V and v OUT (min) = 0V.
To find the small signal performance, first calculate the dc current. The dc current, ID, is
ID = KN’W1
2L1 (VGG1-VTN)2 =
110·12·1 (3-0.7)2 = 291µA
vout/vin = −9.2V/V, Rout = 38.1 kΩ, and f-3dB = 2.78 MHz.
VDD
vOUT
vIN M1
M2VGG1
Figure 5.1-7 Current sink CMOS inverter.
ID
+
-VSG1
Chapter 5 – Section 1 (5/2/04) Page 5.1-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Voltage Transfer Characteristic of the Push-Pull Inverter
0 1 2 3 4
I D (
mA
)
vOUT
0 1 2 3 4 5
v OU
T
vIN
M2
M1
vIN
vOUT
ID
5V
+
-
+
-
W2L2
=2µm1µm
W1L1
= 1µm1µm
Fig. 5.1-8
0.0
0.2
0.4
0.6
0.8
1.0
vIN=1.0VvIN=1.5V
vIN=2.0V
vIN=2.5V
vIN=3.0V
A B C DE
GH I K
F
J
vIN=5.0V vIN=4.0VvIN=4.5V vIN=3.5V
E
D
FG
HI
vIN=3.0V
2
3
4
1
0
M2 active
M2 saturat
edM1 act
iveM1 sat
urated
CA,B 5
vIN=4.5VvIN=3.5V
vIN=2.5V
J,K
vIN=2.0V
vIN=0.5VvIN=1.0V
vIN=1.5V
Notethe rail-to-railoutputvoltageswing
Regions of operation for M1 and M2: M1: vDS1 ≥ vGS1 - VT1 → vOUT ≥ vIN - 0.7V
M2: vSD2 ≥ vSG2-|VT2| → VDD -vOUT ≥ VDD -vIN-|VT2| → vOUT ≤ vIN + 0.7V
Chapter 5 – Section 1 (5/2/04) Page 5.1-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Performance of the Push-Pull Amplifier
gm1vin rds1 gm2vin rds2
+
-
vin
+
-
vout
Fig. 5.1-9
Cout
CM
M2
M1
5V
+
-
+
-
vinvout
Small-signal analysis gives the following results:
voutvin
= −(gm1 + gm2)gds1 + gds2
= − (2/ID)
K'N(W1/L1) + K'P(W2/L2)
λ1 + λ2
Rout = 1
gds1 + gds2
z = gm1+gm2
CM =
gm1+gm2Cgd1+Cgd2
and
p1 = −(gds1 + gds2)
Cgd1 + Cgd2 + Cbd1 + Cbd2 + CLIf z1 > |p1|, then
ω-3dB = gds1 + gds2
Cgd1 + Cgd2 + Cbd1 + Cbd2 + CL
Chapter 5 – Section 1 (5/2/04) Page 5.1-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 5.1-3 - Performance of a Push-Pull InverterThe performance of a push-pull CMOS inverter is to be examined. Assume that W1 =
1 µm, L1 = 1 µm, W2 = 2 µm, L2 = 1µm, VDD = 5 volts, and use the parameters of Table3.1-2 to model M1 and M2. Use the capacitor values of Example 5.1-1 (Cgd1 = Cgd2).Calculate the output-swing limits and the small-signal performance assuming that ID1 =ID2 = 300µA.
SolutionThe output swing is seen to be from 0V to 5V. In order to find the small signal
performance, we will make the important assumption that both transistors are operatingin the saturation region. Therefore:
voutvin
= -257µS - 245µS
12µS + 15µS = -18.6V/V
Rout = 37 kΩ
f-3dB = 2.86 MHz
andz1 = 399 MHz
Chapter 5 – Section 1 (5/2/04) Page 5.1-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Noise Analysis of Inverting AmplifiersNoise model:
en22
en12
M2
M1
NoiseFree
MOSFETs
eout2
VDD
vin
eeq2
M2
M1
NoiseFree
MOSFETs
eout2
VDD
vin
Fig. 5.1-10
*
*
*
Approach:
1.) Assume a mean-square input-voltage-noise spectral density en2 in series with thegate of each MOSFET.
(This step assumes that the MOSFET is the common source configuration.)
2.) Calculate the output-voltage-noise spectral density, eout2 (Assume all sources areadditive).3.) Refer the output-voltage-noise spectral density back to the input to get equivalentinput noise eeq2.
4.) Substitute the type of noise source, 1/f or thermal.
Chapter 5 – Section 1 (5/2/04) Page 5.1-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Noise Analysis of the Active Load Inverter1.) See model to the right.
2.) eout2 = en1
2
gm1
gm22+ en2
2
3.) eeq2 = en1
2
1 +
gm2
gm1
2
en2
en1
2
Up to now, the type of noise is not defined.1/f Noise
Substituting en2= KF
2fCoxWLK’ = B
fWL , into the above gives,
eeq(1/f) =
B1
fW1L1
1/2
1 +
K'2B2
K'1B1
L1
L2
2 1/2
To minimize 1/f noise, 1.) Make L2>>L1, 2.) increase the value of W1 and 3.) choose M1as a PMOS.Thermal Noise
Substituting en2= 8kT3gm into the above gives,
eeq(th) =
8kT
3[2K'1(W/L)1I1]1/2
1+
W2L1K'2
L2W1K'11/2 1/2
To minimize thermal noise, maximize the gain of the inverter.
en22
en12
M2
M1
NoiseFree
MOSFETs
eout2
VDD
vin
eeq2
M2
M1
NoiseFree
MOSFETs
eout2
VDD
vin
Fig. 5.1-10
*
*
*
Chapter 5 – Section 1 (5/2/04) Page 5.1-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Noise Analysis of the Active Load Inverter - Continued
When calculating the contribution of en22 to eout2, it was assumed that the gain wasunity. To verify this assumption consider the following model:
en22
gm2vgs2 rds1vgs2
+
-
rds2 eout2
+
_
Fig. 5.1-11
*
We can show that,eout
2
en22 =
gm2(rds1||rds2)
1 + gm2(rds1||rds2) 2 ≈ 1
Chapter 5 – Section 1 (5/2/04) Page 5.1-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Noise Analysis of the Current Source Load Inverting AmplifierModel:
en22
en12
M2
M1
NoiseFree
MOSFETs
eout2
VDD
vin
eeq2
M2
M1
NoiseFree
MOSFETs
eout2
VDD
vin
Fig. 5.1-12.
VGG2*
* *
The output-voltage-noise spectral density of this inverter can be written as,eout
2 = (gm1rout)2en12 + (gm2rout)2en2
2
or
eeq2 = en1
2 + (gm2rout)2
(gm1rout)2en22 = en1
2
1 +
gm2
gm1
2 en2
2
en12
This result is identical with the active load inverter.Thus the noise performance of the two circuits are equivalent although the small-signalvoltage gain is significantly different.
Chapter 5 – Section 1 (5/2/04) Page 5.1-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Noise Analysis of the Push-Pull AmplifierModel:
en22
en12
VDD
M2
M1
eout2vin
NoiseFree
MOSFETs
Fig. 5.1-13.
*
*
The equivalent input-voltage-noise spectral density of the push-pull inverter can be foundas
eeq =
gm1en1
gm1 + gm2 2 +
gm2en2
gm1 + gm2 2
If the two transconductances are balanced (gm1 = gm2), then the noise contribution ofeach device is divided by two.The total noise contribution can only be reduced by reducing the noise contribution ofeach device. (Basically, both M1 and M2 act like the “load” transistor and “input” transistor, sothere is no defined input transistor that can cause the noise of the load transistor to beinsignificant.)
Chapter 5 – Section 1 (5/2/04) Page 5.1-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of CMOS Inverting Amplifiers
InverterAC Voltage
GainAC OutputResistance Bandwidth (CGB=0)
Equivalent,input-referred,mean-square noise voltage
p-channelactive load inverter
-gm1gm2
1gm2
gm2CBD1+CGS1+CGS2+CBD2 en12 + en22
gm2
gm12
n-channelactive loadinverter
-gm1gm2+gmb2
1gm2+gmb2
gm2+gmb2CBD1+CGD1+CGS2+CBS2 en12 + en22
gm2
gm12
Currentsource loadinverter
-gm1gds1+gds2
1gds1+gds2
gds1+gds2CBD1+CGD1+CDG2+CBD2 en12 + en22
gm2
gm12
n-channeldepletionload inverter ~
-gm1gmb2
1gmb2+gds1+gds2
gmb2+gds1+gds2CBD1+CGD1+CGS2+CBD2 en1 2 + en2 2
gm2
gm12
Push-Pullinverter
-(gm1+gm2)gds1+gds2
1gds1+gds2
gds1+gds2CBD1+CGD1+CGS2+CBD2
gm1en1
gm1+ gm22+
gm1en1
gm1+ gm22
Inverting configurations we did not examine.
Chapter 5 – Section 2 (5/2/04) Page 5.2-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 5.2 - DIFFERENTIAL AMPLIFIERSWhat is a Differential Amplifier?
A differential amplifier is an amplifier that amplifies thedifference between two voltages and rejects the average orcommon mode value of the two voltages.Differential and common mode voltages:
v1 and v2 are called single-ended voltages. They arevoltages referenced to ac ground.The differential-mode input voltage, vID, is the voltage difference between v1 and v2.
The common-mode input voltage, vIC, is the average value of v1 and v2 .
∴ vID = v1 - v2 and vIC = v1+v2
2 ⇒ v1 = vIC + 0.5vID and v2 = vIC - 0.5vID
vOUT = AVDvID ± AVCvIC = AVD(v1 - v2) ± AVC
v1 + v2
2
whereAVD = differential-mode voltage gain
AVC = common-mode voltage gain
+- +
vOUT
-
+
v1
-
+
-
v2
Fig. 5.2-1A
+- +
vOUT
-
vIC
vID2
vID2
Fig. 5.2-1B
Chapter 5 – Section 2 (5/2/04) Page 5.2-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Differential Amplifier Definitions• Common mode rejection rato (CMRR)
CMRR =
AVD
AVC
CMRR is a measure of how well the differential amplifier rejects the common-modeinput voltage in favor of the differential-input voltage.• Input common-mode range (ICMR)
The input common-mode range is the range of common-mode voltages over whichthe differential amplifier continues to sense and amplify the difference signal with thesame gain.
Typically, the ICMR is defined by the common-mode voltage range over which allMOSFETs remain in the saturation region.• Output offset voltage (VOS(out))
The output offset voltage is the voltage which appears at the output of the differentialamplifier when the input terminals are connected together.• Input offset voltage (VOS(in) = VOS)
The input offset voltage is equal to the output offset voltage divided by the differentialvoltage gain.
VOS = VOS(out)
AVD
Chapter 5 – Section 2 (5/2/04) Page 5.2-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Transconductance Characteristic of the Differential AmplifierConsider the following n-channel differentialamplifier (sometimes called a source-coupledpair):
Where should bulk be connected? Consider ap-well, CMOS technology,
yD1 G1 S1 yS2 G2 D2
n+ n+ n+ n+ n+p+
p-well
n-substrate
VDD
Fig. 5.2-3
1.) Bulks connected to the sources: No modulation of VT but large common modeparasitic capacitance.2.) Bulks connected to ground: Smaller common mode parasitic capacitors, butmodulation of VT.
If the technology is n-well CMOS, there is no choice. The bulks must be connected toground.
IBias
iD1 iD2
VDD
VBulk
M1 M2
M3M4 ISS
+-
vG1
vGS1+
-vGS2
vG2
Fig. 5.2-2
vID
Chapter 5 – Section 2 (5/2/04) Page 5.2-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Transconductance Characteristic of the Differential Amplifier - ContinuedDefining equations:
vID = vGS1 − vGS2 =
2iD1
β1/2
−
2iD2
β1/2
and ISS = iD1 + iD2
Solution:
iD1 = ISS2 +
ISS2
βv
2ID
ISS −
β2v4ID
4I2SS
1/2and iD2 =
ISS2 −
ISS2
βv
2ID
ISS −
β2v4ID
4I2SS
1/2
which are valid for vID < 2(ISS/β)1/2.Illustration of the result:
Differentiating iD1 (or iD2)with respect to vID andsetting VID =0V gives
gm = diD1dvID
(VID = 0) = (βISS/4)1/2 =
K'1ISSW1
4L1
1/2 (half the gm of an inverting amplifier)
iD/ISS
0.8
0.2
0.0
1.0
0.6
0.4
1.414 2.0-1.414-2.0vID
(ISS/ß)0.5
iD1
iD2
Fig. 5.2-4
Chapter 5 – Section 2 (5/2/04) Page 5.2-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Voltage Transfer Characteristic of the Differential AmplifierIn order to obtain the voltage transfer characteristic, a load for the differential amplifier
must be defined. We will select a current mirror load as illustrated below.
VBias
ISS
M1 M2
M3 M4
VDD
M5
vGS1+
-vGS2
+-
vG2
-
vOUT
iOUT
vG1
-
iD1 iD2
iD3 iD4
-
+
Fig. 5.2-5
2µm1µm
2µm1µm
2µm1µm
2µm1µm
2µm1µm
VDD2
Note that output signal to ground is equivalent to the differential output signal due to thecurrent mirror.The short-circuit, transconductance is given as
gm = diOUTdvID
(VID = 0) = (βISS)1/2 =
K'1ISSW1
L1
1/2
Chapter 5 – Section 2 (5/2/04) Page 5.2-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Voltage Transfer Function of the Differential Amplifer with a Current Mirror Load
Fig. 330-01
VBias
ISS
M1 M2
M3 M4
VDD
M5
vGS1+
- vGS2+
-vG2
-
vOUT
iOUT
vG1
-
iD1 iD2
iD3 iD4
-
+2µm1µm
2µm1µm
2µm1µm
2µm1µm
2µm1µm
0
1
2
3
4
5
-1 -0.5 0 0.5 1vID (Volts)
v OU
T (
Vol
ts)
M2 saturatedM2 active
M4 activeM4 saturated
VIC = 2V
= 5V
Regions of operation of the transistors:M2 is saturated when, vDS2 ≥ vGS2-VTN → vOUT-VS1 ≥ VIC-0.5vID-VS1-VTN → vOUT ≥ VIC-VTN
where we have assumed that the region of transition for M2 is close to vID = 0V. M4 is saturated when, vSD4 ≥ vSG4 - |VTP| → VDD-vOUT ≥ VSG4-|VTP| → vOUT ≤ VDD-VSG4+|VTP|
The regions of operations shown on the voltage transfer function assume ISS = 100µA.
Note: VSG4 = 2·5050·2 +|VTP| = 1 + |VTP| ⇒ vOUT ≤ 5 - 1 - 0.7 + 0.7 = 4V
Chapter 5 – Section 2 (5/2/04) Page 5.2-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Differential Amplifier Using p-channel Input MOSFETs
VBias IDD
M1 M2
M3 M4
VDD
M5
vSG1
+
-vSG2
+
-
vG2
-
vOUT
iOUT
vG1
-
iD1 iD2
iD3 iD4
-
+
Fig. 5.2-7
++
Chapter 5 – Section 2 (5/2/04) Page 5.2-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Input Common Mode Range (ICMR)ICMR is found by setting vID = 0 and varying vICuntil one of the transistors leaves the saturation.Highest Common Mode VoltagePath from G1 through M1 and M3 to VDD:
VIC(max) =VG1(max) =VG2(max)
=VDD -VSG3 -VDS1(sat) +VGS1
orVIC(max) = VDD - VSG3 + VTN1
Path from G2 through M2 and M4 to VDD:
VIC(max)’ =VDD -VSD4(sat) -VDS2(sat) +VGS2
=VDD -VSD4(sat) + VTN2
∴ VIC(max) = VDD - VSG3 + VTN1
Lowest Common Mode Voltage (Assume a VSS for generality)
VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
where we have assumed that VGS1 = VGS2 during changes in the input common modevoltage.
VBias
ISS
M1 M2
M3 M4
VDD
M5
vGS1+
-vGS2
+-
vG2
-
vOUT
iOUT
vG1
-
iD1 iD2
iD3 iD4
-
+
Fig. 330-02
2µm1µm
2µm1µm
2µm1µm
2µm1µm
2µm1µm
VDD2
Chapter 5 – Section 2 (5/2/04) Page 5.2-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 5.2-1 - Small-Signal Analysis of the Differential-Mode of the Diff. AmpA requirement for differential-mode operation is that the differential amplifier is balanced†.
gm3rds3
1
rds1
gm1vgs1
rds2
gm2vgs2
i3i3
+
-
+
-
+G2
vid
vg1 vg2
G1
C1
-
rds5
S1=S2
rds4
C3
C2
+
-
vout
D1=G3=D3=G4
S3 S4
D2=D4
gm3rds31
rds1gm1vgs1 rds2gm2vgs2
i3
i3
+
-
+
-
+G2
vid
vgs1 vgs2
G1
C1
-
S1=S2=S3=S4
rds4
C3C2
+
-
vout
D1=G3=D3=G4 D2=D4iout'
ISS
M1 M2
M3 M4
VDD
M5
vout
iout
iD1 iD2
iD3 iD4
-
+
Fig. 330-03
VBias
vid
Differential Transconductance:Assume that the output of the differential amplifier is an ac short.
iout’ = gm1gm3rp11 + gm3rp1
vgs1 − gm2vgs2 ≈ gm1vgs1 − gm2vgs2 = gmdvid
where gm1 = gm2 = gmd, rp1 = rds1rds3 and i'out designates the output current into a shortcircuit.
† It can be shown that the current mirror causes this requirement to be invalid because the drain loads are not matched. However, we will continue touse the assumption regardless.
Chapter 5 – Section 2 (5/2/04) Page 5.2-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Analysis of the Differential-Mode of the Diff. Amplifier - ContinuedOutput Resistance: Differential Voltage Gain:
rout = 1
gds2 + gds4 = rds2||rds4 Av =
voutvid
= gmd
gds2 + gds4
If we assume that all transistors are in saturation and replace the small signalparameters of gm and rds in terms of their large-signal model equivalents, we achieve
Av = voutvid
= (K'1ISSW1/L1)1/2
(λ2 + λ4)(ISS/2) = 2
λ2 + λ4
K'1W1
ISSL1
1/2∝
1ISS
Note that the small-signal gain is inverselyproportional to the square root of the biascurrent!Example:
If W1/L1 = 2µm/1µm and ISS = 50µA(10µA), then
Av(n-channel) = 46.6V/V (104.23V/V)
Av(p-channel) = 31.4V/V (70.27V/V)
rout = 1
gds2 + gds4 =
125µA·0.09V-1 = 0.444MΩ (2.22MΩ)
vin
vout
Fig. 330-04
Stong InversionWeakInvers-
ionlog(IBias)≈ 1µA
Chapter 5 – Section 2 (5/2/04) Page 5.2-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Common Mode Analysis for the Current Mirror Load Differential AmplifierThe current mirror load differential amplifier is not a good example for common modeanalysis because the current mirror rejects the common mode signal.
-
+
vic
M1 M2
M4
M5
vout ≈ 0V
VDD
VBias+
-
M3M1-M3-M4
Fig. 5.2-8A
M2
Total common
mode Outputdue to vic
=
Common mode
output due toM1-M3-M4 path
-
Common mode
output due toM2 path
Therefore: • The common mode output voltage should ideally be zero. • Any voltage that exists at the output is due to mismatches in the gain between the two
different paths.
Chapter 5 – Section 2 (5/2/04) Page 5.2-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Analysis of the Common-Mode of the Differential AmplifierThe common-mode gain of the differential amplifier with a current mirror load is ideallyzero.To illustrate the common-mode gain, we need a different type of load so we will considerthe following:
vic
vo1
v1
vo2
v2
VBias
ISS
VDD
M1 M2
M3 M4
M5
vo1
vid
VDD
M1 M2
M3 M4vo2 vo1
vic
vo2
VBias
ISS
VDD
M1 M2
M3 M4
2ISS M5x1
22
Differential-mode circuit Common-mode circuitGeneral circuit
2vid
2
Fig. 330-05
Differential-Mode Analysis:vo1vid
≈ - gm1
2gm3 and
vo2vid
≈ + gm2
2gm4
Note that these voltage gains are half of the active load inverter voltage gain.
Chapter 5 – Section 2 (5/2/04) Page 5.2-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Analysis of the Common-Mode of the Differential Amplifier – Cont’dCommon-Mode Analysis:
Assume that rds1 is large and can beignored (greatly simplifies theanalysis).
∴ vgs1 = vg1-vs1 = vic - 2gm1rds5vgs1
Solving for vgs1 gives
vgs1 = vic
1 + 2gm1rds5
The single-ended output voltage, vo1, as a function of vic can be written as
vo1vic
= - gm1[rds3||(1/gm3)]
1 + 2gm1rds5 ≈ -
(gm1/gm3)1 + 2gm1rds5
≈ - gds52gm3
Common-Mode Rejection Ratio (CMRR):
CMRR = |vo1/vid||vo1/vic| =
gm1/2gm3gds5/2gm3 = gm1rds5
How could you easily increase the CMRR of this differential amplifier?
+
-vic
vgs1+ -
2rds5 rds1
gm1vgs1
rds3 gm31
+
-vo1
Fig. 330-06
Chapter 5 – Section 2 (5/2/04) Page 5.2-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Response of the Differential AmplifierBack to the current mirror load differential amplifier:
gm31gm1vgs1 rds2gm2vgs2
i3
i3
+
-
+
-
+G2
vid
vgs1 vgs2
G1
C1
-
S1=S2=S3=S4
rds4
C3C2
+
-
vout
D1=G3=D3=G4 D2=D4iout'
Fig. 330-07
M1 M2
M3 M4
VDD
M5
vout
-
+
VBias
vidCL
Cbd1
Cbd2
Cbd3 Cbd4
Cgd2Cgd1
Cgs3+Cgs4
Cgd4
Ignore the zeros that occur due to Cgd1, Cgd2 and Cgd4.C1 = Cgd1 + Cbd1 + Cbd3 + Cgs3 + Cgs4,C2 = Cbd2 + Cbd4 + Cgd2 + CL and C3 = Cgd4If C3 ≈ 0, then we can write
Vout(s) ≈ gm1
gds2 + gds4
gm3
gm3 + sC1 Vgs1(s) - Vgs2(s)
ω2
s + ω2 where ω2 ≈
ggs2 + gds4C2
If we further assume that gm3/C1 >> (gds2+gds4)/C2 = ω2then the frequency response of the differential amplifier reduces to
Vout(s)Vid(s) ≅
gm1
gds2 + gds4
ω2
s + ω2(A more detailed analysis will be made in Chapter 6)
Chapter 5 – Section 2 (5/2/04) Page 5.2-15
CMOS Analog Circuit Design © P.E. Allen - 2004
An Intuitive Method of Small Signal AnalysisSmall signal analysis is used so often in analog circuit design that it becomes desirable tofind faster ways of performing this important analysis.Intuitive Analysis (or Schematic Analysis)Technique:1.) Identify the transistor(s) that convert the input voltage to current (these transistorsare called transconductance transistors).2.) Trace the currents to where they flow into an equivalent resistance to ground.3.) Multiply this resistance by the current to get the voltage at this node to ground.4.) Repeat this process until the output is reached.Simple Example:
vin
vout
VDD
R1
gm1vin
VDD
vo1 gm2vo1
R2M1
M2
Fig. 5.2-10C
vo1 = -(gm1vin) R1 → vout = -(gm2vo1)R2 → vout = (gm1R1gm2R2)vin
Chapter 5 – Section 2 (5/2/04) Page 5.2-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Intuitive Analysis of the Current-Mirror Load Differential Amplifier
VBias
M1 M2
M3 M4
VDD
M5
vid+
- +
-vout
gm2vid
-
+
Fig. 5.2-11
2vid2
2gm1vid
2
gm1vid2
gm1vid2
+ -vid
rout
1.) i1 = 0.5gm1vid and i2 = -0.5gm2vid2.) i3 = i1 = 0.5gm1vid3.) i4 = i3 = 0.5gm1vid
4.) The resistance at the output node, rout, is rds2||rds4 or 1
gds2 + gds4
5.) ∴ vout = (0.5gm1vid+0.5gm2vid )rout =gm1vin
gds2+gds4 = gm2vin
gds2+gds4 ⇒ voutvin =
gm1gds2+gds4
Chapter 5 – Section 2 (5/2/04) Page 5.2-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Some Concepts to Help Extend the Intuitive Method of Small-Signal Analysis1.) Approximate the output resistance of any cascode circuit as
Rout ≈ (gm2rds2)rds1where M1 is a transistor cascoded by M2.
2.) If there is a resistance, R, in series with the source of the transconductance transistor,let the effective transconductance be
gm(eff) = gm
1+gmR
Proof:gm2(eff)vin
vin
VBias
M2
M1 vinrds1
M2
gm2(eff)vin gm2vgs2
vgs2
vin
+ -
rds1
iout
Small-signal model
Fig. 5.2-11A
∴ vgs2 = vg2 - vs2 = vin - (gm2rds1)vgs2 ⇒ vgs2 = vin
1+gm2rds1
Thus, iout = gm2vin
1+gm2rds1 = gm2(eff) vin
Chapter 5 – Section 2 (5/2/04) Page 5.2-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Slew Rate of the Differential AmplifierSlew Rate (SR) = Maximum output-voltage rate (either positive or negative)
It is caused by, iOUT = CL dvOUT
dt . When iOUT is a constant, the rate is a constant.
Consider the following current-mirror load, differential amplifiers:
CL
VBias
ISS
M1 M2
M3 M4
VDD
M5
vGS1+
-vGS2
+-
vG2
-
vOUT
iOUT
vG1
-
iD1 iD2
iD3 iD4
-
+
CL
VBias IDD
M1 M2
M3 M4
VDD
M5
vSG1
+
-vSG2
+
-
vG2
-
vOUT
iOUT
vG1
-
iD1 iD2
iD3 iD4
-
+
Fig. 5.2-11B
++
Note that slew rate can only occur when the differential input signal is large enough tocause ISS (IDD) to flow through only one of the differential input transistors.
SR = ISSCL =
IDDCL ⇒ If CL = 5pF and ISS = 10µA, the slew rate is SR = 2V/µs.
(For the BJT differential amplifier slewing occurs at ±100mV whereas for the MOSFETdifferential amplifier it can be ±2V or more.)
Chapter 5 – Section 2 (5/2/04) Page 5.2-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Noise Analysis of the Differential Amplifier
VBias
M1 M2
M3 M4
VDD
M5
Vout
ito2
Fig. 5.2-11C
en12
en42en32
en22 eeq2
VBias
VDD
M5
M1 M2
M3 M4
M5
vOUT
* *
* *
*
Solve for the total output-noise current to get,ito 2 = gm1
2en12 + gm2
2en22 + gm3
2en32 + gm4
2en42
This output-noise current can be expressed in terms of an equivalent input noise voltage,eeq2, given as
ito2 = gm12eeq
2
Equating the above two expressions for the total output-noise current gives,
eeq2 = en1
2 + en22 +
gm3
gm1 2 en3
2 + en42
1/f Noise (en12=en2
2 and en32=en4
2): Thermal Noise (en12=en2
2 and en32=en4
2):
eeq(1/f)=2BP
fW1L1 1 +
K’N BN
K’PBP
L1
L3
2 eeq(th)=
16kT
3[2K'1(W/L)1I1]1/2
1+
W3L1K'3
L3W1K'11/2
Chapter 5 – Section 2 (5/2/04) Page 5.2-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Current-Source Load Differential AmplifierGives a truly balanced differential amplifier.
VDD
IBias
M1 M2
M3 M4
M5
X2
I1 I2
I3 I4
v1 v2
v3 v4
M6
M7X1
X1X1
X1
X1 X1
Fig. 5.2-12
I5
Also, the upper input common-mode range is extended.However, a problem occurs if I1 ≠I3 or if I2 ≠ I4.
I1I3
VDS1<VDS(sat) VDD0
0
Current
I1I3
VSD3<VSD(sat) VDD0
0
Current
Fig. 5.2-13 (a.) I1>I3. (b.) I3>I1.
vDS1 vDS1
Chapter 5 – Section 2 (5/2/04) Page 5.2-21
CMOS Analog Circuit Design © P.E. Allen - 2004
A Differential-Output, Differential-Input AmplifierProbably the best way to solve the current mismatch problem is through the use ofcommon-mode feedback.Consider the following solution to the previous problem.
v1M1 M2
M3 M4
M5
VDD
VSS
IBias
VCM
v4v3
v2
MC2A
MC2B
MC1
MC3
MC4
MC5MB
I3 I4
IC4IC3
Fig. 5.2-14
Common-mode feed-back circuit
Self-resistancesof M1-M4
Operation:• Common mode output voltages are sensed at the gates of MC2A and MC2B and
compared to VCM.
• The current in MC3 provides the negative feedback to drive the common mode outputvoltage to the desired level.
• With large values of output voltage, this common mode feedback scheme has flaws.
Chapter 5 – Section 2 (5/2/04) Page 5.2-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Common-Mode Stabilization of the Diff.-Output, Diff.-Input Amplifier - ContinuedThe following circuit avoids the large differential output signal swing problems.
v1M1 M2
M3 M4
M5
VDD
VSS
IBias
VCM
v4v3
v2MC2
RCM1
MC1
MC3
MC4
MC5MB
I3 I4
IC4IC3
Fig. 5.2-145
Common-mode feed-back circuit
Self-resistancesof M1-M4
RCM2
Note that RCM1 and RCM2 must not load the output of the differential amplifier.
Chapter 5 – Section 2 (5/2/04) Page 5.2-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Design of a CMOS Differential Amplifier with a Current Mirror LoadDesign Considerations:
Constraints SpecificationsPower supplyTechnologyTemperature
Small-signal gainFrequency response (CL)
ICMRSlew rate (CL)
Power dissipation Relationships
Av = gm1Rout
ω-3dB = 1/RoutCL
VIC(max) = VDD - VSG3 + VTN1
VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
SR = ISS/CL
Pdiss = (VDD+|VSS|)xAll dc currents flowing from VDD or to VSS
ALA20
-
+vin M1 M2
M3 M4
M5
vout
VDD
VSS
VBias
CL
I5
Chapter 5 – Section 2 (5/2/04) Page 5.2-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Design of a CMOS Differential Amplifier with a Current Mirror Load - Continued
Schematic-wise, the design procedure is illustrated asshown:
Procedure:1.) Pick ISS to satisfy the slew rate knowing CL orthe power dissipation2.) Check to see if Rout will satisfy the frequencyresponse, if not change ISS or modify circuit
3.) Design W3/L3 (W4/L4) to satisfy the upper ICMR
4.) Design W1/L1 (W2/L2) to satisfy the gain
5.) Design W5/L5 to satisfy the lower ICMR
6.) Iterate where necessaryALA20
-
+vin M1 M2
M3 M4
M5
vout
VDD
VSS
VBias+
-
CL
VSG4+
-
gm1Rout
Min. ICMR I5I5 = SR·CL,
ω-3dB, Pdiss
Max. ICMR
Chapter 5 – Section 2 (5/2/04) Page 5.2-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 5.2-2 - Design of a MOS Differential Amp. with a Current Mirror LoadDesign the currents and W/L values of the current mirror load MOS differential amplifierto satisfy the following specifications: VDD = -VSS = 2.5V, SR ≥ 10V/µs (CL=5pF), f-3dB≥ 100kHz (CL=5pF), a small signal gain of 100V/V, -1.5V≤ICMR≤2V and Pdiss ≤ 1mW.Use the parameters of KN’=110µA/V2, KP’=50µA/V2, VTN=0.7V, VTP=-0.7V,λN=0.04V-1 and λP=0.05V-1.Solution1.) To meet the slew rate, ISS ≥ 50µA. For maximum Pdiss, ISS ≤ 200µA.
2.) f-3dB of 100kHz implies that Rout ≤ 318kΩ. Therefore Rout = 2
(λN+λP)ISS ≤ 318kΩ
∴ ISS ≥ 70µA Thus, pick ISS = 100µA3.) VIC(max) = VDD - VSG3 + VTN1 → 2V = 2.5 - VSG3 + 0.7
VSG3 = 1.2V = 2·50µA
50µA/V2(W3/L3) + 0.7
∴ W3L3 =
W4L4 =
2(0.5)2 = 8
4.) 100=gm1Rout=gm1
gds2+gds4 = 2·110µA/V2(W1/L1)
(0.04+0.05) 50µA = 23.31W1L1 →
W1 L1=
W2 L2 =18.4
Chapter 5 – Section 2 (5/2/04) Page 5.2-26
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 5.2-2 - Continued
5.) VIC(min) = VSS +VDS5(sat)+VGS1 → -1.5 = -2.5+VDS5(sat)+2·50µA
110µA/V2(18.4) + 0.7
VDS5(sat) = 0.3 - 0.222 = 0.0777 ⇒ W5 L5 =
2ISSKN’VDS5(sat)2 = 17.35
We probably should increase W1/L1 to reduce VGS1 and allow for a variation in VTN. Ifwe choose W1/L1 = 40, then VDS5(sat) = 0.149V and W5/L5 = 9. (Larger than specifiedgain should be okay.)
Chapter 5 – Section 3 (5/2/04) Page 5.3-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 5.3 - CASCODE AMPLIFIER
Why Use the Cascode Amplifier?• Can provide higher output resistance and larger gain if the load is also high resistance.• It reduces the Miller effect when the driving source has a large source resistance.
+vIN
-
+
vOUT
-
M2
M1
M3
VDD
VGG3
VGG2Cgd1
Rs2+
-
v1
Fig. 5.3-1
RS
vS
The Miller effect causes Cgd1 to be increased by the value of 1 + (v1/vin) and appear inparallel with the gate-source of M1 causing a dominant pole to occur.The cascode amplifier eliminates this dominant pole by keeping the value of v1/vinsmall by making the value of R2 to be approximately 2/gm2.
Chapter 5 – Section 3 (5/2/04) Page 5.3-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Large-Signal Characteristics of the Cascode Amplifier
0 1 2 3 4 5
I D (
mA
)
vOUT
0 1 2 3 4 5v O
UT
vIN
M2
M1
vIN
vOUT
ID
5V
+-
+
-
W3L3
=2µm1µm
W1L1
= 2µm1µm
Fig. 5.3-2
C
M3
2.3V
A B CD
E
G H
I K
F
J1
0
2
3
4
5
M3 saturated
EHIK
J
M3 active
vIN=5.0VvIN=4.0V
vIN=4.5V
vIN=1.0V
vIN=1.5V
vIN=2.0V
vIN=2.5V
0.0
0.1
0.2
0.3
0.4
0.5vIN=3.5VvIN=3.0V
D
A,B
G F
M2 activeM2 saturated
M1 sat-urated
M1active
3.4V
W2L2
= 2µm1µm
M3
M1 sat. when VGG2-VGS2 ≥ VGS1-VT → vIN ≤ 0.5(VGG2+VTN) where VGS1=VGS2M2 sat. when VDS2≥VGS2-VTN → vOUT-VDS1≥VGG2-VDS1-VTN → vOUT ≥VGG2-VTNM3 is saturated when VDD-vOUT ≥ VDD - VGG3 - |VTP| → vOUT ≤ VGG3 + |VTP|
Chapter 5 – Section 3 (5/2/04) Page 5.3-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Large-Signal Voltage Swing Limits of the Cascode AmplifierMaximum output voltage, vOUT(max):
vOUT(max) = VDD
Minimum output voltage, vOUT(min):
Referencing all potentials to the negative power supply (ground in this case), we mayexpress the current through each of the devices, M1 through M3, as
iD1 = β1
(VDD - VT1)vDS1 - v
2DS12 ≈ β1(VDD - VT1)vDS1
iD2 = β2
(VGG2 - vDS1 - VT2)(vOUT - vDS1) - (vOUT - vDS1)2
2≅ β2(VGG2 - vDS1 - VT2)(vOUT - vDS1)
and
iD3 = β3
2 (VDD − VGG3 − |VT3|)2
where we have also assumed that both vDS1 and vOUT are small, and vIN = VDD. Solving for vOUT by realizing that iD1 = iD2 = iD3 and β1 = β2 we get,
vOUT(min) = β32β2 (VDD − VGG3 − |VT3|)2
1
VGG2 − VT2 + 1
VDD − VT1
Chapter 5 – Section 3 (5/2/04) Page 5.3-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 5.3-1 - Calculation of the Min. Output Voltage for the Cascode Amplifier(a.) Assume the values and parameters used for the cascode configuration plotted in theprevious slide on the voltage transfer function and calculate the value of vOUT(min).
(b.) Find the value of vOUT(max) and vOUT(min) where all transistors are in saturation.
Solution(a.) Using the previous result gives,
vOUT(min) = 0.50 volts.
We note that simulation gives a value of about 0.75 volts. If we include the influence ofthe channel modulation on M3 in the previous derivation, the calculated value is 0.62volts which is closer. The difference is attributable to the assumption that both vDS1 andvOUT are small.
(b.) The largest output voltage for which all transistors of the cascode amplifier are insaturation is given as
vOUT(max) = VDD - VSD3(sat)
and the corresponding minimum output voltage isvOUT(min) = VDS1(sat) + VDS2(sat) .
For the cascode amplifier of Fig. 5.3-2, these limits are 3.0V and 2.7V.Consequently, the range over which all transistors are saturated is quite small for a 5Vpower supply.
Chapter 5 – Section 3 (5/2/04) Page 5.3-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Midband Performance of the Cascode AmplifierSmall-signal model:
gm1vgs1 rds1
+
-vout
vin =vgs1
rds2
rds3
gm2vgs2= -gm2v1
+
-
Small-signal model of cascode amplifier neglecting the bulk effect on M2.
+
-
v1
G1 D1=S2 D2=D3
S1=G2=G3
gm1vin rds1
+
-vout
vin
rds2
rds3
+
-
+
-
v1
G1 D1=S2 D2=D3
1gm2
C2 gm2v1 C3
Simplified equivalent model of the above circuit. Fig. 5.3-3
C1
Using nodal analysis, we can write,[gds1 + gds2 + gm2]v1 − gds2vout = −gm1vin
−[gds2 + gm2]v1 + (gds2 + gds3)vout = 0
Solving for vout/vin yields
voutvin
= −gm1(gds2 + gm2)
gds1gds2 + gds1gds3 + gds2gds3 + gds3gm2 ≅
−gm1gds3
= − 2K'1W1L1IDλ23
The small-signal output resistance is,rout = [rds1 + rds2 + gm2rds1rds2]||rds3 ≅ rds3
Chapter 5 – Section 3 (5/2/04) Page 5.3-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Analysis of the Cascode Amplifier - ContinuedIt is of interest to examine the voltage gain of v1/vin. From the previous nodal equations,
v1vin
= −gm1(gds2+gds3)
gds1gds2+gds1gds3+gds2gds3+gds3gm2 ≈
gds2+gds3
gds3
−gm1
gm2 ≅
−2gm1gm2
= −2 W1L2L1W2
If the W/L ratios of M1 and M2 are equal and gds2 = gds3, then v1/vin is approximately −2.Why is this gain -2 instead of -1?
Consider the small-signal model looking into thesource of M2:The voltage loop is written as,
vs2 = (i1 - gm2vs2)rds2 + i1rds3
= i1(rds2 + rds3) - gm2 rds2vs2 Solving this equation for the ratio of vs2 to i1gives
Rs2 = vs2i1 =
rds2 + rds31 + gm2rds2
We see that Rs2 equals 2/gm2 if rds2 ≈ rds3. Thus, if gm1 ≈ gm2, the voltage gain v1/vin ≈ -2.
Note that:rds3 =0 that Rs2≈1/gm2 or rds3=rds2 that Rs2≈2/gm2 or rds3≈rds2gmrds that Rs2≈rds!!!
Principle: The small-signal resistance looking into the source of a MOSFET depends onthe resistance connected from the drain of the MOSFET to ac ground.
rds2rds3
gm2vs2
vs2
Rs2i1
iA
iB
Fig. 5.3-4
Chapter 5 – Section 3 (5/2/04) Page 5.3-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Response of the Cascode AmplifierSmall-signal model (RS = 0):whereC1 = Cgd1,
C2 = Cbd1+Cbs2+Cgs2, and
C3 = Cbd2+Cbd3+Cgd2+Cgd3+CLThe nodal equations now become:
(gm2 + gds1 + gds2 + sC1 + sC2)v1 − gds2vout = −(gm1 − sC1)vinand
−(gds2 + gm2)v1 + (gds2 + gds3 + sC3)vout = 0
Solving for Vout(s)/Vin(s) gives,
Vout(s)Vin(s) =
1
1 + as + bs2
−(gm1 − sC1)(gds2 + gm2)
gds1gds2 + gds3(gm2 + gds1 + gds2)where
a = C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3)
gds1gds2 + gds3(gm2 + gds1 + gds2)and
b = C3(C1 + C2)
gds1gds2 + gds3(gm2 + gds1 + gds2)
gm1vin rds1
+
-vout
vin
rds2
rds3
+
-
+
-
v1
G1 D1=S2 D2=D3
1gm2
C2 gm2v1 C3
Fig. 5.3-4A
C1
Chapter 5 – Section 3 (5/2/04) Page 5.3-8
CMOS Analog Circuit Design © P.E. Allen - 2004
A Simplified Method of Finding an Algebraic Expression for the Two PolesAssume that a general second-order polynomial can be written as:
P(s) = 1 + as + bs2 =
1 − s
p1
1 − s
p2 = 1 − s
1
p1 +
1p2
+ s2
p1p2Now if |p2| >> |p1|, then P(s) can be simplified as
P(s) ≈ 1 − s
p1 +
s2p1p2
Therefore we may write p1 and p2 in terms of a and b as
p1 = −1a and p2 =
−ab
Applying this to the previous problem gives,
p1 = −[gds1gds2 + gds3(gm2 + gds1 + gds2)]
C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3) ≈ −gds3
C3
The nondominant root p2 is given as
p2 = −[C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3)]
C3(C1 + C2) ≈ −gm2
C1 + C2
Assuming C1, C2, and C3 are the same order of magnitude, and gm2 is greater than gds3,then |p1| is smaller than |p2|. Therefore the approximation of |p2| >> |p1| is valid.
Note that there is a right-half plane zero at z1 = gm1/C1.
Chapter 5 – Section 3 (5/2/04) Page 5.3-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Driving Amplifiers from a High Resistance Source - The Miller EffectExamine the frequency
response of a current-sourceload inverter driven from ahigh resistance source:
Assuming the input is Iin,the nodal equations are, [G1 + s(C1 + C2)]V1 − sC2Vout = Iin and (gm1−sC2)V1+[G3+s(C2+C3)]Vout = 0where G1 = Gs (=1/Rs), G3 = gds1 + gds2, C1 = Cgs1, C2 = Cgd1 and C3 = Cbd1+Cbd2 + Cgd2.Solving for Vout(s)/Vin(s) gives
Vout(s)Vin(s) =
(sC2−gm1)G1G1G3+s[G3(C1+C2)+G1(C2+C3)+gm1C2]+(C1C2+C1C3+C2C3)s2
or
Vout(s)Vin(s) =
−gm1
G3
[1−s(C2/gm1)]1+[R1(C1+C2)+R3(C2+C3)+gm1R1R3C2]s+(C1C2+C1C3+C2C3)R1R3s2
Assuming that the poles are split allows the use of the previous technique to get,
p1 = −1
R1(C1+C2)+R3(C2+C3)+gm1R1R3C2 ≅
−1gm1R1R3C2
andp2 ≅ −gm1C2
C1C2+C1C3+C2C3The Miller effect has caused the input pole, 1/R1C1, to be decreased by a value of gm1R3.
vin Rs
VGG2
VDD
vout
M2
M1
Rs
RsRs
VinC1
C2
C3 R3
C1 ≈ Cgs1
C2 = Cgd1
C3 = Cbd1 + Cbd2 + Cgd2
R3 = rds1||rds2
+
-
Vout
Fig. 5.3-5
+
-
V1gm1V1
Chapter 5 – Section 3 (5/2/04) Page 5.3-10
CMOS Analog Circuit Design © P.E. Allen - 2004
How does the Cascode Amplifier Solve the Miller Effect?The dominant pole of the inverting amplifier with a large source resistance was found tobe
p1(inverter) = −1
R1(C1+C2)+R3(C2+C3)+gm1R1R3C2
Now if a cascode amplifier is used, R3, can be approximated as 2/gm of the cascodingtransistor (assuming the drain sees an rds to ac ground).
∴ p1(cascode) = −1
R1(C1+C2)+
2
gm (C2+C3)+gm1R1
2
gm C2
= −1
R1(C1+C2)+
2
gm (C2+C3)+2R1C2
≈ −1
R1(C1+3C2)
Thus we see that p1(cascode) >> p1(inverter).
Chapter 5 – Section 3 (5/2/04) Page 5.3-11
CMOS Analog Circuit Design © P.E. Allen - 2004
High Gain and High Output Resistance Cascode AmplifierIf the load of the cascodeamplifier is a cascodecurrent source, then bothhigh output resistanceand high voltage gain isachieved.
The output resistance is,
rout ≅ [gm2rds1rds2][gm3rds3rds4] = I -1.5D
λ1λ2
2K'2(W/L)2 +
λ3λ4
2K'3(W/L)3
Knowing rout, the gain is simply
Av = −gm1rout ≅ −gm1[gm2rds1rds2][gm3rds3rds4] ≅ 2K'1(W/L)1I
-1D
λ1λ2
2K'2(W/L)2 +
λ3λ4
2K'3(W/L)3
VDD
VGG4
VGG3
VGG2
vin
vout
Rout
M3
M4
M2
M1gm1vin
rds1
gm2v1 gmbs2v1 rds2 gm3v4 gmbs3v4 rds3
rds4v1
+
-
v4
+
-
vout
+
-
G1 D1=S2 D4=S3
D2=D3
G2=G3=G4=S1=S4
vin
+
-
Fig. 5.3-6
Chapter 5 – Section 3 (5/2/04) Page 5.3-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 5.3-2 - Comparison of the Cascode Amplifier PerformanceCalculate the small-signal voltage gain, output resistance, the dominant pole, and the
nondominant pole for the low-gain, cascode amplifier and the high-gain, cascodeamplifier. Assume that ID = 200 microamperes, that all W/L ratios are 2µm/1µm, andthat the parameters of Table 3.1-2 are valid. The capacitors are assumed to be: Cgd = 3.5fF, Cgs = 30 fF, Cbsn = Cbdn = 24 fF, Cbsp = Cbdp = 12 fF, and CL = 1 pF.
SolutionThe low-gain, cascode amplifier has the following small-signal performance:
Av = −37.1V/VRout = 125kΩp1 ≈ -gds3/C3 → 1.22 MHzp2 ≈ gm2/(C1+C2) → 605 MHz.
The high-gain, cascode amplifier has the following small-signal performance:Av = −414V/VRout = 1.40 MΩp1 ≈ 1/RoutC3 → 108 kHzp2 ≈ gm2/(C1+C2) → 579 MHz
(Note at this frequency, the drain of M2 is shorted to ground by the load capacitance, CL)
Chapter 5 – Section 3 (5/2/04) Page 5.3-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Designing Cascode AmplifiersPertinent design equations for the simple cascode amplifier.
+vIN
-
+
vOUT
-
M2
M1
M3
VDD
VGG3
VGG2
Fig. 5.3-7
I
vOUT(min) =VDS1(sat) + VDS2(sat)
2IKN(W1/L1)
vOUT(max) = VDD - VSD3(sat)
2IKN(W2/L2)
+=
2IKP(W3/L3)
=VDD -
I = PdissVDD
= (SR)·Cout
|Av| = gm1gds3
= 2KN(W1/L1)λP
2I
I = KPW3
2L3(VDD - VGG3-|VTP|)2
VGG2 = VDS1(sat) + VGS2
Chapter 5 – Section 3 (5/2/04) Page 5.3-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 5.3-3 - Design of a Cascode AmplifierThe specs for a cascode amplifier are Av = -50V/V, vOUT(max) = 4V, vOUT(min) = 1.5V,VDD=5V, and Pdiss=1mW. The slew rate with a 10pF load should be 10V/µs or greater.Solution
The slew rate requires a current greater than 100µA while the power dissipationrequires a current less than 200µA. Compromise with 150µA. Beginning with M3,
W3L3
= 2I
KP[VDD-vOUT(max)]2 = 2·15050(1)2 = 6
From this find VGG3: VGG3 = VDD - |VTP| - 2I
KP(W3/L3) = 5 - 1 - 2·15050·6 = 3V
Next, W1L1
= (Avλ)2I
2KN =
(50·0.05)2(150)2·110 = 2.73
To design W2/L2, we will first calculate VDS1(sat) and use the vOUT(min) specification to
define VDS2(sat). VDS1(sat) = 2I
KN(W1/L1) = 2·150
110·4.26 = 0.8V
Subtracting this value from 1.5V gives VDS2(sat) = 0.7V.
∴W2L2
= 2I
KNVDS2(sat)2 = 2·150
110·0.72 = 5.57
Finally, VGG2 = VDS1(sat) + 2I
KN(W2/L2) + VTN = 0.8V+ 0.7V + 0.7V = 2.2V
Chapter 5 – Section 4 (5/2/04) Page 5.4-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 5.4 - CURRENT AMPLIFIERS
What is a Current Amplifier?• An amplifier that has a defined output-input current relationship• Low input resistance• High output resistanceApplication of current amplifiers:
iS RS RL
ii io
CurrentAmplifier
Ai iS RS
RL
iiio
CurrentAmplifier
Aiii -
+
Single-ended input. Differential input. Fig. 5.4-1
RS >> Rin and Rout >> RL
Advantages of current amplifiers:• Currents are not restricted by the power supply voltages so that wider dynamic
ranges are possible with lower power supply voltages.• -3dB bandwidth of a current amplifier using negative feedback is independent of the
closed loop gain.
Chapter 5 – Section 4 (5/2/04) Page 5.4-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Response of a Current Amplifier with Current FeedbackConsider the following current amplifier with resistivenegative feedback applied.
Assuming that the small-signal resistance looking intothe current amplifier is much less than R1 or R2,
io = Ai(i1-i2) = Ai
vin
R1 - io
Solving for io gives
io =
Ai
1+Ai vinR1
→ vout = R2io = R2R1
Ai
1+Ai vin
If Ai(s) = Ao
sωA
+ 1 , then
voutvin =
R2R1
1
1+ 1
Ai(s) =
R2R1
Ao
sωA +(1+Ao)
= R2R1
Ao
1+Ao
1
sωA(1+Ao) +1
∴ ω-3dB = ωA(1+Ao)
R2i2io
Aii1
-
+R1 vout
vin
Fig. 5.4-2
Chapter 5 – Section 4 (5/2/04) Page 5.4-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Bandwidth Advantage of a Current Feedback AmplifierThe unity-gainbandwidth is,
GB = |Av(0)| ω-3dB = R2Ao
R1(1+Ao) · ωA(1+Ao) = R2R1 Ao·ωA =
R2R1 GBi
where GBi is the unity-gainbandwidth of the current amplifier.
Note that if GBi is constant, then increasing R2/R1 (the voltage gain) increases GB.
Illustration:
Ao dB
ωA
R2R1
>1
R2R1
GB1 GB2
Current Amplifier
0dB
Voltage Amplifier,
log10(ω)
Magnitude dB
Fig. 7.2-10
(1+Ao)ωA
GBi
= K
R1Voltage Amplifier, > KR2
1+AoAo dB
1+AoAo dBK
Note that GB2 > GB1 > GBiThe above illustration assumes that the GB of the voltage amplifier realizing the voltagebuffer is greater than the GB achieved from the above method.
Chapter 5 – Section 4 (5/2/04) Page 5.4-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Current Amplifier using the Simple Current MirrorVDD VDD
I1 I2iin iout
M1 M2
Current Amplifier
iin iout
gm1vin
+
-
vinrds1 gm2vin rds2C1 C3
RL
Fig. 5.4-3
C2
≈ 0R
Rin = 1
gm1 Rout =
1λ1Io
and Ai = W2/L2
W1/L1 .
Frequency response:
p1 = -(gm1+gds1)
C1+C2 =
-(gm1+gds1)Cbd1+Cgs1+Cgs2+Cgd2
≈ -gm1
Cbd1+Cgs1+Cgs2+Cgd2
Note that the bandwidth can be almost doubled by including the resistor, R.(R removes Cgs1 from p1)
Chapter 5 – Section 4 (5/2/04) Page 5.4-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 5.4-1- Performance of a Simple Current Mirror as a Current AmplifierFind the small-signal current gain, Ai, the input resistance, Rin, the output resistance,
Rout, and the -3dB frequency in Hertz for the current amplifier of Fig. 5.4-3(a) if 10I1 = I2= 100µA and W2/L2 = 10W1/L1 = 10µm/1µm. Assume that Cbd1 = 10fF, Cgs1 = Cgs2 =100fF, and Cgs2 = 50fF.
SolutionIgnoring channel modulation and mismatch effects, the small-signal current gain,
Ai = W2/L2W1/L1 ≈ 10A/A.
The small-signal input resistance, Rin, is approximately 1/gm1 and is
Rin ≈ 1
2KN(1/1)10µA = 1
46.9µS = 21.3kΩ
The small-signal output resistance is equal to
Rout = 1
λNI2 = 250kΩ.
The -3dB frequency is
ω-3dB = 46.9µS260fF = 180.4x106 radians/sec. → f-3dB = 28.7 MHz
Chapter 5 – Section 4 (5/2/04) Page 5.4-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Self-Biased Cascode Current Mirror Implementation of a Current AmplifierVDD VDD
I1 I2iin iout
Current Amplifier
R
M1 M2
M3 M4
+
-
vout
+
-
vin
Fig. 5.4-4
Rin ≈ R + 1
gm1, Rout ≈ rds2gm4rds4, and Ai =
W2/L2
W1/L1
Chapter 5 – Section 4 (5/2/04) Page 5.4-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 5.4 -2 - Current Amplifier Implemented by the Self-Biased, CascodeCurrent Mirror
Assume that I1 and I2 of the self-biased cascode current mirror are 100µA. R hasbeen designed to give a VON of 0.1V. Thus R = 1kΩ. Find the value of Rin, Rout, and Ai ifthe W/L ratios of all transistors are 182µm/1µm.Solution
The input resistance requires gm1 which is 2·110·182·100 = 2mS
∴ Rin ≈ 1000Ω + 500Ω = 1.5kΩ
From our knowledge of the cascode configuration, the small signal output resistanceshould be
Rout ≈ gm4rds4rds2 = (2001µS)(250kΩ)(250kΩ) = 125MΩ
Because VDS1 = VDS2, the small-signal current gain is
Ai = W2/L2W1/L1
= 1
Simulation results using the level 1 model for this example giveRin=1.497kΩ, Rout = 164.7MΩ and Ai = 1.000 A/A.
Chapter 5 – Section 4 (5/2/04) Page 5.4-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Low-Input Resistance Current AmplifierTo decrease Rin below 1/gmrequires the use of negative,shunt feedback. Considerthe following example.
Feedback concept:Input resistance without feedback ≈ rds1.
Loop gain ≈
gm1
gds1
gm3
gds3 assuming that the resistances of I1 and I3 are very large.
∴ Rin = Rin(no fb.)
1 + Loop gain ≈ rds1
gm1rds1gm3rds3 = 1
gm1gm3rds3
Small signal analysis:iin = gm1vgs1 - gds1vgs3
and vgs3 = -vin vgs1 = vin - (gm3 vgs3rds3) = vin(1+gm3rds3)
∴ iin = gm1(1+gm3rds3)vin + gds1vin ≈ gm1gm3rds3vin ⇒ Rin ≈ 1
gm1gm3rds3
VGG3
M1
M3
M2
VDD VDD
I1 I2 ioutiin
I3
Current Amplifier
gm1vgs1 rds1rds3
gm3vgs3 +
-vgs1
+
-
vgs3
+
-
vin
iin
Fig. 5.4-5
i = 0
Chapter 5 – Section 4 (5/2/04) Page 5.4-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Differential-Input, Current AmplifiersDefinitions for the differential-mode, iID, and common-mode, iIC, input currents of thedifferential-input current amplifier.
+
-
i1
i2iID
iIC2
iIC2
iO
Fig. 5.4-6
iO = AIDiID ± AICiIC = AID(i1 - i2) ± AIC
i1+i2
2Implementations:
I I2I
VDD VDD VDD
i1
i2 i2
iO
i1-i2M1 M2 M3 M4
iO
VDD
i1 i2M1 M2
M3 M4
M5 M6
VGG1
VGG2
Fig. 5.4-7
Chapter 5 – Section 4 (5/2/04) Page 5.4-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary• Current amplifiers have a low input resistance, high output resistance, and a defined
output-input current relationship• Input resistances less than 1/gm require feedback
However, all feedback loops have internal poles that cause the benefits of negativefeedback to vanish at high frequencies.In addition, these feedback loops can have a slow time constant from a pole-zero pair.
• Voltage amplifiers using a current amplifier have high values of gain-bandwidth• Current amplifiers are useful at low power supplies and for switched currentapplications
Chapter 5 – Section 5 (5/2/04) Page 5.5-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 5.5 - OUTPUT AMPLIFIERS
General Considerations of Output AmplifiersRequirements:1.) Provide sufficient output power in the form of voltage
or current.2.) Avoid signal distortion.3.) Be efficient4.) Provide protection from abnormal conditions (short
circuit, over temperature, etc.)Types of Output Amplifiers:1.) Class A amplifiers2.) Source followers3.) Push-pull amplifiers4.) Substrate BJT amplifiers5.) Amplifiers using negative
shunt feedback
f1(vIN)
f2(vIN)
i1
i2 RL vOUT
VDD
VSS
Buffer
vINiOUT
+
-
i1
i2=IQ iOUT
t
Cur
rent
iOUT
t
Cur
rent
i1
i2
iOUTt
Cur
rent
i1
i2
Class A
Class AB
Class B
Fig. 5.5-005
Chapter 5 – Section 5 (5/2/04) Page 5.5-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Class A AmplifiersCurrent source load inverter:
A Class A circuit has currentflow in the MOSFETs duringthe entire period of asinusoidal signal.Characteristics of Class A amplifiers:• Unsymmetrical sinking and sourcing• Linear• Poor efficiency
Efficiency = PRL
PSupply =
vOUT(peak)2
2RL(VDD-VSS)IQ =
vOUT(peak)2
2RL
(VDD -VSS)
(VDD-VSS)
2RL
=
vOUT(peak)
VDD -VSS2
Maximum efficiency occurs when vOUT(peak) = VDD = |VSS| which gives 25%.
CL RL
M2
M1
VGG2
VDD
vIN
vOUTiOUTIQ
iD1
Fig. 5.5-1
iDVDD+|VSS|
VDD
vOUT
RL
IQ
IQRL IQRLVSS
RL dominatesas the load line
VSS
Chapter 5 – Section 5 (5/2/04) Page 5.5-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Optimum Value of Load ResistorDepending on the value of RL, the signal swing can be symmetrical or asymmetrical.(This ignores the limitations of the transistor.)
Fig. 040-03
iD1
VDD+|VSS|
VDD
vDS1
RL
IQ
IQRL IQRL
Minimum RL formaximum swing
0
0
Smaller RL
Larger RL
VSS
Chapter 5 – Section 5 (5/2/04) Page 5.5-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Specifying the Performance of a Class A AmplifierOutput resistance:
rout = 1
gds1+ gds2 = 1
(λ1+λ2)ID
Current:• Maximum sinking current is,
I-OUT=
K'1W12L1 (VDD -VSS - VT1)2 - IQ
• Maximum sourcing current is,
I+OUT =
K'2W22L2 (VDD - VGG2 - |VT2|)2 ≤ IQ
Requirements:• Want rout << RL• |IOUT| > CL·SR
• |IOUT| > vOUT(peak)
RL
The maximum current is determined by both the current required to provide thenecessary slew rate (CL) and to provide a voltage across the load resistor (RL).
Imax due to RL
Imax due to RL
Imax due to CL
iOUT
t
Fig. 5.5-015
Chapter 5 – Section 5 (5/2/04) Page 5.5-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Performance of the Class A AmplifierAlthough we have considered the small-signal performance of the Class A amplifier as thecurrent source load inverter, let us include the influence of the load.The modified small-signal model:
gm1vinvin rds1 rds2 RL
+
-
+
-
voutC2
C1
Fig. 5.5-2
The small-signal voltage gain is:voutvin =
-gm1 gds1+gds2+GL
The small-signal frequency response includes:A zero at
z = gm1Cgd1
and a pole at
p = -(gds1+gds2+GL)
Cgd1+Cgd2+Cbd1+Cbd2+CL
Chapter 5 – Section 5 (5/2/04) Page 5.5-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 5.5-1 - Design of a Simple Class-A Output StageUse Table 3.1-2 to design the W/L ratios of M1 and M2 so that a voltage swing of ±2Vand a slew rate of ≅1 V/µs is achieved if RL = 20 kΩ and CL = 1000 pF. Assume VDD =|VSS| = 3V and VGG2 = 0V. Let L = 2 µm and assume that Cgd1 = 100fF.
SolutionLet us first consider the effects of RL and CL.
iOUT(peak) = ±2V/20kΩ = ±100µA and CL·SR = 10-9·106 = 1000µA
Since the slew rate current is so much larger than the current needed to meet the voltagespecification across RL, we can safely assume that all of the current supplied by theinverter is available to charge CL.
Using a value of ±1 mA,
W1L1
= 2(IOUT-+IQ)
KN’(VDD+|VSS| -VTN)2 =
4000110·(5.3)2
≈ 3µm2µm
and
W2L2
= 2IOUT+
KP’(VDD-VGG2-|VTP|)2 =
200050·(2.3)2
≈ 15µm2µm
The small-signal performance is Av = -8.21 V/V (includes RL = 20kΩ) and rout = 50kΩThe roots are, zero = gm1/Cgd1 ⇒ .59GHz and pole = 1/[(RL||rout)CL)] ⇒ -11.14kHz
Chapter 5 – Section 5 (5/2/04) Page 5.5-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Broadband Harmonic DistortionThe linearity of an amplifier can be characterized by its influence on a pure sinusoidal
input signal.Assume the input is,
Vin(ω) = Vp sin(ωt)
The output of an amplifier with distortion will be
Vout(ω) = a1Vp sin (ωt) + a2Vp sin (2ωt) +...+ anVp sin(nωt)
Harmonic distortion (HD) for the ith harmonic can be defined as the ratio of themagnitude of the ith harmonic to the magnitude of the fundamental.For example, second-harmonic distortion would be given as
HD2 = a2a1
Total harmonic distortion (THD) is defined as the square root of the ratio of the sum of allof the second and higher harmonics to the magnitude of the first or fundamental harmonic.Thus, THD can be expressed as
THD = [a
22 + a
23 +...+ a
2n]1/2
a1The distortion of the class A amplifier is good for small signals and becomes poor atmaximum output swings because of the nonlinearity of the voltage transfer curve forlarge-signal swing
Chapter 5 – Section 5 (5/2/04) Page 5.5-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Class-A Source FollowerN-Channel Source Follower Voltage transfer curve:with current sink bias:
Maximum output voltage swings:vOUT(min) ≈ VSS - VON2 (if RL is large) or vOUT(min) ≈ -IQRL (if RL is small)
vOUT(max) = VDD - VON1 (if vIN > VDD) or vOUT(max) ≈ VDD - VGS1
M3
Fig. 040-01
IQ
VDD
vIN
vOUT
iOUT
M1
M2
VSS
VSS
VDD
VSS
RL
vIN
vOUT
Fig. 040-02
VGS1
VDD-VON1
|VSS|+VON2
VDD-VON1+VGS1
|VSS|+VON2+VGS1
IQRL<|VSS|+VON2
VDD-VGS1
VDD
|VSS|
Triode
Triode
Chapter 5 – Section 5 (5/2/04) Page 5.5-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Output Voltage Swing of the FollowerThe previous results do not include the bulk effect on VT1 of VGS1.
Therefore,
VT1 = VT01 + γ[ 2|φF| -vBS- 2|φF|] ≈ VT01+γ vSB = VT01+γ1 vOUT(max)-VSS
∴ vOUT(max)-VSS ≈VDD-VSS-VON1-VT1 = VDD-VSS-VON1-VT01-γ1 vOUT(max)-VSS
Define vOUT(max)-VSS = vOUT’(max)
which gives the quadratic,
vOUT’(max)+γ1 vOUT’(max)-(VDD-VSS -VON1-VT01)=0
Solving the quadratic gives,
vOUT’(max) ≈ γ12
4 - γ12 γ12+4(VDD-VSS-VON1-VT01) +
γ12+ 4(VDD-VSS-VON1-VT01)4
If VDD = 2.5V, γN = 0.4V1/2, VTN1= 0.7V, and VON1 = 0.2V, then vOUT’(max) = 3.661V
andvOUT(max) = 3.661-2.5 = 0.8661V
Chapter 5 – Section 5 (5/2/04) Page 5.5-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Maximum Sourcing and Sinking Currents for the Source FollowerMaximum Sourcing Current (into a short circuit):We assume that the transistors are in saturation andVDD = -VSS = 2.5V , thus
IOUT(sourcing) = K’1W1
2L1 [VDD − vOUT− VT1]2-IQ
where vIN is assumed to be equal to VDD.
If W1/L1 =10 and if vOUT = 0V, then
VT1 = 1.08V ⇒ IOUT equal to 1.11 mA.
However, as vOUT increases above 0V, the current rapidly decreases.
Maximum Sinking Current:For the current sink load, the sinking current is whatever the sink is biased to provide.IOUT(sinking) = IQ
M3
Fig. 040-01
IQ
VDD
vIN
vOUT
iOUT
M1
M2
VSS
VSS
VDD
VSS
RL
Chapter 5 – Section 5 (5/2/04) Page 5.5-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Efficiency of the Source FollowerAssume that the source followerinput can swing to power supply.Plotting
iD = β2 (vIN - vOUT - VT)2
and
iD = IQ - vOUTRL
Efficiency =
PRLPSupply
=
vOUT(peak)2
2RL(VDD-VSS)IQ =
vOUT(peak)2
2RL
(VDD -VSS)
(VDD-VSS)
2RL
=
vOUT(peak)
VDD -VSS2
Maximum efficiency occurs when vOUT(peak) = VDD = |VSS| which gives 25%.
Comments:• Maximum efficiency occurs for the minimum value of RL which gives maximum swing.• Other values of RL result in less efficiency (and smaller signal swings before clipping)• We have ignored the fact that the dynamic Q point cannot travel along the full length of
the load line because of minimum and maximum voltage limits.
iD
vOUT
VT 2VT 3VT VDD-VT-VT -2VT-3VT VDD
-VT -2VT 0 VT 2VT 3VT 4VT
vIN
VDDVSS
VSS-VTVSS
IQIQRL
Fig. 040-035
IQRL = VSS
Chapter 5 – Section 5 (5/2/04) Page 5.5-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Small Signal Performance of the Source FollowerSmall-signal model:
VoutVin =
gm1gds1 + gds2 + gm1 + gmbs1+GL ≅
gm1gm1 + gmbs1+GL ≅
gm1RL1 +gm1RL
If VDD = -VSS = 2.5V, Vout = 0V, W1/L1 = 10µm/1 µm, W2/L2 = 1µm/1 µm,and ID = 500 µA, thenFor the current sink load follower (RL = ∞):
VoutVin = 0.869V/V, if the bulk effect were ignored, then
VoutVin = 0.963V/V
For a finite load, RL = 1000Ω:VoutVin = 0.512V/V
Fig. 040-04
gm1vgs1
vin rds1 rds2 RL
+
-
+
-
voutC2
C1
vgs1+ -
gmbs1vbs1
gm1vin
vin rds1 rds2 RL
+
-
+
-
voutC2
C1
vgs1+ -
gmbs1voutgm1vout
Chapter 5 – Section 5 (5/2/04) Page 5.5-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Small Signal Performance of the Source Follower - ContinuedThe output resistance is:
Rout = 1
gm1 + gmbs1 + gds1 + gds2
For the current sink load follower:Rout = 830Ω
The frequency response of the source follower:
Vout(s)Vin(s) =
(gm1 + sC1)gds1 + gds2 + gm1 + gmbs1 + GL + s(C1 + C2)
whereC1 = capacitances connected between the input and output ≈ CGS1C2 = Cbs1 +Cbd2 +Cgd2(or Cgs2) + CL
z = - gm1C1 and p ≈ -
gm1+GLC1+C2
The presence of a LHP zero leads to the possibility that in most cases the pole and zerowill provide some degree of cancellation leading to a broadband response.
Chapter 5 – Section 5 (5/2/04) Page 5.5-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Push-Pull Source FollowerCan both sink and sourcecurrent and provide a slightlylower output resistance.
Efficiency:Depends on how thetransistors are biased.• Class B - one transistorhas current flow for only 180° of the sinusoid (half period)
∴ Efficiency = PRL
PVDD =
vOUT(peak)2
2RL
(VDD -VSS)
1
2
2vOUT(peak)
πRL =
π2
vOUT(peak)VDD -VSS
Maximum efficiency occurs when vOUT(peak) =VDD and is 78.5%
• Class AB - each transistor has current flow for more than 180° of the sinusoid.Maximum efficiency is between 25% and 78.5%
VDD
vINvOUT
iOUT
M1
M2 VDD
VBias
VBias
Fig. 060-01
VDD
vIN
vOUTiOUT
M1
M2 VDDVDD
VDD
VGG
M3
M4
M5
M6
RL RL
VSS
VSS VSS VSS
VSS
VSS
Chapter 5 – Section 5 (5/2/04) Page 5.5-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of Class B and Class AB Push-Pull, Source FollowerOutput current and voltage characteristics of the push-pull, source follower (RL = 1kΩ):
-2V
-1V
0V
1V
2V
-2 -1 0 1 2Vin(V)
1mA
0mA
-1mA
vout
vG1
vG2
iD1
iD2
Class B, push-pull, source follower
-2V
-1V
0V
1V
2V
-2 -1 0 1 2Vin(V)
1mA
0mA
-1mA
vout
vG1 iD1
iD2
Class AB, push-pull, source follower Fig. 060-02
vG2
Comments:• Note that vOUT cannot reach the extreme values of VDD and VSS
• IOUT+(max) and IOUT-(max) is always less than VDD/RL or VSS/RL
• For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB
• Note that there is significant distortion at vIN =0V for the Class B push-pull follower
Chapter 5 – Section 5 (5/2/04) Page 5.5-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Performance of the Push-Pull FollowerModel:
gm1vgs1
vin rds1 rds2 RL
+
-
+
-
voutC2
C1
Fig. 060-03
vgs1+ -
gmbs1vbs1 gm2vgs2
gm1vin
vinrds1 rds2
RL
+
-
+
-
voutC2
C1
vgs1+ -
gmbs1voutgm1voutgm21
gmbs2vbs2
gm2vin gmbs2voutgm2vout
voutvin
= gm1 + gm2
gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL
Rout = 1
gds1+gds2+gm1+gmbs1+gm2+gmbs2 (does not include RL)
If VDD = -VSS = 2.5V, Vout = 0V, ID1 = ID2 = 500µA, and W/L = 20µm/2µm, Av = 0.787(RL=∞) and Rout = 448Ω.A zero and pole are located at
z = -(gm1+gm2)
C1 p =
-(gds1+gds2+gm1+gmbs1+gm2+gmbs2+GL)C1+C2
.
These roots will be high-frequency because the associated resistances are small.
Chapter 5 – Section 5 (5/2/04) Page 5.5-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Push-Pull, Common Source AmplifiersSimilar to the class A but can operate as class B providing higher efficiency.
CL RL
vIN vOUT
iOUT
VDD
VTR2
VTR1
M2
M1
Fig. 060-04VSS
Comments:• The batteries VTR1 and VTR2 are necessary to control the bias current in M1 and M2.
• The efficiency is the same as the push-pull, source follower.
Chapter 5 – Section 5 (5/2/04) Page 5.5-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Practical Implementation of the Push-Pull, Common Source Amplifier – Method 1
CL RL
vIN vOUT
iOUT
VDD
M2
M1 M3
M4
M5 M6
M7 M8
VGG3
VGG4
Fig. 060-05VSS
VGG3 and VGG4 can be used to bias this amplifier in class AB or class B operation.
Note, that the bias current in M6 and M8 is not dependent upon VDD or VSS (assumingVGG3 and VGG4 are not dependent on VDD and VSS).
Chapter 5 – Section 5 (5/2/04) Page 5.5-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Practical Implementation of the Push-Pull, Common Source Amplifier – Method 2VDD
VSS
Ib
Ib
I=2Ib
M1
M2
M3 M4
M5
M6
M7
M8 M9
M10
vin+
vin-
I=2Ib
Fig. 060-055
In steady-state, the current through M5 and M6 is 2Ib. If W4/L4 = W9/L9 and W3/L3 =W8/L8, then the currents in M1 and M2 can be determined by the following relationship:
I1 = I2 = Ib
W1/L1
W7/L7 = Ib
W2/L2
W10/L10
If vin+ goes low, M5 pulls the gates of M1 and M2 high. M4 shuts off causing all of the
current flowing through M5 (2Ib) to flow through M3 shutting off M1. The gate of M2 ishigh allowing the buffer to strongly sink current. If vin
- goes high, M6 pulls the gates ofM1 and M2 low. As before, this shuts off M2 and turns on M1 allowing strong sourcing.
Chapter 5 – Section 5 (5/2/04) Page 5.5-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of Class B and Class AB Push-Pull, Inverting AmplifierOutput current and voltage characteristics of the push-pull, inverting amplifier (RL =1kΩ):
-2V
-1V
0V
1V
2V
-2V -1V 0V 1V 2V
-2mA
-1mA
0mA
1mA
2mA
vIN
iD1
iD2
vG2
vG1
vOUT
Class B, push-pull, inverting amplifier.
-2V
-1V
0V
1V
2V
-2V -1V 0V 1V 2V
-2mA
-1mA
0mA
1mA
2mA
vIN
iD1
iD2
vG2
vG1
vOUT
Class AB, push-pull, inverting amplifier. Fig.060-06
iD1 iD2
iD2
iD1
Comments:• Note that there is significant distortion at vIN =0V for the Class B inverter
• Note that vOUT cannot reach the extreme values of VDD and VSS
• IOUT+(max) and IOUT-(max) is always less than VDD/RL or VSS/RL
• For vOUT = 0V, there is quiescent current flowing in M1 and M2 for Class AB
Chapter 5 – Section 5 (5/2/04) Page 5.5-21
CMOS Analog Circuit Design © P.E. Allen - 2004
What about the use of BJTs?
vout
CL
Q1
VDD
M2
vout
CL
Q1
VDD
M2
p-well CMOS n-well CMOS
iB
iB
Fig. 5.5-8A
M3
M3
VDD
VSS VSSVSS
Comments:• Can use either substrate or lateral BJTs.• Small-signal output resistance is 1/gm which can easily be less than 100Ω.
• Unfortunately, only PNP or NPN BJTs are available but not both on a standard CMOStechnology.
• In order for the BJT to sink (or source) large currents, the base current, iB, must belarge. Providing large currents as the voltage gets to extreme values is difficult forMOSFET circuits to accomplish.
• If one considers the MOSFET driver, the emitter can only pull to within vBE+VON of thepower supply rails. This value can be 1V or more.
We will consider the BJT as an output stage in more detail in Sec. 7.1.
Chapter 5 – Section 5 (5/2/04) Page 5.5-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Use of Negative, Shunt Feedback to Reduce the Output ResistanceConcept:
CL RL
vIN vOUT
iOUT
VDD
M2
M1Fig. 060-07
+-
+-
ErrorAmplifier
ErrorAmplifier
VSS
Rout = rds1||rds2
1+Loop Gain
Comments:• Can achieve output resistances as low as 10Ω.• If the error amplifiers are not balanced, it is difficult to control the quiescent current in
M1 and M2• Great linearity because of the strong feedback• Can be efficient if operated in class B or class AB
Chapter 5 – Section 5 (5/2/04) Page 5.5-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Simple Implementation of Neg., Shunt Feedback to Reduce the Output Resistance
CL RL
vIN vOUT
iOUT
VDD
M2
M1
Fig. 060-08
R1 R2
VSS
Loop gain ≈
R1
R1+R2
gm1+gm2
gds1+gds2+GL
∴ Rout = rds1||rds2
1+
R1
R1+R2
gm1+gm2
gds1+gds2+GL
Let R1 = R2, RL = ∞, IBias = 500µA, W1/L1 = 100µm/1µm and W2/L2 = 200µm/1µm.
Thus, gm1 = 3.316mS, gm2 = 3.162mS, rds1 = 50kΩ and rds2 = 40kΩ.
∴ Rout = 50kΩ||40kΩ
1+0.5
3316+3162
25+20 =
22.22kΩ1+0.5(143.9) = 304Ω (Rout = 5.42kΩ if RL = 1kΩ)
Chapter 5 – Section 5 (5/2/04) Page 5.5-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Quasi-Complementary Output StagesQuasi-complementary connections are used to improve the performance of the NMOS orPMOS transistor.Composite connections:
Fig. 5.5-11
G
S
D
ID1M1
Q2
ID
+
-
VSG
G
S
D
+
-VSG
IDG
S
D
ID1
M1
Q2
ID
+
-VGS
G
S
D
+
-VGS ID
NMOS Equivalent:
ID=(1+β2)ID1=(1+β2)
KP’W1
2L1 (VGS-VT)2
∴ The composite has an enhanced KN’
PMOS Equivalent:
ID=(1+β2)ID1=(1+β2)
KP’W1
2L1 (VSG-VT)2
∴ The composite has an enhanced KP’
Chapter 5 – Section 5 (5/2/04) Page 5.5-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Output Amplifiers• The objectives are to provide output power in form of voltage and/or current.• In addition, the output amplifier should be linear and be efficient.• Low output resistance is required to provide power efficiently to a small load resistance.• High source/sink currents are required to provide sufficient output voltage rate due to
large load capacitances.• Types of output amplifiers considered:
Class A amplifierSource followerClass B and AB amplifierUse of BJTsNegative shunt feedback
Chapter 5 – Section 6 (5/2/04) Page 5.6-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 5.6 - HIGH-GAIN AMPLIFIER ARCHITECTURES
High-Gain Amplifiers used in Negative Feedback CircuitsConsider the general, single-loop, negative feedback circuit:
x = either voltage or current
A = xoxi = high-gain amplifier
F = feedback networkClosed-loop gain:
Af = xoxs =
A1+AF
If AF >> 1, then,
Af = xoxs ≈
1F
Therefore, to precisely define the closed-loop gain, Af, we only need to make A large andAf becomes dependent on F which can be determined by passive elements.
A
F
xsxi xo
xf
Σ+
-
Fig. 5.6-1
Chapter 5 – Section 6 (5/2/04) Page 5.6-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Types of AmplifiersThe gain of an amplifier is given as
A = xoxi
Therefore, since x can be voltage or current, there are four types of amplifiers assummarized below.Types ofAmplifers
Voltage-controlled,current-source
Voltage-controlled,voltage-source
Current-controlled,current-source
Current-controlled,voltage-source
xi variable* Voltage Voltage Current Current
xo variable Current Voltage Current Voltage
Desired Ri Large Large Small Small
Desired Ro Large Small Large Small
* The xi , xs, and xf must all be the same type of variable, voltage or current.
Chapter 5 – Section 6 (5/2/04) Page 5.6-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Voltage-Controlled, Current-Source (VCCS) Amplifier
Gmvivi Ri Ro
RS
+
-
io
RL
VCCS
vsDifferentialAmplifier
vi+
-
SecondStage
io
VCCS Fig. 5.6-2
iovs = GM =
GmRoRi(Ri + RS)(Ro + RL)
This amplifier is sometimes called an operational transconductance amplifier (OTA).
Chapter 5 – Section 6 (5/2/04) Page 5.6-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Voltage-Controlled, Voltage-Source (VCVS) Amplifier
Avvivi Ri
Ro
RS
+
-
vo RL
VCVS
vsDifferentialAmplifier
vi+
-
SecondStage
vo
VCVS Fig. 5.6
+
-
OutputStage
vovs = AV =
AvRiRL(RS + Ri)(Ro + RL)
This amplifier is normally called an operational amplifier.
Chapter 5 – Section 6 (5/2/04) Page 5.6-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Current-Controlled, Current-Source (CCCS) Amplifier
Gmvi
ii
Ri RoRS
io
RL
CCCS
is
CurrentDifferentialAmplifier
SecondStage
io
CCCSFig. 5.6-4
ii
i1
i2
iois = AI =
AiRSRo(RS + Ri)(Ro + RL)
Chapter 5 – Section 6 (5/2/04) Page 5.6-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Current-Controlled, Voltage-Source (CCVS) Amplifier
Rmvivi Ri
Ro+
-
vo RL
CCVS
CurrentDifferentialAmplifier
SecondStage
vo
CCVSFig. 5.6-5
+
-
OutputStage
ii
RSis ii
i1
i2
vois = RM =
RmRSRL(Ri + RS)(Ro + RL)
Chapter 5 – Section 7 (5/2/04) Page 5.7-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 5.7 - SUMMARY
This chapter presented the following subjects:5.1 Inverting Amplifiers
Class A (diode load and current sink/source load)Class AB of B (push-pull)
5.2 Differential AmplifiersNeed good common mode rejectionAn excellent input stage for integrated circuit amplifiers
5.3 Cascode AmplifiersUseful for controlling the poles of an amplifier
5.4 Current AmplifiersGood for low power supplies
5.5 Output AmplifiersMinimize the output resistanceMaximize the current sinking/sourcing capability
5.6 High-Gain ArchitecturesPossible block-level implementations using the blocks of this chapter.
Chapter 6 – Introduction (5/2/04) Page 6.0-1
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 6 – CMOS OPERATIONAL AMPLIFIERSChapter Outline6.1 Design of CMOS Op Amps6.2 Compensation of Op Amps6.3 Two-Stage Operational Amplifier Design6.4 Power Supply Rejection Ratio of the Two-Stage Op Amp6.5 Cascode Op Amps6.6 Simulation and Measurement of Op Amps6.7 Macromodels for Op Amps6.8 SummaryGoalUnderstand the analysis, design, and measurement of simple CMOS op ampsDesign Hierarchy
The op amps of this chapter are unbuffered and are OTAsbut we will use the genericterm “op amp”.
Blocks or circuits(Combination of primitives, independent)
Sub-blocks or subcircuits(A primitive, not independent)
Functional blocks or circuits(Perform a complex function)
Fig. 6.0-1
Chapter 6
Chapter 6 – Section 1 (5/2/04) Page 6.1-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 6.1 - DESIGN OF CMOS OPERATIONAL AMPLIFIERSHigh-Level Viewpoint of an Op AmpBlock diagram of a general, two-stage op amp:
Differential Transconductance
Stage
HighGainStage
OutputBuffer
CompensationCircuitry
BiasCircuitry
+
-
v1 vOUT
v2
vOUT'
Fig. 110-01
• Differential transconductance stage:Forms the input and sometimes provides the differential-to-single ended conversion.
• High gain stage:Provides the voltage gain required by the op amp together with the input stage.
• Output buffer:Used if the op amp must drive a low resistance.
• Compensation:Necessary to keep the op amp stable when resistive negative feedback is applied.
Chapter 6 – Section 1 (5/2/04) Page 6.1-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Ideal Op AmpSymbol:
+
-
+
-
+
-
v1
v2vOUT = Av(v1-v2)
VDD
VSS
Fig. 110-02
+
-
i1
i2+
-vi
Null port:If the differential gain of the op amp is large enough then input terminal pair becomes anull port.A null port is a pair of terminals where the voltage is zero and the current is zero.I.e.,
v1 - v2 = vi = 0and
i1 = 0 and i2 = 0
Therefore, ideal op amps can be analyzed by assuming the differential input voltage iszero and that no current flows into or out of the differential inputs.
Chapter 6 – Section 1 (5/2/04) Page 6.1-3
CMOS Analog Circuit Design © P.E. Allen - 2004
General Configuration of the Op Amp as a Voltage Amplifier
+-
+
-
+
-
+
-v1
v2 vout
Fig. 110-03
vinpvinn
R1 R2
Noniverting voltage amplifier:
vinn = 0 ⇒ vout =
R1+R2
R1 vinp
Inverting voltage amplifier:
vinp = 0 ⇒ vout = -
R2
R1 vinn
Chapter 6 – Section 1 (5/2/04) Page 6.1-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.1-1 - Simplified Analysis of an Op Amp CircuitThe circuit shown below is an inverting voltage amplifier using an op amp. Find thevoltage transfer function, vout/vin.
+- +
-
+
-
+
-vin vi vout
R2R1
ii
i1 i2
Virtual Ground Fig. 110-04SolutionIf Av → ∞, then vi → 0 because of the negative feedback path through R2.
(The op amp with –fb. makes its input terminal voltages equal.)vi = 0 and ii = 0
Note that the null port becomes the familiar virtual ground if one of the op amp inputterminals is on ground. If this is the case, then we can write that
i1 = vinR1
and i2 = voutR2
Since, ii = 0, then i1 + i2 = 0 giving the desired result asvoutvin
= - R2R1 .
Chapter 6 – Section 1 (5/2/04) Page 6.1-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Linear and Static Characterization of the Op AmpA model for a nonideal op amp that includes some of the linear, static nonidealities:
+
-v2
v1
v1CMRR
VOS
Ricm
Ricm
in2
en2
IB1
IB2
Cid Rid
Rout vout
Ideal Op Amp
Fig. 110-05
*
whereRid = differential input resistanceCid = differential input capacitanceRicm = common mode input resistanceVOS = input-offset voltageIB1 and IB2 = differential input-bias currentsIOS = input-offset current (IOS = IB1-IB2)CMRR = common-mode rejection ratioe2
n = voltage-noise spectral density (mean-square volts/Hertz)i2n = current-noise spectral density (mean-square amps/Hertz)
Chapter 6 – Section 1 (5/2/04) Page 6.1-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Linear and Dynamic Characteristics of the Op AmpDifferential and common-mode frequency response:
Vout(s) = Av(s)[V1(s) - V2(s)] ± Ac(s)
V1(s)+V2(s)
2
Differential-frequency response:
Av(s) = Av0
s
p1 - 1
s
p2 - 1
s
p3 - 1 ··· =
Av0 p1p2p3···(s -p1)(s -p2)(s -p3)···
where p1, p2, p3,··· are the poles of the differential-frequency response (ignoring zeros).
0dB
20log10(Av0)
|Av(jω)| dB
AsymptoticMagnitude
ActualMagnitude
ω1
ω2 ω3ω
-6dB/oct.
-12dB/oct.
-18dB/oct.
GB
Fig. 110-06
Chapter 6 – Section 1 (5/2/04) Page 6.1-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Other Characteristics of the Op AmpPower supply rejection ratio (PSRR):
PSRR = ∆VDD∆VOUT
Av(s) = Vo/Vin (Vdd = 0)Vo/Vdd (Vin = 0)
Input common mode range (ICMR):ICMR = the voltage range over which the input common-mode signal can varywithout influence the differential performance
Slew rate (SR):SR = output voltage rate limit of the op amp
Settling time (Ts):
+-
Settling Time
Final Value
Final Value + ε
Final Value - ε
ε
ε
vOUT(t)
t00
vOUTvIN
Fig. 110-07Ts
Upper Tolerance
Lower Tolerance
Chapter 6 – Section 1 (5/2/04) Page 6.1-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Classification of CMOS Op AmpsCategorization of op amps:
Conversion
Classic DifferentialAmplifier
Modified DifferentialAmplifier
Differential-to-single endedLoad (Current Mirror)
Source/SinkCurrent Loads
MOS DiodeLoad
TransconductanceGrounded Gate
TransconductanceGrounded Source
Class A (Sourceor Sink Load)
Class B(Push-Pull)
Voltageto Current
Currentto Voltage
Voltageto Current
Currentto Voltage
Hierarchy
FirstVoltageStage
SecondVoltageStage
CurrentStage
Table 110-01
Chapter 6 – Section 1 (5/2/04) Page 6.1-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage CMOS Op AmpClassical two-stage CMOS op amp broken into voltage-to-current and current-to-voltagestages:
+
--
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSSV→I I→V V→I I→V
voutvin
VBias
Fig. 6.1-8
Chapter 6 – Section 1 (5/2/04) Page 6.1-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Folded Cascode CMOS Op AmpFolded cascode CMOS op amp broken into stages.
VSS
VDD
M1 M2
M6
M4
M3
M5
M7
M8
M10
M9
M11
VBias
VBias
VBias
+
-vin vout
+
-
V→I I→I I→V
voutvin
Fig. 6.1-9
Chapter 6 – Section 1 (5/2/04) Page 6.1-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Design of CMOS Op AmpsSteps:1.) Choosing or creating the basic structure of the op amp.
This step is results in a schematic showing the transistors and their interconnections.This diagram does not change throughout the remainder of the design unless thespecifications cannot be met, then a new or modified structure must be developed.
2.) Selection of the dc currents and transistor sizes.Most of the effort of design is in this category.Simulators are used to aid the designer in this phase. The general performance of thecircuit should be known a priori.
3.) Physical implementation of the design.Layout of the transistorsFloorplanning the connections, pin-outs, power supply buses and groundsExtraction of the physical parasitics and resimulationVerification that the layout is a physical representation of the circuit.
4.) Fabrication5.) Measurement
Verification of the specificationsModification of the design as necessary
Chapter 6 – Section 1 (5/2/04) Page 6.1-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Boundary Conditions and Requirements for CMOS Op AmpsBoundary conditions:
1. Process specification (VT, K', Cox, etc.)2. Supply voltage and range3. Supply current and range4. Operating temperature and range
Requirements:1. Gain2. Gain bandwidth3. Settling time4. Slew rate5. Common-mode input range, ICMR6. Common-mode rejection ratio, CMRR7. Power-supply rejection ratio, PSRR8. Output-voltage swing9. Output resistance10. Offset11. Noise12. Layout area
Chapter 6 – Section 1 (5/2/04) Page 6.1-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Specifications for a Typical Unbuffered CMOS Op Amp
Boundary Conditions RequirementProcess Specification See Tables 3.1-1 and 3.1-2Supply Voltage ±2.5 V ±10%Supply Current 100 µATemperature Range 0 to 70°C
Specifications ValueGain ≥ 70 dBGainbandwidth ≥ 5 MHzSettling Time ≤ 1 µsecSlew Rate ≥ 5 V/µsecInput CMR ≥ ±1.5 VCMRR ≥ 60 dBPSRR ≥ 60 dBOutput Swing ≥ ±1.5 VOutput Resistance N/A, capacitive load onlyOffset ≤ ±10 mVNoise ≤ 100nV/ Hz at 1KHzLayout Area ≤ 10,000 min. channel length2
Chapter 6 – Section 1 (5/2/04) Page 6.1-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Some Practical Thoughts on Op Amp Design1.) Decide upon a suitable topology.
• Experience is a great help• The topology should be the one capable of meeting most of the specifications• Try to avoid “inventing” a new topology but start with an existing topology
2.) Determine the type of compensation needed to meet the specifications.• Consider the load and stability requirements• Use some form of Miller compensation or a self-compensated approach (shown
later)3.) Design dc currents and device sizes for proper dc, ac, and transient performance.
• This begins with hand calculations based upon approximate design equations.• Compensation components are also sized in this step of the procedure.• After each device is sized by hand, a circuit simulator is used to fine tune the design
Two basic steps of design:1.) “First-cut” - this step is to use hand calculations to propose a design that has
potential of satisfying the specifications. Design robustness is developed in this step.2.) Optimization - this step uses the computer to refine and optimize the design.
Chapter 6 – Section 2 (5/2/04) Page 6.2-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 6.2 - COMPENSATION OF OP AMPSCompensationObjective
Objective of compensation is to achieve stable operation when negative feedback isapplied around the op amp.Types of Compensation1. Miller - Use of a capacitor feeding back around a high-gain, inverting stage.
• Miller capacitor only• Miller capacitor with an unity-gain buffer to block the forward path through the
compensation capacitor. Can eliminate the RHP zero.• Miller with a nulling resistor. Similar to Miller but with an added series resistance
to gain control over the RHP zero.2. Self compensating - Load capacitor compensates the op amp (later).3. Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be
less than unity.
Chapter 6 – Section 2 (5/2/04) Page 6.2-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Single-Loop, Negative Feedback SystemsBlock diagram:
A(s) = differential-mode voltage gain of theop amp
F(s) = feedback transfer function from theoutput of op amp back to the input.
Definitions:• Open-loop gain = L(s) = -A(s)F(s)
• Closed-loop gain = Vout(s)Vin(s) =
A(s)1+A(s)F(s)
Stability Requirements:The requirements for stability for a single-loop, negative feedback system is,
|A(jω0°)F(jω0°)| = |L(jω0°)| < 1where ω0° is defined as
Arg[−A(jω0°)F(jω0°)] = Arg[L(jω0°)] = 0°Another convenient way to express this requirement is
Arg[−A(jω0dB)F(jω0dB)] = Arg[L(jω0dB)] > 0°where ω0dB is defined as
|A(jω0dB)F(jω0dB)| = |L(jω0dB)| = 1
A(s)
F(s)
Σ-
+Vin(s) Vout(s)
Fig. 120-01
Chapter 6 – Section 2 (5/2/04) Page 6.2-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of the Stability Requirement using Bode Plots
|A(jω
)F(jω
)|
0dB
Arg
[-A
(jω
)F(jω
)] 180°
135°
90°
45°
0° ω0dBω
ω
-20dB/decade
-40dB/decade
ΦM
Frequency (rads/sec.) Fig. Fig. 120-02
A measure of stability is given by the phase when |A(jω)F(jω)| = 1. This phase is calledphase margin.
Phase margin = ΦM = Arg[-A(jω0dB)F(jω0dB)] = Arg[L(jω0dB)]
Chapter 6 – Section 2 (5/2/04) Page 6.2-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Why Do We Want Good Stability?Consider the step response of second-order system which closely models the closed-loopgain of the op amp.
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 5 10 15
45°50°55°
60°65°
70°vout(t)Av0
ωot = ωnt (sec.)Fig. 120-03
+-
A “good” step response is one that quickly reaches its final value.Therefore, we see that phase margin should be at least 45° and preferably 60° or larger.(A rule of thumb for satisfactory stability is that there should be less than three rings.)Note that good stability is not necessarily the quickest risetime.
Chapter 6 – Section 2 (5/2/04) Page 6.2-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Uncompensated Frequency Response of Two-Stage Op AmpsTwo-Stage Op Amps:
Fig. 120-04
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
-
+vin
Q1 Q2
Q3 Q4
Q5
Q6
Q7
vout
VCC
VEE
VBias+
-
Small-Signal Model:
vout
Fig. 120-05
gm1vin2
R1 C1
+
-v1
gm2vin2 gm4v1 R2 C2 gm6v2
+
-v2 R3 C3
+
-
D1, D3 (C1, C3) D2, D4 (C2, C4) D6, D7 (C6, C7)
Note that this model neglects the base-collector and gate-drain capacitances for purposesof simplification.
Chapter 6 – Section 2 (5/2/04) Page 6.2-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Uncompensated Frequency Response of Two-Stage Op Amps - ContinuedFor the MOS two-stage op amp:
R1 ≈ 1
gm3 ||rds3||rds1 ≈ 1
gm3 R2 = rds2|| rds4 and R3 = rds6|| rds7
C1 = Cgs3+Cgs4+Cbd1+Cbd3 C2 = Cgs6+Cbd2+Cbd4 and C3 = CL +Cbd6+Cbd7For the BJT two-stage op amp:
R1 = 1
gm3 ||rπ3||rπ4||ro1||ro3≈1
gm3 R2 = rπ6|| ro2|| ro4 ≈ rπ6 and R3 = ro6|| ro7
C1 = Cπ3+Cπ4+Ccs1+Ccs3 C2 = Cπ6+Ccs2+Ccs4 and C3 = CL+Ccs6+Ccs7
Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives,
voutgm1vinR2 C2 gm6v2
+
-v2 R3 C3
+
-
Fig. 120-06
Voutgm1VinRI CI gmIIVI
+
-VI RII CII
+
-
The locations for the two poles are given by the following equations
p’1 = −1
RICIand p’2 =
−1RIICII
where RI (RII) is the resistance to ground seen from the output of the first (second) stageand CI (CII) is the capacitance to ground seen from the output of the first (second) stage.
Chapter 6 – Section 2 (5/2/04) Page 6.2-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Uncompensated Frequency Response of an Op Amp
0dB
Avd(0) dB
-20dB/decade
log10(ω)
log10(ω)
180°
90°
0°
Phase Shift
GB
|p1'|
-40dB/decade
45°
135°
-45°/decade
-45°/decade
|p2'|
|A(jω
)|A
rg[-
A(jω
)]
ω0dB Fig. 120-07
If we assume that F(s) = 1 (this is the worst case for stability considerations), then theabove plot is the same as the loop gain.Note that the phase margin is much less than 45°.Therefore, the op amp must be compensated before using it in a closed-loopconfiguration.
Chapter 6 – Section 2 (5/2/04) Page 6.2-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Miller Compensation of the Two-Stage Op Amp
Fig. 120-08
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
-
+vin
Q1 Q2
Q3 Q4
Q5
Q6
Q7
VCC
VEE
VBias+
-
CM
CI
Cc
CII
vout
CI
Cc
CII
CM
The various capacitors are:Cc = accomplishes the Miller compensation
CM = capacitance associated with the first-stage mirror (mirror pole)
CI = output capacitance to ground of the first-stage
CII = output capacitance to ground of the second-stage
Chapter 6 – Section 2 (5/2/04) Page 6.2-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Compensated Two-Stage, Small-Signal Frequency Response Model SimplifiedUse the CMOS op amp to illustrate:1.) Assume that gm3 >> gds3 + gds1
2.) Assume that gm3CM >> GB
Therefore,
-gm1vin2 CM
1gm3 gm4v1
gm2vin2 C1 rds2||rds4
gm6v2 rds6||rds7 CL
v1 v2Cc
+
-
vout
Fig. 120-09
rds1||rds3
gm1vin rds2||rds4 gm6v2 rds6||rds7CII
v2Cc
+
-
voutCI
+
-vin
Same circuit holds for the BJT op amp with different component relationships.
Chapter 6 – Section 2 (5/2/04) Page 6.2-10
CMOS Analog Circuit Design © P.E. Allen - 2004
General Two-Stage Frequency Response Analysiswhere gmI = gm1 = gm2, RI = rds2||rds4, CI = C1
and gmII = gm6, RII = rds6||rds7, CII = C2 = CL
Nodal Equations: -gmIVin = [GI + s(CI + Cc)]V2 - [sCc]Vout and 0 = [gmII - sCc]V2 + [GII + sCII + sCc]Vout
Solving using Cramer’s rule gives,Vout(s)Vin(s) =
gmI(gmII - sCc)GIGII+s [GII(CI+CII)+GI(CII+Cc)+gmIICc]+s2[CICII+CcCI+CcCII]
= Ao[1 - s (Cc/gmII)]
1+s [RI(CI+CII)+RII(C2+Cc)+gmIIR1RIICc]+s2[RIRII(CICII+CcCI+CcCII)]where, Ao = gmIgmIIRIRII
In general, D(s) =
1-sp1
1-sp2
= 1-s
1
p1 +
1p2
+s2
p1p2 → D(s) ≈ 1-
sp1
+ s2
p1p2 , if |p2|>>|p1|
∴ p1 = -1
RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc ≈
-1gmIIR1RIICc
, z = gmII
Cc
p2 = -[RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc]
RIRII(CICII+CcCI+CcCII) ≈ -gmIICc
CICII+CcCI+CcCII ≈ -gmIICII , CII > Cc > CI
gmIVin RI gmIIV2 RII CII
V2Cc
+
-VoutCI
+
-Vin
Fig.120-10
Chapter 6 – Section 2 (5/2/04) Page 6.2-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Results for Miller Compensation of the Two-Stage Op AmpThere are three roots of importance:1.) Right-half plane zero:
z1= gmIICc =
gm6Cc
This root is very undesirable- it boosts the magnitude while decreasing the phase.2.) Dominant left-half plane pole (the Miller pole):
p1 ≈ -1
gmIIRIRIICc = -(gds2+gds4)(gds6+gds7)
gm6CcThis root accomplishes the desired compensation.
3.) Left-half plane output pole:
p2 ≈ -gmIICII ≈
-gm6CL
This pole must be ≥ unity-gainbandwidth or the phase margin will not be satisfied.Root locus plot of the Miller compensation:
jω
σ
Cc=0Open-loop poles
Closed-loop poles, Cc≠0
p2 p2' p1p1' z1 Fig. 120-11
Chapter 6 – Section 2 (5/2/04) Page 6.2-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Compensated Open-Loop Frequency Response of the Two-Stage Op Amp
0dB
Avd(0) dB
-20dB/decade
log10(ω)
log10(ω)
Phase Margin
180°
90°
0°
Phase Shift
GB
-40dB/decade
45°
135°
|p1'|
No phase margin
Uncompensated
Compensated
-45°/decade
-45°/decade
|p2'||p1| |p2|
|A(jω
)F(jω
)|
Arg
[-A
(jω
)F(jω
)|
Compensated
Uncompensated
Fig. 120-12
Note that the unity-gainbandwidth, GB, is
GB = Avd(0)·|p1| = (gmIgmIIRIRII)1
gmIIRIRIICc = gmICc =
gm1Cc =
gm2Cc
Chapter 6 – Section 2 (5/2/04) Page 6.2-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Conceptually, where do these roots come from?1.) The Miller pole:
|p1| ≈ 1
RI(gm6RIICc)
2.) The left-half plane output pole:
|p2| ≈ gm6CII
3.) Right-half plane zero (One source of zeros is frommultiple paths from the input to output):
vout =
-gm6RII(1/sCc)
RII + 1/sCc v’ +
RII
RII + 1/sCc v’’ =
-RII
gm6
sCc - 1
RII + 1/sCc v
where v = v’ = v’’.
VDD
CcRII
vout
vI
M6RI
≈gm6RIICcFig. 120-13
VDD
CcRII
vout
M6CII
GB·Cc
1 ≈ 0
VDD
RII
vout
M6CII
Fig. 120-14
VDD
CcRII
vout
v'v''
M6
Fig. 120-15
Chapter 6 – Section 2 (5/2/04) Page 6.2-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of the Mirror PoleUp to this point, we have neglected the influence of the pole, p3, associated with thecurrent mirror of the input stage. A small-signal model for the input stage that includesC3 is shown below:
gm3rds31
rds1
gm1Vin
rds2
i3
i3 rds4C3
+
-Vo1
2gm2Vin
2
Fig. 120-16
The transfer function from the input to the output voltage of the first stage, Vo1(s), can bewritten as
Vo1(s) Vin(s) =
-gm12(gds2+gds4)
gm3+gds1+gds3
gm3+ gds1+gds3+sC3 + 1 ≈
-gm12(gds2+gds4)
sC3 + 2gm3
sC3 + gm3
We see that there is a pole and a zero given as
p3 = - gm3C3
and z3 = - 2gm3C3
Chapter 6 – Section 2 (5/2/04) Page 6.2-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of the Mirror Pole – ContinuedFortunately, the presence of the zero tends to negate the effect of the pole. Generally,
the pole and zero due to C3 is greater than GB and will have very little influence on thestability of the two-stage op amp.
The plot shown illustratesthe case where these roots areless than GB and even thenthey have little effect onstability.
In fact, they actuallyincrease the phase marginslightly because GB isdecreased.
0dB
Avd(0) dB
-6dB/octave
log10(ω)
log10(ω)
Phase margiignoring C3
180°
90°
0°
Phase Shift
GB
-12dB/octave
45°
135°
Cc = 0
-45°/decade
-45°/decade
F = 1
Cc ≠ 0
Cc = 0
Cc ≠ 0
|p1| |p2|
Cc = 0
Cc ≠ 0
|p3||z3|
Magnitude influence of C3
Phase margin due to C3
Fig. 120-17
Chapter 6 – Section 2 (5/2/04) Page 6.2-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of the Conditions for Stability of the Two-Stage Op Amp• Unity-gainbandwith is given as:
GB = Av(0)·|p1| = (gmIgmIIRIRII)·
1
gmIIRIRIICc =
gmICc
= (gm1gm2R1R2)·
1
gm2R1R2Cc =
gm1Cc
• The requirement for 45° phase margin is:
±180° - Arg[AF] = ±180° - tan-1
ω
|p1| - tan-1
ω
|p2| - tan-1
ω
z = 45°
Let ω = GB and assume that z ≥ 10GB, therefore we get,
±180° - tan-1
GB
|p1| - tan-1
GB
|p2| - tan-1
GB
z = 45°
135° ≈ tan-1(Av(0)) + tan-1
GB
|p2| + tan-1(0.1) = 90° + tan-1
GB
|p2| + 5.7°
39.3° ≈ tan-1
GB
|p2| ⇒ GB|p2| = 0.818 ⇒ |p2| ≥ 1.22GB
• The requirement for 60° phase margin: |p2| ≥ 2.2GB if z ≥ 10GB
• If 60° phase margin is required, then the following relationships apply:gm6Cc >
10gm1Cc ⇒ gm6 > 10gm1 and
gm6C2 >
2.2gm1Cc ⇒ Cc > 0.22C2
Chapter 6 – Section 2 (5/2/04) Page 6.2-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Controlling the Right-Half Plane ZeroWhy is the RHP zero a problem?Because it boosts the magnitude but lags the phase - the worst possible combination forstability.
jω
σ
jω1
jω2
jω3
θ1θ2θ3
Fig. 430-01
180° > θ1 > θ2 > θ3
z1
Solution of the problem:If a zero is caused by two paths to the output, then eliminate one of the paths.
Chapter 6 – Section 2 (5/2/04) Page 6.2-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Use of Buffer to Eliminate the Feedforward Path through the Miller CapacitorModel:
The transferfunction is givenby the followingequation,
Vo(s)Vin(s) =
(gmI)(gmII)(RI)(RII)1 + s[RICI + RIICII + RICc + gmIIRIRIICc] + s2[RIRIICII(CI + Cc)]
Using the technique as before to approximate p1 and p2 results in the following
p1 ≅ −1
RICI + RIICII + RICc + gmIIRIRIICc ≅
−1gmIIRIRIICc
and
p2 ≅ −gmIICc
CII(CI + Cc)Comments:
Poles are approximately what they were before with the zero removed.For 45° phase margin, |p2| must be greater than GB
For 60° phase margin, |p2| must be greater than 1.73GB
Fig. 430-02
InvertingHigh-GainStage
Cc
vOUT gmIvin RIgmIIVI
RII CII
VICc
+
-VoutCI
+
-Vin Vout
+1
Chapter 6 – Section 2 (5/2/04) Page 6.2-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Use of Buffer with Finite Output Resistance to Eliminate the RHP ZeroAssume that the unity-gain buffer has an output resistance of Ro.
Model:
InvertingHigh-GainStage
+1Cc
vOUT gmIvin RIgmIIVI
RII CII
VICc
+
-
VoutCI
+
-Vin Ro
Ro
Vout
Fig. 430-03
Ro
It can be shown that if the output resistance of the buffer amplifier, Ro, is not neglectedthat another pole occurs at,
p4 ≅ −1
Ro[CICc/(CI + Cc)]
and a LHP zero at
z2 ≅ −1
RoCc
Closer examination shows that if a resistor, called a nulling resistor, is placed in serieswith Cc that the RHP zero can be eliminated or moved to the LHP.
Chapter 6 – Section 2 (5/2/04) Page 6.2-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero)†
InvertingHigh-GainStage
Cc
vOUT
Rz
gmIvin RIgmIIVI RII CII
Cc
+
-
VoutCI
+
-Vin
Rz
Fig. 430-04
VI
Nodal equations:
gmIVin + VIRI
+ sCIVI +
sCc
1 + sCcRz (VI − Vout) = 0
gmIIVI + VoRII
+ sCIIVout +
sCc
1 + sCcRz (Vout − VI) = 0
Solution:Vout(s)Vin(s) =
a1 − s[(Cc/gmII) − RzCc]1 + bs + cs2 + ds3
wherea = gmIgmIIRIRIIb = (CII + Cc)RII + (CI + Cc)RI + gmIIRIRIICc + RzCcc = [RIRII(CICII + CcCI + CcCII) + RzCc(RICI + RIICII)]d = RIRIIRzCICIICc
† W,J. Parrish, "An Ion Implanted CMOS Amplifier for High Performance Active Filters", Ph.D. Dissertation, 1976, Univ. of CA., Santa Barbara.
Chapter 6 – Section 2 (5/2/04) Page 6.2-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Use of Nulling Resistor to Eliminate the RHP - ContinuedIf Rz is assumed to be less than RI or RII and the poles widely spaced, then the roots of theabove transfer function can be approximated as
p1 ≅ −1
(1 + gmIIRII)RICc ≅
−1gmIIRIIRICc
p2 ≅ −gmIICc
CICII + CcCI + CcCII ≅
−gmIICII
p4 = −1
RzCI
and
z1 = 1
Cc(1/gmII − Rz)
Note that the zero can be placed anywhere on the real axis.
Chapter 6 – Section 2 (5/2/04) Page 6.2-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Conceptual Illustration of the Nulling Resistor ApproachVDD
CcRII
Vout
V'V''
M6
Rz
Fig. Fig. 430-05
The output voltage, Vout, can be written as
Vout = -gm6RII
Rz + 1
sCc
RII + Rz + 1
sCc
V’ + RII
RII + Rz + 1
sCc
V” = -RII
gm6Rz + gm6sCc
- 1
RII + Rz + 1
sCc
V
when V = V’ = V’’.Setting the numerator equal to zero and assuming gm6 = gmII gives,
z1 = 1
Cc(1/gmII − Rz)
Chapter 6 – Section 2 (5/2/04) Page 6.2-23
CMOS Analog Circuit Design © P.E. Allen - 2004
A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p2We desire that z1 = p2 in terms of the previous notation.Therefore,
1Cc(1/gmII − Rz) =
−gmIICII
The value of Rz can be found as
Rz =
Cc + CII
Cc (1/gmII)
With p2 canceled, the remaining roots are p1 and p4(the pole due to Rz) . For unity-gainstability, all that is required is that
|p4| > Av(0)|p1| = Av(0)
gmIIRIIRICc =
gmICc
and (1/RzCI) > (gmI/Cc) = GB
Substituting Rz into the above inequality and assuming CII >> Cc results in
Cc > gmIgmII
CICII
This procedure gives excellent stability for a fixed value of CII (≈ CL).
Unfortunately, as CL changes, p2 changes and the zero must be readjusted to cancel p2.
jω
Fig. 430-06σ
-p4 -p2 -p1 z1
Chapter 6 – Section 2 (5/2/04) Page 6.2-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Increasing the Magnitude of the Output Pole†
The magnitude of the output pole , p2, can be increased by introducing gain in the Millercapacitor feedback path. For example,
VDD
VSS
VBias
Cc
M6
M7
M8
M9M10
M12M11
vOUTIin R1 R2 C2
rds8
gm8Vs8
Cc
VoutV1
+
-
+
-
+
-Vs8
Iin R1 R2 C2gm8Vs8
VoutV1
+
-
+
-
+
-Vs8
1gm8
Cc
gm6V1
gm6V1
Cgd6
Cgd6
Fig. 6.2-15B
The resistors R1 and R2 are defined as
R1 = 1
gds2 + gds4 + gds9 and R2 =
1gds6 + gds7
where transistors M2 and M4 are the output transistors of the first stage.Nodal equations:
Iin = G1V1-gm8Vs8 = G1V1-
gm8sCc
gm8 + sCc Vout and 0 = gm6V1+
G2+sC2+ gm8sCcgm8+sCc
Vout
† B.K. Ahuja, “An Improved Frequency Compensation Technique for CMOS Operational Amplifiers,” IEEE J. of Solid-State Circuits, Vol. SC-18,
No. 6 (Dec. 1983) pp. 629-633.
Chapter 6 – Section 2 (5/2/04) Page 6.2-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Increasing the Magnitude of the Output Pole - ContinuedSolving for the transfer function Vout/Iin gives,
VoutIin
=
-gm6
G1G2
1 + sCcgm8
1 + s
Ccgm8
+ C2G2
+ CcG2
+ gm6CcG1G2
+ s2
CcC2
gm8G2
Using the approximate method of solving for the roots of the denominator gives
p1 = -1
Ccgm8
+ CcG2
+ C2G2
+ gm6CcG1G2
≈ -6
gm6rds2Cc
and
p2 ≈ -
gm6rds2Cc6
CcC2gm8G2
= gm8rds2G2
6
gm6
C2 =
gm8rds
3 |p2’|
where all the various channel resistance have been assumed to equal rds and p2’ is theoutput pole for normal Miller compensation.Result: Dominant pole is approximately the same and the output pole is increased by ≈ gmrds.
Chapter 6 – Section 2 (5/2/04) Page 6.2-26
CMOS Analog Circuit Design © P.E. Allen - 2004
Increasing the Magnitude of the Output Pole - ContinuedIn addition there is a LHP zero at -gm8/sCc and a RHP zero due to Cgd6 (shown dashedin the model on Page 6.2-20) at gm6/Cgd6.
Roots are:
jω
σgm6Cgd6
-gm8Cc
-gm6gm8rds3C2
-1gm6rdsCc Fig. 6.2-16A
Chapter 6 – Section 2 (5/2/04) Page 6.2-27
CMOS Analog Circuit Design © P.E. Allen - 2004
Concept Behind the Increasing of the Magnitude of the Output Pole
VDD
Ccrds7
vout
M6 CII
GB·Cc
1 ≈ 0
VDD
vout
M6CII
M8
gm8rds8
Fig. Fig. 430-08
rds73
Rout = rds7||
3
gm6gm8rds8 ≈ 3
gm6gm8rds8
Therefore, the output pole is approximately,
|p2| ≈ gm6gm8rds8
3CII
Chapter 6 – Section 2 (5/2/04) Page 6.2-28
CMOS Analog Circuit Design © P.E. Allen - 2004
Identification of Poles from a Schematic1.) Most poles are equal to the reciprocal product of the resistance from a node to groundand the capacitance connected to that node.2.) Exceptions (generally due to feedback):
a.) Negative feedback:
-A
R1
C2
C1
C3
-A
R1
C2
C1 C3(1+A)RootID01
b.) Positive feedback (A<1):
+A
R1
C2
C1
C3
+A
R1
C2
C1 C3(1-A)RootID02
Chapter 6 – Section 2 (5/2/04) Page 6.2-29
CMOS Analog Circuit Design © P.E. Allen - 2004
Identification of Zeros from a Schematic1.) Zeros arise from poles in
the feedback path.
If F(s) = 1
sp1
+1 , then
VoutVin
= A(s)
1+A(s)F(s) = A(s)
1+A(s)1
sp1
+1
=A(s)
s
p1 +1
sp1
+1+ A(s)
2.) Zeros are also created by two pathsfrom the input to the output and one ofmore of the paths is frequency dependent.
vin vout
F(s)
A(s)Σ−
+RootID03
VDD
CcRII
vout
v'v''
M6
Fig. 120-15
Chapter 6 – Section 2 (5/2/04) Page 6.2-30
CMOS Analog Circuit Design © P.E. Allen - 2004
Feedforward CompensationUse two parallel paths to achieve a LHP zero for lead compensation purposes.
CcA
VoutVi
InvertingHigh GainAmplifier
CII RII
RHP Zero Cc-A
VoutVi
InvertingHigh GainAmplifier
CII RII
LHP Zero
A
CII RIIVi Vout
Cc
gmIIVi
+
-
+
- Fig.430-09
Cc
VoutVi +1
LHP Zero using Follower
Vout(s)Vin(s) =
ACcCc + CII
s + gmII/ACc
s + 1/[RII(Cc + CII)]
To use the LHP zero for compensation, a compromise must be observed.• Placing the zero below GB will lead to boosting of the loop gain that could deteriorate
the phase margin.• Placing the zero above GB will have less influence on the leading phase caused by the
zero.Note that a source follower is a good candidate for the use of feedforward compensation.
Chapter 6 – Section 2 (5/2/04) Page 6.2-31
CMOS Analog Circuit Design © P.E. Allen - 2004
Self-Compensated Op AmpsSelf compensation occurs when the load capacitor is the compensation capacitor (cannever be unstable for resistive feedback)
Fig. 430-10
-
+vin vout
CL
+
-Gm
Rout(must be large)
Increasing CL
|dB|
Av(0) dB
0dB ω
Rout
-20dB/dec.
Voltage gain:voutvin = Av(0) = GmRout
Dominant pole:
p1 = -1
RoutCL
Unity-gainbandwidth:
GB = Av(0)·|p1| = GmCL
Stability:Large load capacitors simply reduce GB but the phase is still 90° at GB.
Chapter 6 – Section 2 (5/2/04) Page 6.2-32
CMOS Analog Circuit Design © P.E. Allen - 2004
Slew Rate of a Two-Stage CMOS Op AmpRemember that slew rate occurs when currents flowing in a capacitor become limited andis given as
Ilim = C dvCdt where vC is the voltage across the capacitor C.
-
+vin>>0
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
Cc
CL
I5
Assume a virtural ground
I7
I6I5 ICL
Positive Slew Rate
-
+vin<<0
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
Cc
CL
I5
Assume a virtural ground
I7
I6=0I5 ICL
Negative Slew Rate Fig. 140-05
SR+ = min
I5
Cc, I6-I5-I7
CL = I5Cc because I6>>I5 SR- = min
I5
Cc, I7-I5CL =
I5Cc if I7>>I5.
Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew rateof the two-stage op amp should be,
SR = I5Cc
Chapter 6 – Section 3 (5/2/04) Page 6.3-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 6.3 - TWO-STAGE OP AMP DESIGN
Unbuffered, Two-Stage CMOS Op Amp
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
Cc
CL
Fig. 6.3-1
Notation:
Si = WiLi = W/L of the ith transistor
Chapter 6 – Section 3 (5/2/04) Page 6.3-2
CMOS Analog Circuit Design © P.E. Allen - 2004
DC Balance Conditions for the Two-Stage Op AmpFor best performance, keep all transistors insaturation.M4 is the only transistor that cannot be forcedinto saturation by internal connections orexternal voltages.Therefore, we develop conditions to force M4 tobe in saturation.1.) First assume that VSG4 = VSG6. This willcause “proper mirroring” in the M3-M4 mirror.Also, the gate and drain of M4 are at the samepotential so that M4 is “guaranteed” to be insaturation.
2.) If VSG4 = VSG6, then I6 =
S6
S4 I4
3.) However, I7 =
S7
S5 I5 =
S7
S5 (2I4)
4.) For balance, I6 must equal I7 ⇒ S6S4 =
2S7S5 called the “balance conditions”
5.) So if the balance conditions are satisfied, then VDG4 = 0 and M4 is saturated.
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
Cc
CL
-+VSG6
-+VSG4
I4
I5
I7
I6
Fig. 6.3-1A
Chapter 6 – Section 3 (5/2/04) Page 6.3-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Design Relationships for the Two-Stage Op Amp
Slew rate SR = I5Cc
(Assuming I7 >>I5 and CL > Cc)
First-stage gain Av1 = gm1
gds2 + gds4 =
2gm1I5(λ2 + λ4)
Second-stage gain Av2 = gm6
gds6 + gds7 =
gm6I6(λ6 + λ7)
Gain-bandwidth GB = gm1Cc
Output pole p2 = −gm6CL
RHP zero z1 = gm6Cc
60° phase margin requires that gm6 = 2.2gm2(CL/Cc) if all other roots are ≥ 10GB.
Positive ICMR Vin(max) = VDD − I5β3 − |VT03|(max) + VT1(min))
Negative ICMR Vin(min) = VSS + I5β1 + VT1(max) + VDS5(sat)
Saturation voltageVDS(sat) = 2IDSβ (all transistors are saturated)
Chapter 6 – Section 3 (5/2/04) Page 6.3-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Op Amp SpecificationsThe following design procedure assumes that specifications for the following parametersare given.1. Gain at dc, Av(0)2. Gain-bandwidth, GB3. Phase margin (or settling time)4. Input common-mode range, ICMR5. Load Capacitance, CL
6. Slew-rate, SR7. Output voltage swing8. Power dissipation, Pdiss
-
+
vin M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
Cc
CL
VSG4+
-
Max. ICMRand/or p3
VSG6+
-
Vout(max)
I6
gm6 or Proper Mirroring
VSG4=VSG6
Cc ≈ 0.2CL(PM = 60°)
GB =gm1Cc
Min. ICMR I5 I5 = SR·Cc Vout(min)
Fig. 160-02
Chapter 6 – Section 3 (5/2/04) Page 6.3-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Unbuffered Op Amp Design ProcedureThis design procedure assumes that the gain at dc (Av), unity gain bandwidth (GB), inputcommon mode range (Vin(min) and Vin(max)), load capacitance (CL), slew rate (SR),settling time (Ts), output voltage swing (Vout(max) and Vout(min)), and power dissipation(Pdiss) are given. Choose the smallest device length which will keep the channelmodulation parameter constant and give good matching for current mirrors.1. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60° phase
margin we use the following relationship. This assumes that z ≥ 10GB.Cc > 0.22CL
2. Determine the minimum value for the “tail current” (I5) from the largest of the twovalues.
I5 = SR .Cc or I5 ≅ 10
VDD + |VSS|
2 .Ts
3. Design for S3 from the maximum input voltage specification.
S3 = I5
K'3[VDD − Vin(max) − |VT03|(max) + VT1(min)]2
4. Verify that the pole of M3 due to Cgs3 and Cgs4 (= 0.67W3L3Cox) will not be dominant byassuming it to be greater than 10 GB
gm32Cgs3
> 10GB.
Chapter 6 – Section 3 (5/2/04) Page 6.3-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Unbuffered Op Amp Design Procedure - Continued5. Design for S1 (S2) to achieve the desired GB.
gm1 = GB . Cc → S2 = gm22
K'2I5
6. Design for S5 from the minimum input voltage. First calculate VDS5(sat) then find S5.
VDS5(sat) = Vin(min) − VSS− I5β1 −VT1(max) ≥ 100 mV → S5 =
2I5K'5[VDS5(sat)]2
7. Find S6 by letting the second pole (p2) be equal to 2.2 times GB and assuming thatVSG4 = VSG6.
gm6 = 2.2gm2(CL/Cc) and gm6gm4
= 2KP'S6I6
2KP'S4I4 =
S6S4
I6I4
= S6S4
→ S6 = gm6gm4
S4
8. Calculate I6 from
I6 = gm62
2K'6S6
Check to make sure that S6 satisfies the Vout(max) requirement and adjust as necessary.
9. Design S7 to achieve the desired current ratios between I5 and I6.S7 = (I6/I5)S5 (Check the minimum output voltage requirements)
Chapter 6 – Section 3 (5/2/04) Page 6.3-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Unbuffered Op Amp Design Procedure - Continued10. Check gain and power dissipation specifications.
Av = 2gm2gm6
I5(λ2 + λ3)I6(λ6 + λ7) Pdiss = (I5 + I6)(VDD + |VSS|)
11. If the gain specification is not met, then the currents, I5 and I6, can be decreased orthe W/L ratios of M2 and/or M6 increased. The previous calculations must be recheckedto insure that they are satisfied. If the power dissipation is too high, then one can onlyreduce the currents I5 and I6. Reduction of currents will probably necessitate increase ofsome of the W/L ratios in order to satisfy input and output swings.12. Simulate the circuit to check to see that all specifications are met.
Chapter 6 – Section 3 (5/2/04) Page 6.3-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.3-1 - Design of a Two-Stage Op AmpUsing the material and device parameters given in Tables 3.1-1 and 3.1-2, design an
amplifier similar to that shown in Fig. 6.3-1 that meets the following specifications.Assume the channel length is to be 1µm and the load capacitor is CL = 10pF.
Av > 3000V/V VDD = 2.5V VSS = -2.5VGB = 5MHz SR > 10V/µs 60° phase marginVout range = ±2V ICMR = -1 to 2V Pdiss ≤ 2mW
Solution1.) The first step is to calculate the minimum value of the compensation capacitor Cc,
Cc > (2.2/10)(10 pF) = 2.2 pF
2.) Choose Cc as 3pF. Using the slew-rate specification and Cc calculate I5.
I5 = (3x10-12)(10x106) = 30 µA
3.) Next calculate (W/L)3 using ICMR requirements.
(W/L)3 = 30x10-6
(50x10-6)[2.5 − 2 − .85 + 0.55]2 = 15 → (W/L)3 = (W/L)4 = 15
Chapter 6 – Section 3 (5/2/04) Page 6.3-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.3-1 - Continued4.) Now we can check the value of the mirror pole, p3, to make sure that it is in factgreater than 10GB. Assume the Cox = 0.4fF/µm2. The mirror pole can be found as
p3 ≈ -gm32Cgs3
= - 2K’pS3I3
2(0.667)W3L3Cox = 2.81x109(rads/sec)
or 448 MHz. Thus, p3, is not of concern in this design because p3 >> 10GB.5.) The next step in the design is to calculate gm1 to get
gm1 = (5x106)(2π)(3x10-12) = 94.25µS
Therefore, (W/L)1 is
(W/L)1 = (W/L)2 = gm12
2K’NI1 =
(94.25)2
2·110·15 = 2.79 ≈ 3.0 ⇒ (W/L)1 = (W/L)2 = 3
6.) Next calculate VDS5,
VDS5 = (−1) − (−2.5) −30x10-6
110x10-6·3 - .85 = 0.35V
Using VDS5 calculate (W/L)5 from the saturation relationship.
(W/L)5 = 2(30x10-6)
(110x10-6)(0.35)2 = 4.49 ≈ 4.5 → (W/L)5 = 4.5
Chapter 6 – Section 3 (5/2/04) Page 6.3-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.3-1 - Continued7.) For 60° phase margin, we know that
gm6 ≥ 10gm1 ≥ 942.5µS
Assuming that gm6 = 942.5µS and knowing that gm4 = 150µS, we calculate (W/L)6 as
(W/L)6 = 15 942.5x10-6
(150x10-6) = 94.25 ≈ 94
8.) Calculate I6 using the small-signal gm expression:
I6 = (942.5x10-6)2
(2)(50x10-6)(94.25) = 94.5µA ≈ 95µA
If we calculate (W/L)6 based on Vout(max), the value is approximately 15. Since 94exceeds the specification and maintains better phase margin, we will stay with (W/L)6 =94 and I6 = 95µA.
With I6 = 95µA the power dissipation is
Pdiss = 5V·(30µA+95µA) = 0.625mW.
Chapter 6 – Section 3 (5/2/04) Page 6.3-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.3-1 - Continued9.) Finally, calculate (W/L)7
(W/L)7 = 4.5
95x10-6
30x10-6 = 14.25 ≈ 14 → (W/L)7 = 14
Let us check the Vout(min) specification although the W/L of M7 is so large that this isprobably not necessary. The value of Vout(min) is
Vout(min) = VDS7(sat) = 2·95
110·14 = 0.351V
which is less than required. At this point, the first-cut design is complete.10.) Now check to see that the gain specification has been met
Av = (92.45x10-6)(942.5x10-6)
15x10-6(.04 + .05)95x10-6(.04 + .05) = 7,697V/V
which exceeds the specifications by a factor of two. .An easy way to achieve more gainwould be to increase the W and L values by a factor of two which because of thedecreased value of λ would multiply the above gain by a factor of 20.11.) The final step in the hand design is to establish true electrical widths and lengthsbased upon ∆L and ∆W variations. In this example ∆L will be due to lateral diffusion only.Unless otherwise noted, ∆W will not be taken into account. All dimensions will berounded to integer values. Assume that ∆L = 0.2µm. Therefore, we have
Chapter 6 – Section 3 (5/2/04) Page 6.3-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.3-1 - ContinuedW1 = W2 = 3(1 − 0.4) = 1.8 µm ≈ 2µmW3 = W4 = 15(1 − 0.4) = 9µmW5 = 4.5(1 - 0.4) = 2.7µm ≈ 3µmW6 = 94(1 - 0.4) = 56.4µm ≈ 56µmW7 = 14(1 - 0.4) = 8.4 ≈ 8µm
The figure below shows the results of the first-cut design. The W/L ratios shown do notaccount for the lateral diffusion discussed above. The next phase requires simulation.
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
Cc = 3pF
CL =10pF
3µm1µm
3µm1µm
15µm1µm
15µm1µm
M84.5µm1µm
30µA
4.5µm1µm
14µm1µm
94µm1µm
30µA
95µA
Fig. 6.3-3
Chapter 6 – Section 3 (5/2/04) Page 6.3-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Incorporating the Nulling Resistor into the Miller Compensated Two-Stage Op AmpCircuit:
VDD
VSS
IBias
CL
CcCM vout
VBVA
M1 M2
M3 M4
M5
M6
M7M9
M10
M11
M12
vin+vin-
M8
Fig. 160-03
VC
We saw earlier that the roots were:
p1 = − gm2AvCc
= − gm1AvCc
p2 = − gm6CL
p4 = − 1
RzCIz1 =
−1RzCc − Cc/gm6
where Av = gm1gm6RIRII.
(Note that p4 is the pole resulting from the nulling resistor compensation technique.)
Chapter 6 – Section 3 (5/2/04) Page 6.3-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Design of the Nulling Resistor (M8)In order to place the zero on top of the second pole (p2), the following relationship musthold
Rz = 1
gm6
CL + Cc
Cc =
Cc+CL
Cc
12K’PS6I6
The resistor, Rz, is realized by the transistor M8 which is operating in the active regionbecause the dc current through it is zero. Therefore, Rz, can be written as
Rz = ∂vDS8∂iD8
VDS8=0=
1K’PS8(VSG8-|VTP|)
The bias circuit is designed so that voltage VA is equal to VB.
∴ |VGS10| − |VT| = |VGS8| − |VT|⇒ VSG11 = VSG6 ⇒
W11
L11 =
I10
I6
W6
L6In the saturation region
|VGS10| − |VT| = 2(I10)
K'P(W10/L10) = |VGS8| − |VT|
∴ Rz = 1
K’PS8
K’PS102I10
= 1S8
S10
2K’PI10
Equating the two expressions for Rz gives
W8
L8 =
Cc
CL + Cc
S10S6I6I10
Chapter 6 – Section 3 (5/2/04) Page 6.3-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.3-2 - RHP Zero CompensationUse results of Ex. 6.3-1 and design compensation circuitry so that the RHP zero is
moved from the RHP to the LHP and placed on top of the output pole p2. Use device datagiven in Ex. 6.3-1.Solution
The task at hand is the design of transistors M8, M9, M10, M11, and bias current I10.The first step in this design is to establish the bias components. In order to set VA equal toVB, thenVSG11 must equal VSG6. Therefore,
S11 = (I11/I6)S6Choose I11 = I10 = I9 = 15µA which gives S11 = (15µA/95µA)94 = 14.8 ≈ 15.
The aspect ratio of M10 is essentially a free parameter, and will be set equal to 1.There must be sufficient supply voltage to support the sum of VSG11, VSG10, and VDS9.The ratio of I10/I5 determines the (W/L) of M9. This ratio is
(W/L)9 = (I10/I5)(W/L)5 = (15/30)(4.5) = 2.25 ≈ 2
Now (W/L)8 is determined to be
(W/L)8 =
3pF
3pF+10pF 1·94·95µA
15µA = 5.63 ≈ 6
Chapter 6 – Section 3 (5/2/04) Page 6.3-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.3-2 - ContinuedIt is worthwhile to check that the RHP zero has been moved on top of p2. To do this,
first calculate the value of Rz. VSG8 must first be determined. It is equal to VSG10, which is
VSG10 = 2I10
K’PS10 + |VTP| =
2·1550·1 + 0.7 = 1.474V
Next determine Rz.
Rz = 1
K’PS8(VSG10-|VTP|) = 106
50·5.63(1.474-.7) = 4.590kΩ
The location of z1 is calculated as
z1 = −1
(4.590 x 103)(3x10-12) − 3x10-12
942.5x10-6
= -94.46x106 rads/sec
The output pole, p2, is
p2 = 942.5x10-6
10x10-12 = -94.25x106 rads/sec
Thus, we see that for all practical purposes, the output pole is canceled by the zerothat has been moved from the RHP to the LHP.
The results of this design are summarized below.W8 = 6 µm W9 = 2 µm W10 = 1 µm W11 = 15 µm
Chapter 6 – Section 3 (5/2/04) Page 6.3-17
CMOS Analog Circuit Design © P.E. Allen - 2004
An Alternate Form of Nulling Resistor
To cancel p2,
z1 = p2 → Rz = Cc+CL
gm6ACC =
1gm6B
Which gives
gm6B = gm6A
Cc
Cc+CL
In the previous example,gm6A = 942.5µS, Cc = 3pF
and CL = 10pF.
Choose I6B = 10µA to get
gm6B = gm6ACc
Cc + CL →
2KPW6BI6B
L6B =
Cc
Cc+CL
2KPW6AID6
L6A
orW6B
L6B =
3
132 I6A
I6B W6A
L6A =
3
132
95
10 (94) = 47.6 → W6B = 48µm
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
CcCL
M11 M10
M6B
M8 M9
Fig. 6.3-4A
Chapter 6 – Section 3 (5/2/04) Page 6.3-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Programmability of the Two-Stage Op AmpThe following relationships depend on the bias
current, Ibias, in the following manner and allow forprogrammability after fabrication.
Av(0) = gmIgmIIRIRII ∝ 1
IBias
GB = gmI
Cc ∝ IBias
Pdiss = (VDD+|VSS|)(1+K1+K2)IBias ∝ Ibias
SR = K1IBias
Cc ∝ IBias
Rout = 1
2λK2IBias ∝
1IBias
|p1| = 1
gmIIRIRIICc ∝
IBias2
IBias ∝ IBias
1.5
|z| = gmII
Cc ∝ IBias
Illustration of the Ibias dependence →
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
IBias
Fig. 6.3-04D
K1IBiasK2IBias
103
102
100
101
10-1
10-2
10-31 10 100
IBiasIBias(ref)
|p1|Pdiss and SR
GB and z
Ao and Rout
Fig. 160-05
Chapter 6 – Section 3 (5/2/04) Page 6.3-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation of the Electrical DesignArea of source or drain = AS = AD = W[L1 + L2 + L3]where
L1 = Minimum allowable distance between the contact in the S/D and thepolysilicon (5µm)
L2 = Width of a minimum size contact (5µm)L3 = Minimum allowable distance from contact in S/D to edge of S/D (5µm)
∴ AS = AD = Wx15µmPerimeter of the source or drain = PD = PS = 2W + 2(L1+L2+L3)∴ PD = PS = 2W + 30µm
Illustration:
Poly
Diffusion Diffusion
L
W
L3 L2 L1 L1 L2 L3
Fig. 6.3-5
Chapter 6 – Section 3 (5/2/04) Page 6.3-20
CMOS Analog Circuit Design © P.E. Allen - 2004
5-to-1 Current Mirror with Different Physical Performances
InputOutput
Ground
InputOutput
Ground
(a)
(b)Figure 6.3-6 The layout of a 5-to-1 current mirror. (a) Layout which minimizesarea at the sacrifice of matching. (b) Layout which optimizes matching.
Metal 1
Poly
Diffusion
Contacts
Chapter 6 – Section 3 (5/2/04) Page 6.3-21
CMOS Analog Circuit Design © P.E. Allen - 2004
1-to-1.5 Transistor Matching
Figure 6.3-7 The layout of two transistors with a 1.5 to 1 matching usingcentroid geometry to improve matching.
Gate 2Drain 2
Source 2
Gate 1Drain 1
Source 1
Metal 2 Metal 1 Poly Diffusion Contacts
2 2 21 1
Chapter 6 – Section 3 (5/2/04) Page 6.3-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Reduction of ParasiticsThe major objective of good layout is to minimize the parasitics that influence the design.Typical parasitics include:
Capacitors to ac groundSeries resistance
Capacitive parasitics is minimized by minimizing area and maximizing the distancebetween the conductor and ac ground.Resistance parasitics are minimized by using wide busses and keeping the bus lengthshort.For example:
At 2mΩ/square, a metal run of 1000µm and 2µm wide will have 1Ω of resistance.At 1 mA this amounts to a 1 mV drop which could easily be greater than the least
significant bit of an analog-digital converter. (For example, a 10 bit ADC with VREF =1V has an LSB of 1mV)
Chapter 6 – Section 3 (5/2/04) Page 6.3-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Technique for Reducing the Overlap CapacitanceSquare Donut Transistor:
Source
Drain
Source
Gate
Source
Source
Figure 6.3-8 Reduction of Cgd by a donut shaped transistor.
Metal 1
Poly
Diffusion
Contacts
Note: Can get more W/L in less area with the above geometry.
Chapter 6 – Section 3 (5/2/04) Page 6.3-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Chip Voltage Bias Distribution Scheme
+-
Rext
VDD
BandgapVoltage,
VBG
M7
M5
M4
M1
Q1 Q2
M2
M3
M6
M8 M9
M10
M11
M12
Q3
IPTAT R1 R2
M13
M14
M15
M16
xn
IREF
R3
R4
Figure 6.3-9 Generation of a reference voltage which is distributed on the chipas a current to slave bias circuits.
VDD
VPBias1
VPBias2
VNBias2
VNBias1
Remote portion of chip
M2A M4A
M3A
Location of reference voltage
SlaveBias
Circuit
M5A
M6A
R2A
R1A
M1A
MasterVoltage
ReferenceCircuit
Chapter 6 – Section 4 (5/2/04) Page 6.4-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 6.4 - PSRR OF THE TWO-STAGE OP AMPWhat is PSRR?
PSRR = Av(Vdd=0)Add(Vin=0)
How do you calculate PSRR?You could calculate Av and Add and divide,however
+
- VDD
VSS
Vdd
Vout
V2
V1
V2
V1
Av(V1-V2)
±AddVddVss
Vout
Fig. 180-02
Vout = AddVdd + Av(V1-V2) = AddVdd - AvVout→ Vout(1+Av) = AddVdd
∴VoutVdd =
Add1+Av ≈
AddAv =
1PSRR+ (Good for frequencies up to GB)
+
- VDD
VSS
Vdd
V2
V1Vss
VoutVin
Fig.180-01
Chapter 6 – Section 4 (5/2/04) Page 6.4-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Positive PSRR of the Two-Stage Op Amp
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vdd
CI
gm1V5
rds1
gm1Vout
rds2
gm6(V1-Vdd)
gm2V5
rds5
gm31 I3 rds4
I3
rds6
Vout
rds7CI
Cc
CII
+
-
V1
+
-
Vdd
VddI3
gm3-
Fig. 180-03
+ V5 -
gm1Vout
rds2
gm6(V1-Vdd)rds4 rds6
Vout rds7CI
Cc
CII
+
-
V1
+
-
Vdd
-
gds1Vdd
-
V5 ≈ 0
The nodal equations are:(gds1 + gds4)Vdd = (gds2 + gds4 + sCc + sCI)V1 − (gm1 + sCc)Vout
(gm6 + gds6)Vdd = (gm6 − sCc)V1 + (gds6 + gds7 + sCc + sCII)Vout
Using the generic notation the nodal equations are:GIVdd = (GI + sCc + sCI)V1 − (gmI + sCc)Vout(gmII + gds6)Vdd = (gmII − sCc)V1 + (GII + sCc + sCII)Vout
whereGI = gds1 + gds4 = gds2 + gds4, GII = gds6 + gds7, gmI = gm1 = gm2 and gmII = gm6
Chapter 6 – Section 4 (5/2/04) Page 6.4-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Positive PSRR of the Two-Stage Op Amp - ContinuedUsing Cramers rule to solve for the transfer function,Vout/Vdd, and inverting the transferfunction gives the following result.
VddVout
= s2[CcCI+CICII + CIICc]+ s[GI(Cc+CII) + GII(Cc+CI) + Cc(gmII − gmI)] + GIGII+gmIgmII
s[Cc(gmII+GI+gds6) + CI(gmII + gds6)] + GIgds6
We may solve for the approximate roots of numerator as
PSRR+ = VddVout
≅
gmIgmII
GIgds6
sCc
gmI + 1
s(CcCI+CICII+CcCII)
gmII Cc + 1
sgmIICc
GIgds6 + 1
where gmII > gmI and that all transconductances are larger than the channelconductances.
∴ PSRR+ = VddVout
=
gmIgmII
GIgds6
sCc
gmI + 1
sCII
gmII + 1
sgmIICcGIgds6
+ 1 =
GIIAvo
gds6
s
GB + 1
s
|p2| + 1
sGIIAvo
gds6GB + 1
Chapter 6 – Section 4 (5/2/04) Page 6.4-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Positive PSRR of the Two-Stage Op Amp - Continued
|PSR
R+(jω
)| dB
GIIAv0
0gds6GBGIIAv0
GB |p2|ω
Fig. 180-04
gds6
At approximately the dominant pole, the PSRR falls off with a -20dB/decade slope anddegrades the higher frequency PSRR + of the two-stage op amp.Using the values of Example 6.3-1 we get:
PSRR+(0) = 68.8dB, z1 = -5MHz, z2 = -15MHz and p1 = -906Hz
Chapter 6 – Section 4 (5/2/04) Page 6.4-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Concept of the PSRR+ for the Two-Stage Op Amp
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vdd
CI
Fig. 180-05
Cc
Vdd Rout
Vout
Other sourcesof PSRR+ besides Cc
1RoutCc
ω
VoutVdd
0dB
1.) The M7 current sink causes VSG6 to act like a battery.2.) Therefore, Vdd couples from the source to gate of M6.3.) The path to the output is through any capacitance from gate to drain of M6.Conclusion:
The Miller capacitor Cc couples the positive power supply ripple directly to the output.
Must reduce or eliminate Cc.
Chapter 6 – Section 4 (5/2/04) Page 6.4-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Negative PSRR of the Two-Stage Op Amp withVBias Grounded
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vss
CI
Fig. 180-06
gmIVoutRI CI
gmIIV1CII RII
gm7Vss
+
-Vout
Cc
VBias grounded
Nodal equations for VBias grounded:
0 = (GI + sCc+sCI)V1 - (gmI+sCc)Vogm7Vss = (gMII-sCc)V1 + (GII+sCc+sCII)Vo
Solving for Vout/Vss and inverting gives
VssVout
= s2[CcCI+CICII+CIICc]+s[GI(Cc+CII)+GII(Cc+CI)+Cc(gmII −gmI)]+GIGII+gmIgmII
[s(Cc+CI)+GI]gm7
Chapter 6 – Section 4 (5/2/04) Page 6.4-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Negative PSRR of the Two-Stage Op Amp withVBias Grounded - Continued
Again using techniques described previously, we may solve for the approximate roots as
PSRR- = VssVout
≅
gmIgmII
GIgm7
sCc
gmI + 1
s(CcCI+CICII+CcCII)
gmII Cc + 1
s(Cc+CI)
GI + 1
This equation can be rewritten approximately as
PSRR- = VssVout
≅
gmIgmII
GIgm7
sCc
gmI + 1
sCII
gmII + 1
sCc
GI + 1
=
GIIAv0
gm7
s
GB + 1
s
|p2| +1
s
GB gmIGI
+1
Comments:
PSRR- zeros = PSRR + zerosDC gain ≈ Second-stage gain,
PSRR- pole ≈ (Second-stage gain) x (PSRR+ pole)Assuming the values of Ex. 6.3-1 gives a gain of 23.7 dB and a pole -147 kHz. The dcvalue of PSRR- is very poor for this case, however, this case can be avoided by correctlyimplementing VBias which we consider next.
Chapter 6 – Section 4 (5/2/04) Page 6.4-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Negative PSRR of the Two-Stage Op Amp withVBias Connected to VSS
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vss
CI
Fig. 180-07
rds5
rds6 Vout
rds7
CI
CcCgd7
+
-V1
+
-
Vss
gmIVoutgmIIV1RI
VBias connected to VSS
CII
If the value of VBias is independent of Vss, then the model shown results. The nodalequations for this model are
0 = (GI + sCc + sCI)V1 - (gmI + sCc)Voutand
(gds7 + sCgd7)Vss = (gmII - sCc)V1 + (GII + sCc + sCII + sCgd7)Vout
Again, solving for Vout/Vss and inverting gives
VssVout
= s2[CcCI+CICII+CIICc+CICgd7+CcCgd7]+s[GI(Cc+CII+Cgd7)+GII(Cc+CI)+Cc(gmII−gmI)]+GIGII+gmIgmII
(sCgd7+gds7)(s(CI+Cc)+GI)
Chapter 6 – Section 4 (5/2/04) Page 6.4-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Negative PSRR of the Two-Stage Op Amp withVBias Connected to VSS - Continued
Assuming that gmII > gmI and solving for the approximate roots of both the numeratorand denominator gives
PSRR- = VssVout
≅
gmIgmII
GIgds7
sCc
gmI + 1
s(CcCI+CICII+CcCII)
gmII Cc + 1
sCgd7
gds7 +1
s(CI+Cc)
GI + 1
This equation can be rewritten as
PSRR- = VssVout
≈
GIIAv0
gds7
s
GB + 1
s
|p2| +1
sCgd7
gds7 +1
sCc
GI + 1
Comments:• DC gain has been increased by the ratio of GII to gds7
• Two poles instead of one, however the pole at -gds7/Cgd7 is large and can be ignored.
Using the values of Ex. 6.3-1 and assume that Cds7 = 10fF, gives,
PSRR-(0) = 76.7dB and Poles at -71.2kHz and -149MHz
Chapter 6 – Section 4 (5/2/04) Page 6.4-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Response of the Negative PSRR of the Two-Stage Op Amp with VBiasConnected to VSS
|PSR
R- (
jω)|
dB
GIIAv0
0GB |p2|
ω
Fig. 180-08
gds7
GICc
Invalidregion of analysis
Chapter 6 – Section 4 (5/2/04) Page 6.4-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Approximate Model for Negative PSRR with VBias Connected to Ground
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vss
CI
Fig. 180-09
VBias grounded
VSS
VssVBias
issM5 or M7
Path through the input stage is not importantas long as the CMRR is high.Path through the output stage:
vout ≈ issZout = gm7ZoutVss
∴VoutVss = gm7Zout = gm7Rout
1
sRoutCout+1
Vss
20 to40dB
Vout
0dBRoutCout
1 ωFig.180-10
Chapter 6 – Section 4 (5/2/04) Page 6.4-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Approximate Model for Negative PSRR with VBias Connected to VSS
What is Zout?
Zout = VtIt ⇒
It = gmIIV1 = gmII
gmIVt
GI+sCI+sCc
Thus, Zout = GI+s(CI+Cc)
gmIgMII
∴VssVout =
1+ rds7Zout1 =
s(Cc+CI) + GI+gmIgmIIrds7s(Cc+CI) + GI ⇒ Pole at
-GICc+CI
The two-stage op amp will never have good PSRR because of the Miller compensation.
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vss
CI
Fig. 180-11
VBias connected to VSS
rds7
vout
ZoutVss
rds7
Path through Cgd7is negligible
Fig.180-12
Vtrds6||rds7
VoutCI
Cc
+
-V1
+
-gmIVoutgmIIV1RI
CII+Cgd7It
Chapter 6 – Section 5 (5/2/04) Page 6.5-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 6.5 - CASCODE OP AMPSWhy Cascode Op Amps?• Control of the frequency behavior• Can get more gain by increasing the output resistance of a stage• In the past section, PSRR of the two-stage op amp was insufficient for many applications• A two-stage op amp can become unstable for large load capacitors (if nulling resistor is
not used)• We will see in future sections that the cascode op amp leads to wider ICMR and/or
smaller power supply requirementsWhere Should the Cascode Technique be Used?• First stage -
Good noise performanceRequires level translation to second stageDegrades the Miller compensation
• Second stage -Self compensatingIncreases the efficiency of the Miller compensationIncreases PSRR
Chapter 6 – Section 5 (5/2/04) Page 6.5-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Use of Cascoding in the First Stage of the Two-Stage Op Amp
-
+ vin
M1 M2
M3 M4
M5
vo1
VDD
VSS
VBias+
-
R
VBias
2vin2
-
+
MC2MC1
MC4MC3
-
+ vin
M1 M2
M3 M4
M5
vo1
VDD
VSS
VBias+
-
R
2vin2
-
+
MC2MC1
MC4MC3
MB1 MB2
MB3 MB4
MB5
Fig. 6.5-1
-
+
VBias
Implementation of the floating voltage VBias.
Rout of the first stage is RI ≈ (gmC2rdsC2rds2)||(gmC4rdsC4rds4)
Voltage gain = vo1vin = gm1RI [The gain is increased by approximately 0.5(gMCrdsC)]
As a single stage op amp, the compensation capacitor becomes the load capacitor.
Chapter 6 – Section 5 (5/2/04) Page 6.5-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.5-1 Single-Stage, Cascode Op Amp PerformanceAssume that all W/L ratios are 10 µm/1 µm, and that IDS1 = IDS2 = 50 µA of single
stage op amp. Find the voltage gain of this op amp and the value of CI if GB = 10 MHz.Use the model parameters of Table 3.1-2.Solution
The device transconductances aregm1 = gm2 = gmI = 331.7 µS
gmC2 = 331.7µS
gmC4 = 223.6 µS.
The output resistance of the NMOS and PMOS devices is 0.5 MΩ and 0.4 MΩ,respectively.∴ RI = 25 MΩ
Av(0) = 8290 V/V.
For a unity-gain bandwidth of 10 MHz, the value of CI is 5.28 pF.
What happens if a 100pF capacitor is attached to this op amp?GB goes from 10MHz to 0.53MHz.
Chapter 6 – Section 5 (5/2/04) Page 6.5-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage Op Amp with a Cascoded First-Stage
Cc
-
+ vin
M1 M2
M3 M4
M5
vo1
VDD
VSS
VBias+
-
R
2vin2
-
+
MC2MC1
MC4MC3
MB1 MB2
MB3 MB4
MB5
-
+
VBias
MT1
MT2
M6
M7
vout
Fig. 6.5-2
• MT1 and MT2 are required for level shifting fromthe first-stage to the second.
• The PSRR+ is improved by the presence of MT1• Internal loop pole at the gate of M6 may cause the
Miller compensation to fail.• The voltage gain of this op amp could easily be 100,000V/V
σ
jω
z1p1p2p3Fig. 6.5-2
Chapter 6 – Section 5 (5/2/04) Page 6.5-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage Op Amp with a Cascode Second-Stage
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
Cc
CL
VBP
VBN
MC6
MC7
Fig. 6.5-3
Rz
Av = gmIgmIIRIRII where gmI = gm1 = gm2, gmII = gm6,
RI = 1
gds2 + gds4 =
2(λ2 + λ4)ID5
and RII = (gmC6rdsC6rds6)||(gmC7rdsC7rds7)
Comments:• The second-stage gain has greatly increased improving the Miller compensation• The overall gain is approximately (gmrds)3 or very large• Output pole, p2, is approximately the same if Cc is constant• The zero RHP is the same if Cc is constant
Chapter 6 – Section 5 (5/2/04) Page 6.5-6
CMOS Analog Circuit Design © P.E. Allen - 2004
A Balanced, Two-Stage Op Amp using a Cascode Output Stage
vout =
gm1gm8
gm3 vin2 +
gm2gm6 gm4
vin2 RII
=
gm1
2 +gm2
2 kvin RII = gm1·k·RII vin
whereRII = (gm7rds7rds6)||(gm12rds12rds11)
and
k = gm8gm3 =
gm6gm4
This op amp is balanced because the drain-to-ground loads for M1 and M2 are identical.
TABLE 1 - Design Relationships for Balanced, Cascode Output Stage Op Amp.
Slew rate = Iout
CLGB =
gm1gm8
gm3CLAv =
12
gm1gm8
gm3 +
gm2gm6
gm4 RII
Vin(max) = VDD −
I5
β3
1/2− |VTO3|(max) +VT1(min) Vin(min) = VSS + VDS5 +
I5
β1
1/2 + VT1(min)
-
+
vin
M1 M2
M3
M4
M5
M6
M11
vout
VDD
VSS
VBias+
-
CL
R1M9
M10
R2
M14
M15
M8
M12
M7
M13
Fig. 6.5-4
Chapter 6 – Section 5 (5/2/04) Page 6.5-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.5-2 Design of Balanced, Cascoded Output Stage Op AmpThe balanced, cascoded output stage op amp is a useful alternative to the two-stage
op amp. Its design will be illustrated by this example. The pertinent design equations forthe op amp were given above. The specifications of the design are as follows:
VDD = −VSS = 2.5 V Slew rate = 5 V/µs with a 50 pF loadGB = 10 MHz with a 25 pF load Av ≥ 5000Input CMR = −1V to +1.5 V Output swing = ±1.5 V
Use the parameters of Table 3.1-2 and let all device lengths be 1 µm.Solution
While numerous approaches can be taken, we shall follow one based on the abovespecifications. The steps will be numbered to help illustrate the procedure.1.) The first step will be to find the maximum source/sink current. This is found from theslew rate.
Isource/Isink = CL × slew rate = 50 pF(5 V/µs) = 250 µA
2.) Next some W/L constraints based on the maximum output source/sink current aredeveloped. Under dynamic conditions, all of I5 will flow in M4; thus we can write
Max. Iout(source) = (S6/S4)I5 and Max. Iout(sink) = (S8/S3)I5
The maximum output sinking current is equal to the maximum output sourcing current ifS3 = S4, S6 = S8, and S10 = S11
Chapter 6 – Section 5 (5/2/04) Page 6.5-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.5-2 - Continued3.) Choose I5 as 100 µA. This current (which can be changed later) gives
S6 = 2.5S4 and S8 = 2.5S3
Note that S8 could equal S3 if S11 = 2.5S10. This would minimize the power dissipation.
4.) Next design for ±1.5 V output capability. We shall assume that the output mustsource or sink the 250µA at the peak values of output. First consider the negative outputpeak. Since there is 1 V difference between VSS and the minimum output, let VDS11(sat) =VDS12(sat) = 0.5 V (we continue to ignore the bulk effects). Under the maximum negativepeak assume that I11 = I12 = 250 µA. Therefore
0.5 = 2I11
K'NS11 =
2I12K'NS12
= 500 µA
(110 µA/V2)S11
which gives S11 = S12 = 18.2 and S9 = S10 = 18.2. For the positive peak, we get
0.5 = 2I6
K'PS6 =
2I7K'PS7
= 500 µA
(50 µA/V2)S6
which gives S6 = S7 = S8 = 40 and S3 = S4 = (40/2.5) = 16.
5.) Next the values of R1 and R2 are designed. For the resistor of the self-biased cascodewe can write R1 = VDS12(sat)/250µA = 2kΩ and R2 = VSD7(sat)/250µA = 2kΩ
Chapter 6 – Section 5 (5/2/04) Page 6.5-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.5-2 - ContinuedUsing this value of R1 (R2) will cause M11 to slightly be in the active region underquiescent conditions. One could redesign R1 to avoid this but the minimum outputvoltage under maximum sinking current would not be realized. 6.) Now we must consider the possibility of conflict among the specifications.
First consider the input CMR. S3 has already been designed as 16. Using ICMRrelationship, we find that S3 should be at least 4.1. A larger value of S3 will give a highervalue of Vin(max) so that we continue to use S3 = 16 which gives Vin(max) = 1.95V.
Next, check to see if the larger W/L causes a pole below the gainbandwidth.Assuming a Cox of 0.4fF/µm2 gives the first-stage pole of
p3 = -gm3
Cgs3+Cgs8 = - 2K’PS3I3
(0.667)(W3L3+W8L8)Cox = 33.15x109 rads/sec or 5.275GHz
which is much greater than 10GB.7.) Next we find gm1 (gm2). There are two ways of calculating gm1.
(a.) The first is from the Av specification. The gain isAv = (gm1/2gm4)(gm6 + gm8) RII
Note, a current gain of k could be introduced by making S6/S4 (S8/S3 = S11/S3) equal to k.
gm6gm4 =
gm11gm3 =
2KP’·S6·I62KP’·S4·I4 = k
Chapter 6 – Section 5 (5/2/04) Page 6.5-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.5-2 - ContinuedCalculating the various transconductances we get gm4 = 282.4 µS, gm6 = gm7 = gm8 = 707µS, gm11 = gm12 = 707 µS, rds6 = rd7 = 0.16 MΩ, and rds11 = rds12 = 0.2 MΩ. Assumingthat the gain Av must be greater than 5000 and k = 2.5 gives gm1 > 72.43 µS.
(b.) The second method of finding gm1 is from the GB specifications. Multiplying the gainby the dominant pole (1/CIIRII) gives
GB = gm1(gm6 + gm8)
2gm4CL
Assuming that CL= 25 pF and using the specified GB gives gm1 = 251 µS.
Since this is greater than 72.43µS, we choose gm1 = gm2 = 251µS. Knowing I5 gives S1 =S2 = 5.7 ≈ 6.
8.) The next step is to check that S1 and S2 are large enough to meet the −1V input CMRspecification. Use the saturation formula we find that VDS5 is 0.261 V. This gives S5 =26.7 ≈ 27. The gain becomes Av = 6,925V/V and GB = 10 MHz for a 25 pF load. We shallassume that exceeding the specifications in this area is not detrimental to the performanceof the op amp.9.) With S5 = 7 then we can design S13 from the relationship
S13 = I13I5 S5 =
125µA100µA27 = 33.75 ≈ 34
Chapter 6 – Section 5 (5/2/04) Page 6.5-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.5-2 - Continued10.) Finally we need to design the value of VBias, which can be done with the values of S5and I5 known. However, M5 is usually biased from a current source flowing into a MOSdiode in parallel with the gate-source of M5. The value of the current source comparedwith I5 would define the W/L ratio of the MOS diode.
Table 2 summarizes the values of W/L that resulted from this design procedure. Thepower dissipation for this design is seen to be 2 mW. The next step would be beginsimulation.
Table 2 - Summary of W/L Ratios for Example 6.5-2S1 = S2 = 6S3 = S4 = 16S5 = 27S6 = S7 = S8 = S14 = S15 = 40S9 = S10 = S11 = S12 = 18.2S13 = 34
Chapter 6 – Section 5 (5/2/04) Page 6.5-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Technological Implications of the Cascode Configuration
Fig. 6.5-5
Poly IIPoly I
n+ n+n-channel
p substrate/well
A B C D
Thinoxide
A
B
C
D
If a double poly CMOS process is available, internode parasitics can be minimized.As an alternative, one should keep the drain/source between the transistors to a minimumarea.
Fig. 6.5-5A
Poly I
n+ n+n-channel
p substrate/well
A B C D
Thinoxide
A
B
C
D
Poly I
Minimum Polyseparation
n-channeln+
Chapter 6 – Section 5 (5/2/04) Page 6.5-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Input Common Mode Range for Two Types of Differential Amplifier Loads
vicm
M1 M2
M3 M4
M5
VDD
VSS
VBias+
-
+
-
VSG3
M1 M2
M3 M4
M5
VDD
VSS
VBias+
-
+
-
VSD3
VBP
+
-
VSD4
+
-
VSD4
VDD-VSG3+VTN
VSS+VDS5+VGS1
InputCommon
ModeRange
vicm
VDD-VSD3+VTN
VSS+VDS5+VGS1
InputCommon
ModeRange
Differential amplifier witha current mirror load. Fig. 6.5-6
Differential amplifier withcurrent source loads.
In order to improve the ICMR, it is desirable to use current source (sink) loads withoutlosing half the gain.The resulting solution is the folded cascode op amp.
Chapter 6 – Section 5 (5/2/04) Page 6.5-14
CMOS Analog Circuit Design © P.E. Allen - 2004
The Folded Cascode Op Amp
Comments:• I4 and I5, should be designed so that I6 and I7 never become zero (i.e. I4=I5=1.5I3)
• This amplifier is nearly balanced (would be exactly if RA was equal to RB)
• Self compensating• Poor noise performance, the gain occurs at the output so all intermediate transistors
contribute to the noise along with the input transistors. (Some first stage gain can beachieved if RA and RB are greater than gm1 or gm2.
RB
-
+vin
M1 M2
M4 M5
M6
M11
vout
VDD
VSS
VBias+
-
CLR2
M7
M8 M9
M10M3
Fig. 6.5-7
I3
I4 I5
I6 I7
I1 I2
R1
M13
M14
M12
RA
A B
Chapter 6 – Section 5 (5/2/04) Page 6.5-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Small-Signal Analysis of the Folded Cascode Op AmpModel:
Recalling what welearned about theresistance looking intothe source of thecascode transistor;
RA = rds6+R2+(1/gm10)
1 + gm6rds6 ≈
1gm6
and RB = rds7 + RII
1 + gm7rds7 ≈
RIIgm7rds7
where RII ≈gm9rds9rds11
The small-signal voltage transfer function can be found as follows. The current i10 iswritten as
i10 = -gm1(rds1||rds4)vin2[RA + (rds1||rds4)] ≈
-gm1vin2
and the current i7 can be expressed as
i7 = gm2(rds2||rds5)vin
2
RII
gm7rds7 + (rds2||rds5)
= gm2vin
2
1 + RII(gds2+gds5)
gm7rds7
= gm2vin2(1+k) where k =
RII(gds2+gds5)gm7rds7
The output voltage, vout, is equal to the sum of i7 and i10 flowing through Rout. Thus,
voutvin
=
gm1
2 + gm2
2(1+k) Rout =
2+k
2+2k gmIRout
gm1vin2 rds1 rds4
rds6
gm6vgs6
R2+
RA
gm2vin2 rds2 rds5
rds7
gm7vgs7
RII
RB
i10
i10+
-vgs7
+
-vgs6
Fig. 140-07
+
-vout
i7
1gm10
Chapter 6 – Section 5 (5/2/04) Page 6.5-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Response of the Folded Cascode Op AmpThe frequency response of the folded cascode op amp is determined primarily by theoutput pole which is given as
pout = -1
RoutCout
where Cout is all the capacitance connected from the output of the op amp to ground.
All other poles must be greater than GB = gm1/Cout. The approximate expressions foreach pole is1.) Pole at node A: pA ≈ - gm6/CA
2.) Pole at node B: pB ≈ - gm7/CB
3.) Pole at drain of M6: p6 ≈ -1
(R2+1/gm10)C6
4.) Pole at source of M8: p8 ≈ -gm8/C85.) Pole at source of M9: p9 ≈ -gm9/C96.) Pole at gate of M10: p10 ≈ -gm10/C10where the approximate expressions are found by the reciprocal product of the resistanceand parasitic capacitance seen to ground from a given node. One might feel that becauseRB is approximately rds that this pole might be too small. However, at frequencies wherethis pole has influence, Cout, causes Rout to be much smaller making pB also non-dominant.
Chapter 6 – Section 5 (5/2/04) Page 6.5-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.5-3 - Folded Cascode, CMOS Op AmpAssume that all gmN = gmP = 100µS, rdsN = 2MΩ, rdsP = 1MΩ, and CL = 10pF. Find allof the small-signal performance values for the folded-cascode op amp.
RII = 0.4GΩ, RA = 10kΩ, and RB = 4MΩ ∴ k = 0.4x109(0.3x10-6)
100 = 1.2
voutvin
=
2+1.2
2+2.4 (100)(57.143) = 4,156V/V
Rout = RII ||[gm7rds7(rds5||rds2)] = 400MΩ||[(100)(0.667MΩ)] = 57.143MΩ
|pout| = 1
RoutCout =
157.143MΩ·10pF = 1,750 rads/sec. ⇒ 278Hz ⇒ GB = 1.21MHz
Chapter 6 – Section 5 (5/2/04) Page 6.5-18
CMOS Analog Circuit Design © P.E. Allen - 2004
PSRR of the Folded Cascode Op Amp
Consider the following circuit used to model the PSRR-:
Vout
Vss
Cgd11
M11
M9
VDD
R
Fig. 6.5-9A
Vss Vout
Cgd9
Rout
+
-
Cgd9
VGS11
VGSG9
Vss
Vss
Vss
rds11
Cout
rds9
This model assumes that gate, source and drain of M11 and the gate and source of M9 allvary with VSS.
We shall examine Vout/Vss rather than PSRR-. (Small Vout/Vss will lead to large PSRR-.)
The transfer function of Vout/Vss can be found as
VoutVss
≈ sCgd9Rout
sCoutRout+1 for Cgd9 < Cout
The approximate PSRR- is sketched on the next page.
Chapter 6 – Section 5 (5/2/04) Page 6.5-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Response of the PSRR- of the Folded Cascode Op Amp
VoutVss
GB
Cgd9Rout
|PSRR-|
dB
0dB
Fig. 6.5-10A
log10(ω)
1
Cout
Cgd9
Other sources of Vss injection, i.e. rds9
Dominantpole frequency
|Avd(ω)|
We see that the PSRR of the cascode op amp is much better than the two-stage op amp.
Chapter 6 – Section 5 (5/2/04) Page 6.5-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Design Approach for the Folded-Cascode Op AmpStep Relationship Design Equation/Constraint Comments
1 Slew Rate I3 = SR·CL
2 Bias currents inoutput cascodes
I4 = I5 = 1.2I3 to 1.5I3 Avoid zero current incascodes
3 Maximum outputvoltage, vout(max) S5=
2I5KP’VSD52 , S7=
2I7KP’VSD72 , (S4=S14=S5 &
S13=S6=S7)
VSD5(sat)=VSD7(sat)= 0.5[VDD-Vout(max)]
4 Minimum outputvoltage, vout(min) S11=
2I11KN’VDS112 , S9=
2I9KN’VDS92 , (S10=S11&S8=S9) VDS9(sat)=VDS11(sat)
= 0.5(Vout(max)-VSS)
5 Self-bias cascode R1 = VSD14(sat)/I14 and R2 = VDS8(sat)/I6
6GB =
gm1CL
S1=S2= gm12
KN’I3 =
GB2CL2
KN’I3
7 Minimum inputCM
S3 = 2I3
KN’
Vin(min)-VSS- (I3/KN’S1) -VT1 2
8 Maximum inputCM
S4 = S5 =2I4
KP’ VDD-Vin(max)+VT1 2
S4 and S5 must meetor exceed value in step3
9 DifferentialVoltage Gain
voutvin
=
gm1
2 + gm2
2(1+k) Rout =
2+k
2+2k gmIRout k = RII(gds2+gds4)
gm7rds7
10 Power dissipation Pdiss = (VDD-VSS)(I3+I12+I10+I11)
Chapter 6 – Section 5 (5/2/04) Page 6.5-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.5-3 Design of a Folded-Cascode Op AmpFollow the procedure given to design the folded-cascode op amp when the slew rate is10V/µs, the load capacitor is 10pF, the maximum and minimum output voltages are ±2Vfor ±2.5V power supplies, the GB is 10MHz, the minimum input common mode voltage is-1.5V and the maximum input common mode voltage is 2.5V. The differential voltagegain should be greater than 5,000V/V and the power dissipation should be less than5mW. Use channel lengths of 1µm.SolutionFollowing the approach outlined above we obtain the following results.
I3 = SR·CL = 10x106·10-11 = 100µA
Select I4 = I5 = 125µA.
Next, we see that the value of 0.5(VDD-Vout(max)) is 0.5V/2 or 0.25V. Thus,
S4 = S5 = S14 = 2·125µA
50µA/V2·(0.25V)2 = 2·125·16
50 = 80
and assuming worst case currents in M6 and M7 gives,
S6 = S7 = S13 = 2·125µA
50µA/V2(0.25V)2 = 2·125·16
50 = 80 The value of 0.5(Vout(min)-|VSS|) is also 0.25V which gives the value of S8, S9, S10 and S11
as S8 = S9 = S10 = S11 = 2·I8
KN’VDS82 = 2·125
110·(0.25)2 = 36.36
Chapter 6 – Section 5 (5/2/04) Page 6.5-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.5-3 - ContinuedThe value of R1 and R2 is equal to 0.25V/125µA or 2kΩ. In step 6, the value of GB givesS1 and S2 as
S1 = S2 = GB2·CL2
KN’I3 =
(20πx106)2(10-11)2
110x10-6·100x10-6 = 35.9
The minimum input common mode voltage defines S3 as
S3 = 2I3
KN’
Vin(min)-VSS-I3
KN’S1 - VT1
2 =
200x10-6
110x10-6
-1.5+2.5-100
110·35.9 -0.7 2 = 91.6
We need to check that the values of S4 and S5 are large enough to satisfy the maximuminput common mode voltage. The maximum input common mode voltage of 2.5 requires
S4 = S5 ≥ 2I4
KP’[VDD-Vin(max)+VT1]2 = 2·125µA
50x10-6µA/V2[0.7V]2 = 10.2
which is much less than 80. In fact, with S4 = S5 = 80, the maximum input common modevoltage is 3V. Finally, S12, is given as
S12 = 125100 S3 = 114.53
The power dissipation is found to bePdiss = 5V(125µA+125µA+125µA) = 1.875mW
Chapter 6 – Section 5 (5/2/04) Page 6.5-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.5-3 - ContinuedThe small-signal voltage gain requires the following values to evaluate:
S4, S5, S13, S14: gm = 2·125·50·80 = 1000µS and gds = 125x10-6·0.05 = 6.25µS
S6, S7: gm = 2·75·50·80 = 774.6µS and gds = 75x10-6·0.05 = 3.75µS
S8, S9, S10, S11: gm = 2·75·110·36.36 = 774.6µS and gds = 75x10-6·0.04 = 3µS
S1, S2: gmI = 2·50·110·35.9 = 628µS and gds = 50x10-6(0.04) = 2µS
Thus,
RII ≈ gm9rds9rds11 = (774.6µS)
1
3µS
1
3µS = 86.07MΩ
Rout ≈ 86.07MΩ||(774.6µS)
1
3.75µS
1
2µS+6.25µS = 19.40MΩ
k = RII(gds2+gds4)
gm7rds7 =
86.07MΩ(2µS+6.25µS)(3.75µS)774.6µS = 3.4375
The small-signal, differential-input, voltage gain is
Avd =
2+k
2+2k gmIRout =
2+3.4375
2+6.875 0.628x10-3·19.40x106 = 7,464 V/V
The gain is larger than required by the specifications which should be okay.
Chapter 6 – Section 5 (5/2/04) Page 6.5-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Comments on Folded Cascode Op Amps• Good PSRR• Good ICMR• Self compensated• Can cascade an output stage to get extremely high gain with lower output resistance
(use Miller compensation in this case)• Need first stage gain for good noise performance• Widely used in telecommunication circuits where large dynamic range is required
Chapter 6 – Section 6 (5/2/04) Page 6.6-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 6.6 - SIMULATION AND MEASUREMENT OF OP AMPS
Simulation and Measurement ConsiderationsObjectives:• The objective of simulation is to verify and optimize the design.• The objective of measurement is to experimentally confirm the specifications.Similarity Between Simulation and Measurement:• Same goals• Same approach or techniqueDifferences Between Simulation and Measurement:• Simulation can idealize a circuit• Measurement must consider all nonidealities
Chapter 6 – Section 6 (5/2/04) Page 6.6-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulating or Measuring the Open-Loop Transfer Function of the Op AmpCircuit (Darkened op amp identifies the op amp under test):
Simulation:This circuit will give the voltage transferfunction curve. This curve should identify:
1.) The linear range of operation2.) The gain in the linear range3.) The output limits4.) The systematic input offset voltage5.) DC operating conditions, power dissipation6.) When biased in the linear range, the small-signal frequency response can be
obtained7.) From the open-loop frequency response, the phase margin can be obtained (F = 1)
Measurement:This circuit probably will not work unless the op amp gain is very low.
Fig. 240-01
+ -VOSvIN
vOUTVDD
VSSRLCL
Chapter 6 – Section 6 (5/2/04) Page 6.6-3
CMOS Analog Circuit Design © P.E. Allen - 2004
A More Robust Method of Measuring the Open-Loop Frequency ResponseCircuit:
vIN vOUT
VDD
VSSRLCLRC
Fig. 240-02
Resulting Closed-Loop Frequency Response:dB
log10(w)
Av(0)
1RC RC
Av(0)
Op AmpOpen LoopFrequencyResponse
Fig. 240-03
0dB
Make the RC product as large as possible.
Chapter 6 – Section 6 (5/2/04) Page 6.6-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.6-1 – Measurement of the Op Amp Open-Loop GainDevelop the closed-loop frequency response for op amp circuit used to measure the open-loop frequency response. Sketch the closed-loop frequency response of the magnitude ofVout/Vin if the low frequency gain is 4000 V/V, the GB = 1MHz, R = 10MΩ, and C = 10µF. Solution
The open-loop transfer function of the op amp is,
Av(s) = GB
s +(GB/Av(0)) = 2πx106
s +500π
The closed-loop transfer function of the op amp can be expressed as,
vOUT = Av(s)
-1/sC
R+(1/sC) vOUT +vIN
= Av(s)
-1/RC
s+(1/RC) vOUT +vIN
∴ vOUT
vIN =
-[s +(1/RC)]Av(s)s +(1/RC)+Av(s)/RC
= -[s +(1/RC)]
s +(1/RC)Av(s) +1/RC
= -(s+0.01)
s +0.01Av(s) +0.01
Substituting, Av(s) gives,vOUT
vIN =
-2πx106s -2πx104
(s+0.01)(s+500π)+2πx104 = -2πx106s -2πx104
s2+500πs +2πx104 = -2πx106(s +0.01)
(s+41.07)(s+1529.72)
-20
0
20
40
60
80
0.001 0.1 10 1000 105 107
Mag
nitu
de, d
B
Radian Frequency (radians/sec)
|Av(jω)|
Vout(jω)Vin(jω)
S01E2S2
Chapter 6 – Section 6 (5/2/04) Page 6.6-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation and Measurement of Open-Loop Frequency Response with ModerateGain Op Amps
vIN vOUTVDD
VSSRLCL
R
R
+
-
vi
Fig. 240-04
Make R as large and measure vout and vi to get the open loop gain.
Chapter 6 – Section 6 (5/2/04) Page 6.6-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation or Measurement of the Input Offset Voltage of an Op Amp
VOS
vOUT=VOSVDD
VSSRLCL
+
-
Fig. 6.6-4
Types of offset voltages:1.) Systematic offset - due to mismatches in current mirrors, exists even with ideally
matched transistors.2.) Mismatch offset - due to mismatches in transistors (normally not available in
simulation except through Monte Carlo methods).
Chapter 6 – Section 6 (5/2/04) Page 6.6-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation of the Common-Mode Voltage Gain
VOSvout
VDD
VSSRLCL
+ -
vcm
+
-
Fig. 6.6-5
Make sure that the output voltage of the op amp is in the linear region.
Chapter 6 – Section 6 (5/2/04) Page 6.6-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Measurement of CMRR and PSRRConfiguration:
Note that vI ≈ vOS1000 or vOS ≈ 1000vI
How Does this Circuit Work?
Note:1.) PSRR- can be measured similar toPSRR+ by changing only VSS.2.) The ±1V perturbation can bereplaced by a sinusoid to measureCMRR or PSRR as follows:
PSRR+ = 1000·vdd
vos , PSRR- = 1000·vss
vos
and CMRR = 1000·vcm
vos
CMRR: PSRR:1.) Set VDD’ = VDD + 1V VSS’ = VSS + 1V vOUT’ = vOUT + 1V2.) Measure vOS
called vOS13.) Set VDD’ = VDD - 1V VSS’ = VSS - 1V vOUT’ = vOUT - 1V4.) Measure vOS
called vOS25.)
CMRR=2000
|vOS2-vOS1|
1.) Set VDD’ = VDD + 1V VSS’ = VSS vOUT’ = 0V2.) Measure vOScalled vOS33.) Set VDD’ = VDD - 1V VSS’ = VSS vOUT’ = 0V4.) Measure vOS
called vOS45.)
PSRR+=2000
|vOS4-vOS3|
vOS
vOUTVDD
VSSRLCL
+
-
+- 100kΩ
100kΩ
10kΩ
10Ω
vSET
vI
Fig. 240-07
Chapter 6 – Section 6 (5/2/04) Page 6.6-9
CMOS Analog Circuit Design © P.E. Allen - 2004
How Does the Previous Idea Work?A circuit is shown which is used to measurethe CMRR and PSRR of an op amp. Provethat the CMRR can be given as
CMRR = 1000 vicm
vos
SolutionThe definition of the common-mode rejectionratio is
CMRR =
Avd
Acm =
(vout/vid)(vout/vicm)
However, in the above circuit the value of voutis the same so that we get
CMRR = vicmvid
But vid = vi and vos ≈ 1000vi = 1000vid ⇒ vid = vos
1000
Substituting in the previous expression gives, CMRR = vicmvos
1000
= 1000 vicm
vos
vos
vOUTVDD
VSSRLCL
+
-
+- 100kΩ
100kΩ
10kΩ
10Ω
vicm
vi
Fig. 240-08
vicm
Chapter 6 – Section 6 (5/2/04) Page 6.6-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation of CMRR of an Op AmpNone of the above methods are really suitable for simulation of CMRR.Consider the following:
VDD
VSS
Vcm
Vout
V2
V1
V2
V1
Av(V1-V2)
±AcVcmVcm
Vout
Vcm
Vcm
+
-
Fig. 6.6-7
Vout = Av(V1-V2) ±Acm
V1+V2
2 = -AvVout ± AcmVcm
Vout = ±Acm
1+Av Vcm ≈
±Acm
Av Vcm
∴ |CMRR| = Av
Acm =
Vcm
Vout
(However, PSRR+ must equal PSRR-)
Chapter 6 – Section 6 (5/2/04) Page 6.6-11
CMOS Analog Circuit Design © P.E. Allen - 2004
CMRR of Ex. 6.3-1 using the Above Method of Simulation
45
50
55
60
65
70
75
80
85
10 100 1000 104 105 106 107 108
|CM
RR
| dB
Frequency (Hz)
-200
-150
-100
-50
0
50
100
150
200
10 100 1000 104 105 106 107 108
Arg
[CM
RR
] D
egre
es
Frequency (Hz) Fig. 240-10
Chapter 6 – Section 6 (5/2/04) Page 6.6-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Direct Simulation of PSRRCircuit:
VDD
VSS
Vdd
Vout
V2
V1
V2
V1
Av(V1-V2)
±AddVddVss
Vss = 0
Fig. 6.6-9
+
-
Vout = Av(V1-V2) ±AddVdd = -AvVout ± AddVdd
Vout = ±Add
1+Av Vdd ≈
±Add
Av Vdd
∴ PSRR+ = Av
Add =
Vdd
Vout and PSRR- =
Av
Ass =
Vss
Vout
Works well as long as CMRR is much greater than 1.
Chapter 6 – Section 6 (5/2/04) Page 6.6-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation or Measurement of ICMR
vIN
vOUTVDD
VSSRLCL
+
-
Fig.240-11
ICMR
IDD
vOUT
vIN
1
1
Also, monitor IDD or ISS.
ISS
Initial jump in sweep is due to the turn-on of M5.Should also plot the current in the input stage (or the power supply current).
Chapter 6 – Section 6 (5/2/04) Page 6.6-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Measurement or Simulation of the Open-Loop Output ResistanceMethod 1:
+
-vI
vOUT VDD
VSS
RL
+-
VO1VO2
vOUT
vI(mV)
Without RL
With RLVOS
Fig. 240-12
Rout = RL
V01
V02 − 1 or vary RL until VO2 = 0.5VO1 ⇒ Rout = RL
Method 2:
VSS
VDD
+-
Ro
RoutvIN
R 100R
Fig. 240-13
Rout =
1
Ro +
1100R +
Av100Ro
-1 ≅
100RoAv
Chapter 6 – Section 6 (5/2/04) Page 6.6-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Measurement or Simulation of Slew Rate and Settling Time
vin
voutVDD
VSSRLCL
+
-
IDD Settling ErrorTolerance
1
+SR
1
-SR
Peak Overshoot
Feedthrough
vin
vout
Settling Time
Volts
t
Fig. 240-14
If the slew rate influences the small signal response, then make the input step size smallenough to avoid slew rate (i.e. less than 0.5V for MOS).
Chapter 6 – Section 6 (5/2/04) Page 6.6-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Phase Margin and Peak Overshoot RelationshipIt can be shown (Appendix C) that:
Phase Margin (Degrees) = 57.2958cos-1[ 4ζ4+1 - 2ζ2]
Overshoot (%) = 100 exp
-πζ
1-ζ2
For example, a 5% overshootcorresponds to a phase margin ofapproximately 64°.
0
10
20
30
40
50
60
70
80
Phas
e M
argi
n (D
egre
es)
1.0
10
0 0.2 0.4 0.6 0.8 1
Ove
rsho
ot (
%)
Phase Margin Overshoot
100
0.1
ζ= 12Q
Fig. 240-15
Chapter 6 – Section 6 (5/2/04) Page 6.6-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.6-2 Simulation of the CMOS Op Amp of Ex. 6.3-1.The op amp designed in Example 6.3-
1 and shown in Fig. 6.3-3 is to be analyzedby SPICE to determine if the specificationsare met. The device parameters to be usedare those of Tables 3.1-2 and 3.2-1. Inaddition to verifying the specifications ofExample 6.3-1, we will simulate PSRR+
and PSRR-.Solution/Simulation
The op amp will be treated as asubcircuit in order to simplify the repeated analyses. The table on the next page gives theSPICE subcircuit description of Fig. 6.3-3. While the values of AD, AS, PD, and PS couldbe calculated if the physical layout was complete, we will make an educated estimate ofthese values by using the following approximations.
AS = AD ≅ W[L1 + L2 + L3]PS = PD ≅ 2W + 2[L1 + L2 + L3]
where L1 is the minimum allowable distance between the polysilicon and a contact in themoat (Rule 5C of Table 2.6-1), L2 is the length of a minimum-size square contact to moat(Rule 5A of Table 2.6-1), and L3 is the minimum allowable distance between a contact tomoat and the edge of the moat (Rule 5D of Table 2.6-1).
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
Cc = 3pF
CL =10pF
3µm1µm
3µm1µm
15µm1µm
15µm1µm
M84.5µm1µm
30µA
4.5µm1µm
14µm1µm
94µm1µm
30µA
95µA
Fig. 240-16
Chapter 6 – Section 6 (5/2/04) Page 6.6-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.6-2 - ContinuedOp Amp Subcircuit:
-
+vin vout
VDD
VSS
+
-6
2
1
8
9 Fig. 240-17
.SUBCKT OPAMP 1 2 6 8 9M1 4 2 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18UM2 5 1 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18UM3 4 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42UM4 5 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42UM5 3 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21UM6 6 5 8 8 PMOS1 W=94U L=1U AD=564P AS=564P PD=200U PS=200UM7 6 7 9 9 NMOS1 W=14U L=1U AD=84P AS=84P PD=40U PS=40UM8 7 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21UCC 5 6 3.0P.MODEL NMOS1 NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P+LD=0.016U TOX=14N.MODEL PMOS1 PMOS VTO=-0.7 KP=50U GAMMA=0..57 LAMBDA=0.05 PHI=0.8+MJ=0.5 MJSW=.35 CGBO=700P CGSO=220P CGDO=220P CJ=560U CJSW=350P +LD=0.014U TOX=14NIBIAS 8 7 30U.ENDS
Chapter 6 – Section 6 (5/2/04) Page 6.6-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.6-2 - ContinuedPSPICE Input File for the Open-Loop Configuration:
EXAMPLE 1 OPEN LOOP CONFIGURATION.OPTION LIMPTS=1000VIN+ 1 0 DC 0 AC 1.0VDD 4 0 DC 2.5VSS 0 5 DC 2.5VIN - 2 0 DC 0CL 3 0 10PX1 1 2 3 4 5 OPAMP
...(Subcircuit of previous slide)
....OP.TF V(3) VIN+.DC VIN+ -0.005 0.005 100U.PRINT DC V(3).AC DEC 10 1 10MEG.PRINT AC VDB(3) VP(3).PROBE (This entry is unique to PSPICE).END
Chapter 6 – Section 6 (5/2/04) Page 6.6-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.6-2 - ContinuedOpen-loop transfer characteristic of Example 6.3-1:
-2
-1
0
1
2
-2 -1.5 -1.0 -0.5 0 0.5 1 1.5 2
v OU
T(V
)
vIN(mV)
2.5
-2.5
VOS
Fig. 240-18
Chapter 6 – Section 6 (5/2/04) Page 6.6-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.6-2 - ContinuedOpen-loop transfer frequency response of Example 6.3-1:
-40
-20
0
20
40
60
80
10 100 1000 104 105 106 107 108
Mag
nitu
de (
dB)
Frequency (Hz)
GB-200
-150
-100
-50
0
50
100
150
200
10 100 1000 104 105 106 107 108
Phas
e Sh
ift (
Deg
rees
)
Frequency (Hz)
GBPhase Margin
Fig. 6.6-16
Chapter 6 – Section 6 (5/2/04) Page 6.6-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.6-2 - ContinuedInput common mode range of Example 6.3-1:
EXAMPLE 6.6-1 UNITY GAIN CONFIGURATION..OPTION LIMPTS=501VIN+ 1 0 PWL(0 -2 10N -2 20N 2 2U 2 2.01U -2 4U -2 4.01U+ -.1 6U -.1 6.0 1U .1 8U .1 8.01U -.1 10U -.1)VDD 4 0 DC 2.5 AC 1.0VSS 0 5 DC 2.5CL 3 0 20PX1 1 3 3 4 5 OPAMP
...(Subcircuit of Table 6.6-1)
....DC VIN+ -2.5 2.5 0.1.PRINT DC V(3).TRAN 0.05U 10U 0 10N.PRINT TRAN V(3) V(1).AC DEC 10 1 10MEG.PRINT AC VDB(3) VP(3).PROBE (This entry is unique to PSPICE).END
vin
vout
VDD
VSS
+
-3
3
1
4
5
Fig. 6.6-16A
Subckt.
-3
-2
-1
0
1
2
3
4
-3 -2 -1 0 1 2 3
vOU
T (V
)
vIN(V)
ID(M5)
0
10
20
30
40
ID(M
5) µ
A
Input CMR
Fig. 240-21
Chapter 6 – Section 6 (5/2/04) Page 6.6-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.6-2 - ContinuedPositive PSRR of Example 6.3-1:
-20
0
20
40
60
80
10 100 1000 104 105 106 107 108
|PSR
R+(jω
)| dB
Frequency (Hz)
-100
-50
0
50
100
10 100 1000 104 105 106 107 108
Arg
[PSR
R+(jω
)] (
Deg
rees
)
Frequency (Hz)
100
Fig. 240-22
Chapter 6 – Section 6 (5/2/04) Page 6.6-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.6-2 - ContinuedNegative PSRR of Example 6.3-1:
10 100 1000 104 105 106 107 108
|PSR
R- (
jω)|
dB
Frequency (Hz)
-200
-150
-100
-50
0
50
100
150
200
10 100 1000 104 105 106 107 108
Arg
[PSR
R- (
jω)]
(D
egre
es)
Frequency (Hz)
20
40
60
80
100
120
Fig. 240-23
PSRR+
Chapter 6 – Section 6 (5/2/04) Page 6.6-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.6-2 - ContinuedLarge-signal and small-signal transient response of Example 6.3-1:
-1.5
-1
-0.5
0
0.5
1
1.5
0 1 2 3 4 5
Vol
ts
Time (Microseconds)
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
2.5 3.0 3.5 4.0 4.5
Vol
ts
Time (Microseconds)
vin(t)
vout(t)
vin(t)
vout(t)
Fig. 240-24
Why the negative overshoot on the slew rate?If M7 cannot sink sufficient current then the output stage
slews and only responds to changes at the output via thefeedback path which involves a delay.
Note that -dvout/dt ≈ -2V/0.3µs = -6.67V/µs. For a 10pFcapacitor this requires 66.7µA and only 95µA-66.7µA = 28µAis available for Cc. For the positive slew rate, M6 can providewhatever current is required by the capacitors and canimmediately respond to changes at the output.
M6
M7
vout
VDD
VSS
VBias-
Cc
CL
+
95µA
iCc iCL dvoutdt
Fig. 240-25
Chapter 6 – Section 6 (5/2/04) Page 6.6-26
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.6-2 - ContinuedComparison of the Simulation Results with the Specifications of Example 6.3-1:
Specification(Power supply = ±2.5V)
Design(Ex. 6.3-1)
Simulation(Ex. 1)
Open Loop Gain >5000 10,000GB (MHz) 5 MHz 5 MHzInput CMR (Volts) -1V to 2V -1.2 V to 2.4 V,Slew Rate (V/µsec) >10 (V/µsec) +10, -7(V/µsec)Pdiss (mW) < 2mW 0.625mWVout range (V) ±2V +2.3V, -2.2VPSRR+ (0) (dB) - 87PSRR- (0) (dB) - 106Phase margin (degrees) 60° 65°Output Resistance (kΩ) - 122.5kΩ
Chapter 6 – Section 6 (5/2/04) Page 6.6-27
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.6-3Why is the negative-going overshootlarger than the positive-going overshooton the small-signal transient response ofthe last slide?Consider the following circuit andwaveform:
During the rise time,iCL = CL(dvout/dt )= 10pF(0.2V/0.1µs) = 20µA and iCc = 3pf(2V/µs) = 6µA∴ i6 = 95µA + 20µA + 6µA = 121µA ⇒ gm6 = 1066µS (nominal was 942.5µS)During the fall time, iCL = CL(-dvout/dt) = 10pF(-0.2V/0.1µs) = -20µAand iCc = -3pf(2V/µs) = -6µA∴ i6 = 95µA - 20µA - 6µA = 69µA ⇒ gm6 = 805µS
The dominant pole is p1 ≈ (RIgm6RIICc)-1 but the GB is gmI/Cc = 94.25µS/3pF =31.42x106 rads/sec and stays constant. Thus we must look elsewhere for the reason.Recall that p2 ≈ gm6/CL which explains the difference.
∴ p2(95µA) = 94.25x106 rads/sec, p2(121µA) = 106.6 x106 rads/sec, and p2(69µA) =80.05 x106 rads/sec. Thus, the phase margin is less during the fall time than the rise time.
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
CcCL
VBias
95µA
94/1i6iCL
0.1V
-0.1V
0.1µs 0.1µs
t
Fig. 240-26
iCc
Chapter 6 – Section 7 (5/2/04) Page 6.7-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 6.7 - MACROMODELS FOR OP AMPSMacromodel
A macromodel is a model that captures some or all of the performance of a circuitusing different components (generally simpler).
A macromodel uses resistors, capacitors, inductors, controlled sources, and someactive devices (mostly diodes) to capture the essence of the performance of a complexcircuit like an op amp without modeling every internal component of the op amp.
Op Amp Characterization• Small signal, frequency independent• Small signal, frequency dependent• Large signal
Time independentTime dependent
Chapter 6 – Section 7 (5/2/04) Page 6.7-2
CMOS Analog Circuit Design © P.E. Allen - 2004
SMALL SIGNAL, FREQUENCY INDEPENDENT, OP AMP MODELSSimple Model
vov1
v2
A Rid
v1
v2
Ro
voAvdRo
(v1-v2)
o
Rid
v1
v2
RoAvd (v1-v2)
1
3
1
2
3
2
4
v
(a.) (b.) (c.) Fig. 010-01
Figure 1 - (a.) Op amp symbol. (b.) Thevenin form of simple model. (c.) Norton form ofsimple model.
SPICE Description of Fig. 1cRID 1 2 RidRO 3 0 RoGAVD 0 3 1 2 Avd/Ro
Subcircuit SPICE Description for Fig. 1c.SUBCKT SIMPLEOPAMP 1 2 3RID 1 2 RidRO 3 0 RoGAVD 0 3 1 2 Avd/Ro
.ENDS SIMPLEOPAMP
Chapter 6 – Section 7 (5/2/04) Page 6.7-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.7-1 - Use of the Simple Op Amp ModelUse SPICE to find the voltage gain, vout/vin, the input resistance, Rin, and the outputresistance, Rout of Fig. 2. The op amp parameters are Avd = 100,000, Rid = 1MΩ, and Ro =100Ω. Find the input resistance, Rin, the output resistance, Rout, and the voltage gain, Av,of the noninverting voltage amplifier configuration when R1 = 1kΩ and R2 = 100kΩ.Solution
The circuit with the SPICE node numbers identified is shown in Fig. 2.
Figure 2 – Noninverting voltage amplifier for Ex. 1.
The input file for this example is given as follows.Example 1VIN 1 0 DC 0 AC 1XOPAMP1 1 3 2 SIMPLEOPAMPR1 3 0 1KOHMR2 2 3 100KOHM.SUBCKT SIMPLEOPAMP 1 2 3RID 1 2 1MEGOHMRO 3 0 100OHMGAVD/RO 0 3 1 2 1000.ENDS SIMPLEOPAMP.TF V(2) VIN.END
The command .TF finds the small signal inputresistance, output resistance, and voltage or currentgain of an amplifier. The results extracted from theoutput file are:
**** SMALL-SIGNAL CHARACTERISTICS V(2)/VIN = 1.009E+02 INPUT RESISTANCE AT VIN = 9.901E+08 OUTPUT RESISTANCE AT V(2) = 1.010E-01.
+
-vin
vout
R2 = 100kΩR1 = 1kΩ
1
3
2A1
Rin Rout
Fig. 010-02
Chapter 6 – Section 7 (5/2/04) Page 6.7-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Common Mode ModelElectrical Model:
vo = Avd(v1-v2) + Acm
Ro
v1+v2
2
Macromodel:
Rid
1
2
Ric1
Ric2
vo
-
+3
Ro
Linear Op Amp Macromodel
Avcv12Ro
Avcv22RoAvd(v1-v2)
Ro
Fig. 010-03
Figure 3 - Simple op amp model including differential and common mode behavior.SPICE File:
.SUBCKT LINOPAMP 1 2 3RIC1 1 0 RicRID 1 2 RidRIC2 2 0 Ric
GAVD/RO 0 3 1 2 Avd/RoGAVC1/RO 0 3 1 0 Avc/2RoGAVC2/RO 0 3 2 0 Avc/2RoRO 3 0 Ro.ENDS LINOPAMP
Chapter 6 – Section 7 (5/2/04) Page 6.7-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Small Signal, Frequency Dependent Op Amp ModelsDominant Pole Model:
Avd(s) = Avd(0)
(s/ω1) + 1 where ω1= 1
R1C1 (dominant pole)
Model Using Passive Components:
Rid
v1
v2
vo1
2R1 C1
Avd(0)R1
(v1-v2)
3
Fig. 010-04
Figure 4 - Macromodel for the op amp including the frequency response of Avd.
Model Using Passive Components with Constant Output Resistance:
Rid
v1
v2
vo31
2R1 C1 Ro
v3Ro
4
Avd(0)R1
(v1-v2)
Fig. 010-05
Figure 5 - Frequency dependent model with constant output resistance.
Chapter 6 – Section 7 (5/2/04) Page 6.7-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.7-2 - Frequency Response of the Noninverting Voltage AmplifierUse the model of Fig. 4 to find the frequency response of Fig. 2 if the gain is +1, +10,
and +100 V/V assuming that Avd(0) = 105 and ω1= 100 rads/sec.Solution
The parameters of the model are R2/R1 = 0, 9, and 99. Let us additionally select Rid =1MΩ and Ro = 100Ω. We will use the circuit of Fig. 2 and insert the model as asubcircuit. The input file for this example is shown below.
Example 2VIN 1 0 DC 0 AC 1*Unity Gain ConfigurationXOPAMP1 1 31 21LINFREQOPAMPR11 31 0 15GOHMR21 21 31 1OHM*Gain of 10 ConfigurationXOPAMP2 1 32 22LINFREQOPAMP
R12 32 0 1KOHMR22 22 32 9KOHM*Gain of 100 ConfigurationXOPAMP3 1 33 23LINFREQOPAMPR13 33 0 1KOHMR23 23 33 99KOHM.SUBCKTLINFREQOPAMP 1 2 3RID 1 2 1MEGOHM
GAVD/RO 0 3 1 2 1000R1 3 0 100C1 3 0 100UF.ENDS.AC DEC 10 100 10MEG.PRINT AC V(21) V(22) V(23).PROBE.END
Chapter 6 – Section 7 (5/2/04) Page 6.7-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.7-2 - Continued
-20dB
-10dB
0dB
10dB
20dB
30dB
40dB
100Hz 1kHz 10kHz 100kHz 1MHz 10MHz
Gain of 100
Gain of 10
Gain of 1
15.9kHz 159kHz 1.59MHz
Fig. 010-06
Figure 6 - Frequency response of the 3 noninverting voltage amplifiers of Ex. 2.
Chapter 6 – Section 7 (5/2/04) Page 6.7-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Behavioral Frequency ModelUse of Laplace behavioral modeling capability in PSPICE.GAVD/RO 0 3 LAPLACE V(1,2) = 1000/(0.01s+1).
Implements,
GAvd/Ro = Avd(s)
Ro =
Avd(0)Ro
sω1 + 1
where Avd(0) = 100,000, Ro = 100Ω, and ω1 = 100 rps
Chapter 6 – Section 7 (5/2/04) Page 6.7-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Differential and Common Mode Frequency Dependent Models
Figure 7 - Op amp macromodel forseparate differential and commonvoltage gain frequency responses.
Rid
2
Ric1
Ric2
vo
-
+3
Op Amp Macromodel
Avcv12Ro
Avcv22Ro
Avd(v1-v2)Ro
v3Ro
R1
R2C2
C1
4
5
Rov4Ro
1
Fig. 010-07
Chapter 6 – Section 7 (5/2/04) Page 6.7-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Zeros in the Transfer FunctionModels:
3
Avd(v1-v2)R1
R1C1 vo
-
+
v3Ro
RokAvdRo
(v1-v2)
4
(a.) (b.)
3
Avd(v1-v2)Ro
Ro
L1
vo
-
+
4
Fig. 010-08
Figure 8 - (a.) Independent zero model. (b.) Method of modeling zeros withoutintroducing new nodes.Inductor:
Vo(s) =
Avd(0)
Ro (sL1 + Ro) [V1(s)-V2(s)] = Avd(0)
s
Ro/L1 + 1 [V1(s)-V2(s)] .
Feedforward:
Vo(s) =
Avd(0)
(s/ω1) +1 1+k(s/ω1)+k [V1(s)-V2(s)] .
The zero can be expressed as z1 = -ω1
1 + 1k
where k can be + or - by reversing the direction of the current source.
Chapter 6 – Section 7 (5/2/04) Page 6.7-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.7-3 - Modeling Zeros in the Op Amp Frequency ResponseUse the technique of Fig. 8b to model an op amp with a differential voltage gain of
100,000, a pole at 100rps, an output resistance of 100Ω, and a zero in the right-half,complex frequency plane at 107 rps.Solution
The transfer function we want to model is given as
Vo(s) = 105(s/107 - 1)(s/100 + 1) .
Let us arbitrarily select R1 as 100kΩ which will make the GAVD/R1 gain unity. To getthe pole at 100rps, C1 = 1/(100R1) = 0.1µF. Next, we want z1 to be 107 rps. Since ω1 =100rps, then Eq. (6) gives k as -10-5. The following input file verifies this model.
Example 3VIN 1 0 DC 0 AC 1XOPAMP1 1 0 2 LINFREQOPAMP.SUBCKT LINFREQOPAMP 1 2 4RID 1 2 1MEGOHMGAVD/R1 0 3 1 2 1R1 3 0 100KOHMC1 3 0 0.1UF
GV3/RO 0 4 3 0 0.01GAVD/RO 4 0 1 2 0.01RO 4 0 100.ENDS.AC DEC 10 1 100MEG.PRINT AC V(2) VDB(2) VP(2).PROBE.END
Chapter 6 – Section 7 (5/2/04) Page 6.7-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.7-3 - ContinuedThe asymptotic magnitude frequency response of this simulation is shown in Fig. 9.
We note that although the frequency response is plotted in Hertz, there is a pole at 100rps(15.9Hz) and a zero at 1.59MHz (10Mrps). Unless we examined the phase shift, it is notpossible to determine whether the zero is in the RHP or LHP of the complex frequencyaxis.
VD
B(2
)
0dB
20dB
40dB
60dB
80dB
100dB
1Hz 100Hz10Hz 1kHz 10kHz 100kHz 1MHz 10MHz
15.9Hz or 100rps
1.59MHz or 10Mrps
Frequency Fig. 010-09
Figure 9 - Asymptotic magnitude frequency response of the op amp model of Ex. 6.7-3.
Chapter 6 – Section 7 (5/2/04) Page 6.7-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Large Signal Macromodels for the Op AmpOutput and Input Voltage Limitations
Nonlinear Op Amp Macromodel
10 vo
-
+3
Ro
Avcv42Ro 11
D6+
-
+
-
D5
VOH VOL
Avcv52Ro
Rid
1
2 5
Ric1
Ric2
7D1 D2
+
-
+
-
RLIM 4
6
D3 D49+
-
+
-
RLIM
8
VIH1
VIH2 VIL2
VIL1
AvdRo
(v4-v5)
Fig. 010-10
Figure 10 - Op amp macromodel that limits the input and output voltages.Subcircuit Description
.SUBCKT NONLINOPAMP 1 2 3RIC1 1 0 RicmRLIM1 1 4 0.1D1 4 6 IDEALMODVIH1 6 0 VIH1D2 7 4 IDEALMODVIL1 7 0 VIL1RID 4 5 RidRIC2 2 0 RicmRLIM2 2 5 0.1D3 5 8 IDEALMODVIH2 8 0 VIH1
D4 9 5 IDEALMODVIL2 9 0 VIL2GAVD/RO 0 3 4 5 Avd/RoGAVC1/RO 0 3 4 0 Avc/RoGAVC2/RO 0 3 5 0 Avc/RoRO 3 0 RoD5 3 10 IDEALMODVOH 10 0 VOHD6 11 3 IDEALMODVOL 11 0 VOL.MODEL IDEALMOD D N=0.001
.ENDS
Chapter 6 – Section 7 (5/2/04) Page 6.7-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.7-4 - Illustration of the Voltage Limits of the Op AmpUse the macromodel of Fig. 10 to plot vOUT as a function of vIN for the noninverting,
unity gain, voltage amplifier when vIN is varied from -15V to +15V. The op ampparameters are Avd(0) = 100,000, Rid = 1MΩ, Ricm = 100MΩ, Avc(0) = 10, Ro = 100Ω,VOH = -VOL = 10V, VIH1 =VIH2 = -VIL1 = -VIL2 = 5V.Solution
The input file for this example is given below.Example 4VIN 1 0 DC 0XOPAMP 1 2 2 NONLINOPAMP.SUBCKT NONLINOPAMP 1 2 3RIC1 1 0 100MEGRLIM1 1 4 0.1D1 4 6 IDEALMODVIH1 6 0 5VD2 7 4 IDEALMOD
VIL1 7 0 -5VRID 4 5 1MEGRIC2 2 0 100MEGRLIM2 2 5 0.1D3 5 8 IDEALMODVIH2 8 0 5VD4 9 5 IDEALMODVIL2 9 0 -5vGAVD/RO 0 3 4 5 1000GAVC1/2RO 0 3 4 0 0.05GAVC2/2RO 0 3 5 0 0.05
RO 3 0 100D5 3 10 IDEALMODVOH 10 0 10VD6 11 3 IDEALMODVOL 11 0 -10V.MODEL IDEALMOD D N=0.0001.ENDS.DC VIN -15 15 0.1.PRINT V(2).PROBE.END
Chapter 6 – Section 7 (5/2/04) Page 6.7-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.7-4 - Illustration of the Voltage Limits of the Op Amp - Continued
-7.5V
-5V
-2.5V
0V
2.5V
5V
7.5V
-10V -5V 0V 5V 10V
V(2)
VIN Fig. 010-11
Figure 11 - Simulation results for Ex. 4.
Chapter 6 – Section 7 (5/2/04) Page 6.7-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Output Current LimitingTechnique:
D1
D2
D3
D4
ILimit
Io Io
Io2
ILimit2
Io2
Io2
Io2
ILimit2
Fig. 010-12
Macromodel for Output Voltage and Current Limiting:
Rid
v1
v2
Ro
vo31
2AvdRo
(v1-v2)7+
-
8+
-
D1
D2
D3
D4D5 D6
ILimit VOH VOL
45
6
Fig. 010-13
Chapter 6 – Section 7 (5/2/04) Page 6.7-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.7-5 - Influence of Current Limiting on the Amplifier Voltage TransferCurve
Use the model above to illustrate the influence of current limiting on the voltagetransfer curve of an inverting gain of one amplifier. Assume the VOH = -VOL = 10V, VIH = -VIL = 10V, the maximum output current is ±20mA, and R1 = R2 = RL = 500Ω where RL is aresistor connected from the output to ground. Otherwise, the op amp is ideal.Solution
For the ideal op amp we will choose Avd = 100,000, Rid = 1MΩ, and Ro = 100Ω andassume one cannot tell the difference between these parameters and the ideal parameters.The remaining model parameters are VOH = -VOL = 10V and ILimit = ±20mA.
The input file for this simulation is given below. Example 5 - Influence of Current Limiting on the Amplifier Voltage Transfer Curve
VIN 1 0 DC 0R1 1 2 500R2 2 3 500RL 3 0 500XOPAMP 0 2 3 NONLINOPAMP.SUBCKT NONLINOPAMP 1 2 3RID 1 2 1MEGOHMGAVD 0 4 1 2 1000RO 4 0 100D1 3 5 IDEALMODD2 6 3 IDEALMODD3 4 5 IDEALMOD
D4 6 4 IDEALMODILIMIT 5 6 20MAD5 3 7 IDEALMODVOH 7 0 10VD6 8 3 IDEALMODVOL 8 0 -10V.MODEL IDEALMOD D N=0.00001.ENDS.DC VIN -15 15 0.1.PRINT DC V(3).PROBE.END
Chapter 6 – Section 7 (5/2/04) Page 6.7-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.7-5 - ContinuedThe resulting plot of the output voltage, v3, as a function of the input voltage, vIN is shownin Fig. 14.
-10V
-5V
0V
5V
10V
V(3
)
-15V -10V -5V 0V 5V 10V 15VVIN Fig. 010-14
Figure 14 - Results of Example 5.
Chapter 6 – Section 7 (5/2/04) Page 6.7-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Slew Rate Limiting (Time Dependency)Slew Rate:
dvo
dt = ±ISR
C1 = Slew Rate
Macromodel:
Rid
v1
v2
vo3
1
2R1
C1Avd(0)R1
(v1-v2)
D1
D2
D3
D4
6
7Ro
v4-v5Ro
45
ISR
Fig. 010-15
Chapter 6 – Section 7 (5/2/04) Page 6.7-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.7-6 - Simulation of the Slew Rate of A Noninverting Voltage AmplifierLet the gain of a noninverting voltage amplifier be 1. If the input signal is given as
vin(t) = 10 sin(4x105πt)use the computer to find the output voltage if the slew rate of the op amp is 10V/µs.Solution
We can calculate that the op amp should slew when the frequency is 159kHz. Let usassume the op amp parameters of Avd = 100,000, ω1 = 100rps, Rid = 1MΩ, and Ro =100Ω. The simulation input file based on the macromodel of Fig. 15 is given below.
Example 6 - Simulation of slew rate limitation
VIN 1 0 SIN(0 10 200K)XOPAMP 1 2 2 NONLINOPAMP.SUBCKT NONLINOPAMP 1 2 3RID 1 2 1MEGOHMGAVD/R1 0 4 1 2 1R1 4 0 100KOHMC1 4 5 0.1UFD1 0 6 IDEALMOD
D2 7 0 IDEALMODD3 5 6 IDEALMODD4 7 5 IDEALMODISR 6 7 1AGVO/R0 0 3 4 5 0.01RO 3 0 100.MODEL IDEALMOD D N=0.0001.ENDS
Chapter 6 – Section 7 (5/2/04) Page 6.7-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 6.7-6 - ContinuedThe simulation results are shown in Fig. 16. The input waveform is shown along with theoutput waveform. The influence of the slew rate causes the output waveform not to beequal to the input waveform.
-10V
-5V
0V
5V
10V
0µs 2µs 4µs 6µs 8µs 10µs
InputVoltage
OutputVoltage
Time Fig. 010-16
Figure 16 - Results of Ex. 6 on modeling the slew rate of an op amp.
Chapter 6 – Section 7 (5/2/04) Page 6.7-22
CMOS Analog Circuit Design © P.E. Allen - 2004
SPICE Op Amp Library ModelsMacromodels developed from the data sheet for various components.Key Aspects of Op Amp Macromodels:
• Use the simplest op amp macromodel for a given simulation.• All things being equal, use the macromodel with the min. no. of nodes.• Use the SUBCKT feature for repeated use of the macromodel.• Be sure to verify the correctness of the macromodels before using.• Macromodels are a good means of trading simulation completeness for decreased
simulation time.
Chapter 6 – Section 8 (5/2/04) Page 6.8-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 6.8 - SUMMARY• Topics
Design of CMOS op ampsCompensation of op amps
- Miller- Self-compensating- Feedforward
Two-stage op amp designPower supply rejection ratio of the two-stage op ampCascode op ampsSimulation and measurement of op ampsMacromodels of op amps
• Purpose of this chapter is to introduce the simple two-stage op amp to illustrate theconcepts of op amp design and to form the starting point for the improvement ofperformance of the next chapter.
• The design procedures given in this chapter are for the purposes of understanding andapplying the design relationships and should not be followed rigorously as the designergains experience.
Chapter 7 – Introduction (5/2/04) Page 7.0-1
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 7 - HIGH-PERFORMANCE CMOS OPERATIONALAMPLIFIERS
Chapter Outline7.1 Buffered Op Amps7.2 High-Speed/Frequency Op Amps7.3 Differential Output Op Amps7.4 Micropower Op Amp7.5 Low-Noise Op Amps7.6 Low Voltage Op Amps7.7 SummaryGoalTo illustrate the degrees of freedomand choices of different circuitarchitectures that can enhance theperformance of a given op amp. Two-Stage
Op Amp
BufferedHigh FrequencyDifferential
Output
Low Power Low Noise
Low Voltage Fig. 7.0-1
Chapter 7 – Section 1 (5/2/04) Page 7.1-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 7.1 – BUFFERED OP AMPSObjectiveThe objective of this presentation is:1.) Illustrate the method of lowering the output resistance of simple op amps2.) Show examplesOutline• Open-loop MOSFET buffered op amps• Closed-loop MOSFET buffered op amps• BJT output op amps• Summary
Chapter 7 – Section 1 (5/2/04) Page 7.1-2
CMOS Analog Circuit Design © P.E. Allen - 2004
What is a Buffered Op Amp?A buffered op amp is an op amp with a low value of output resistance, Ro.
Typically, 10Ω ≤ Ro ≤ 1000Ω
RequirementsGenerally the same as for the output amplifier:• Low output resistance• Large output signal swing• Low distortion• High efficiencyTypes of Buffered Op Amps• Buffered op amps using MOSFETs
With and without negative feedback• Buffered op amps using BJTs
Chapter 7 – Section 1 (5/2/04) Page 7.1-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Source-Follower, Push-Pull Output Op Amp
vout
VDD
VDD
Cc
-
+vin
M1 M2
M3
VSS
R1
M5
M6
R1
M7
M8
R1
M13
M14
VSS
VDD
VSS
M22
M21
IBias
M9
M10
M11
M12
M4
M17
M18
M15
M16
M19
M20
Fig. 7.1-1
CL
Buffer
-+VSG18
-+VSG21
-
+VGS19
-
+VGS22
I17
I20
Rout = 1
gm21+gm22 ≤ 1000Ω, Av(0) = 65dB (IBias=50µA), and GB = 60MHz for CL = 1pF
Output bias current?M18-M19-M21-M22 loop ⇒ VSG18+VGS19 = VSG21+VGS22
which gives2I18
KPS18 + 2I19
KNS19 = 2I21
KPS21 + 2I22
KNS22
Chapter 7 – Section 1 (5/2/04) Page 7.1-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Crossover-Inverter, Buffer Stage Op AmpPrinciple: If the buffer has high output resistance and voltage gain (common source), thisis okay if when loaded by a small RL the gain of this stage is approximately unity.
-
+vin
M1 M2
M3 M4
M5
M6M7
vout
VDD
VSS
C2=5pF
RL
+-
C1=8pF
100µA
140014
24007.5
24014144
14
24014
4607.5
3607.5
Cross over stage Output StageFig. 7.1-2
Inputstage
vin'
This op amp is capable of delivering 160mW to a 100Ω load while only dissipating 7mWof quiescent power!
Chapter 7 – Section 1 (5/2/04) Page 7.1-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Crossover-Inverter, Buffer Stage Op Amp - ContinuedHow does the output buffer work?The two inverters, M1-M3 and M2-M4 are designed to work over different regions of thebuffer input voltage, vin’.
Consider the idealized voltage transfer characteristic of the crossover inverters:
VDDVA
M6 Active
M6 Satur-ated
M5 Active
M5 Saturated
VB
M1-M3Inverter
M2-M4Inverter
0 vin'
Fig. 7.1-3
M1 M2
M3 M4M7
vout
VDD
VSS
C2=5pFC1=8pF
100µA
24014144
14
24014
4607.5
3607.5
vin'
M6
M5 RL
voutVDD
VSS
Crossover voltage ≡ VC = VB-VA ≥ 0
VC is designed to be small and positive for worst case variations in processing(Maximum value of VC ≈ 110mV)
Chapter 7 – Section 1 (5/2/04) Page 7.1-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Crossover-Inverter, Buffer Stage Op Amp - ContinuedPerformance Results for the Crossover-Inverter, Buffer Stage CMOS Op Amp
Specification PerformanceSupply Voltage ± 6 VQuiescent Power 7 mWOutput Swing (100ΩLoad)
8.1 Vpp
Open-Loop Gain (100ΩLoad)
78.1 dB
Unity Gainbandwidth 260kHzVoltage Spectral NoiseDensity at 1kHz
1.7 µV/ Hz
PSRR at 1kHz 55 dBCMRR at 1kHz 42 dBInput Offset Voltage(Typical)
10 mV
Chapter 7 – Section 1 (5/2/04) Page 7.1-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Compensation of Op Amps with Output AmplifiersCompensation of a three-stage amplifier:This op amp introduces a third pole, p’3 (whatabout zeros?)With no compensation,
Vout(s)Vin(s) =
-Avo
s
p’1 - 1
s
p’2 - 1
s
p’3 - 1
Illustration of compensation choices:
p1'p2'p3' p1
p2
p3
jω
σp1'p2'p3' p1
p2
p3=
jω
σ
Miller compensation applied around both the second and the third stage.
Miller compensation applied around the second stage only. Fig. 7.1-5
Compensated polesUncompensated poles
vin vout+-
x1v2
Unbufferedop amp
Outputstage
Polesp1' and p2'
Pole p3'
+
-
Fig. 7.1-4
CL RL
Chapter 7 – Section 1 (5/2/04) Page 7.1-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Low Output Resistance Op AmpTo get low output resistance using MOSFETs, negative feedback must be used.Ideal implementation:
CL RL
viin vout
iout
VDD
M2
M1
Fig. 7.1-5A
+-
+-
ErrorAmplifier
ErrorAmplifier
VSS
+-
GainAmplifier
Comments:• The output resistance will be equal to rds1||rds2 divided by the loop gain
• If the error amplifiers are not perfectly matched, the bias current in M1 and M2 is notdefined
Chapter 7 – Section 1 (5/2/04) Page 7.1-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Low Output Resistance Op Amp - ContinuedOffset correction circuitry:
-
+vin
A1
M16 M9
vout
VDD
VSS
VBias+
-
Cc
+-
+-
+-M8
M17
M8A
M13M6A
M6
M12 M11
M10
A2
VOS
Error Loop
Fig. 7.1-6
Unbufferedop amp
The feedback circuitry of the two error amplifiers tries to insure that the voltages inthe loop sum to zero. Without the M9-M12 feedback circuit, there is no way to adjust theoutput for any error in the loop. The circuit works as follows:
When VOS is positive, M6 tries to turn off and so does M6A. IM9 reduces thusreducing IM12. A reduction in IM12 reduces IM8A thus decreasing VGS8A. VGS8Aideally decreases by an amount equal to VOS. A similar result holds for negativeoffsets and offsets in EA2.
Chapter 7 – Section 1 (5/2/04) Page 7.1-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Low Output Resistance Op Amp - ContinuedError amplifiers:
vin M1 M2
M3 M4
M5
M6
M6A
vout
VDD
VSS
VBias+
-
Cc1
A1 amplifier
MR1
Fig. 7.1-7
Chapter 7 – Section 1 (5/2/04) Page 7.1-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Low Output Resistance Op Amp - Complete Schematic
Compensation:Uses nulling Miller compensation.
Short circuit protection:MP3-MN3-MN4-MP4-MP5MN3A-MP3A-MP4A-MN4A-MN5A(max. output ±60mA)
M2
M3 M4
M5
M1
vout
VDD
VSS
VBiasN+
-
Cc
+-
VBiasP+
-
Cc1
M16M3H M4H MP4
MP3
MP5
MR1
M8
M17 MN3 MN4
M6
M6A
M13 M12 M11
MR2Cc2
M8A
M9
MN5A
MN4A
MN3A
MP4A
MP3A
M4HA
M4A M3A
M3HA
M1AM2A
M5Avin+
-
Fig. 7.1-8
M10
RC
R1 RL CL
CC
C1
gm1 gm6
Chapter 7 – Section 1 (5/2/04) Page 7.1-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Low Output Resistance Op Amp - ContinuedTable 7.1-2 Performance Characteristics of the Low Output Resistance Op Amp:
Specification Simulated Results Measured ResultsPower Dissipation 7.0 mW 5.0 mWOpen Loop Voltage Gain 82 dB 83 dBUnity Gainbandwidth 500kHz 420 kHzInput Offset Voltage 0.4 mV 1 mVPSRR+(0)/PSRR-(0) 85 dB/104 dB 86 dB/106 dB
PSRR+(1kHz)/PSRR-(1kHz) 81 dB/98 dB 80 dB/98 dBTHD (Vin = 3.3Vpp) RL = 300Ω 0.03% 0.13%(1 kHz) CL = 1000pF 0.08% 0.32%(4 kHz)THD (Vin = 4.0Vpp) RL = 15KΩ 0.05% 0.13%(1 kHz) CL = 200pF 0.16% 0.20%(4 kHz)
Settling Time (0.1%) 3 µs <5 µsSlew Rate 0.8 V/µs 0.6 V/µs1/f Noise at 1kHz - 130 nV/ HzBroadband Noise - 49 nV/ Hz
Rout ≈ rds6||rds6ALoop Gain ≈
50kΩ5000 = 10Ω
Chapter 7 – Section 1 (5/2/04) Page 7.1-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Low-Output Resistance Op Amp - ContinuedComponent sizes for the low-resistance op amp:
Transistor/Capacitor µm/µm or pF Transistor/Capacitor µm/µm or pFM16 184/9 M8A 481/6M17 66/12 M13 66/12M8 184/6 M9 27/6M1, M2 36/10 M10 6/22M3, M4 194/6 M11 14/6M3H, M4H 16/12 M12 140/6M5 145/12 MP3 8/6M6 2647/6 MN3 244/6MRC 48/10 MP4 43/12CC 11.0 MN4 12/6M1A, M2A 88/12 MP5 6/6M3A, M4A 196/6 MN3A 6/6M3HA, M4HA 10/12 MP3A 337/6M5A 229/12 MN4A 24/12M6A 2420/6 MP4A 20/12CF 10.0 MN5A 6/6
Chapter 7 – Section 1 (5/2/04) Page 7.1-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Simpler Implementation of Negative Feedback to Achieve Low Output Resistance
Output Resistance:
Rout = Ro
1+LG
where
Ro = 1
gds6+gds7
and
|LG| = gm22gm4
(gm6+gm7)Ro
Therefore, the output resistance is
Rout = 1
(gds6+gds7)
1 +
gm2
2gm4 (gm6+gm7)Ro
.
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
CL
M8
M10
M9
Fig. 7.1-9
1/1 10/1200µA 10/1
10/1 10/1
1/1
1/1
1/1
10/1 10/1
Chapter 7 – Section 1 (5/2/04) Page 7.1-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.1-1 - Low Output Resistance Using the Simple Shunt Negative FeedbackBufferFind the output resistance of above op amp using the model parameters of Table 3.1-2.SolutionThe current flowing in the output transistors, M6 and M7, is 1mA which gives Ro of
Ro = 1
(λN+λP)1mA = 10000.09 = 11.11kΩ
To calculate the loop gain, we find that
gm2 = 2KN’·10·100µA = 469µS
gm4 = 2KP’·1·100µA = 100µS
and gm6 = 2KP’·10·1000µA = 1mS
Therefore, the loop gain is
|LG| = 469100 12·11.11 = 104.2
Solving for the output resistance, Rout, gives
Rout = 11.11kΩ1 + 104.2 = 106Ω (Assumes that RL is large)
Chapter 7 – Section 1 (5/2/04) Page 7.1-16
CMOS Analog Circuit Design © P.E. Allen - 2004
BJTs Available in CMOS TechnologyIllustration of an NPN substrate BJT available in a p-well CMOS technology:
n- substrate (Collector)
p- well (Base)
n+ (Emitter) p+
n+
Emitter Base Collector(VDD)
Collector (VDD)
Emitter
Base
Fig. 7.1-10
Comments:• gm of the BJT is larger than the FET so that the output resistance w/o feedback is lower
• Can use the lateral or substrate BJT but since the collector is on ac ground, thesubstrate BJT is preferred
• Current is required to drive the BJT
Chapter 7 – Section 1 (5/2/04) Page 7.1-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage Op Amp with a Class-A BJT Output Buffer StagePurpose of the M8-M9 sourcefollower:1.) Reduce the output resistance
(includes whatever is seen fromthe base to ground divided by1+βF)
2.) Reduces the output load at thedrains of M6 and M7
Small-signal output resistance :
Rout ≈ rπ10 + (1/gm9)
1+ßF =
1gm10
+ 1
gm9(1+ßF)
= 51.6Ω+6.7Ω = 58.3Ω where I10=500µA, I8=100µA, W9/L9=100 and ßF is 100Maximum output voltage:
vOUT(max) = VDD - VSD8(sat) - vBE10 = VDD - 2KP’
I8(W8/L8) - Vt ln
Ic10
Is10
Voltage gain:voutvin
≈
gm1
gds2+gds4
gm6
gds6+gds7
gm9
gm9+gmbs9+gds8+gπ10
gm10RL
1+gm10RL
Compensation will be more complex because of the additional stages.
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
CcCL
IBias
Q10
M11
M12
M13
Fig. 7.1-11
M8
M9
Output Buffer
RL
vin
+
-
Chapter 7 – Section 1 (5/2/04) Page 7.1-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.1-2 - Designing the Class-A, Buffered Op AmpUse the parameters of Table 3.1-2 along with the BJT parameters of Is = 10-14A and
ßF = 100 to design the class-A, buffered op amp to give the following specifications.Assume the channel length is to be 1µm.VDD = 2.5V VSS = -2.5V GB = 5MHz Avd(0) ≥ 5000V/V Slew rate ≥ 10V/µs
RL = 500Ω Rout ≤ 100Ω CL = 100pF ICMR = -1V to 2V
SolutionBecause the specifications above are similar to the two-stage design of Ex. 6.3-1, we
can use these results for the first two stages of our design. However, we must convert theresults of Ex. 6.3-1 to a PMOS input stage. The results of doing this give W1= W2 =6µm, W3 = W4 = 7µm, W5 = 11µm, W6 = 43µm, and W7 = 34µm.
BJT follower:SR = 10V/µs and 100pF capacitor give I11 = 1mA.
∴ If W13 = 44µm, then W11 = 44µm(1000µA/30µA) = 1467µm.I11 = 1mA ⇒ 1/gm10 = 0.0258V/1mA = 25.8Ω
MOS follower:To source 1mA, the BJT must provide 2mA which requires 20µA from the MOS follower. Therefore, select a bias current of 100µA for M8. If W12 = 44µm, then W8 = 44µm(100µA/30µA) = 146µm.
Chapter 7 – Section 1 (5/2/04) Page 7.1-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.1-2 - ContinuedIf 1/gm10 is 25.8Ω, then design gm9 as
gm9=1
Rout - (1/gm10) (1+ßF) = 1
(100-25.8)(101) = 133.4µS gm9 and I9 ⇒ W/L = 0.809
Let us select W/L = 10 for M9 in order to make sure that the contribution of M9 to theoutput resistance is sufficiently small and to increase the gain closer to unity. This gives atransconductance of M9 of 300µS.
To calculate the voltage gain of the MOS follower we need to find gmbs9.
∴ gmbs9 = gm9γN
2 2φF + VBS9 =
300·0.42 0.7+2 = 36.5µS
where we have assumed that the value of VSB9 is approximately 2V.
∴ AMOS = 300µS
300µS+36.5µS+4µS+5µS = 0.8683 V/V.
The voltage gain of the BJT follower is
ABJT = 500
25.8+500 = 0.951 V/V
Thus, the gain of the op amp isAvd(0) = (7777)(0.8683)(0.951) = 6422 V/V
The power dissipation of this amplifier is, Pdiss. = 5V(1255µA) = 6.27mW
Chapter 7 – Section 1 (5/2/04) Page 7.1-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage Op Amp with a Class-AB BJT Output Buffer StageThis amplifier can reduce the quiescent power dissipation.
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
Cc
CL
vin
IBias
Q8
M10
Fig. 7.1-12
M9
Output Buffer
RL
+
-95µA
133µA
Slew Rate:
SR+ = I+OUT
CL =
(1 + βF)I7CL
and SR- = β9(VDD − 1V + |VSS| − VT0)2
2CL
If βF = 100, CL = 1000pF and I7 = 95µA then SR+ = 8.59V/µs.
Assuming a W9/L9 = 60 (I9 = 133µA), ±2.5V power supplies and CL = 1000pF gives SR-
= 35.9V/µs.(The current is not limited by I7 as it is for the positive slew rate.)
Chapter 7 – Section 1 (5/2/04) Page 7.1-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage Op Amp with a Class-AB BJT Output Buffer StageSmall-signal characteristics:
Nodal equations:gmIVin = (GI + sCc)V1 − sCcV2 + 0Vout
0 = (gmII − sCc)V1 + (GII + gπ + sCc + sCπ)V2 − (gπ + sCπ)Vout 0 ≅ gm9V1 − (gm13 + sCπ)V2 + (gm13 + sCπ)Vout where gπ > G3
The approximate voltage transfer function is:V9(s)Vin(s) ≈ Av0
(s/z1) − 1 (s/z2) − 1
(s/p1) − 1 (s/p2) − 1where
Av0 = −gmIgmII
GIGIIz1 =
1Cc
gmII −
Cπgm13
1 + gm9gmII
z2 = −gm13Cπ +
gmIICc
1 + gm9gmII
p1 = −GIGIIgmIICc
1 + gm9
βFgmII +
CπCc
GIGII
gm13gmII
-1p2 ≅
−gm13gmII
(gmII + gm9)Cπ
VoutgmIVin R1
+
V1
-gmIIV2
R2
Cc
+
V2
-
Cπ
+ -Vπ
gm8Vπ
R3 gm9V1
Fig. 7.1-13
rπ
Chapter 7 – Section 1 (5/2/04) Page 7.1-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage Op Amp with a Class-AB BJT Output Buffer Stage - ContinuedOutput stage current, IC8:
IC8 = ID9 = S9S6
ID6 = 6043 95µA = 133µA
Small-signal output resistance:
rout = rπ + RII
1 + βF =
19.668kΩ + 116.96kΩ101 =1353Ω
if I6 =I7 = 95µA, and βF = 100.
Loading effect of RL on the voltagetransfer curve (increasing W9/L9 willimprove the negative part at the costof power dissipation):
-3
-2
-1
0
1
2
-2 -1.5 -1 -0.5 0
v OU
T (V
olts
)
vIN (Volts)
RL =50ΩRL = 100Ω
RL = 1000Ω
Fig. 7.1-14A0.5 1 1.5 2
Chapter 7 – Section 1 (5/2/04) Page 7.1-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.1-3 - Performance of the Two-Stage, Class AB Output BufferUsing the transistor currents given above for the output stages (output stage of the
two-stage op amp and the buffer stage), find the small-signal output resistance and themaximum output voltage when RL = 50Ω. Use the W/L values of Example 7.1-2 andassume that the NPN BJT has the parameters of ßF = 100 and IS = 10fA.
SolutionIt was shown on the previous slide that the small-signal output resistance is
rout = rπ + rds6||rds7
1+ßF =
19.668kΩ + 116.96kΩ101 = 1353Ω
Obviously, the MOS buffer of Fig. 7.1-11 would decrease this value.The maximum output voltage is given above is only valid if the load current is small.
If this is not the case, then a better approach is to assume that all of the current in M7becomes base current for Q8. This base current is multiplied by 1+ßF to give the sourcingcurrent. If M9 is off, then all this current flows through the load resistor to give an outputvoltage of
vOUT(max) ≈ (1+ßF)I7RL
If the value of vOUT(max) is close to VDD, then the source-drain voltage across M7 maybe too small to be in saturation causing I7 to decrease. Using the above equation, wecalculate vOUT(max) as (101)·95µA·50Ω or 0.48V which is close to the simulation resultsshown using the parameters of Table 3.1-2.
Chapter 7 – Section 1 (5/2/04) Page 7.1-24
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• A buffered op amp requires an output resistance between 10Ω ≤ Ro ≤ 1000Ω
• Output resistance using MOSFETs only can be reduced by,
- Source follower output (1/gm)
- Negative shunt feedback (frequency is a problem in this approach)• Use of substrate (or lateral) BJT’s can reduce the output resistance because gm is
larger than the gm of a MOSFET
• Adding a buffer stage to lower the output resistance will most likely complicate thecompensation of the op amp
Chapter 7 – Section 2 (5/2/04) Page 7.2-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 7.2 – HIGH SPEED/FREQUENCY OP AMPSObjectiveThe objective of this presentation is:1.) Explore op amps having high frequency response and/or high slew rate2.) Give examplesOutline
• Extending the GB of conventional op amps• Switched op amps• Current feedback op amps• Programmable gain amplifiers• Parallel path op amps• Summary
Chapter 7 – Section 2 (5/2/04) Page 7.2-2
CMOS Analog Circuit Design © P.E. Allen - 2004
What is the Influence of GB on the Frequency Response?The op amp is primarily designed to be used with negative feedback. When the productof the op amp gain and feedback gain (loss) is not greater than unity, negative feedbackdoes not work satisfactorily.Example of a gain of -10 voltage amplifier:
0dB
20dB
|Avd(0)| dB
Magnitude
log10(ω)GBωA ω-3dB
Op amp frequency response
Amplifier with a gain of -10
Fig. 7.2-1
What causes the GB?We know that
GB = gmC
where gm is the transconductance that converts the input voltage to current and C is thecapacitor that causes the dominant pole.This relationship assumes that all higher-order poles are greater than GB.
Chapter 7 – Section 2 (5/2/04) Page 7.2-3
CMOS Analog Circuit Design © P.E. Allen - 2004
What is the Limit of GB?The following illustrates whathappens when the next higher pole isnot greater than GB:
For a two-stage op amp, the polesand zeros are:
1.) Dominant pole p1 = -gm1
Av(0)Cc
2.) Output pole p2 = -gm6CL
3.) Mirror pole p3 = -gm3
Cgs3+Cgs4
4.) Nulling pole p4 = -1
RzCI
5.) Nulling zero z1 = -1
RzCc-(Cc/gm6)
0dB
20dB
|Avd(0)| dB
Magnitude
log10(ω)GBωA ω-3dB
Op amp frequency response
Amplifier with a gain of -10
Fig. 7.2-2
Next higher pole-40dB/dec
Chapter 7 – Section 2 (5/2/04) Page 7.2-4
CMOS Analog Circuit Design © P.E. Allen - 2004
A Procedure to Increase the GB of a Two-Stage Op Amp1.) Use the nulling zero to cancel the closest pole beyond the dominant pole.2.) The maximum GB would be equal to the magnitude of the second closest pole beyond
the dominant pole.3.) Adjust the dominant pole so that 2.2GB ≈ (second closest pole beyond the dominant
pole)Illustration which assumes that p2 is the next closest pole beyond the dominant pole:
0dB
|Avd(0)| dB
Magnitude
log10(ω)
Fig. 7.2-3
-40dB/dec
-p1-p2 = z1-p4-p3
|p1| |p2|
|p4||p3|
-60dB/dec-80dB/dec
Before cancellingp2 by z1 and increasing p1
jωσ
|p1|
GB
-p1New Old
GBIncrease
OldGBNew
Old New
Chapter 7 – Section 2 (5/2/04) Page 7.2-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.2-1 - Increasing the GB of the Op Amp Designed in Ex. 6.3-1Use the two-stage op amp designed
in Example 6.3-1 and apply the aboveapproach to increase the gainbandwidthas much as possible.Solution1.) First find the values of p2, p3, and p4.
(a.) From Ex. 6.3-2, we see thatp2 = -94.25x106 rads/sec.
(b.) p3 was found in Ex. 6.3-1 asp3 = -2.81x109 rads/sec.
(c.) To find p4, we must find CI which is the output capacitance of the first stage of the opamp. CI consists of the following capacitors,
CI = Cbd2 + Cbd4 + Cgs6 + Cgd2 + Cgd4
For Cbd2 the width is 3µm ⇒ L1+L2+L3 = 3µm ⇒ AS/AD=9µm2 and PS/PD = 12µm.For Cbd4 the width is 15µm ⇒ L1+L2+L3 = 3µm ⇒ AS/AD=45µm2 and PS/PD = 36µm.
From Table 3.2-1:Cbd2 = (9µm2)(770x10-6F/m2) + (12µm)(380x10-12F/m) = 6.93fF+4.56fF = 11.5fF
Cbd4 = (45µm2)(560x10-6F/m2) + (36µm)(350x10-12F/m) = 25.2fF+12.6F ≈ 37.8fF
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
Cc = 3pF
CL =10pF
3µm1µm
3µm1µm
15µm1µm
15µm1µm
M84.5µm1µm
30µA
4.5µm1µm
14µm1µm
94µm1µm
30µA
95µA
Fig. 7.2-3A
Rz
Chapter 7 – Section 2 (5/2/04) Page 7.2-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.2-1 - ContinuedCgs6 is given by Eq. (10b) of Sec. 3.2 and is
Cgs6 = CGDO·W6+0.67(CoxW6L6)=(220x10-12)(94x10-6)+(0.67)(24.7x10-4)(94x10-12)
= 20.7fF + 154.8fF = 175.5fF
Cgd2 = 220x10-12x3µm = 0.66fF and Cgd4 = 220x10-12x15µm = 3.3fF
Therefore, CI = 11.5fF + 37.8fF + 175.5fF + 0.66fF + 3.3fF = 228.8fF. Although Cbd2 andCbd4 will be reduced with a reverse bias, let us use these values to provide a margin. Infact, we probably ought to double the whole capacitance to make sure that other layoutparasitics are included. Thus let CI be 300fF.
In Ex. 6.3-2, Rz was 4.591kΩ which gives p4 = - 0.726x109 rads/sec.
2.) Using the nulling zero, z1, to cancel p2, gives p4 as the next smallest pole.
For 60° phase margin GB = |p4|/2.2 if the next smallest pole is more than 10GB.
∴ GB = 0.726x109/2.2 = 0.330x109 rads/sec. or 52.5MHz.This value of GB is designed from the relationship that GB = gm1/Cc. Assuming gm1 is
constant, then Cc = gm1/GB = (94.25x10-6)/(0.330x109) = 286fF. It might be useful toincrease gm1 in order to keep Cc above the surrounding parasitic capacitors (Cgd6 =20.7fF). The success of this method assumes that there are no other roots with amagnitude smaller than 10GB.
Chapter 7 – Section 2 (5/2/04) Page 7.2-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.2-2 - Increasing the GB of the Folded Cascode Op Amp of Ex. 6.5-3Use the folded-cascode op amp designed
in Example 6.5-3 and apply the aboveapproach to increase the gainbandwidth asmuch as possible. Assume that thedrain/source areas are equal to 2µm times thewidth of the transistor and that all voltagedependent capacitors are at zero voltage.Solution
The poles of the folded cascode op amp are:
pA ≈ -1
RACA (the pole at the source of M6 )
pB ≈ -1
RBCB (the pole at the source of M7)
p6 ≈ -1
(R2+1/gm10)C6 (the pole at the drain of M6)
p8 ≈ -gm8C8
(the pole at the source of M8 ) p9≈ -gm9C9
(the pole at the source of M9)
and p10 ≈ -gm10C10
(the pole at the gates of M10 and M11)
RB
-
+vin
M1 M2
M4 M5
M6
M11
vout
VDD
VSS
VBias+
-
CLR2
M7
M8 M9
M10M3
Fig. 6.5-7
I3
I4 I5
I6 I7
I1 I2
R1
M13
M14
M12
RA
A B
Chapter 7 – Section 2 (5/2/04) Page 7.2-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.2-2 - ContinuedLet us evaluate each of these poles.1,) For pA, the resistance RA is approximately equal to gm6 and CA is given as
CA = Cgs6 + Cbd1 + Cgd1 + Cbd4 + Cbs6 + Cgd4
From Ex. 6.5-3, gm6 = 744.6µS and capacitors giving CA are found using the parametersof Table 3.2-1 as,
Cgs6 = (220x10-12·80x10-6) + (0.67)(80x10-6·10-6·24.7x10-4) = 149fF
Cbd1 = (770x10-6)(35.9x10-6·2x10-6) + (380x10-12)(2·37.9x10-6) = 84fFCgd1 = (220x10-12·35.9x10-6) = 8fFCbd4 = Cbs6 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fF
andCgd4 = (220x10-12)(80x10-6) = 17.6fF
Therefore,CA = 149fF + 84fF + 8fF + 147fF + 17.6fF + 147fF = 0.553pF
Thus,
pA = -744.6x10-6
0.553x10-12 = -1.346x109 rads/sec.
2.) For the pole, pB, the capacitance connected to this node isCB = Cgd2 + Cbd2 + Cgs7 + Cgd5 + Cbd5 + Cbs7
Chapter 7 – Section 2 (5/2/04) Page 7.2-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.2-2 - ContinuedThe various capacitors above are found as
Cgd2 = (220x10-12·35.9x10-6) = 8fFCbd2 = (770x10-6)(35.9x10-6·2x10-6) + (380x10-12)(2·37.9x10-6) = 84fFCgs7 = (220x10-12·80x10-6) + (0.67)(80x10-6·10-6·24.7x10-4) = 149fFCgd5 = (220x10-12)(80x10-6) = 17.6fF
andCbd5 = Cbs7 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fF
The value of CB is the same as CA and gm6 is assumed to be the same as gm7 giving pB =pA = -1.346x109 rads/sec.3.) For the pole, p6, the capacitance connected to this node is
C6= Cbd6 + Cgd6 + Cgs8 + Cgs9
The various capacitors above are found asCbd6 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fF
Cgs8 = (220x10-12·36.4x10-6) + (0.67)(36.4x10-6·10-6·24.7x10-4) = 67.9fFand
Cgs9 = Cgs8 = 67.9fF Cgd6 = Cgd5 = 17.6fFTherefore,
C6 = 147fF + 17.6fF + 67.9fF + 67.9fF= 0.300pF
Chapter 7 – Section 2 (5/2/04) Page 7.2-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.2-2 - Continued
From Ex. 6.5-3, R2 = 2kΩ and gm6 = 744.6x10-6. Therefore, p6, can be expressed as
-p6 = 1
2x103 + (106/744.6) 0.300x10-12 = 0.966x109 rads/sec.
4.) Next, we consider the pole, p8. The capacitance connected to this node isC8= Cbd10 + Cgd10 + Cgs8 + Cbs8
These capacitors are given as,Cbs8 = Cbd10 = (770x10-6)(36.4x10-6·2x10-6) + (380x10-12)(2·38.4x10-6) = 85.2fFCgs8 = (220x10-12·36.4x10-6) + (0.67)(36.4x10-6·10-6·24.7x10-4) = 67.9fF
andCgd10 = (220x10-12)(36.4x10-6) = 8fF
The capacitance C8 is equal toC8 = 67.9fF + 8fF + 85.2fF + 85.2fF = 0.246pF
Using the gm8 of Ex. 6.5-3 of 774.6µS, the pole p8 is found as, -p8 = 3.149x109 rads/sec.
5.) The capacitance for the pole at p9 is identical with C8. Therefore, since gm9 is also774.6µS, the pole p9 is equal to p8 and found to be -p9 = 3.149x109 rads/sec.
6.) Finally, the capacitance associated with p10 is given as C10 = Cgs10 + Cgs11 + Cbd8
These capacitors are given as
Chapter 7 – Section 2 (5/2/04) Page 7.2-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.2-2 - Continued Cgs10 = Cgs11 = (220x10-12·36.4x10-6) + (0.67)(36.4x10-6·10-6·24.7x10-4) = 67.9fF
and Cbd8 = (770x10-6)(36.4x10-6·2x10-6) + (380x10-12)(2·38.4x10-6) = 85.2fF
Therefore, C10 = 67.9fF + 67.9fF + 85.2fF = 0.221pF
which gives the pole p10 as -744.6x10-6/0.246x10-12 = -3.505x109 rads/sec.The poles are summarized below:
pA = -1.346x109 rads/sec pB = -1.346x109 rads/sec p6 = -0.966x109 rads/sec
p8 = -3.149x109 rads/sec p9 = -3.149x109 rads/sec p10 = -3.505x109 rads/sec
The smallest of these poles is p6. Since pA and pB are not much larger than p6, wewill find the new GB by dividing p6 by 5 (rather than 2.2) to get 200x106 rads/sec. Thusthe new GB will be 200/2π or 32MHz. The magnitude of the dominant pole is given as
pdominant = GB
Avd(0) = 200x106
7,464 = 26,795 rads/sec.
The value of load capacitor that will give this pole is
CL = 1
pdominant·Rout =
126.795x103·19.4MΩ ≈ 1.9pF
Therefore, the new GB = 32MHz compared with the old GB = 10MHz.
Chapter 7 – Section 2 (5/2/04) Page 7.2-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Conclusion for Increasing the GB of Op AmpsMaximum GB depends on the input transconductance and the capacitance that causesthe dominant pole.
Quantity MOSFET OpAmp
BJT Op Amp
gm dependence2K’
W
L IDIC
kT/q = ICVt
Maximum gm ≈ 1 mA/V ≈ 20 mA/V
GB for 10pF 15 MHz 300 MHzGB for 1pF 150 MHz 3 GHz
Note that the power dissipation will be large for large GB because current is needed forlarge gm.
Assumption:All higher-order roots are above GB.The larger GB, the more difficult this becomes.
Conclusion: • The best CMOS op amps have a GB of 10-50MHz • The best BJT op amps have a GB of 100-200MHz
Chapter 7 – Section 2 (5/2/04) Page 7.2-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Switched AmplifiersSwitched amplifiers are time varying circuits that yield circuits with smaller parasiticcapacitors and therefore higher frequency response. Such circuits are called dynamicallybiased.• Switched amplifiers require a nonoverlapping clock• Switched amplifiers only work during a portion of a clock period• Bias conditions are setup on one clock phase and then maintained by capacitance on the
active phase• Switched amplifiers use switches and capacitors resulting in feedthrough problems• Simplified circuits on the active phase minimize the parasiticsTypical clock:
φ1
t
φ2T
tT0 0.5 1 1.5 2
Fig. 7.2-3B
Chapter 7 – Section 2 (5/2/04) Page 7.2-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Dynamically Biased Inverting Amplifier
vinM1
M2
vout
VDD
VSS
CB
COS
φ1 φ1
φ1
φ2
Fig. 7.2-4
ID
During phase 1 the offset and bias of the inverter is sampled and applied to COS and CB.
During phase 2 COS is connected in series with the input and provides offset cancelingplus bias for M1. CB provides the bias for M2.
(This circuit illustrates the concept of switched amplifiers but is too simple to illustratethe reduction of bias parasitics.)
Chapter 7 – Section 2 (5/2/04) Page 7.2-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Dynamically Biased, Push-Pull, Cascode Op Amp
M1
M2
M3
M4
M6
M7
vout
VDD
VSS
C1
M5
M8
C2
vin+IB
φ1
φ1
φ1 φ2
φ2
φ2
vin-
+-VB2
+-VB1
Fig.7.2-5
Push-pull, cascode amplifier: M1-M2 and M3-M4Bias circuitry: M5-M6-C2 and M7-M8-C1Parasitics can be further reduced by using a double-poly process to eliminate bulk-drainand bulk-source capacitances at the drain of M1-source of M2 and drain of M4-source ofM3 (see Fig. 6.5-5).
Chapter 7 – Section 2 (5/2/04) Page 7.2-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Dynamically Biased, Push-Pull, Cascode Op Amp - ContinuedOperation:
M6
M7
VDD
VSS
C1
M5
M8
C2
vin+IB
+-VB2
+-VB1
+
-VDD-VB2-vin+
+
-vin+-VSS-VB1
M1
M2
M3
M4
vout
VDD
VSS
C1
C2
vin-
+
-VDD-VB2-vin+
+
-vin+-VSS-VB1
VDD-VB2-(vin+-vin-)
VSS+VB1-(vin+-vin-)
Equivalent circuit during the φ1 clock period Equivalent circuit during the φ2 clock period.Fig. 7.2-6
Chapter 7 – Section 2 (5/2/04) Page 7.2-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Dynamically Biased, Push-Pull, Cascode Op Amp - ContinuedThis circuit will operate on both clock phases† .
Performance (1.5µm CMOS):• 1.6mW dissipation• GB ≈ 130MHz (CL=2.2pF)
• Settling time of 10ns (CL=10pF)
This amplifier was used with a28.6MHz clock to realize a 5th-order switched capacitor filterhaving a cutoff frequency of3.5MHz.
† S. Masuda, et. al., “CMOS Sampled Differential Push-Pull Cascode Op Amp,” Proc. of 1984 International Symposium on Circuits and Systems,Montreal, Canada, May 1984, pp. 1211-12-14.
M1
M2
M3
M4
M6
M7
vout
VDD
VSS
C1
M5
M8
C2
vin+IB φ2
φ1
φ1
φ1vin-
+
-VB2
+
-VB1
Fig. 7.2-7
C4
C3
φ2
φ2
φ2 φ1
φ1 φ2
φ2 φ1
Chapter 7 – Section 2 (5/2/04) Page 7.2-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Current Feedback Op AmpsWhy current feedback:• Higher GB• Less voltage swing ⇒ more dynamic rangeWhat is a current amplifier?
Ri2
i1
i2io
+
-
CurrentAmplifier
Ri1
Ro
Fig. 7.2-8A
Requirements:io = Ai(i1-i2)Ri1 = Ri2 = 0ΩRo = ∞
Ideal source and load requirements:Rsource = ∞RLoad = 0Ω
Chapter 7 – Section 2 (5/2/04) Page 7.2-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Bandwidth Advantage of a Current Feedback AmplifierConsider the inverting voltage amplifiershown using a current amplifier withnegative current feedback:
The output current, io, of the currentamplifier can be written as
io = Ai(s)(i1-i2) = -Ai(s)(iin + io)The closed-loop current gain, io/iin, can befound as
ioiin
= -Ai(s)
1+Ai(s)
However, vout = ioR2 and vin = iinR1. Solving for the voltage gain, vout/vin gives
voutvin
= ioR2iinR1
=
-R2
R1
Ai(s)
1+Ai(s)
If Ai(s) = Ao
sωA + 1
, then
voutvin
=
-R2
R1
Ao
1+Ao
ωA(1+Ao)
s + ωA(1+Ao) ⇒ Av(0) = -R2Ao
R1(1+Ao) and ω-3dB = ωA(1+Ao)
vinvout
+-
+-
i1
i2 io
io
vout
CurrentAmplifier
R1R2iin
VoltageBufferFig. 7.2-9
Chapter 7 – Section 2 (5/2/04) Page 7.2-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Bandwidth Advantage of a Current Feedback Amplifier - ContinuedThe unity-gainbandwidth is,
GB = |Av(0)| ω-3dB = R2Ao
R1(1+Ao) · ωA(1+Ao) = R2R1 Ao·ωA =
R2R1 GBi
where GBi is the unity-gainbandwidth of the current amplifier.
Note that if GBi is constant, then increasing R2/R1 (the voltage gain) increases GB.
Illustration:
Ao dB
ωA
R2R1
>1
R2R1
GB1 GB2
Current Amplifier
0dB
Voltage Amplifier,
log10(ω)
Magnitude dB
Fig. 7.2-10
(1+Ao)ωA
GBi
= K
R1Voltage Amplifier, > KR2
1+AoAo dB
1+AoAo dBK
Note that GB2 > GB1 > GBiThe above illustration assumes that the GB of the voltage amplifier realizing the voltagebuffer is greater than the GB achieved from the above method.
Chapter 7 – Section 2 (5/2/04) Page 7.2-21
CMOS Analog Circuit Design © P.E. Allen - 2004
A Simple Current Mirror Implementation of a High Frequency AmplifierSince the gain of the current amplifier does not need to be large, consider a unity-gaincurrent mirror implementation:
vin
vout
VSS
VDD
M1 M2
M3
M5 M6M4 M7
M8
R2R1
M9IBias
Fig. 7.2-11
An inverting amplifier with a gain of 10 is achieved if R2 = 20R1 assuming the gain of thecurrent mirror is unity.What is the GB of this amplifier?
GB = |Av(0)|ω-3dB = R2Ao
R1(1+Ao) · 1
R2Co = Ao
(1+Ao)R1Co = 1
2R1Co
where Co is the capacitance seen at the output of the current mirror.
If R1 = 10kΩ and Co = 250fF, then GB = 31.83MHz.
Limitations:
R1>Rin = 1/gm1 and R2 < rds2||rds6 ⇒R2R1 << gm1(rds2||rds6)
Chapter 7 – Section 2 (5/2/04) Page 7.2-22
CMOS Analog Circuit Design © P.E. Allen - 2004
A Wide-Swing, Cascode Current Mirror Implementation of a High FrequencyAmplifierThe current mirror shown below increases the value of R2 by increasing the outputresistance of the current mirror.
vin
M2
M6
M4
M5
vout
VDD
VSS
R2
M13
M14
R1
M3
M1
IBias
M7 M8 M9
M10 M11
M12R4
Fig. 7.2-12
M15
New limitations:
R1 > 1
gm1 and R2 < gm4rds4rds2||gm6rds6rds8 ⇒ R2R1 << gm1(gm4rds4rds2||gm6rds6rds8)
Chapter 7 – Section 2 (5/2/04) Page 7.2-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.2-3 - Design of a High GB Voltage Amplifier using Current FeedbackDesign the wide-swing, cascode voltage amplifier to achieve a gain of -10V/V and a
GB of 500MHz which corresponds to a -3dB frequency of 50MHz.Solution
Since we know what the gain is to be, let us begin by assuming that Co will be100fF. Thus to get a GB of 500MHz, R1 must be 3.2kΩ and R2 = 32kΩ. Therefore,1/gm1 must be less than 3200Ω (say 300Ω). Therefore we can write
gm1 = 2KI’(W/L) = 1
300Ω → 5.56x10-6 = K’·I ·WL → 0.0505 = I·
WL
At this point we have a problem because if W/L is small to minimize Co, the current willbe too high. If we select W/L = 200µm/1µm we will get a current of 0.25mA. However,using this W/L for M4 and M6 will give a value of Co that is greater than 100fF.Therefore, select W/L = 200 for M1, M3, M5 and M7 and W/L = 20µm/1µm for M2, M4,M6, and M8 which gives a current in these transistors of 25µA.Since R2/R1 is multiplied by 1/11 let R2 be 110 times R1 or 352kΩ.
Now select a W/L for M12 of 20µm/1µm which will now permit us to calculate Co.We will assume zero-bias on all voltage dependent capacitors. Furthermore, we willassume the diffusion area as 2µm times the W. Co can be written as
Co = Cgd4 + Cbd4 + Cgd6 + Cbd6 + Cgs12
Chapter 7 – Section 2 (5/2/04) Page 7.2-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.2-3 - Design of a High GB Voltage Amplifier using Current Feedback -Cont’d
The information required to calculate these capacitors is found from Table 3.2-1. Thevarious capacitors are,
Cgd4 = Cgd6 = CGDOx10µm = (220x10-12)(20x10-6) = 4.4fFCbd4 = CJxAD4+CJSWxPD4 = (770x10-6)(20x10-12)+(380x10-12)(44x10-6)
= 15.4fF+16.7fF = 32.1fFCbd6 = (560x10-6)(20x10-12)+(350x10-12)(44x10-6) = 26.6fFCgs12 = (220x10-12)(20x10-6) + (0.67)(20x10-6·10-6·24.7x10-4) = 37.3fF
Therefore,Co = 4.4fF+32.1fF+4.4fF+26.6fF+37.3fF = 105fFNote that if we had not reduced the W/L of M2, M4, M6, and M8 that Co would have
easily exceeded 100fF. Since 105fF is close to our original guess of 100fF, let us keep thevalues of R1 and R2. If this value was significantly different, then we would adjust thevalues of R1 and R2 so that the GB is 500MHz. One must also check to make sure thatthe input pole is greater than 500MHz.
The design is completed by assuming that IBias = 100µA and that the current in M9through M12 be 100µA. Thus W13/L13 = W14/L14 = 20µm,/1µm and W9/L9 throughW12/L12 are 20µm/1µm.
Chapter 7 – Section 2 (5/2/04) Page 7.2-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.2-3 - Continued
Frequency (Hz)
|vou
t/vin
| dB
Fig. 7.2-13
-30
-20
-10
0
10
20
30
105 106 107 108 109 1010
f-3dB GB
-20dB/dec
-40dB/dec
R1 = 3.2kΩ
R1 = 1kΩ
Simulation Results:f-3dB ≈ 38MHz GB ≈ 300MHz Closed-loop gain = 18dB
(Loss of -2dB is attributed to source follower and R1)
Note second pole at about 1GHz. To get these results, it was necessary to bias the inputat -1.7VDC using ±3V power supplies.If R1 is decreased to 1kΩ results in:
Gain of 26.4dB, f-3dB = 32MHz, and GB = 630MHz
Chapter 7 – Section 2 (5/2/04) Page 7.2-26
CMOS Analog Circuit Design © P.E. Allen - 2004
A 71 MHz Programmable Gain Amplifier using a Current AmplifierThe following circuit has been submitted for fabrication in 0.25µm CMOS:
M1
VDD
VSS
R1
+1 +1
VBias
+ -vout
vin+ vin-
M2
x2= 1/4
x4=1/8
x2= 1/4
x4=1/8
x1=1/2
x1=1/2
R2 R2
Fig. 7.2-135A
R1 and the current mirrors are used for gain variation. R2 is fixed.
Can cascade this amplifier for higher gains
BW = BWi 21/n-1 for n = 2, BW = 0.64 BWi
Chapter 7 – Section 2 (5/2/04) Page 7.2-27
CMOS Analog Circuit Design © P.E. Allen - 2004
Implementation of a 60dB Gain, 500MHz –3dB Frequency PGA
Chapter 7 – Section 2 (5/2/04) Page 7.2-28
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation ResultsOutput voltage swing is 1.26V for a 2.5V power supply.Voltage gain is 0 to 60dB in 2dB steps (gain error = ±0.17dB)Maximum GB is 1.5GHzTotal current: 3.6mA
Chapter 7 – Section 2 (5/2/04) Page 7.2-29
CMOS Analog Circuit Design © P.E. Allen - 2004
A 71 MHz CMOS Programmable Gain Amplifier†
Uses 3 ac-coupled stages.First stage (0-20dB, common gate for matching and NF):
vout
VDD
vout
CMFB
VBP
VBN
0dB2dB
VB1
vin
VB1
vin
0dB 2dB
M2dB M0dB M2dBM0dB
M2 M2
M3
Fig. 7.2-137A
Rin = 330Ω to match source driving requirementAll current sinks are identical for the differential switches.Dominant pole at 150MHz.
† P. Orsatti, F. Piazza, and Q. Huang, “A 71 MHz CMOS IF-Basdband Strip for GSM, IEEE JSSC, vol. 35, No. 1, Jan. 2000, pp. 104-108.
Chapter 7 – Section 2 (5/2/04) Page 7.2-30
CMOS Analog Circuit Design © P.E. Allen - 2004
A 71 MHz PGA – ContinuedSecond stage (-10dB to 20dB):
M2 M2
M3
M2 M2
M3
CMFB
-10dB
-10dB
vout vout
VBP
VBN
vin vin
Fig. 7.2-137A
M5
M4
M6
M2dB M0dB
0dBLoad -10dB
Load
M5
M4
M6
M2dBM0dB
0dB 2dB0dB2dB
VDD
Dominant pole is also at 150MHzFor VDD = 2.5V, at 60dB gain, the total current is 2.6mA
IIP3 ≈ +1dBm
Chapter 7 – Section 2 (5/2/04) Page 7.2-31
CMOS Analog Circuit Design © P.E. Allen - 2004
Parallel Path Op AmpsThis type of op amp combines a high-gain, low-frequency path with a low-gain, high-frequency path.
+-
+-
+
-+
+
vout
vo1
vo2
vin
A1
A2
|p1| |p2|
|p3|
GBlog10(f)
dB
|Avd1(0|) dB
|Avd2(0|) dB
0 dB
|Avd1(s)|
|Avd2(s)|
Fig. 7.2-14
Comments:• Op amp will be conditionally stable• Compensation will be challenging
Chapter 7 – Section 2 (5/2/04) Page 7.2-32
CMOS Analog Circuit Design © P.E. Allen - 2004
Multipath Nested Miller Compensation†
vinvout
gm3 gm2 -gm1
gm4
Cm2
Cm1
Fig. 7.2-15
Comments:• All Miller capacitances must be around inverting stages• Ensure that the RHP zeros generated by the Miller compensation are canceled• Avoid pole-zero doublets which can introduce a slow time constant
† R.G.H. Eschauzier and J.H.Huijsing, Frequency Compensation Techniques for Low-Power Operational Amplifiers, Kluwer Academic publishers,1995, Chapter 6.
Chapter 7 – Section 2 (5/2/04) Page 7.2-33
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of Hybrid Nested Miller Compensation†
(Note that this example is notmultipath.)Compensating Results:1) Cm1 pushes p4 to higherfrequencies and p3 down to lowerfrequencies2) Cm2 pushes p2 to higherfrequencies and p1 down to lowerfrequencies3) Cm3 pushes p3 to higher frequencies (feedback path) & pulls p1 further to lowerfrequenciesEquations:
GB ≈ gm1/C m3 p2 ≈ gm2/Cm3 p3 ≈ gm3Cm3 / (Cm1Cm2) p4 ≈ gm4/CL
Design:GB < p2, p3, p4
† R.G. H. Eschauzier et. al., “A Programmable 1.5V CMOS Class-AB Operational Amplifier with Hybrid Nested Miller Compensation for 120dB Gain and 6MHz UGT,” IEEE J.of Solid State Circuits, vol. 29, No. 12, pp. 1497-1504, Dec. 1994.
vinvout-gm3-gm2-gm1 -gm4
Cm3
Cm1
Fig. 7.2-16
Cm2
p1 p2 p3 p4
R2R1 R3 RL CL
Chapter 7 – Section 2 (5/2/04) Page 7.2-34
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of the Hybrid Nested Miller Compensation Technique
jω
σp4 p3 p2 p1
jω
σp4 p3 p2 p1
jω
σp4 p3p2 p1
jω
σp4 p3 p2 p1
Cm1
Cm2
Cm3
Fig. 7.2-17
Chapter 7 – Section 2 (5/2/04) Page 7.2-35
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• Normal op amps limited by gm/C
• Typical limit for CMOS op amp is GB ≈ 50MHz • Other approaches to high frequency CMOS op amps:
Current amplifiers (Transimpedance amplifiers)Switched amplifier (simplifies the circuit ⇒ reduce capacitances)Parallel path op amps (compensation becomes more complex)
• What does the future hold?Reduction of channel lengths mean:* Reduced capacitances ⇒ Higher GB’s* Higher transconductances (larger values of K’) ⇒ Higher GB’s* Increased channel conductance ⇒ Lower gains (more stages required)* Reduction of power supply ⇒ Increased capacitances
In otherwords, there should be some improvement in op amp GB’s but it won’t beinversely proportional to the decrease in channel length. I.e. maybe GB’s ≈ 100MHzfor 0.2µm CMOS.
Chapter 7 – Section 3 (5/2/04) Page 7.3-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 7.3 – DIFFERENTIAL OUTPUT OP AMPSObjectiveThe objective of this presentation is:1.) Design and analysis of differential output op amps2.) Examine the problem of common mode stabilizationOutline• Advantages and disadvantages of fully differential operation• Six different differential output op amps• Techniques of stabilizing the common mode output voltage• Summary
Chapter 7 – Section 3 (5/2/04) Page 7.3-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Why Differential Output Op Amps?
• Cancellation of common mode signals including clock feedthrough
• Increased signal swing
v1
v2
v1-v2t
t
t
A
-AA
-A
2A
-2A Fig. 7.3-1
• Cancellation of even-order harmonics
Symbol:
-
+vin vout+
-
-
+
-
+
Fig. 7.3-1A
Chapter 7 – Section 3 (5/2/04) Page 7.3-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Common Mode Output Voltage StabilizationIf the common mode gain not small, it may cause the common mode output voltage to
be poorly defined.Illustration:
VDD
vod
t
Fig. 7.3-2
VSS
0
VDD
vod
t
VSS
0
VDD
vod
t
VSS
0
CM output voltage = 0
CM output voltage =0.5VDD
CM output voltage =0.5VSS
Chapter 7 – Section 3 (5/2/04) Page 7.3-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage, Miller, Differential-In, Differential-Out Op Amp
Note that theupper ICMR isVDD - VSGP + VTN
Output common mode range (OCMR) = VDD+ |VSS| - VSDP(sat) - VDSN(sat)
The maximum peak-to-peak output voltage ≤ 2·OCMRConversion between differential outputs and single-ended outputs:
vod CL
+
-+-+
-vid
+
-vo1 2CL
+
-+-+
-vid
+
-
vo2+
-2CL
Fig. 7.3-4
vi1 M1 M2
M3 M4
M5
M6M8
VDD
VSS
VBN+-
Cc
M9
Cc
VBP+-
vi2
vo1vo2RzRz
M7
Fig. 7.3-3
Chapter 7 – Section 3 (5/2/04) Page 7.3-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Differential-Output, Folded-Cascode, Class-A Op Amp
VDD
VSS
R1
M14
R2
M8
M10VBias
vi1 vi2 vo1vo2M1 M2
M3
M4 M5
M7M6
M9
M11
M12
M13
M15
M16
M17Fig. 7.3-5
OCMR = VDD + |VSS| - 2VSDP(sat) -2VDSN(sat)
Chapter 7 – Section 3 (5/2/04) Page 7.3-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Push-Pull Output
vi1M1 M2
M3 M4
M5
M6
M7
VDD
VSS
VBN+
-
Cc
M9
Cc
VBP+-
vi2
vo1 vo2RzRz
M8
Fig. 7.3-6
M10 M12
M13
M14
Comments:• Able to actively source and sink output current• Output quiescent current poorly defined
Chapter 7 – Section 3 (5/2/04) Page 7.3-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage, Differential Output, Folded-Cascode Op Amp
VDD
VSS
R1
M16 M8
M10
VBias
vi1 vi2vo1vo2 M1 M2
M3
M4 M5
M7M6
M9
M11
M14 M15
M12 M13
CcRz CcRz
M17
M18
M19
M20
Fig. 7.3-7A
Note that the followers M11-M13 and M10-M12 are necessary for level translation to theoutput stage.
Chapter 7 – Section 3 (5/2/04) Page 7.3-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Unfolded Cascode Op Amp with Differential-Outputs
VDD
VSS
VBias
R2 M22
M23
R1
M19
M20
M1 M2
M3 M4M5 M6M7 M8
M9 M10
M11
M12M13
M14
M15 M16M17
M18
M21
vo1vi1 vi2
vo2
Fig. 7.3-8
Chapter 7 – Section 3 (5/2/04) Page 7.3-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Cross-Coupled Differential Amplifier StageOne of the problems with some of the previous stages, is that the quiescent output currentwas not well defined.The following input stage solves this problem.
M1 M2
M3 M4
VGS2
VSG4
VGS1
VSG3
i1
i1i2
i2
vi1 vi2
Fig. 7.3-9
vGS1+
-
vSG4+
-vSG3
+
-
vGS2+
-
Operation:Voltage loop vi1 - vi2 = -VGS1+ vGS1 + vSG4 - VSG4 = VSG3 - vSG3 - vGS2 + VGS2
Using the notation for ac, dc, and total variables gives,vi2 - vi1 = vid = (vsg1 + vgs4) = -(vsg3 + vgs2)
If M1 = M2 = M3 = M4, then half of the differential input is applied across each transistorwith the correct polarity.
∴ i1 = gm1vid
2 = gm4vid
2 and i2 = -gm2vid
2 = -gm3vid
2
Chapter 7 – Section 3 (5/2/04) Page 7.3-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Class AB, Differential Output Op Amp using a Cross-Coupled Differential InputStage
M1 M2
M3 M4
M5 M6
M7
VDD
VSS
VBias+
-
R1
M24
M25
R2
M27
M28
M8M9 M10
M11 M12
M13
M14
M15
M16
M17 M18
M19 M20
M21 M22
M26
M23
vo2
vi2vi1
vo1
Fig. 7.3-10
Quiescent output currents are defined by the current in the input cross-coupleddifferential amplifier.
Chapter 7 – Section 3 (5/2/04) Page 7.3-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Common-Mode Output Voltage Stabilization
VDD
VSS
io2(source)
io2(sink)
io1(source)
io1(sink)
Ro1
Ro3
Ro2
Ro4
M1 M2Common-modefeedback circuit
vo1 vo2
Fig. 7.3-11
Model of output of differentialoutput op amp
Operation:M1 and M2 sense the common-mode output voltage.If this voltage rises, the currents in M1 and M2 decrease.This decreased current flowing through Ro3 and Ro4 cause the common-mode outputvoltage to decrease with respect to VSS.
Chapter 7 – Section 3 (5/2/04) Page 7.3-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Common-ModeStabilization
vi1 M1 M2
M3 M4
M5
M6M7
VDD
VSS
VBN+-
Cc
M9
Cc
VBP
+
-
vi2
vo1vo2RzRz
M8
Fig. 7.3-12
M10 M11
Comments:• Simple• Unreferenced
Chapter 7 – Section 3 (5/2/04) Page 7.3-13
CMOS Analog Circuit Design © P.E. Allen - 2004
A Referenced Common-Mode Output Voltage Stabilization Scheme
VDD
VSS
M1 M2M3 M4
M5 M6
Vocm To correctioncircuitry
vo1 vo2
I5I6
Iocm
Fig. 7.3-13
Operation:1.) The desired common-mode output voltage, Vocm, creates Iocm.
2.) The actual common-mode output voltage creates current I5 which is mirrored to I6 .
3.) If M1 through M4 are matched and the current mirror is ideal, then when Iocm = I6the actual common-mode output voltage should be equal to the desired common-mode output voltage.
4.) The above steps assume that a correction circuitry exists that changes the common-mode output voltage in the correct manner.
Chapter 7 – Section 3 (5/2/04) Page 7.3-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Common Mode Feedback CircuitsImplementation of common mode feedback circuit:
v1M1 M2
M3 M4
M5
VDD
VSS
IBias
VCM
v4v3
v2
MC2A
MC2B
MC1
MC3
MC4
MC5MB
I3 I4
IC4IC3
Fig. 7.3-13A
Common-mode feed-back circuit
Self-resistancesof M1-M4
This scheme can be applied to any differential output amplifier.Caution:
Be sure to check the stability of common-mode feedback loops, particularly those thatare connected to op amps that have a cascode output. The gain of the common-modefeedback loop can easily reach that of a two-stage amplifier.
Chapter 7 – Section 3 (5/2/04) Page 7.3-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Common Mode Feedback Circuits – ContinuedThe previous circuit suffers when the input common mode voltage is low because thetransistors MC2A and MC2B have a poor negative input common mode voltage.The following circuit alleviates this disadvantage:
v1M1 M2
M3 M4
M5
VDD
VSS
IBias
VCM
v4v3
v2MC2MC1
MC3
MC4
MC5MB
I3 I4
IC4IC3Common-mode feed-back circuit
RCM1 RCM2
Fig. 7.3-15New
Chapter 7 – Section 3 (5/2/04) Page 7.3-16
CMOS Analog Circuit Design © P.E. Allen - 2004
External Common-Mode Output Voltage Stabilization Scheme for Discrete-TimeApplications
Ccm+
-+-+
-vid
vo1
vo2CMbias
φ1 φ2
Ccm Vocm
φ1 φ2
φ1
φ1
φ1 Fig. 7.3-14
Operation:1.) During the φ1 phase, both Ccm are charged to the desired value of Vocm and CMbias
= Vocm.
2.) During the φ2 phase, the Ccm capacitors are connected between the differentialoutputs and the CMbias node. The average value applied to the CMbias node will beVocm.
Chapter 7 – Section 3 (5/2/04) Page 7.3-17
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• Advantages of differential output op amps:
- 6 dB increase in signal amplitude
- Cancellation of even harmonics
- Cancellation of common mode signals including clock feedthrough• Disadvantages of differential output op amps:
- Need for common mode output voltage stabilization
- Compensation of common mode feedback loop
- Difficult to interface with single-ended circuits• Most differential output op amps are truly balanced• For push-pull outputs, the quiescent current should be well defined• Common mode feedback schemes include,
- Unreferenced
- Referenced
Chapter 7 – Section 4 (5/2/04) Page 7.4-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 7.4 – LOW POWER OP AMPSObjectiveThe objective of this presentation is:1.) Examine op amps that have minimum static power
- Minimize power dissipation- Work at low values of power supply- Tradeoff speed for less power
Outline• Weak inversion• Methods of creating an overdrive• Examples• Summary
Chapter 7 – Section 4 (5/2/04) Page 7.4-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Subthreshold OperationMost micropower op amps use transistors in the subthreshold region.Subthreshold characteristics:
100nA
1µA
Weak Inversion
Transition
Strong InversionSquare Law
Exponential
iD
vGS
iD
vDSVT
100nAvGS =VT
vGS ≤VT
Fig. 7.4-0A1V 2V000
0
iD = WL IDO exp
qvGS
nkT (1+λvDS) ⇒ gm = qIDnkT and gds ≈ λID
Operation with channel length = Lmin also will normally be in weak inversion.
Chapter 7 – Section 4 (5/2/04) Page 7.4-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage, Miller Op Amp Operating in Weak Inversion
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
Cc
CL
Fig.7.4-1
Low frequency response:
Avo = gm2gm6
ro2ro4
ro2 + ro4
ro6ro7
ro6 + ro7 =
1n2n6(kT/q)2(λ2 + λ4)(λ6 + λ7) (No longer ∝
1ID
)
GB and SR:
GB = ID1
(n1kT/q)C and SR = ID5C = 2
ID1C = 2GB
n1 kTq = 2GBn1Vt
Chapter 7 – Section 4 (5/2/04) Page 7.4-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.4-1 Gain and GB Calculations for Subthreshold Op Amp.Calculate the gain, GB, and SR of the op amp shown above. The currents are ID5 =
200 nA and ID7 = 500 nA. The device lengths are 1 µm. Values for n are 1.5 and 2.5 forp-channel and n-channel transistors respectively. The compensation capacitor is 5 pF.Use Table 3.1-2 as required. Assume that the temperature is 27 °C. If VDD = 1.5V andVSS = -1.5V, what is the power dissipation of this op amp?
SolutionThe low-frequency small-signal gain is,
Av = 1
(1.5)(2.5)(0.026)2(0.04 + 0.05)(0.04 + 0.05) = 43,701 V/V
The gain bandwidth is
GB = 100 × 10-9
2.5(0.026)(5 × 10-12) = 307,690 rps ≅ 49.0 kHz
The slew rate isSR = (2)(307690)(2.5)(0.026) = 0.04 V/µs
The power dissipation is,Pdiss = 3(0.7µA) =2.1µW
Chapter 7 – Section 4 (5/2/04) Page 7.4-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Push-Pull Output Op Amp in Weak Inversion
First stage gain is,
Avo = gm2gm4
= ID2n4VtID4n2Vt
= ID2n4ID4n2
≅ 1
Total gain is,
Avo = gm1(S6/S4)
(gds6 + gds7) = (S6/S4)
(λ6 + λ7)n1Vt
At room temperature (Vt = 0.0259V) andfor typical device lengths, gains of 60dBcan be obtained.The GB is,
GB = gm1C
S6
S4 =
gm1bC
vout
VDD
VSS
VBias+
-
Cc
M1 M2
M3 M4
M5
M6
M7
M8
M9
vi2
Fig. 7.4-2
Chapter 7 – Section 4 (5/2/04) Page 7.4-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Increasing the Gain of the Previous Op Amp1.) Can reduce the currents in M3and M4 and introduce gain in thecurrent mirrors.2.) Use a cascode output stage(can’t use self-biased cascode,currents are too low).
Av =
gm1+gm2
2 Rout
= gm1
gds6gds10gm10 +
gds7gds11gm11
=
I52nnVt
I72λn2
I7nnVt
+ I72λp2
I7npVt
=
I5
2I7
1
nnVt2(nnλn2+npλp2)
Can easily achieve gains greater than 80dB with power dissipation of less than 1µW.
M6
M7
vout
VDD
VSS
VBias
+
-
Cc
M1 M2
M3 M4
M5
M8
M9
vi2
M10
M11M12
M13M14
M15
vi1
I5
+
-
VT+2VON
+
-
VT+2VON
Fig. 7.4-3A
Chapter 7 – Section 4 (5/2/04) Page 7.4-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Increasing the Output Current for Weak Inversion OperationA significant disadvantage of the weak inversion is that very small currents are availableto drive output capacitance so the slew rate becomes very small.Dynamically biased differential amplifier input stage:
VDD
VSS
VBias+
-
vi2 vi1M2M1
M3 M4
M5
I5
M18 M19M20 M21
M22 M23M24 M25M26 M27
M28 M29
i1 i2 i2 i2i1i1
A(i2-i1) A(i1-i2)
Fig. 7.4-4
Note that the sinking current for M1 and M2 isIsink = I5 + A(i2-i1) + A(i1-i2) where (i2-i1) and (i1-i2) are only positive or zero.
If vi1>vi2, then i2>i1 and the sinking current is increased by A(i2-i1).
If vi2>vi1, then i1>i2 and the sinking current is increased by A(i1-i2).
Chapter 7 – Section 4 (5/2/04) Page 7.4-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Dynamically Biased Differential Amplifier - ContinuedHow much output current is available from this circuit if there is no current gain from theinput to output stage?Assume transistors M18 through M21 are equal to M3 and M4 and that transistors M22through M27 are all equal.
LetW28L28 = A
W26
L26 and W29L29 = A
W27
L27
The output current available can be found by assuming that vin = vi1-vi2 > 0.∴ i1 + i2 = I5 + A(i2-i1)
The ratio of i2 to i1 can be expressed asi2i1 = exp
vin
nVt
Defining the output current as iOUT = b(i2-i1) and combining the above two equationsgives,
iOUT = bI5
exp
vin
nVt - 1
(1+A) - (A-1)exp
vin
nVt
⇒ iOUT = ∞ when A = 2.16 and vinnVt = 1
where b corresponds to any current gain through current mirrors (M6-M4 and M8-M3).
Chapter 7 – Section 4 (5/2/04) Page 7.4-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Overdrive of the Dynamically Biased Differential Amplifier
The enhanced output current isaccomplished by the use of positivefeedback (M28-M2-M19-M28).The loop gain is,
LG =
gm28
gm4
gm19
gm26 = A gm19gm4 = A
Note that as the output currentincreases, the transistors leave the weakinversion region and the above analysisis no longer valid.
A = 0
A = 0.3A = 1
A = 1.5
A = 2
IOUT
I5
2
1
00 1 2
vIN nVt Fig. 7.4-5
Chapter 7 – Section 4 (5/2/04) Page 7.4-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Increasing the Output Current for Strong Inversion OperationAn interesting technique is to bias the output transistor of a current mirror in the activeregion and then during large overdrive cause the output transistor to become saturatedcausing a significant current gain.Illustration:
+Vds2
-
i1 i2
M1 M2
Fig. 7.4-6 Vds1(sat)0.1Vds1(sat)
100µA
531µA
i2 for W2/L2 = 5.31(W1/L1)
VoltsC
urre
nt
i1
Chapter 7 – Section 4 (5/2/04) Page 7.4-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.4-2 Current Mirror with M2 operating in the Active RegionAssume that M2 has a voltage across the drain-source of 0.1Vds(sat). Design the
W2/L2 ratio so that I1 = I2 = 100µA if W1/L1 = 10. Find the value of I2 if M2 is saturated.Solution
Using the parameters of Table 3.1-2, we find that the saturation voltage of M2 is
Vds1(sat) = 2I1
KN’ (W2/L2) = 200
110·10 = 0.4264V
Now using the active equation of M2, we set I2 = 100µA and solve for W2/L2.100µA = KN’(W2/L2)[Vds1(sat)·Vds2 - 0.5Vds22] = 110µA/V2(W2/L2)[0.426·0.0426 - 0.5·0.04262]V2 = 1.883x106(W2/L2)
Thus,
100 =1.883(W2/L2) →W2L2
= 53.12
Now if M2 should become saturated, the value of the output current of the mirror with100µA input would be 531µA or a boosting of 5.31 times I1.
Chapter 7 – Section 4 (5/2/04) Page 7.4-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Implementation of the Current Mirror Boosting Concept
VDD
VSS
i1
i1
i2
i2
i2 i2i1 i1
ki2 ki1
ki1
M8
M7
M5
M6
M10
M14
M16
M12
M11
M15
M13
M9
M17
M18
M19
M20
M21 M22
M23 M24
vo2vo1
Fig.7.4-7
M1 M2
M3 M4
VBias
+
-
M25 M26
M27 M28
M29 M30
vi2vi1
ki2
k = overdrive factor of the current mirror
Chapter 7 – Section 4 (5/2/04) Page 7.4-13
CMOS Analog Circuit Design © P.E. Allen - 2004
A Better Way to Achieve the Current Mirror BoostingIt was found that when the current mirror boosting idea illustrated on the previous slidewas used that when the current increased through the cascode device (M16) that VGS16increased limiting the increase of VDS12. This can be overcome by the following circuit.
M1 M2
M3
M4M5
VDD
iin+IB iin
kiin
IB
1/1
1/1 1/1
50/1
210/1
Fig. 7.4-7A
Chapter 7 – Section 4 (5/2/04) Page 7.4-14
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• Operation of transistors is generally in weak inversion• Boosting techniques are needed to get output sourcing and sinking currents that are
larger than that available during quiescent operation• Be careful about using circuits at weak inversion, i.e. the self-biased cascode will cause
the resistor to be too large
Chapter 7 – Section 5 (5/2/04) Page 7.5-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 7.5 – LOW NOISE OP AMPSObjectiveThe objective of this presentation is:1.) Review the principles of low noise design2.) Show how to reduce the noise of op ampsOutline• Review of noise analysis• Low noise op amps• Low noise op amps using lateral BJTs• Low noise op amps using doubly correlated sampling• Summary
Chapter 7 – Section 5 (5/2/04) Page 7.5-2
CMOS Analog Circuit Design © P.E. Allen - 2004
IntroductionWhy do we need low noise op amps?Dynamic range:
Signal-to-noise ratio (SNR)
= Maximum RMS Signal
Noise
(SNDR includes both noise and distortion)Consider a 14 bit digital-to-analog converter with a 1V reference with a bandwidth of1MHz.
Maximum RMS signal is 0.5V
2 = 0.3535 Vrms
A 14 bit D/A converter requires 14x6dB dynamic range or 84 dB or 16,400.
∴ The value of the least significant bit (LSB) = 0.353516,400 = 21.6µVrms
If the equivalent input noise of the op amp is not less than this value, then the LSBcannot be resolved and the D/A converter will be in error. An op amp with an equivalentinput-noise spectral density of 10nV/ Hz will have an rms noise voltage of approximately(10nV/ Hz)(1000 Hz) = 10µVrms in a 1MHz bandwidth.
VDD
Noise + Distortion
Dynamic Range = 6dBx(Number. of bits)
Fig. 7.5-0B
Chapter 7 – Section 5 (5/2/04) Page 7.5-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Transistor Noise Sources (Low-Frequency)Drain current model:
i 2n1
D
G
S
D
G
S
M1 M1
M1 isnoiseless
M1 isnoisy
Fig. 7.5-0A
i2n =
8kTgm
3 + (KF)IDfCoxL2 or i
2n =
8kTgm(1+η)
3 + (KF)IDfCoxL2 if vBS ≠ 0
Recall that η = gmbsgm
Gate voltage model assuming common source operation:D
G
S
D
G
S
M1 M1
M1 isnoiseless
M1 isnoisy
Fig. 7.5-0C
e2n1
*
e2n =
i2N
gm2 =
8kT
3gm + KF
2fCoxWLK’ or e2n =
8kT(1+η)
3gm + KF
2fCoxWLK’ if vBS ≠ 0
Chapter 7 – Section 5 (5/2/04) Page 7.5-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Minimization of Noise in Op Amps1.) Maximize the signal gain as close to the input as possible. (As a consequence, only
the input stage will contribute to the noise of the op amp.)2.) To minimize the 1/f noise:
a.) Use PMOS input transistors with appropriately selected dc currents and W and Lvalues.
b.) Use lateral BJTs to eliminate the 1/f noise.c.) Use chopper stabilization to reduce the low-frequency noise.
Noise Analysis1.) Insert a noise generator for each transistor that contributes to the noise. (Generally
ignore the current source transistor of source-coupled pairs.)2.) Find the output noise voltage across an open-circuit or output noise current into a
short circuit.3.) Reflect the total output noise back to the input resulting in the equivalent input noise
voltage.
Chapter 7 – Section 5 (5/2/04) Page 7.5-5
CMOS Analog Circuit Design © P.E. Allen - 2004
A Low-Noise, Two-Stage, Miller Op Amp
M3 M4
M6
vout
VDD
VSS
VBias
Cc
+
-
vin+
-M1 M2
M8 M9
M7M5
M10
M11
Fig. 7.5-1
VDD
VSS
e2n3 e2
n4
VBias VBias
M1 M2
M3 M4
M8 M9
e2n2
e2n1
e2n6
e2n7
I5M7
M6
e2to
VSG7
*
*
*
*
* *
e2n8
*
e2n9
*
The total output-noise voltage spectral density, e2to, is as follows where gm8(eff) ≈ 1/rds1,
e2to = gm6
2RII2
e2n6+e
2n7 +RI2
gm12e2n1+gm22e
2n2+gm32e
2n3+gm42e
2n4 + (e
2n8/rds12) + (e
2n9/rds22)
Divide by (gm1RIgm6RII)2 to get the eq. input-noise voltage spectral density, e2eq, as
e2eq =
e2to
(gm1gm6RIRII)2 = 2e
2n6
gm12RI2 + 2e
2n1
1+
gm3
gm12
e2
n3
e2
n1 +
e2
n8
gm12rds12e2
n1 ≈ 2e
2n1
1+
gm3
gm1
2
e
2n3
e2n1
where e2n6 = e
2n7, e
2n3 = e
2n4, e
2n1 = e
2n2 and e
2n8 = e
2n9 and gm1RI is large.
Chapter 7 – Section 5 (5/2/04) Page 7.5-6
CMOS Analog Circuit Design © P.E. Allen - 2004
1/f Noise of a Two-Stage, Miller Op AmpConsider the 1/f noise:Therefore the noise generators are replaced by,
e2ni =
BfWiLi
(V2/Hz) and i2ni =
2BK’IifLi2
(A2/Hz)
Therefore, the approximate equivalent input-noise voltage spectral density is,
e2eq = 2e
2n1
1 +
KN’BN
KP’BP
L1
L32 (V2/Hz)
Comments;
• Because we have selected PMOS input transistors, e2
n1 has been minimized if wechoose W1L1 (W2L2) large.
• Make L1<<L3 to remove the influence of the second term in the brackets.
Chapter 7 – Section 5 (5/2/04) Page 7.5-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Thermal Noise of a Two-Stage, Miller Op AmpLet us focus next on the thermal noise:The noise generators are replaced by,
e2ni ≈
8kT3gm
(V2/Hz) and i2ni ≈
8kTgm3 (A2/Hz)
where the influence of the bulk has been ignored.The approximate equivalent input-noise voltage spectral density is,
e2eq = 2e
2n1
1+
gm3
gm12
e2n3
e2n1
= 2e2n1
1 + KNW3L1KPW1L3
(V2/Hz)
Comments:• The choices that reduce the 1/f noise also reduce the thermal noise.
Noise Corner:Equating the equivalent input-noise voltage spectral density for the 1/f noise and thethermal noise gives the noise corner, fc, as
fc = 3gmB
8kTWL
Chapter 7 – Section 5 (5/2/04) Page 7.5-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.5-1 Design of A Two-Stage, Miller Op Amp for Low 1/f NoiseUse the parameters of Table 3.1-2 along with the value of KF = 4x10-28 F·A for
NMOS and 0.5x10-28 F·A for PMOS and design the previous op amp to minimize the 1/fnoise. Calculate the corresponding thermal noise and solve for the noise cornerfrequency. From this information, estimate the rms noise in a frequency range of 1Hz to100kHz. What is the dynamic range of this op amp if the maximum signal is a 1V peak-to-peak sinusoid?Solution1.) The 1/f noise constants, BN and BP are calculated as follows.
BN = KF
2CoxKN’ = 4x10-28F·A
2·24.7x10-4F/m2·110x10-6A2/V = 7.36x10-22 (V·m)2
and
BP = KF
2CoxKP’ = 0.5x10-28F·A
2·24.7x10-4F/m2·50x10-6A2/V = 2.02x10-22 (V·m)2
2.) Now select the geometry of the various transistors that influence the noiseperformance.
To keep e2n1 small, let W1 = 100µm and L1 = 1µm. Select W3 = 100µm and L3 =
20µm and letW8 and L8 be the same as W1 and L1 since they little influence on the noise.
Chapter 7 – Section 5 (5/2/04) Page 7.5-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.5-1 - ContinuedOf course, M1 is matched with M2, M3 with M4, and M8 with M9.
∴ e2n1 =
BPfW1L1
= 2.02x10-22
f·100µm·1µm = 2.02x10-12
f (V2/Hz)
e2eq = 2x
2.02x10-12
f
1 +
110·7.36
50·2.022
1
202 =
4.04x10-12
f 1.1606 = 4.689x10-12
f (V2/Hz)
Note at 100Hz, the voltage noise in a 1Hz band is ≈ 4.7x10-14V2(rms) or 0.216µV(rms).3.) The thermal noise at room temperature is
e2n1 =
8kT3gm
= 8·1.38x10-23·300
3·707x10-6 = 1.562x10-17 (V2/Hz)
which gives
e2eq = 2·1.562x10-17
1 + 110·100·150·100·20 = 3.124x10-17·1.33= 4.164x10-17 (V2/Hz)
4.) The noise corner frequency is found by equating the two expressions for e2eq to get
fc = 4.689x10-12
4.164x10-17 = 112.6kHz
This noise corner is indicative of the fact that the thermal noise is much less than the 1/fnoise.
Chapter 7 – Section 5 (5/2/04) Page 7.5-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.5-1 - Continued5.) To estimate the rms noise in the bandwidth from 1Hz to 100,000Hz, we will ignorethe thermal noise and consider only the 1/f noise. Performing the integration gives
Veq(rms)2 = ⌡⌠
1
105
4.689x10-12
f df = 4.689x10-12[ln(100,000) - ln(1)]
= 0.540x10-10 Vrms2 = 7.34 µVrmsThe maximum signal in rms is 0.353V. Dividing this by 7.34µV gives 48,044 or 93.6dBwhich is equivalent to about 15 bits of resolution.6.) Note that the design of the remainder of the op amp will have little influence on thenoise and is not included in this example.
Chapter 7 – Section 5 (5/2/04) Page 7.5-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Lateral BJTSince the 1/f noise is associated with current flowing at the surface of the channel, thelateral BJT offers a lower 1/f noise input device because the majority of current flowsbeneath the surface.
n+ p+ n+ n+n+
p-well
n-substrate
Base EmitterVertical Collector (VDD)
Base
Emitter
LateralCollector
LateralCollector
VerticalCollector
(VDD)
Cross-section of a NPN lateral BJT. Symbol. Fig. 7.5-3
Comments:• Base of the BJT is the well• Two collectors-one horizontal (desired) and one vertical (undesired)
• Collector efficiency is defined as Lateral collector currentTotal collector current and is 60-70%
• Reverse biased collector-base acts like a photodetector and is often used for light-sensing purposes
Chapter 7 – Section 5 (5/2/04) Page 7.5-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Field-Aided Lateral BJTPolysilicon gates are used to ensure that the region beneath the gate does not invertforcing all current flow away from the surface and further eliminating the 1/f noise.
n+ p+ n+ n+n+
p-well
n-substrate
BaseEmitter
Vertical Collector (VDD)
Base
Emitter
LateralCollector
LateralCollector
VerticalCollector
(VDD)
Cross-section of a field-aided NPN lateral BJT. Symbol. Fig. 7.5-4
Gates
Gate
Chapter 7 – Section 5 (5/2/04) Page 7.5-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Physical Layout of a Lateral PNP Transistor Experimental Results for
a x40 PNP lateral BJT:
Base Lateral Emitter GateVerticalCollectorCollector
n-substrate
n-diffusion
p-diffusion
Polysilicon
Metal
p-well
Fig. 7.5-7A
Generally, the above structure is made as small aspossible and then paralleled with identical geomet-ries to achieve the desired BJT.
Characteristic ValueTransistor area 0.006mm2
Lateral β 90Lateralefficiency
70%
Base resistance 150Ωen at 5 Hz 2.46nV/ Hzen at midband 1.92nV/ Hzfc(en) 3.2Hz
in at 5 Hz 3.53pA/ Hzin at midband 0.61pA/ Hzfc(in) 162 Hz
fT 85 MHz
Early voltage 16V1.2µm CMOS with n-well
Chapter 7 – Section 5 (5/2/04) Page 7.5-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Low-Noise Op Amp using Lateral BJT’s at the Input
vout
VDD
VSS
Cc = 1pF
VSS
Q1 Q2
M3 M4
M5
M6
M7
M8 M9
M10 M11
M12
M13M14
M15M16
R1=34kΩ
D1
Rz = 300Ω
48018
48018
1303.6
43.86.6
45.63.6
81.63.6
5113.61296
3.6
3841.2
2701.246.8
3.6
46.83.6
58.27.2
58.27.2
vi1vi2
Fig. 7.5-6
Experimental noiseperformance:
0
2
4
6
8
10
10 100 1000 104 105
Frequency (Hz)
Noi
se (
nV/
Hz) Eq. input noise voltage of low-noise op amp
Voltage noise of lateral BJT at 170µA
Fig. 7.5-7
Chapter 7 – Section 5 (5/2/04) Page 7.5-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Experimental Performance for the Low-Noise Op Amp
Experimental Performance ValueCircuit area (1.2µm) 0.211 mm2
Supply Voltages ±2.5 VQuiescent Current 2.1 mA-3dB frequency (at a gain of 20.8 dB) 11.1 MHzen at 1Hz 23.8 nV/ Hzen (midband) 3.2 nV/ Hzfc(en) 55 Hz
in at 1Hz 5.2 pA/ Hzin (midband) 0.73 pA/ Hzfc(in) 50 HzInput bias current 1.68 µAInput offset current 14.0 nAInput offset voltage 1.0 mVCMRR(DC) 99.6 dBPSRR+(DC) 67.6 dB
PSRR-(DC) 73.9 dBPositive slew rate (60 pF, 10 kΩ load) 39.0 V/µSNegative slew rate (60 pF, 10 kΩ load) 42.5 V/µS
Chapter 7 – Section 5 (5/2/04) Page 7.5-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Chopper-Stabilized Op Amps - Doubly Correlated Sampling (DCS)Illustration of the use of chopper stabilization to remove the undesired signal, vu, form thedesired signal, vin.
+1
-1t
T fc = 1
vin
vu
voutvB vB
Vin(f)
Vu(f)
VB(f)
ffc0 2fc
f
f
3fcVC(f)
ffc0 2fc 3fc
A1 A2
Clock
VA(f)
ffc0 2fc 3fc
vA
Fig. 7.5-8
Chapter 7 – Section 5 (5/2/04) Page 7.5-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Chopper-Stabilized AmplifierVDD
VSS
φ1
φ1
φ2
φ2
IBias
M1 M2
M3 M4
+
-
vin
VDD
VSS
φ1
φ1
φ2
φ2
IBias
M5 M6
M7 M8
Circuit equivalent during φ1 phase:
A1
+
-
-
+
A2
+
-
-
+
vu2vu1
vueq
Circuit equivalent during the φ2 phase:
A1
+
-
-
+
A2
+
-
-
+
vu2vu1
vueq
vueq = vu1 + vu2A1
vueq = -vu1 + A1
vu2 , vueq(aver) = vu2A1
Fig. 7.5-10
Chopper-stabilized Amplifier:
Chapter 7 – Section 5 (5/2/04) Page 7.5-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Experimental Noise Response of the Chopper-Stabilized Amplifier
10
100
1000
0 10 20 30 40 50Frequency (kHz)
nV/
Hz
Without chopper
With chopperfc = 16kHz
With chopper fc = 128kHz
Fig. 7.5-11
Comments: • The switches in the chopper-stabilized op amp introduce a thermal noise equal to kT/C
where k is Boltzmann’s constant, T is absolute temperature and C are capacitorscharged by the switches (parasitics in the case of the chopper-stabilized amplifier).
• Requires two-phase, non-overlapping clocks. • Trade-off between the lowering of 1/f noise and the introduction of the kT/C noise.
Chapter 7 – Section 5 (5/2/04) Page 7.5-19
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• Primary sources of noise for CMOS circuits is thermal and 1/f• Noise analysis:
1.) Insert a noise generator for each transistor that contributes to the noise.(Generally ignore the current source transistor of source-coupled pairs.)
2.) Find the output noise voltage across an open-circuit or output noise current into ashort circuit.
3.) Reflect the total output noise back to the input resulting in the equivalent inputnoise voltage.
• Noise is reduced in op amps by making the input stage gain as large as possible andreducing the noise of this stage as much as possible.
• The input stage noise can be reduced by using lateral BJTs (particularily the 1/f noise)• Doubly correlated sampling can transfer the noise at low frequencies to the clock
frequency (this technique is used to achieve low input offset voltage op amps).
Chapter 7 – Section 6 (5/2/04) Page 7.6-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 7.6 – LOW VOLTAGE OP AMPSObjectiveThe objective of this presentation is:1.) How to design standard circuit blocks with reduced power supply voltage2.) Introduce new methods of designing low voltage circuitsOutline• Low voltage input stages• Low voltage bias circuits• Low voltage op amps• Examples• Summary
Chapter 7 – Section 6 (5/2/04) Page 7.6-2
CMOS Analog Circuit Design © P.E. Allen - 2004
IntroductionWhile low voltage op amps can be easily designed in weak inversion, strong
inversion leads to higher performance and is the focus of this section.Semiconductor Industry Associates Roadmap for Power Supplies:
1995 1998 2001 2004 2007 2010
3.0V
2.5V
2.0V
1.5V
1.0V
0.35µm 0.25µm 0.18µm 0.13µm 0.10µm 0.07µmFeature Size
Pow
er S
uppl
y V
olta
ge
Year
Desktop Systems
Portable Systems
Fig. 7.6-2
SingleCell
Voltage
Threshold voltages will remain about 0.5 to 0.7V in order to allow the MOSFET to beturned off.
Chapter 7 – Section 6 (5/2/04) Page 7.6-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Implications of Low-Voltage, Strong-Inversion Operation
• Reduced power supply means decreased dynamic range• Nonlinearity will increase because the transistor is working close to VDS(sat)
• Large values of λ because the transistor is working close to VDS(sat)
• Increased drain-bulk and source-bulk capacitances because they are less reverse biased.• Large values of currents and W/L ratios to get high transconductance• Small values of currents and large values of W/L will give smallVDS(sat)
• Severely reduced input common mode range• Switches will require charge pumps
Approach• Low voltage input stages with reasonable ICMR• Low voltage bias and load circuits• Low voltage op amps
Chapter 7 – Section 6 (5/2/04) Page 7.6-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Differential Amplifier with Current Source Loads
Minimum power supply (ICMR = 0):VDD(min) = VSD3(sat)-VT1+VGS1+VDS5(sat)
= VSD3(sat)+VDS1(sat)+VDS5(sat)
Input common-mode range:Vicm(upper) = VDD - VSD3(sat) + VT1
Vicm(lower) = VDS5(sat) + VGS1
Example:If the threshold magnitudes are 0.7V, VDD = 1.5V and the saturation voltages are
0.3V, thenVicm(upper) = 1.5 - 0.3 + 0.7 = 1.9V and Vicm(lower) = 0.3 + 1.0 = 1.3V
giving an ICMR of 0.6V.
vicm M1 M2
M3 M4
M5
VDD
VDS5(sat)VBias
+
-
VBias+
-
VGS1
-VT1
VSD3(sat)
Fig. 7.6-3
Chapter 7 – Section 6 (5/2/04) Page 7.6-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Increasing ICMR using Parallel Input StagesTurn-on voltage for the n-channel input:
Vonn = VDSN5(sat) + VGSN1Turn-on voltage for the p-channel input:
Vonp = VDD - VSDP5(sat) - VSGP1The sum of Vonn and Vonp equals the minimumpower supply.Regions of operation:
VDD > Vicm > Vonp: (n-channel on and p-channel off) gm(eq) = gmN
Vonp ≥ Vicm ≥ Vonn: (n-channel on and p-channel on) gm(eq) = gmN + gmP
Vonn > Vicm > 0 : (n-channel off and p-channel on) gm(eq) = gmP
where gm(eq) is the equivalent input transconductance of the above input stage, gmN isthe input transconductance for the n-channel input and gmP is the input transconduct-ance for the p-channelinput.
VDD
MN1 MN2MP1 MP2
MP3MP4
MP5MN3MN4
MN5
IBias
M6
M7
Fig. 7.6-4
Vicm Vicm
0 VSDP5(sat)+VGSN1 VDD-VSDP5(sat)+VGSN1 VDD
gmN+gmP
gmNgmP
gm(eff)
Vicm
n-channel onn-channel off n-channel onp-channel onp-channel on p-channel off
Fig. 7.6-5
Vonn Vonp
Chapter 7 – Section 6 (5/2/04) Page 7.6-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Removing the Nonlinearity in Transconductances as a Function of ICMRIncrease the bias current in the different-ial amplifier that is on when the otherdifferential amplifier is off.
Three regions of operation depending onthe value of Vicm:
1.) Vicm < Vonn: n-channel diff. amp.off and p-channel on with Ip = 4Ib:
gm(eff) = KP’WP
LP 2 Ib
2.) Vonn < Vicm < Vonp: both on with
In = Ip = Ib:
gm(eff) = KN’WN
LN Ib + KP’WP
LP Ib
3.) Vicm > Vonp: p-channel diff. amp. off and n-channel on with In = 4Ib:
gm(eff) = KN’WN
LN 2 Ib
VDD
Ib
Ib1:3
3:1
MN1
MP1 MP2
MN2MB2 MB1
VB2 VB1
Inn
Ipp
Ip
In
VicmVicm
Fig. 7.6-6
Chapter 7 – Section 6 (5/2/04) Page 7.6-7
CMOS Analog Circuit Design © P.E. Allen - 2004
How Does the Current Compensation Work?Set VB1 = Vonn and VB2 = Vonp.
VonnMN1 MN2
MB1vicmvicm
IppIn
IbIf vicm >Vonn then In = Ib and Ipp=0
If vicm <Vonn then In = 0 and Ipp=Ib
VDD
Vonp
MP1 MP2
MB2vicmvicm
Inn Ip
IbIf vicm <Vonp then Ip = Ib and Inn=0
If vicm >Vonp then Ip = 0 and Inn=Ib
Fig. 7.6-6A
Result:
gm(eff)
Vonn Vonp VDD
Vicm00
gmN=gmP
Fig. 7.6-7
The above techniques and many similar ones are good for power supply values down toabout 1.5V. Below than, different techniques must be used or the technology must bemodified (natural devices).
Chapter 7 – Section 6 (5/2/04) Page 7.6-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Bulk-Driven MOSFETA depletion device would permit large ICMR even with very small power supply voltagesbecause VGS is zero or negative.
When a MOSFET is driven from the bulk with the gate held constant, it acts like adepletion transistor.Cross-section of an n-channelbulk-driven MOSFET:
Large signal equation:
iD = KN’W
2L
VGS - VT0 - γ 2|φF| - vBS + γ 2|φF| 2
Small-signal transconductance:
gmbs = γ (2KN’W/L)ID
2 2|φF| - VBS
p-well
n+
n+
n+
p+ Channel
QP
QV
Bulk Drain Gate Source Substrate
VDDVGSVDSvBS
DepletionRegion
n substrateFig. 7.6-8
Chapter 7 – Section 6 (5/2/04) Page 7.6-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Bulk-Driven MOSFET - ContinuedTransconductance characteristics:
Saturation: VDS > VBS – VP gives,
VBS = VP + VON
iD = IDSS
1 - VBSVP
2
Comments:• gm (bulk) > gm(gate) if VBS > 0
(forward biased )• Noise of both configurations are the same (any differences comes from the gate versus
bulk noise)• Bulk-driven MOSFET tends to be more linear at lower currents than the gate-driven
MOSFET• Very useful for generation of IDSS floating current sources.
0
500
1000
1500
2000
-3 -2 -1 0 1 2 3
Dra
in C
urre
nt (
µA
)
Gate-Source or Bulk-Source Voltage (Volts)
IDSS
Bulk-source driven
Gate-sourcedriven
Fig. 7.6-9
Chapter 7 – Section 6 (5/2/04) Page 7.6-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Bulk-Driven, n-channel Differential AmplifierWhat is the ICMR?
Vicm(min) = VSS + VDS5(sat) + VBS1 = VSS + VDS5(sat) - |VP1| + VDS1(sat)
Note that Vicm can be less than VSS if |VP1| > VDS5(sat) + VDS1(sat)
Vicm(max) = ?
As Vicm increases, the current throughM1 and M2 is constant so the sourceincreases. However, the gate voltage staysconstant so that VGS1 decreases. Sincethe current must remain constant throughM1 and M2 because of M5, the bulk-source voltage becomes less negativecausing VTN1 to decrease and maintainthe currents through M1 and M2 constant.If Vicm is increased sufficiently, the bulk-source voltage will become positive.However, current does not start to flowuntil VBS is greater than 0.3 volts so theeffective Vicm(max) is
Vicm(max) ≈ VDD - VSD3(sat) - VDS1(sat) + VBS1.
VDD
VSS
M1 M2
M3 M4
M5M6
M7
IBiasvi1 vi2
Fig. 7.6-10
+ VBS1-
+ VBS2-
+ VGS-
Chapter 7 – Section 6 (5/2/04) Page 7.6-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of the ICMR of the Bulk-Driven, Differential Amplifier
-50nA
0
50nA
100nA
150nA
Bul
k-So
urce
Cur
rent
Input Common-Mode Voltage-0.50V -0.25V 0.00V 0.25V 0.50V
200nA
250nA
Fig. 7.6-10A
Comments:• Effective ICMR is from VSS to VDD -0.3V
• The transconductance of the input stage can vary as much as 100% over the ICMRwhich makes it very difficult to compensate
Chapter 7 – Section 6 (5/2/04) Page 7.6-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Low-Voltage Current Mirrors using the Bulk-Driven MOSFETThe biggest problem with current mirrors is the large minimum input voltage required forpreviously examined current mirrors.If the bulk-driven MOSFET is biased with a current that exceeds IDSS then it isenhancement and can be used as a current mirror.
VDD
iin
iout
M1 M2
+
-VGS
+-
VBS+
-VGS
VDD
iin iout
M1 M2
+
-VGS1
+-
VBS1+
-VGS2
M3 M4
Simple bulk-driven current mirror
Cascodebulk-driven current mirror. Fig.7.6-11
+-
VBS3+
-VGS3
+-
VGS4
The cascode current mirror gives a minimum input voltage of less than 0.5V for currentsless than 100µA
0
1 10-5
2 10-5
3 10-5
4 10-5
5 10-5
6 10-5
0 0.2 0.4 0.6 0.8 1
Cascode Current MirrorAll W/L's = 200µm/4µm
Iout
(A
)
Vout (V)
Iin=50µA
Iin=40µA
Iin=30µA
Iin=20µA
Iin=10µA
2µm CMOS
Fig. 7.6-12
Chapter 7 – Section 6 (5/2/04) Page 7.6-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Simple Current Mirror with Level ShiftingSince the drain can be VT less than the gate, the drain could be biased to reduce theminimum input voltage as illustrated.
VDD
M1 M2
Q3
+
-VEB
iout
iin IBias
Fig. 7.6-13
Chapter 7 – Section 6 (5/2/04) Page 7.6-14
CMOS Analog Circuit Design © P.E. Allen - 2004
A Low-Voltage Current Mirror with Wide Input and Output SwingsThe current mirror below requires a power supply of VT+3VON and has a Vin(min) =VON and a Vout(min) = 2VON (less for the regulated cascode output mirror).
iin
M1 M2
M3
VDD
IB
M4
M5
M6
M7
iout
I1-IB IB I2
or
iin
M1
M2
M3
VDD
IB1
M4
M5M6
M7
iout
I1 IB2 I2IB1
IB2
Fig. 7.6-13A
Chapter 7 – Section 6 (5/2/04) Page 7.6-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Bandgap Topologies Compatible with Low Voltage Power Supply
VPTAT
VBE
IPTAT
VRef
VDD
Voltage-mode bandgap topology.
INL
VRef
VDD
IVBE
VDD
IPTAT
VDD
Current-mode bandgap topology.
VRef
VDD
IPTAT
VDDVDD
INL
IVBE
R2
R3
R1
Voltage-current mode bandgap topology.Fig. 7.6-14
Chapter 7 – Section 6 (5/2/04) Page 7.6-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Method of Generating Currents with VBE and PTAT Temperature Coefficients
M3 M4M5
M6
M7
VDD
VPTATR1
+
-
Vout1
+
-
R2
Q1 Q2
IPTAT IPTAT
R3
Vout2
+
-
R4
IVBE
IVBEIPTATBuss
IVBEBuss
M8
M9
Figure 7.6-15A
VBE
+
-
Vout1 = IPTATR2 =
VPTAT
R1R2 = VPTAT
R2R1
Vout2 = IVBER4 =
VBE
R3R4 = VBE
R4R3
Chapter 7 – Section 6 (5/2/04) Page 7.6-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Technique for Canceling the Bandgap CurvatureVDD
M1 M2 M3 M4
IVBE K1IPTAT
1:K2 1:K3
I2 INLK3INL
Cur
rent K2IVBE K1IPTAT
Temperature
INL
M2 activeM3 off
M2 sat.M3 on
Circuit to generate nonlinear correction term, INL. Illustration of the various currents.Fig. 7.6-16
INL = 0, K2IVBE > K1IPTAT
K1IPTAT - K2IVBE, K2IVBE < K1IPTAT
The combination of the above concept with the previous slide yielded a curvature-corrected bandgap reference of 0.596V with a TC of 20ppm/C° from -15C° to 90C° usinga 1.1V power supply.† In addition, the line regulation was 408 ppm/V for 1.2≤VDD≤10Vand 2000 ppm/V for 1.1≤VDD≤10V. The quiescent current was 14µA.
† G.A. Rincon-Mora and P.E. Allen, “A 1.1-V Current-Mode and Piecewise-Linear Curvature-Corrected Bandgap Reference,” J. of Solid-StateCircuits, vol. 33, no. 10, October 1998, pp. 1551-1554.
Chapter 7 – Section 6 (5/2/04) Page 7.6-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Low-Voltage Op Amp using Classical Techniques (VDD ≥≥≥≥2222VT)
-
+vin
M1 M2
M3 M4
M5
M13
M7
vout
VDD
Cc
CL
IBiasR1M6
M8 M9 M14M10
M11
M12
M15
M16
Fig. 7.6-17
+
-
VT+2VON
+
-VON
+
-VON
+
-VT+VON
+-
VT+VON
Clever use of classical techniques.Balanced inputs.
Chapter 7 – Section 6 (5/2/04) Page 7.6-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.6-1 - Design of a Low-Voltage Op Amp using the Previous TopologyUse the parameters of Table 3.1-2 to design the op amp above to meet the
specifications given below.VDD = 2V Vicm(max) = 2.5V Vicm(min) = 1V
Vout(max) = 1.75V Vout(min) = 0.5V GB = 10MHz
Slew rate = ±10V/µs Phase margin = 60° for CL = 10pFSolution
Assuming the conditions for a two-stage op amp necessary to achieve 60° phasemargin and that the RHP zero is at least 10GB gives
Cc = 0.2CL = 2pF
The slew rate is directly related to the current in M5 and gives
I5 = Cc·SR = 2x10-12·107 = 20µA
We also know the input transconductances from GB and Cc. They are given as
gm1 = gm2 = GB·Cc = 20πx106·2x10-12 = 125.67µS
Knowing the current flow in M1 and M2 gives the W/L ratios as
W1L1
= W2L2
= gm12
2KN’(I1/2) = (125.67x10-6)2
2·110x10-6·10x10-6 = 7.18
Chapter 7 – Section 6 (5/2/04) Page 7.6-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.6-1 - ContinuedNext, we find the W/L of M5 that will satisfy Vicm(min) specification.
Vicm(min) = VDS5(sat) + VGS1(10µA) = 1VThis gives
VDS5(sat) = 1 - 2·10
110·7.18 - 0.75 = 1-0.159-0.75 = 0.0909V
∴ VDS5(sat) = 0.0909 = 2·I5
KN’(W5/L5) →W5L5
= 2·20
110·(0.0909)2 = 44
The design of M3 and M4 is accomplished from the upper input common mode voltage:Vicm(max) = VDD-VSD3(sat)+VTN = 2-VSD3(sat)+0.75 = 2.5V
Solving for VSD3(sat) gives 0.25V. Assume that the currents in M6 and M7 are 20µA.This gives a current of 30µA in M3 and M4. Knowing the current in M3 (M4) gives
VSD3(sat) ≤ 2·30
50·(W3/L3) →W3L3
= W4L4
≥ 2·30
(0.25)2·50 = 19.2
Next, using the VSD(sat) = V ON of M3 and M4, design M10 through M12. Let usassume that I10 = I5 = 20µA which gives W10/L10 = 44. R1 is designed as R1 =0.25V/20µA = 12.5kΩ. The W/L ratios of M11 and M12 can be expressed as
W11L11
= W12L12
= 2·I11
KP’·VSD11(sat)2 = 2·20
50·(0.25)2 = 12.8
Chapter 7 – Section 6 (5/2/04) Page 7.6-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.6-1 - ContinuedSince the source-gate voltages and currents of M6 and M7 are the same as M11 and M12then the W/L values are equal. Thus
W6/L6 = W7/L7 = 12.8M8 and M9 should be as small as possible to reduce the parasitic (mirror) pole.
However, the voltage drop across M4, M6 and M8 must be less than the power supply.Using this to design the gate-source voltage of M8 gives
VGS8 = VDD - 2VON = 2V - 2·0.25 = 1.5VThus,
W8L8
= W9L9
= 2·I8
KN’·VDS8(sat)2 = 2·30
110·(0.75)2 = 0.97 ≈ 1
Because M8 and M9 are small, the mirror pole will be insignificant. The next poles ofinterest would be those at the sources of M6 and M7. Assuming the channel length is1µm, these poles are given as
p6 ≈ gm6CGS6
= 2KP'·(W6/L6)·I6
(2/3)·W6·L6·Cox =
2·50·12.8·20 x10-6
(2/3)·12.8·1·2.47x10-15 = 7.59x109 rads/sec
which is about 100 times greater than GB.Finally, the W/L ratios of the second stage must be designed. We can either use the
relationship for 60° phase margin of gm14 = 10gm1 = 1256.7µS or consider propermirroring between M9 and M14.
Chapter 7 – Section 6 (5/2/04) Page 7.6-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 7.6-1 - ContinuedSubstituting 1256.7µS for gm14 and 0.5V for VDS14 in W/L = gm/(KN' VDS(sat)) givesW14/L14 = 22.85 which gives I14 = 314µA. The W/L of M13 is designed by thenecessary current ratio desired between the two transistors and is
W13L13
= I13I12
I12 = 31420 ·12.8 = 201
Now, check to make sure that the Vout(max) is satisfied. The saturation voltage of M13 is
VSD13(sat) = 2·I13
KP' (W13/L13) = 2·314
50·201 = 0.25V
which exactly meets the specification. For proper mirroring, the W/L ratio of M14 is,W9L9
= I9I14
W14L14
= 1.46
Since W9/L9 was selected as 1, this is close enough.The parameters are gds7 = 1µS, gds8 = 0.8µS, gds13 = 15.7µS and gds14 = 12.56µS.
Therefore small signal voltage gain is (RI ≈ rds9 because M7 is part of a cascode conf.)voutvin
≈
gm1
gds9
gm14
gds13+gds14 =
125.6
1.8
1256.7
28.26 = 69.78·44.47 = 3,103V/V
The power dissipation, including Ibias of 20µA, is 708µW.The minimum power supply voltage is VT + 3∆V ≈ 1.5V if VT = 0.7V and ∆V ≈ 0.25V.
Chapter 7 – Section 6 (5/2/04) Page 7.6-23
CMOS Analog Circuit Design © P.E. Allen - 2004
A 1-Volt, Two-Stage Op AmpUses a bulk-driven differential input amplifier.
vin+
vout
VDD=1V
IBias
Cc=30pF
CL
Rz=1kΩ
vin-
M1 M2
M3 M4Q5 Q6
M7
M8 M9 M10 M11M12
2000/2
400/2 400/2 400/2
6000/6 6000/6 3000/6 6000/6
Fig. 7.6-18
Chapter 7 – Section 6 (5/2/04) Page 7.6-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Performance of the 1-Volt, Two-Stage Op AmpSpecification (VDD=0.5V, VSS=-0.5V) Measured Performance (CL = 22pF)
DC open-loop gain 49dB (Vicm mid range)Power supply current 300µAUnity-gainbandwidth (GB) 1.3MHz (Vicm mid range)Phase margin 57° (Vicm mid range)Input offset voltage ±3mVInput common mode voltage range -0.475V to 0.450VOutput swing -0.475V to 0.491VPositive slew rate +0.7V/µsecNegative slew rate -1.6V/µsecTHD, closed loop gain of -1V/V -60dB (0.75Vp-p, 1kHz sinewave)
-59dB (0.75Vp-p, 10kHz sinewave)THD, closed loop gain of +1V/V -59dB (0.75Vp-p, 1kHz sinewave)
-57dB (0.75Vp-p, 10kHz sinewave)Spectral noise voltage density 367nV/ Hz @ 1kHz
181nV/ Hz @ 10kHz,81nV/ Hz @ 100kHz444nV/ Hz @ 1MHz
Positive Power Supply Rejection 61dB at 10kHz, 55dB at 100kHz, 22dB at 1MHzNegative Power Supply Rejection 45dB at 10kHz, 27dB at 100kHz, 5dB at 1MHz
Chapter 7 – Section 6 (5/2/04) Page 7.6-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Further Considerations of the using the Bulk - Current Driven Bulk†
The bulk can be used to reduce the threshold sufficiently to permit low voltageapplications. The key is to keep the substrate current confined.One possible technique is:
IBB
S
G
D
B
IBB
S
G
D
BIE
ICD ICS
Reduced Threshold MOSFET Parasitic BJT
n-well
p+ p+
n+
Source Drain
Gate
p- substrateLayout Fig. 7.6-19
Problem:Want to limit the BJT current to some value called, Imax.Therefore,
IBB = Imax
βCS + βCD + 1
† T. Lehmann and M. Cassia, “1V Power Supply CMOS Cascode Amplifier,” IEEE J. of Solid-State Circuits, Vol. 36, No. 7, 2001
Chapter 7 – Section 6 (5/2/04) Page 7.6-26
CMOS Analog Circuit Design © P.E. Allen - 2004
Current-Driven Bulk Technique - ContinuedBias circuit for keeping the Imax definedindependent of BJT betas.
Note:ID,C = ICD + IDIS,E = ID + IE + IR
The circuit feedback causes a bulk bias currentIBB and hence a bias voltage VBIAS such that
IS,E = ID + IBB(1+βCS + βCD) + IR regardless of the actual values of the β’s.
Use VBias1 and VBias2 to set ID,C ≈ 1.1ID , IS,E ≈ 1.3ID and IR ≈ 0.1ID which sets Imaxat 0.1ID.
For the circuit to work,VBE < VTN + IRR and |VTP| + VDS(sat) < VTN + IRR
If |VTP| > VTN, then the level shifter IRR can be eliminated.
M1 M2
M3
M4M5
M6
M7
VDD
VSS
VBias1
M8
VBias2VBias
IBB
IS,E
ID,C
Fig. 7.6-20
R
IR
+
-
Chapter 7 – Section 6 (5/2/04) Page 7.6-27
CMOS Analog Circuit Design © P.E. Allen - 2004
A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique
-
+vin M1 M2
M3 M4M5
M6
M7
vout
VDD
VSS
VBiasN
Cx
CL
VBiasP
M8
M9 M10
M11 M12
M13
M14M15
M16
M17
Fig. 7.6-21
Transistors with forward-biased bulks are in a shaded box.For large common mode input changes, Cx, is necessary to avoid slewing in the inputstage.To get more voltage headroom at the output, the transistors of the cascode mirror havetheir bulks current driven.
Chapter 7 – Section 6 (5/2/04) Page 7.6-28
CMOS Analog Circuit Design © P.E. Allen - 2004
A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique -ContinuedExperimental results:
0.5µm CMOS, 40µA total bias current (Cx = 10pF)
Supply Voltage 1.0V 0.8V 0.7VCommon-mode
input range0.0V-0.65V 0.0V-0.4V 0.0V-0.3V
High gain outputrange
0.35V-0.75V
0.25V-0.5V 0.2V-0.4V
Output saturationlimits
0.1V-0.9V 0.15V-0.65V
0.1V-0.6V
DC gain 62dB-69dB 46dB-53dB 33dB-36dBGain-Bandwidth 2.0MHz 0.8MHz 1.3MHz
Slew-Rate(CL=20pF)
0.5V/µs 0.4V/µs 0.1V/µs
Phase margin(CL=20pF)
57° 54° 48°
The nominal value of bulk current is 10nA gives a 10% increase in differential pairquiescent current assuming a BJT β of 100.
Chapter 7 – Section 6 (5/2/04) Page 7.6-29
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• Integrated circuit power supplies are rapidly decreasing (today 2-3Volts)• Classical analog circuit design techniques begin to deteriorate at 1.5-2 Volts• Approaches for lower voltage circuits:
- Use natural NMOS transistors (VT ≈ 0.1V)
- Drive the bulk terminal
- Forward bias the bulk
- Use depeletion devices• The dynamic range will be compressed if the noise is not also reduced• Fortunately, the threshold reduction continues to allow the techniques of this section to
be used in today’s technology
Chapter 7 – Section 7 (5/2/04) Page 7.7-1
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 7 - SUMMARY
This chapter has considered improved op amp performance in the areas of:• Op amps that can drive low output load resistances and large output capacitances• Op amps with improved bandwidth• Op amps with differential output• Op amps having low power dissipation• Op amps having low noise• Op amps that can work at low voltages
The objective of this chapter has been to show how to improve the performance of an opamp.
• We found that improvements are always possible• The key is to balance the tradeoffs against the particular performance improvement• This chapter is an excellent example of the degrees of freedom and choices that
different circuit architectures can offer.
We also illustrated further the approaches to designing op ampsThe next chapter begins the transition from analog to digital with the introduction of thecomparator.
Chapter 8 – Introduction (5/2/04) Page 8.0-1
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 8 – COMPARATORS
Chapter Outline8.1 Characterization of Comparators8.2 Two-Stage, Open-Loop Comparators8.3 Other Open-Loop Comparators8.4 Improving the Performance of Open-Loop Comparators8.5 Discrete-Time Comparators8.6 High-Speed Comparators8.7 Summary
Chapter 8 – Section 1 (5/2/04) Page 8.1-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 8.1 – CHARACTERIZATION OF COMPARATORSObjectiveThe objective of this section is:1.) Introduction to the comparator2.) Characterization of the comparatorOutline• Static characterization• Dynamic characterization• Summary
Chapter 8 – Section 1 (5/2/04) Page 8.1-2
CMOS Analog Circuit Design © P.E. Allen - 2004
What is a Comparator?The comparator is essentially a 1-bit analog-digital converter.
Input is analogOutput is digital
Types of comparators:• Open-loop (op amps without compensation)• Regenerative (use of positive feedback - latches)• Combination of open-loop and regenerative comparators
Chapter 8 – Section 1 (5/2/04) Page 8.1-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Circuit Symbol for a Comparator
+-
vP
vNvO
Fig. 8.1-1
Static Characteristics• Gain• Output high and low states• Input resolution• Offset• NoiseDynamic Characteristics• Propagation delay• Slew rate
Chapter 8 – Section 1 (5/2/04) Page 8.1-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Noninverting and Inverting ComparatorsThe comparator output is binary with the two-level outputs defined as,
VOH = the high output of the comparator
VOL = the low level output of the comparator
Voltage transfer function of an Noninverting and Inverting Comparator:vo
VOH
vP-vN
VOL
Noninverting Comparator
vo
VOH
vP-vN
VOL
Inverting Comparator
Fig. 8.1-2A
Chapter 8 – Section 1 (5/2/04) Page 8.1-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Static Characteristics - Zero-order Model for a ComparatorVoltage transfer function curve:
vo
VOH
vP-vN
VOL Fig. 8.1-2
Model:
f0(vP-vN)+
vO
+
- -
vP
vN
vP-vN
Comparator
f0(vP-vN) = VOH for (vP-vN) > 0
VOL for (vP-vN) < 0 Fig. 8.1-3
Gain = Av =
lim∆V→0
VOH-VOL
∆V where ∆V is the input voltage change
Chapter 8 – Section 1 (5/2/04) Page 8.1-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Static Characteristics - First-Order Model for a ComparatorVoltage transfer curve:
where for a noninverting comparator,VIH = smallest input voltage at which the output voltage is VOHVIL = largest input voltage at which the output voltage is VOL
Model:
The voltage gain is Av = VOH − VOLVIH − VIL
vo
VOH
vP-vN
VOL Fig. 8.1-4
VIH
VIL
f1(vP-vN)+
vO
+
- -
vP
vN
vP-vN
Comparator
f1(vP-vN) =
VOH for (vP-vN) > VIH
VOL for (vP-vN) < VIL Fig. 8.1-5
Av(vP-vN) for VIL< (vP-vN)<VIH
Chapter 8 – Section 1 (5/2/04) Page 8.1-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Static Characteristics - First-Order Model including Input Offset VoltageVoltage transfer curve:
vo
VOH
vP-vN
VOL Fig. 8.1-6
VIH
VIL
VOS
VOS = the input voltage necessary to make the output equal VOH+VOL
2 when vP = vN.
Model:
f1(vP'-vN')+
vO
+
- -
vP
vN
vP'-vN'
Comparator Fig. 8.1-7
vP'
vN'
±VOS
Other aspects of the model:ICMR = input common mode voltage range (all transistors remain in saturation)Rin = input differential resistance
Ricm = common mode input resistance
Chapter 8 – Section 1 (5/2/04) Page 8.1-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Static Characteristics - Comparator NoiseNoise of a comparator is modeled as if the comparator were biased in the transitionregion.
vo
VOH
vP-vN
VOL
Fig. 8.1-8
Rms Noise
Transition Uncertainty
Noise leads to an uncertainty in the transition region which causes jitter or phase noise.
Chapter 8 – Section 1 (5/2/04) Page 8.1-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Dynamic Characteristics - Propagation Time DelayRising propagation delay time:
vo
VOH
tVOL
vi
t
Fig. 8.1-9
VIH
VIL
vo = VOH+VOL
2
vi = VIH+VIL
2tp
= vP-vN
Propagation delay time = Rising propagation delay time + Falling propagation delay time
2
Chapter 8 – Section 1 (5/2/04) Page 8.1-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Dynamic Characteristics - Single-Pole ResponseModel:
Av(s) = Av(0)sωc + 1
= Av(0)sτc+1
whereAv(0) = dc voltage gain of the comparator
ωc = 1τc = -3dB frequency of the comparator or the magnitude of the pole
Step Response:
vo(t) = Av(0) [1 - e-t/τc]Vinwhere
Vin = the magnitude of the step input.
Chapter 8 – Section 1 (5/2/04) Page 8.1-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Dynamic Characteristics - Propagation Time DelayThe rising propagation time delay for a single-pole comparator is:
VOH-VOL2 = Av(0) [1 - e-tp/τc]Vin → tp = τc ln
1
1 - VOH -VOL2Av(0)Vin
Define the minimum input voltage to the comparator as,
Vin(min) = VOH -VOL
Av(0) → tp = τc ln
1
1- Vin(min)
2VinDefine k as the ratio of the input step voltage, Vin, to the minimum input voltage, Vin(min),
k = Vin
Vin(min) → tp = τc ln
2k
2k-1
Thus, if k = 1, tp = 0.693τc.
Illustration:
Obviously, the more overdriveapplied to the input, the smallerthe propagation delay time.
+
-
VOH
VOL
tp(max)0t0
VOH+VOL2
Vin > Vin(min)
Vin = Vin(min)
vin
vout
vout
Fig. 8.1-10tp
Chapter 8 – Section 1 (5/2/04) Page 8.1-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Dynamic Characteristics - Slew Rate of a ComparatorIf the rate of rise or fall of a comparator becomes large, the dynamics may be limited by
the slew rate.Slew rate comes from the relationship,
i = C dvdt
where i is the current through a capacitor and v is the voltage across it.If the current becomes limited, then the voltage rate becomes limited.Therefore for a comparator that is slew rate limited we have,
tp = ∆T = ∆VSR =
VOH- VOL2·SR
whereSR = slew rate of the comparator.
Chapter 8 – Section 1 (5/2/04) Page 8.1-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.1-1 - Propagation Delay Time of a ComparatorFind the propagation delay time of an open loop comparator that has a dominant pole
at 103 radians/sec, a dc gain of 104, a slew rate of 1V/µs, and a binary output voltageswing of 1V. Assume the applied input voltage is 10mV.
Solution
The input resolution for this comparator is 1V/104 or 0.1mV. Therefore, the 10mVinput is 100 times larger than vin(min) giving a k of 100. Therefore, we get
tp = 1
103 ln
2·100
2·100-1 = 10-3 ln
200
199 = 5.01µs
For slew rate considerations, we get
tp = 1
2·1x106 = 0.5µs
Therefore, the propagation delay time for this case is the larger or 5.01µs.
Chapter 8 – Section 2 (5/2/04) Page 8.2-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 8.2 – TWO-STAGE OPEN-LOOP COMPARATORSObjectiveThe objective of this section is:1.) Illustrate the performance and design of a two-stage open-loop comparatorOutline• Two-stage, open-loop comparator performance• Initial states of the two-stage, open-loop comparator• Propagation delay time of a slewing, two-stage, open-loop comparator• Design of a two-stage, open-loop comparator• Summary
Chapter 8 – Section 2 (5/2/04) Page 8.2-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Two-Stage ComparatorAn important category of comparators are those which use a high-gain stage to drive
their outputs between VOH and VOL for very small input voltage changes.
The two-stage op amp without compensation is an excellent implementation of a high-gain, open-loop comparator.
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
CL
Fig. 8.2-1
Chapter 8 – Section 2 (5/2/04) Page 8.2-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Performance of the Two-Stage, Open-Loop ComparatorWe know the performance should be similar to the uncompensated two-stage op amp.Emphasis on comparator performance:• Maximum output voltage
VOH = VDD - (VDD-VG6(min)-|VTP|)
1 - 1 - 8I7
β6(VDD-VG6(min)-|VTP|)2
• Minimum output voltageVOL = VSS
• Small-signal voltage gain
Av(0) =
gm1
gds2+gds4
gm6
gds6+gds7
• PolesInput: Output:
p1 = -(gds2+gds4)
CI p2 =
-(gds6+gds7)CII
• Frequency response
Av(s) = Av(0)
s
p1 - 1
s
p2 - 1
Chapter 8 – Section 2 (5/2/04) Page 8.2-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.2-1 - Performance of a Two-Stage ComparatorEvaluate VOH, VOL, Av(0), Vin(min), p1, p2, for the two-stage comparator in Fig. 8.2-1.
Assume that this comparator is the circuit of Ex. 6.3-1 with no compensation capacitor,Cc, and the minimum value of VG6 = 0V. Also, assume that CI = 0.2pF and CII = 5pF. Solution
Using the above relations, we find that
VOH = 2.5 - (2.5-0-0.7)
1 - 1 - 8·234x10-6
50x10-6·38(2.5-0-0.7)2 = 2.2V
The value of VOL is -2.5V. The gain was evaluated in Ex. 6.3-1 as Av(0) = 7696.Therefore, the input resolution is
Vin(min) = VOH-VOL
Av(0) = 4.7V7696 = 0.611mV
Next, we find the poles of the comparator, p1 and p2. From Ex. 6.3-1 we find that
p1 = - gds2 + gds4
CI = -
15x10-6(0.04+0.05)0.2x10-12 = -6.75x106 (1.074MHz)
and
p2 = - gds6 + gds7
CII = -
95x10-6(0.04+0.05)5x10-12 = -1.71x106 (0.272MHz)
Chapter 8 – Section 2 (5/2/04) Page 8.2-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Linear Step Response of the Two-Stage ComparatorThe step response of a circuit with two real poles (p1 ≠ p2) is,
vout(t) = Av(0)Vin
1 + p2etp1
p1-p2 -
p1etp2
p1-p2
Normalizing gives,
vout’(tn ) = vout(t)
Av(0)Vin = 1 -
mm-1e-tn +
1m-1e-mtn where m =
p2p1 ≠ 1 and tn = -tp1
If p1 = p2 (m =1), then vout’(tn) = 1 - etp1 + tp1etp1 = 1 - e-tn - tne-tn
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10Normalized Time (tn = -tp1 )
Nor
mal
ized
Out
put V
olta
ge
m = 0.25m = 0.5m = 1m = 2
m = 4
m = p2p1
Fig. 8.2-2
Chapter 8 – Section 2 (5/2/04) Page 8.2-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Linear Step Response of the Two-Stage Comparator - ContinuedThe above results are valid as long as the slope of the linear response does not exceed theslew rate.• Slope at t = 0 is zero• Maximum slope occurs at (m ≠1)
tn(max) = ln(m)m-1
and isdvout’(tn(max))
dtn =
mm-1
exp
-ln(m)
m-1 - exp
-mln(m)m-1
• For the two-stage comparator using NMOS input transistors, the slew rate is
SR- = I7CII
SR+ = I6-I7CII
= 0.5β6(VDD-VG6(min)-|VTP|)2 - I7
CII
Chapter 8 – Section 2 (5/2/04) Page 8.2-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.2-2 - Step Response of Ex. 8.2-1Find the maximum slope of Ex. 8.2-1 and the time at which it occurs if the magnitude
of the input step is vin(min). If the dc bias current in M7 is 100µA, at what value of loadcapacitance, CL would the transient response become slew limited? If the magnitude ofthe input step is 100vin(min), what is the new value of CL at which slewing would occur?Solution
The poles of the comparator were given in Ex. 8.2-1 as p1 = -6.75x106 rads/sec. andp2 = -1.71x106 rads/sec. This gives a value of m = 0.253. From the previous expressions,the maximum slope occurs at tn(max) = 1.84 secs. Dividing by |p1| gives t(max) =0.272µs. The slope of the transient response at this time is found as
dvout’(tn(max))dtn = -0.338[exp(-1.84) - exp(-0.253·1.84)] = 0.159 V/sec
Multiplying the above by |p1| givesdvout’(t(max))
dt = 1.072V/µsTherefore, if the slew rate is less than 1.072V/µs, the transient response will experienceslewing. Also, if CL ≥ 100µA/1.072V/µs or 93.3pF, the comparator will slew.
If the input is 100vin(min), then we must unnormalize the output slope as follows.dvout’(t( max))
dt = vin
vin(min) dvout’(t( max))
dt = 100·1.072V/µs = 107.2V/µs
Therefore, the comparator will now slew with a load capacitance of 0.933pF.
Chapter 8 – Section 2 (5/2/04) Page 8.2-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Propagation Delay Time (Non-Slew)To find tp, we want to set 0.5(VOH-VOL) equal to vout(tn). However, vout(tn) given as
vout(tn) = Av(0)Vin
1 - m
m-1e-tn + 1
m-1e-mtn
can’t be easily solved so approximate the step response as a power series to get
vout(tn) ≈ Av(0)Vin
1 - m
m-1
1-tn+ tn2
2 + ··· + 1
m-1
1-mtn+ m2tn2
2 +··· ≈ mtn2Av(0)Vin
2
Therefore, set vout(tn) = 0.5(VOH-VOL)
VOH+VOL2 ≈
mtpn2Av(0)Vin
2or
tpn ≈ VOH+VOLmAv(0)Vin
= Vin(min)
mVin =
1mk
This approximation is particularly good for large values of k.
Chapter 8 – Section 2 (5/2/04) Page 8.2-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.2-3 - Propagation Delay Time of a Two-Pole Comparator (Non-Slew)Find the propagation time delay of Ex. 8.2-1 if Vin = 10mV, 100mV and 1V.
SolutionFrom Ex. 8.2-1 we know
that Vin(min) = 0.611mV and m= 0.253. For Vin = 10mV, k =16.366 which gives tpn ≈ 0.491.The propagation time delay isequal to 0.491/6.75x106 or72.9nS. This corresponds wellwith Fig. 8.2-2 where thenormalized propagation timedelay is the time at which theamplitude is 1/2k or 0.031which corresponds to tpn ofapproximately 0.5. Similarly,for Vin = 100mV and 1V we geta propagation time delay of23ns and 7.3ns, respectively.
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10Normalized Time (tn = tp1 = t/τ1)
Nor
mal
ized
Out
put V
olta
ge
m = 0.25m = 0.5m = 1m = 2
m = 4
m = p2p1
Fig. 8.2-2A
= 0.031
0.52
12k
tp = 6.75x1060.52 = 77ns
Chapter 8 – Section 2 (5/2/04) Page 8.2-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Initial Operating States for the Two-Stage, Open-Loop ComparatorWhat are the initial operating states forthe two-stage, open-loop comparator?
1.) Assume vG2 = VREF and vG1>VREFwith i1 < ISS and i2>0.
Initially, i4 > i2 and vo1 increases,M4 becomes active and i4 decreasesuntil i3 = i4. vo1 is in the range of,
VDD - VSD4(sat) < vo1 < VDD, vG1 > VREF, i1 < ISS and i2 > 0
and the value of vout is
vout ≈ VSS vG1 > VREF, i1 < ISS and i2 > 0
2.) Assume vG2 = VREF and vG1 >>VREF, therefore i1 = ISS and i2 = 0 which gives
vo1 = VDD and vout = VSS
vG1 M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
CII
Fig. 8.2-3
vG2
i1 i2 CI
ISS
vo1
i4i3
Chapter 8 – Section 2 (5/2/04) Page 8.2-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Initial Operating States - Continued3.) Assume vG2 = VREF and vG1 < VREF with i1>0 and i2<ISS.
Initially, i4 < i2 and vo1 decreases. When vo1 ≤ VREF - VTN, M2 becomes active andi2 decreases. When i1 = i2 = ISS/2 the circuit stabilizes and vo1 is in the range of,
VREF - VGS2 < vo1 < VREF - VGS2 + VDS2(sat)or
VS2 < vo1 < VS2 + VDS2(sat), vG1 < VG2, i1 > 0 and i2 < ISSFor the above conditions,
vout = VDD - (VDD-vo1-|VTP|)
1 - 1 - β7ISS
β5β6(VDD˚-vo1-|VTP|)2
4.) Assume vG2 = VREF and vG1 << VREF, therefore i2 = ISS and i1 = 0.
Same as in 3.) but now as vo1 approaches vS2 with ISS/2 flowing, the value of vGS2becomes larger and M5 becomes active and ISS decreases. In the limit, ISS → 0,vDS2 ≈ 0and vDS5 ≈ 0 resulting in
vo1 ≈ VSS and vout = VDD - (VDD-VSS-
|VTP|)
1 - 1 - β7ISS
β5β6(VDD-VSS-|VTP|)2
Chapter 8 – Section 2 (5/2/04) Page 8.2-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Initial Operating States - Continued5.) Assume vG1 = VREF and vG2>VREF with i2 < ISS and i1>0.
Initially, i4 < i2 and vo1 falls, M2 becomes active and i2 decreases until i1 = i2 = ISS/2.Therefore,
VREF - VGS2(ISS/2) < vo1 < VREF - VGS2(ISS/2) +VDS2(sat)or
VS2(ISS/2) < vo1 < VS2(ISS/2) + VDS2(sat), vG2 > VREF, i1 > 0 and i2 < ISSand the value of vout is
vout = VDD - (VDD-vo1-|VTP|)
1 - 1 - β7ISS
β5β6(VDD˚-vo1-|VTP|)2
6.) Assume that vG1 = VREF and vG2 >> VREF. When the source voltage of M1 or M2causes M5 to be active, then ISS decreases and
vo1 ≈ VSS and vout = VDD - (VDD-VSS-|VTP|)
1 - 1 - β7ISS
β5β6(VDD -VSS-|VTP|)2
7.) Assume vG1 = VREF and vG2 < VREF and i1 <ISS and i2 > 0. Consequently, i4>i2which causes vo1 to increase. When M4 becomes active i4 decreases until i2 = i4 atwhich vo1 stabilizes at (M6 will be off under these conditions and vout ≈ VSS).
VDD - VSD4(sat) < vo1 < VDD, vG2 < VREF, i1 < ISS and i2 > 0
Chapter 8 – Section 2 (5/2/04) Page 8.2-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Initial Operating States - Continued8.) Finally if vG2 <<VREF, then i1 = ISS and i2 =0 and
vo1 ≈ VDD and vout ≈ VSS.
Summary of the Initial Operating States of the Two-Stage, Open-Loop Comparator usinga N-channel, Source-coupled Input Pair:
Conditions Initial State of vo1 Initial State of voutvG1>VG2, i1<ISS and i2>0 VDD-VSD4(sat) < vo1 < VDD VSSvG1>>VG2, i1=ISS and i2=0 VDD VSSvG1<VG2, i1>0 and i2<ISS vo1=VG2-VGS2,act(ISS/2), ≈VSS if M5
act.Eq. (19), Sec. 5.1 for PMOS
vG1<<VG2, i1>0 and i2<ISS VSS Eq. (19), Sec. 5.1 for PMOS
vG2>VG1, i1>0 and i2<ISS VS2(ISS/2)<vo1<VS2(ISS/2)+VDS2(sat) Eq. (19), Sec. 5.1 for PMOS
vG2>>VG1, i1>0 and i2<ISS VG1-VGS1(ISS/2) , ≈VSS if M5 active Eq. (19), Sec. 5.1 for PMOS
vG2<VG1, i1<ISS and i2>0 VDD-VSD4(sat) < vo1 < VDD VSSvG2<<VG1, i1=ISS and i2=0 VDD VSS
Chapter 8 – Section 2 (5/2/04) Page 8.2-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Trip Point of an InverterIn order to determine the propagation delay time, it is
necessary to know when the second stage of the two-stagecomparator begins to “turn on”.Second stage:
Trip point:Assume that M6 and M7 are saturated. (We know that the
steepest slope occurs for this condition.)Equate i6 to i7 and solve for vin which becomes the trip point.
∴ vin = VTRP = VDD - |VTP| - KN(W7/L7)KP(W6/L6) (VBias- VSS -VTN)
Example:If W7/L7 = W6/L6, VDD = 2.5V, VSS = -2.5V, and VBias = 0V the trip point for the
circuit above is
VTRP = 2.5 - 0.7 - 110/50 (0 +2.5 -0.7) = -0.870V
vin
M6
M7
vout
VDD
VSS
+
-i6
i7
Fig. 8.2-4
VBias
Chapter 8 – Section 2 (5/2/04) Page 8.2-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Propagation Delay Time of a Slewing, Two-Stage, Open-Loop ComparatorPreviously we calculated the propagation delay time for a nonslewing comparator.If the comparator slews, then the propagation delay time is found from
ii = Cidvidti = Ci
∆vi∆ti
whereCi is the capacitance to ground at the output of the i-th stage
The propagation delay time of the i-th stage is,
ti = ∆ti = Ci∆ViIi
The propagation delay time is found by summing the delays of each stage.tp = t1 + t2 + t3 + ···
Chapter 8 – Section 2 (5/2/04) Page 8.2-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.2-5 - Propagation Time Delay of a Two-Stage, Open-Loop ComparatorFor the two-stage comparator shown
assume that CI = 0.2pF and CII = 5pF.Also, assume that vG1 = 0V and that vG2has the waveform shown. If the inputvoltage is large enough to cause slew todominate, find the propagation time delayof the rising and falling output of thecomparator and give the propagation timedelay of the comparator.
2.5V
-2.5V
t(µs)0V 0.2 0.4 0.60
Fig. 8.2-5
vG2
Solution1.) Total delay = sum of the first and second stage delays, t1 and t22.) First, consider the change of vG2 from -2.5V to 2.5V at 0.2µs.
The last row of Table 8.2-1 gives vo1 = +2.5V and vout = -2.5V
3.) tf1, requires CI, ∆Vo1, and I5. CI = 0.2pF, I5 = 30µA and ∆V1 can be calculated byfinding the trip point of the output stage/
vG2
M1 M2
M3 M4
M5
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
CII =5pF
3µm1µm
3µm1µm
4.5µm1µm
4.5µm1µm
M84.5µm1µm
30µA
4.5µm1µm
35µm1µm
38µm1µm
30µA
234µA
Fig. 8.2-5A
CI =0.2pF
vo1
vG1
Chapter 8 – Section 2 (5/2/04) Page 8.2-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.2-5 - Continued4.) The trip point of the output stage by setting the current of M6 when saturated equalto 234µA.
β62 (VSG6-|VTP|)2 = 234µA → VSG6 = 0.7 +
234·250·38 = 1.196V
Therefore, the trip point of the second stage is VTRP2 = 2.5 - 1.196 = 1.304V
Therefore, ∆V1 = 2.5V - 1.304V = VSG6 = 1.196V. Thus the falling propagation timedelay of the first stage is
tfo1 = 0.2pF
1.196V
30µA = 8 ns
5.) The rising propagation time delay of the second stage requires CII, ∆Vout, and I6. CIIis given as 5pF, ∆Vout = 2.5V (assuming the trip point of the circuit connected to theoutput of the comparator is 0V), and I6 can be found as follows:
VG6(guess) ≈ 0.5[VG6(I6=234µA) + VG6(min)]
VG6(min) = VG1 - VGS1(ISS/2) + VDS2 ≈ -VGS1(ISS/2) = -0.7 - 2·15
110·3 = -1.00V
VG6(guess) ≈ 0.5(1.304V-1.00V) = 0.152V
Therefore VSG6 = 2.348V and I6 = β62 (VSG6-|VTP|)2 =
38·502 (2.348 - 0.7)2 = 2,580µA
Chapter 8 – Section 2 (5/2/04) Page 8.2-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.2-5 - Continued6.) The rising propagation time delay for the output can expressed as
trout = 5pF
2.5V
2,580µA-234µA = 5.3 ns
Thus the total propagation time delay of the rising output of the comparator isapproximately 13.3 ns and most of this delay is attributable to the first stage.7.) Next consider the change of vG2 from 2.5V to -2.5V which occurs at 0.4µs. We shallassume that vG2 has been at 2.5V long enough for the conditions of Table 8.2-1 to bevalid. Therefore, vo1 ≈ VSS = -2.5V and vout ≈ VDD. The propagation time delays for thefirst and second stages are calculated as
tro1 = 0.2pF
1.304V-(-1.00V)
30µA = 15.4 ns
tfout = 5pF
2.5V
234µA = 53.42ns
8.) The total propagation time delay of thefalling output is 68.82 ns. Taking theaverage of the rising and falling propagationtime delays gives a propagation time delayfor this two-stage, open-loop comparator ofabout 41.06ns.
-3V
-2V
-1V
0V
1V
2V
3V
200ns 300ns 400ns 500ns 600ns
vout
vo1
Time Fig. 8.2-6
VTRP6 = 1.304V
Falling prop.delay timeRising prop.
delay time
Chapter 8 – Section 2 (5/2/04) Page 8.2-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Design of a Two-Stage, Open-Loop ComparatorTable 8.2-2 Design of the Two-Stage, Open-Loop Comparator of Fig. 8.2-3 for a LinearResponse.
Specifications: tp, CII ,Vin(min), VOH, VOL, Vicm+, Vicm
-, and overdrive Constraints: Technology, VDD and VSS
Step Design Relationships Comments
1|pI| = |pII| =
1
tp mk, and I7 = I6 =
|pII|CIIλN+λP
Choose m = 1
2 W6L6
= 2·I6
KP’(VSD6(sat))2 and
W7˚L7
= 2·I7
KN’(VDS7(sat))2
VSD6(sat) = VDD-VOH
VDS7(sat) = VOL - VSS
3Guess CI as 0.1pF to 0.5pF ∴ I5 = I7
2CICII
A result of choosing m = 1.
Will check CI later
4 W3L3
= W4L4
= I5
KP’(VSG3-|VTP|)2
VSG3 = VDD-Vicm++VTN
5
gm1 = Av(0)(gds2+gds4)(gds6+gds7)
gm6
W1L1
= W2L2
= gm1
2
KNI5 gm6 =
2KP’W6I6L6
Av(0) = VOH-VOLVin(min)
6 Find CI and check assumption
CI = Cgd2+Cgd4+Cgs6+Cbd2+Cbd4
If CI is greater than the guess in step 3, thenincrease CI and repeat steps 4 through 6
7VDS5(sat) = Vicm
--VGS1-VSS W5L5
= 2·I5
KN’(VDS5(sat))2
If VDS5(sat) is less than 100mV, increase W1/L1.
Chapter 8 – Section 2 (5/2/04) Page 8.2-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.2-6 - Two-Stage, Open-Loop Comparator Design for a Linear Response.Assume the specifications of the
comparator shown are given below.tp = 50ns VOH = 2V VOL = -2VVDD = 2.5V VSS = -2.5V CII = 5pF
Vin(min) = 1mV Vicm+ = 2V Vicm- = -1.25VAlso assume that the overdrive will be a factorof 10. Use this architecture to achieve theabove specifications and assume that allchannel lengths are to be 1µm.Solution
Following the procedure outlined in Table8.2-2, we choose m = 1 to get
|pI| = |pII| = 109
50 10 = 6.32x106 rads/sec
This gives
I6 = I7 = 6.32x106·5x10-12
0.04+0.05 = 351µA→ I6 = I7 = 400µATherefore,
W6L6
= 2·400
(0.5)2·50 = 64 andW7L7
= 2·400
(0.5)2·110 = 29
vG1 M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
CII
Fig. 8.2-3
vG2
i1 i2 CI
ISS
vo1
i4i3
Chapter 8 – Section 2 (5/2/04) Page 8.2-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.2-6 - ContinuedNext, we guess CI = 0.2pF. This gives I5 = 32µA and we will increase it to 40µA
for a margin of safety. Step 4 gives VSG3 as 1.2V which results in
W3L3
= W4L4
= 40
50(1.2-0.7)2 = 3.2 → W3L3
= W4L4
= 4
The desired gain is found to be 4000 which gives an input transconductance of
gm1 = 4000·0.09·20
44.44 = 162µS
This gives the W/L ratios of M1 and M2 as
W1L1
= W2L2
= (162)2
110·40 = 5.96 → W1L1
= W2L2
= 6
To check the guess for CI we need to calculate it which is done as
CI = Cgd2+Cgd4+Cgs6+Cbd2+Cbd4 = 0.9fF+1.3fF+119.5fF+20.4fF+36.8fF = 178.9fF
which is less than what was guessed so we will make no changes.
Chapter 8 – Section 2 (5/2/04) Page 8.2-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.2-6 - ContinuedFinally, the W/L value of M5 is found by finding VGS1 as 0.946V which gives
VDS5(sat) = 0.304V. This gives
W5L5
= 2·40
(0.304)2·110 = 7.87 ≈ 8
Obviously, M5 and M7 cannot be connected gate-gate and source-source. The value of I5and I7 must be derived separately as illustrated below. The W values are summarizedbelow assuming that all channel lengths are 1µm.
W1 = W2 = 6µm W3 =W4 = 4µm W5 = 8µm W6 = 64µm W7 = 29µm
M5 M7
VSS
400µA40µA
10µA
10µA 40µA
M8 M9
M10 M11
M128/12/1
2/1
2/1
29/1
8/1
3/1
Fig. 8.2-7
VDD
Chapter 8 – Section 2 (5/2/04) Page 8.2-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Design of a Two-Stage Comparator for a Slewing ResponseTable 8.2-3 Two-Stage, Open-Loop Comparator Design for a Slewing Response.
Specifications: tp, CII ,Vin(min), VOH, VOL, Vicm+, Vicm
- Constraints: Technology, VDD and VSS
Step Design Relationships Comments
1I7 = I6 = CII·
dvoutdt =
CII(VOH-VOL)tp
Assume the trip point of the output is (VOH-VOL)/2. Let tp1 = tp2 = 0.5tp
2 W6L6
= 2·I6
KP’(VSD6(sat))2 and
W7L7
= 2·I7
KN’(VDS7(sat))2
VSD6(sat) = VDD-VOH
VDS7(sat) = VOL - VSS
3 Guess CI as 0.1pF to 0.5pF Typically 0.1pf<CI<0.5pF
4I5 = CI·
dvo1dt ≈
CI(VOH-VOL)tp
Assume that vo1 swings between VOH andVOL.
5 W3L3
= W4L4
= I5
KP’(VSG3-|VTP|)2
VSG3 = VDD-Vicm++VTN
6
gm1 = Av(0)(gds2+gds4)(gds6+gds7)
gm6
W1L1
= W2L2
= gm1
2
KNI5 gm6 =
2KP’W6I6L6
Av(0) = VOH-VOLVin(min)
7 Find CI and check assumptionCI = Cgd2+Cgd4+Cgs6+Cbd2+Cbd4
If CI is greater than the guess in step 3, increasethe value of CI and repeat steps 4 through 6
8VDS5(sat) = Vicm
--VGS1-VSS W5L5
= 2·I5
KN’(VDS5(sat))2
If VDS5(sat) is less than 100mV, increase W1/L1.
Chapter 8 – Section 2 (5/2/04) Page 8.2-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.2-7 - Two-Stage, Open-Loop Comparator Design for a Slewing ResponseAssume the specifications of Fig. 8.2-3 are given below.
tp = 50ns VOH = 2V VOL = -2V VDD = 2.5V VSS = -2.5VCII = 5pF Vin(min) = 1mV Vicm+ = 2V Vicm- = -1.25V
Design a two-stage, open-loop comparator using the circuit of Fig. 8.2-3 to the abovespecifications and assume all channel lengths are to be 1µm.Solution
Following the procedure outlined in Table 8.2-3, we calculate I6 and I7 as
I6 = I7 = 5x10-12·450x10-9 = 400µA
Therefore,W6L6
= 2·400
(0.5)2·50 = 64 andW7L7
= 2·400
(0.5)2·110 = 29
Next, we guess CI = 0.2pF. This gives
I5 = 0.2pF(4V)
50ns = 16µA → I5 = 20µA
Step 5 gives VSG3 as 1.2V which results in
W3L3
= W4L4
= 20
50(1.2-0.7)2 = 1.6 → W3L3
= W4L4
= 2
Chapter 8 – Section 2 (5/2/04) Page 8.2-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.2-7 - ContinuedThe desired gain is found to be 4000 which gives an input transconductance of
gm1 = 4000·0.09·10
44.44 = 81µS
This gives the W/L ratios of M1 and M2 as
W3L3
= W4L4
= (81)2
110·40 = 1.49 → W1L1
= W2L2
= 2
To check the guess for CI we need to calculate it which done as
CI = Cgd2+Cgd4+Cgs6+Cbd2+Cbd4 = 0.9fF+0.4fF+119.5fF+20.4fF+15.3fF = 156.5fF
which is less than what was guessed.
Finally, the W/L value of M5 is found by finding VGS1 as 1.00V which gives VDS5(sat)= 0.25V. This gives
W5L5
= 2·20
(0.25)2·110 = 5.8 ≈ 6
As in the previous example, M5 and M7 cannot be connected gate-gate and source-source and a scheme like that of Example 8.2-6 must be used. The W values aresummarized below assuming that all channel lengths are 1µm.
W1 = W2 = 2µm W3 =W4 = 4µm W5 = 6µm W6 = 64µm W7 = 29µm
Chapter 8 – Section 2 (5/2/04) Page 8.2-26
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• The two-stage, open-loop comparator has two poles which should as large as possible• The transient response of a two-stage, open-loop comparator will be limited by either
the bandwidth or the slew rate• It is important to know the initial states of a two-stage, open-loop comparator when
finding the propagation delay time• If the comparator is gainbandwidth limited then the poles should be as large as possible
for minimum propagation delay time• If the comparator is slew rate limited, then the current sinking and sourcing ability
should be as large as possible
Chapter 8 – Section 3 (5/2/04) Page 8.3-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 8.3– OTHER OPEN-LOOP COMPARATORSObjectiveThe objective of this section is:1.) Show other types of continuous-time, open-loop comparatorsOutline• Push-pull comparators• Comparators that can drive large capacitors
Chapter 8 – Section 3 (5/2/04) Page 8.3-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Push-Pull ComparatorsClamped:
-
+vin
M1 M2
M3
M4
M5
M6
vout
VDD
VSS
VBias+
-
CL
M9
M8
M7
Fig. 8.3-1
Comments:• Gain reduced → Larger input resolution• Push-pull output → Higher slew rates
Chapter 8 – Section 3 (5/2/04) Page 8.3-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Push-Pull Comparators - ImprovedCascode output stage:
-
+vin
M1 M2
M3
M4
M5
M6
M11
vout
VDD
VSS
VBias+
-
CII
R1M9
M10
R2
M14
M15
M8
M12
M7
M13
Fig. 8.3-2
Comments:• Can also use the folded cascode architecture• Cascode output stage result in a slow linear response (dominant pole is small)• Poorer noise performance
Chapter 8 – Section 3 (5/2/04) Page 8.3-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Comparators that Can Drive Large Capacitive Loads
-
+vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
CII
M8
M9
M10
M11
Fig. 8.3-3
Comments:• Slew rate = 3V/µs into 50pF• Linear rise/fall time = 100ns into 50pF• Propagation delay time ≈ 1µs• Loop gain ≈ 32,000 V/V
Chapter 8 – Section 3 (5/2/04) Page 8.3-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Self-Biased Differential Amplifier†
M1 M2
M3 M4
M6
M5
VDD
VSS
vin+ vin-vout
M3 M4
M6
VDD
M1 M2
M5
VSS
vin+ vin-
VBias
VBias Extremelylarge sourcingcurrent
Fig. 8.3-4
Advantage:Large sink or source current with out a large quiescent current.
Disadvantage:
Poor common mode range (vin+ slower than vin-)
† M. Bazes, “Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, Feb.1991, pp. 165-168.
Chapter 8 – Section 4 (5/2/04) Page 8.4-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 8.4– IMPROVING THE PERFORMANCE OFCOMPARATORS
ObjectiveThe objective of this section is:1.) Improve the performance of continuous-time, open-loop comparatorsOutline• Autozeroing techniques• Comparators using hysteresis• Summary
Chapter 8 – Section 4 (5/2/04) Page 8.4-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Autozeroing TechniquesUse the comparator as an op amp to sample the dc input offset voltage and cancel theoffset during operation.
+-
VOS VOS+
-
IdealComparator
+-
VOS
IdealComparator
CAZ VOS+
-
+-
VOS
IdealComparator
CAZ
vIN vOUT
Model of Comparator. Autozero Cycle Comparison CycleFig. 8.4-1
Comments:• The comparator must be stable in the unity-gain mode (self-compensating comparators
are good, the two-stage op comparator would require compensation to be switched induring the autozero cycle.)
• Complete offset cancellation is limited by charge injection
Chapter 8 – Section 4 (5/2/04) Page 8.4-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Differential Implementation of Autozeroed Comparators
VOS+
-
+-
VOS
IdealComparator
CAZ
vIN-
vOUTφ1
φ1
φ1
φ2 +-
VOS
vOUT = VOS
VOS+ -
+-
VOS
Comparator during φ1 phase
Comparator during φ2 phaseDifferential Autozeroed Comparator
vOUT
Fig. 8.4-2
vIN+
φ2
vIN+
vIN-
Chapter 8 – Section 4 (5/2/04) Page 8.4-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Single-Ended Autozeroed ComparatorsNoninverting:
+-φ2
φ2
φ1 CAZ
φ1
φ1vOUTvIN
Fig. 8.4-3
Inverting:
+-φ2
CAZ
φ1
φ1
vOUTvIN
Fig. 8.4-4
Comment on autozeroing:Need to be careful about noise that gets sampled onto the autozeroing capacitor and is
present on the comparison phase of the process.
Chapter 8 – Section 4 (5/2/04) Page 8.4-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of Input Noise on the ComparatorComparator without hysteresis:
vin
voutVOH
VOL
Comparatorthreshold
t
t
Fig. 8.4-6A
Comparator with hysteresis:
vin
voutVOH
VOL
t
t
VTRP+
VTRP-
Fig. 8.4-6B
Chapter 8 – Section 4 (5/2/04) Page 8.4-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Use of Hysteresis for Comparators in a Noisy EnvironmentTransfer curve of a comparator with hysteresis:
vOUT
vIN
VTRP+
VTRP-
VOH
VOL
Fig. 8.4-5
vOUT
vIN
VOH
VOL
00
R1R2
(VOH-VOL) VTRP+
VTRP-
Counterclockwise Bistable Clockwise Bistable
Hysteresis is achieved by the use of positive feedback• Externally• Internally
Chapter 8 – Section 4 (5/2/04) Page 8.4-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Noninverting Comparator using External Positive FeedbackCircuit:
Upper Trip Point:Assume that vOUT = VOL, the upper trip point occurs when,
0 =
R1
R1+R2VOL +
R2
R1+R2VTRP
+ → VTRP+ = -
R1R2
VOL
Lower Trip Point:Assume that vOUT = VOH, the lower trip point occurs when,
0 =
R1
R1+R2VOH +
R2
R1+R2VTRP
- → VTRP- = -
R1R2
VOH
Width of the bistable characteristic:
∆Vin = VTRP+-VTRP
- =
R1
R2 VOH -VOL
vOUT
vIN
VOH
VOL
+-
vOUTvIN R1
R2
R1VOLR2
R1VOHR2
Fig. 8.4-7
00
R1R2
(VOH-VOL) -
-
Chapter 8 – Section 4 (5/2/04) Page 8.4-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Inverting Comparator using External Positive FeedbackCircuit:
+- vOUT
vIN
R1R2
vOUT
vIN
VOH
VOL
R1VOHR1VOL
Fig. 8.4-8
00
R1R1+R2
(VOH-VOL)
R1+R2R1+R2
Upper Trip Point:
vIN = VTRP+ =
R1
R1+R2VOH
Lower Trip Point:
vIN = VTRP- =
R1
R1+R2VOL
Width of the bistable characteristic:
∆Vin = VTRP+-VTRP
- =
R1
R1+R2 VOH -VOL
Chapter 8 – Section 4 (5/2/04) Page 8.4-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Horizontal Shifting of the CCW Bistable CharacteristicCircuit:
vOUT
vIN
VOH
VOL
+-
vOUTvIN R1
R2
R1VOHR2
Fig. 8.4-9
00
R1R2
(VOH-VOL)
VREFR1|VOL|
R2
R1+R2R2
VREF
Upper Trip Point:
VREF =
R1
R1+R2VOL +
R2
R1+R2VTRP
+ → VTRP+ =
R1+R2
R2VREF -
R1R2
VOL
Lower Trip Point:
VREF =
R1
R1+R2VOH +
R2
R1+R2VTRP
- → VTRP- =
R1+R2
R2VREF -
R1R2
VOH
Shifting Factor:
R1+R2
R2 VREF
Chapter 8 – Section 4 (5/2/04) Page 8.4-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Horizontal Shifting of the CW Bistable CharacteristicCircuit:
+- vOUT
vIN
R1R2
Fig. 8.4-10
VREF
vOUT
vIN
VOH
VOL
R1|VOL|
00
R1 (VOH-VOL)
R1VOH
R1+R2
R2VREF
R1+R2
R1+R2
R1+R2
Upper Trip Point:
vIN = VTRP+ =
R1
R1+R2VOH +
R2
R1+R2VREF
Lower Trip Point:
vIN = VTRP- =
R1
R1+R2VOL +
R2
R1+R2VREF
Shifting Factor:
R2
R1+R2 VREF
Chapter 8 – Section 4 (5/2/04) Page 8.4-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.4-1 Design of an Inverting Comparator with Hysteresis
Use the inverting bistable to design a high-gain, open-loop comparator having anupper trip point of 1V and a lower trip point of 0V if VOH = 2V and VOL = -2V.
Solution
Putting the values of this example into the above relationships gives
1 =
R1
R1+R2 2 +
R2
R1+R2VREF
and
0 =
R1
R1+R2 (-2) +
R2
R1+R2VREF
Solving these two equations gives 3R1 = R2 and VREF = (2/3)V.
Chapter 8 – Section 4 (5/2/04) Page 8.4-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Hysteresis using Internal Positive FeedbackSimple comparator with internal positive feedback:
VSS
IBias
vo1 vo2
vi1 vi2M1 M2
M3 M4M6 M7
M5M8
VDD
Fig. 8.4-11
Chapter 8 – Section 4 (5/2/04) Page 8.4-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Internal Positive Feedback - Upper Trip PointAssume that the gate of M1 is on ground and theinput to M2 is much smaller than zero. Theresulting circuit is:
M1 on, M2 off → M3 and M6 on, M4 and M7 off.
∴ vo2 is high.
M6 would like to source the current i6 = W6/L6W3L3 i1
As vin begins to increase towards the trip point, thecurrent flow through M2 increases. When i2 = i6,the upper trip point will occur.
∴ i5 = i1+i2 = i3+i6 = i3+
W6/L6
W3/L3 i3 = i3
1 + W6/L6W3/L3 → i1 = i3 =
i51 + [(W6/L6)/(W3/L3)]
Also, i2 = i5 - i1 = i5 - i3Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives
VTRP+ = vGS2 - vGS1 = 2i2β2 + VT2 -
2i1β1 - VT1
VSS
vo1 vo2
M1 M2
M3 M4M6 M7
M5
VDD
Fig. 8.4-12A
I5
i1 = i3
vin
i2 = i6
Chapter 8 – Section 4 (5/2/04) Page 8.4-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Internal Positive Feedback - Lower Trip PointAssume that the gate of M1 is on ground and the inputto M2 is much greater than zero. The resulting circuitis:
M2 on, M1 off → M4 and M7 on, M3 and M6 off.∴ vo1 is high.
M7 would like to source the current i7 = W7/L7W4/L4 i2
As vin begins to decrease towards the trip point, thecurrent flow through M1 increases. When i1 = i7, thelower trip point will occur.
∴ i5 = i1+i2 = i7+i4 =
W7/L7
W4/L4 i4 +i4 = i4
1 + W7/L7W4/L4
→ i2 = i4 = i5
1 + [(W7/L7)/(W4/L4)]
Also, i1 = i5 - i2 = i5 - i4Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives
VTRP- = vGS2 - vGS1 = 2i2β2 + VT2 -
2i1β1 - VT1
Fig. 8.4-12BVSS
vo1 vo2
vi1M1 M2
M3 M4M6 M7
M5
VDD
I5
i2 = i4
vi1
i1 = i7
vin
Chapter 8 – Section 4 (5/2/04) Page 8.4-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.4-2 - Calculation of Trip Voltages for a Comparator with Hysteresis
Consider the circuit shown. Using thetransistor device parameters given in Table3.1-2 calculate the positive and negativethreshold points if the device lengths are all 1µm and the widths are given as: W1 = W2 = W6= W7 = 10 µm and W3 = W4 = 2 µm. The gateof M1 is tied to ground and the input is thegate of M2. The current, i5 = 20 µA
Solution
To calculate the positive trip point,assume that the input has been negative and isheading positive.
i6 = (W/L)6(W/L)3
i3 = (5/1)(i3) → i3 = i5
1 + [(W/L)6/(W/L)3] = i1 = 20 µA1 + 5 = 3.33 µA
i2 = i5 − i1 = 20 − 3.33 = 16.67 µA → vGS1 =
2i1
β11/2
+VT1 =
2·3.33
(5)1101/2
+0.7 = 0.81V
vGS2 =
2i2
β21/2
+ VT2 =
2·16.67
(5)1101/2
+ 0.7 = 0.946V∴ VTRP+ ≅ vGS2−vGS1 = 0.946−0.810 = 0.136V
VSS
IBias
vo1 vo2
vi1 vi2M1 M2
M3 M4M6 M7
M5M8
VDD
Fig. 8.4-11
Chapter 8 – Section 4 (5/2/04) Page 8.4-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.4-2 - ContinuedDetermining the negative trip point, similar analysis yields
i4 = 3.33 µAi1 = 16.67 µAvGS2 = 0.81VvGS1 = 0.946VVTRP- ≅ vGS2 − vGS1 = 0.81 − 0.946 = −0.136V
PSPICE simulation results of this circuit are shown below.
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
vo2
(volts)
vin (volts) Fig. 8.4-13
Chapter 8 – Section 4 (5/2/04) Page 8.4-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Complete Comparator with Internal Hysteresis
VSS
IBias
vout
vi1 vi2M1 M2
M3 M4M6 M7
M5M8
VDD
Fig. 8.4-14
M8M9
M10 M11
Chapter 8 – Section 4 (5/2/04) Page 8.4-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Schmitt TriggerThe Schmitt trigger is a circuit that has better defined switching points.Consider the following circuit:
How does this circuit work?Assume the input voltage, vin, is low and the output
voltage, vout , is high.
M3, M4 and M5 are on and M1, M2 and M6 are off.When vin is increased from zero, M2 starts to turn on causingM3 to start turning off. Positive feedback causes M2 to turnon further and eventually both M1 and M2 are on and theoutput is at zero.
The upper switching point, VTRP+ is found as follows:
When vin is low, the voltage at the source of M2 (M3) is
vS2 = VDD-VTN3
VTRP+ = vin when M2 turns on given as VTRP+ = VTN2 + vS2
VTRP+ occurs when the input voltage causes the currents in M3 and M1 to be equal.
vin
M1
M2
M3M4
M5
M6
vout
VDD
Fig. 8.4-15
Chapter 8 – Section 4 (5/2/04) Page 8.4-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Schmitt Trigger – ContinuedThus, iD1 = β1( VTRP+ - VTN1)2 = β3( VDD - vS2- VTN3) 2 = iD3
which can be written as, assuming that VTN2 = VTN3,
β1( VTRP+ - VTN1) 2 = β3( VDD – VTRP+)2 ⇒ VTRP+ = VTN1 + β3/β1 VDD
1 + β3/β1
The switching point, VTRP- is found in a similar manner and is:
β5( VDD - VTRP- - VTP5)2 = β6( VTRP-)2 ⇒ VTRP- = β5/β6 (VDD - VTP5)
1 + β5/β6
The bistable characteristic is,
vin
vout
VDD
VDD0 0 VTRP- VTRP+
Fig. 8.4-16
Chapter 8 – Section 4 (5/2/04) Page 8.4-20
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• Open-loop, continuous-time comparators can be improved in the areas of:
- Current sinking and sourcing
- Removal of offset voltages
- Removal of the influence of a noisy signal through hysteresis• Comparators with hysteresis (positive feedback)
- External
- Internal
Chapter 8 – Section 5 (5/2/04) Page 8.5-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 8.5 – DISCRETE-TIME COMPARATORS (LATCHES)ObjectiveThe objective of this section is:1.) Illustrate discrete-time comparators2.) Estimate the propagation delay timeOutline• Switched capacitor comparators• Regenerative comparators (latches)• Summary
Chapter 8 – Section 5 (5/2/04) Page 8.5-2
CMOS Analog Circuit Design © P.E. Allen - 2004
A Differential Switched Capacitor Comparator Avoiding Common Mode Problems
+
-
V1
CCp
φ1
V2
φ1
φ2Vout
+
-VOS
A
+ -VC
+
-V1 - VOS
C Cp
V2
Vout
+
-VOS
A
+ -
+
-+
-VOS
Fig. 8.5-1
A switched capacitor comparator Equivalent circuit when the φ2 switches are closed
φ1 Phase:
The V1 input is sampled and the dc input offset voltage is autozeroed.
VC(φ1) = V1 - VOS and VCp(φ1) = VOSφ2 Phase:
Vout(φ2) =-A
V2C
C+Cp -
(V1-VOS)CC+Cp
+ VOSCpC+Cp
+ AVOS
= -A
(V2-V1) C
C+Cp + VOS
C
C+Cp +
CpC+Cp
+ AVOS = -A(V2-V1) C
C+Cp ≈ A(V1-V2)
if Cp is smaller than C.
Chapter 8 – Section 5 (5/2/04) Page 8.5-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Differential-In, Differential-Out Switched Capacitor Comparator
-
+
vin +
- +
-
-
+
vout
φ2 φ1
φ1
φ2 φ1
φ1
C
C
Fig. 8.5-2
Comments:• Reduces the influence of charge injection• Eliminates even harmonics
Chapter 8 – Section 5 (5/2/04) Page 8.5-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Regenerative ComparatorsRegenerative comparators use positive feedback to accomplish the comparison of twosignals. Latches have a faster switching speed that the previous bistable comparators.NMOS and PMOS latch:
I1 I2
M1 M2
VDD
vo1 vo2
I1 I2
VDD
vo1 vo2
M1 M2
Fig. 8.5-3PMOS latchNMOS latch
How is the input applied to a latch?The inputs are initially applied to the outputs of the latch.
Vo1’ = initial input applied to vo1Vo2’ = initial input applied to vo2
Chapter 8 – Section 5 (5/2/04) Page 8.5-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Step Response of a LatchCircuit:
Ri and Ci are theresistance and capacitanceseen to ground from the i-th transistor.Nodal equations:
gm1Vo2+G1Vo1+sC1
Vo1- Vo1’
s = gm1Vo2+G1Vo1+sC1V o1-C1Vo1’ = 0
gm2Vo1+G2Vo2+sC2
Vo2- Vo2’
s = gm2Vo1+G2Vo2+sC2V o2-C2Vo2’ = 0
Solving for Vo1 and Vo2 gives,
Vo1 = R1C1
sR1C1+1 Vo1’ - gm1R1
sR1C1+1 Vo2 = τ1
sτ1+1 Vo1’ - gm1R1sτ1+1 Vo2
Vo2 = R2C2
sR2C2+1 Vo2’ - gm2R2
sR2C2+1 Vo1 = τ2
sτ2+1 Vo2’ - gm2R2sτ2+1 Vo1
Defining the output, ∆Vo, and input, ∆Vi, as
∆Vo = Vo2-Vo1 and ∆Vi = Vo2’-Vo1’
M2M1
I1 I2
vo2
VDD VDD
vo1
gm1Vo2 R1Vo1's
C1Vo1Vo2
+
-
+
-gm2Vo1 R2
Vo2's
C2Vo2
+
-
Fig. 8.5-4
Chapter 8 – Section 5 (5/2/04) Page 8.5-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Step Response of the Latch - ContinuedSolving for ∆Vo gives,
∆Vo = Vo2-Vo1 = τ
sτ+1 ∆Vi + gmRsτ+1 ∆Vo
or
∆Vo = τ ∆Vi
sτ+(1-gmR) =
τ ∆Vi1-gmRsτ
1-gmR + 1 =
τ’ ∆Visτ’+1
where
τ’ = τ
1-gmR
Taking the inverse Laplace transform gives
∆vo(t) = ∆Vi e-t/τ = ∆Vi e-t(1-gmR) /τ ≈ egmRt/τ∆Vi, if gmR >>1.
Define the latch time constant as
τL = |τ’| ≈ τ
gmR = Cgm
= 0.67WLCox
2K’(W/L)I = 0.67Cox WL3
2K’I
if C ≈ Cgs.∴ ∆Vout(t) = et/τL ∆Vi
Chapter 8 – Section 5 (5/2/04) Page 8.5-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Step Response of a Latch - ContinuedNormalize the output voltage by (VOH-VOL) to get
∆Vout(t)VOH-VOL
= et/τL ∆Vi
VOH-VOL
which is plotted as,
The propagation delay time is tp = τL ln
VOH- VOL
2∆Vi
0
0.2
0.4
0.6
0.8
1
0 1 2 3 4 5tτL
∆VoutVOH-VOL 0.01
0.5 0.4 0.3
0.20.1
0.050.03
0.005
∆Vi
Fig. 8.5-5
VOH-VOL
Chapter 8 – Section 5 (5/2/04) Page 8.5-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 8.5-1 - Time domain characteristics of a latch.
Find the time it takes from the time the latch is enabled until the output voltage,∆Vout, equals VOH-VOL if the W/L of the latch NMOS transistors is 10µm/1µm and thelatch dc current is 10µA when ∆Vi = 0.1(VOH-VOL) and ∆Vi = 0.01(VOH-VOL). Find thepropagation time delay (∆Vout=0.5(VOH-VOL)) for the latch for each of these conditions.
SolutionThe transconductance of the latch transistors is
gm = 2·110·10·10 = 148µS
The output conductance is 0.4µS which gives gmR of 370V/V. Since gmR is greater than1, we can use the above results. Therefore the latch time constant is found as
τL = 0.67CoxWL3
2K’I = 0.67(24x10-4)(10·1)x10-18
2·110x10-6·10x10-6 = 108ns
If we assume that the propagation time delay is the time for the output to reach (VOH-VOL), then for ∆Vi = 0.01(VOH-VOL) that tp = 4.602τL = 497ns and for ∆Vi = 0.1(VOH-VOL)that tp = 2.306τL = 249ns.
If we assume that the propagation time delay is the time when the output is 0.5(VOH-VOL), then using the above results or Fig. 8.5-5 we find for ∆Vi = 0.01(VOH-VOL) that tp =3.91τL = 422ns and for ∆Vi = 0.1(VOH-VOL) that tp = 1.61τL = 174ns.
Chapter 8 – Section 5 (5/2/04) Page 8.5-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Comparator using a Latch with a Built-In Threshold†
How does it operate?1.) Devices in shaded region operate in thetriode region.2.) When the latch/reset goes high, the uppercross-coupled inverter-latch regenerates. Thedrain currents of M5 and M6 are steered toobtain a final state determined by the mismatchbetween the R1 and R2 resistances.
1
R1 = KN
W1L (vin+ - VT) +
W2L (VREF- - VT)
and
1
R2 = KN
W1L (vin- - VT) +
W2L (VREF+ - VT)
3.) The input voltage which causes R1 and R2 to be equal is given byvin(threshold) = (W2/W1)VREF
W2/W1 = 1/4 generates a threshold of ±0.25VREF.Performance → 20Ms/s & 200µW
† T.B. Cho and P.R. Gray, “A 10b, 20Msamples/s, 35mW pipeline A/D Converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, March1995.
VDD
vin+ vin-
vout+ vout-
M1
M3
M5
M7M9
M2
M4
M6
M8
M10
φ1φ1
φ1 φ1
VREF+VREF-
M1M2
Latch/Reset
Latch/Reset
R1 R2
Fig. 8.5-6
Chapter 8 – Section 5 (5/2/04) Page 8.5-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Simple, Low Power Latched Comparator†
VDD
vin+ vin-
vout+ vout-
M1
M3
M5
M7M9
M2
M4
M6
M8
M10
φ1φ1
φ1 φ1
Fig. 8.5-7
Dissipated 50µW when clocked at 2MHz.
† A. Coban, “1.5V, 1mW, 98-dB Delta-Sigma ADC”, Ph.D. dissertation, School of ECE, Georgia Tech, Atlanta, GA 30332-0250.
Chapter 8 – Section 5 (5/2/04) Page 8.5-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Dynamic LatchCircuit:
vout+
VDD
φLatch
φLatch
VREF
vout-vin
M1 M2
M3 M4
M5
M6
M7
M8
Fig. 8.5-8
Input offset voltage distribution:
0 5 10 15-5-10-150
10
20
N
umbe
rof
Sam
ples
Input offset voltage (mV)
L = 1.2µm(0.6µm Process)σ = 5.65
Fig. 8.5-9
Power dissipation/sampling rate = 4.3µW/Ms/s
Chapter 8 – Section 5 (5/2/04) Page 8.5-12
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• Discrete-time comparators must work with clocks• Switched capacitor comparators use op amps to transfer charge and autozero• Regenerative comparators (latches) use positive feedback• The propagation delay of the regenerative comparator is slow at the beginning and
speeds up rapidly as time increases• The highest speed comparators will use a combination of open-loop comparators and
latches
Chapter 8 – Section 6 (5/2/04) Page 8.6-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 8.6 – HIGH-SPEED COMPARATORSObjectiveThe objective of this presentation is:1.) Show how to achieve high-speed comparatorsOutline• Concepts of high-speed comparators• Amplifier-latch comparators• Summary
Chapter 8 – Section 6 (5/2/04) Page 8.6-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Conceptual Illustration of a Cascaded ComparatorHow does a cascaded, high-speed comparator work?
A0sT+1
A0sT+1
A0sT+1
A0sT+1
A0sT+1
A0sT+1
Linearsmallsignal
Linearsmallsignal
Linear& largesignal
Largesignalsmall C
Largesignalbigger C
Largesignalbig C Fig. 8.6-1
Assuming a small overdrive,1.) The initial stage build the driving capability.2.) The latter stages swing rail-to-rail and build the ability to quickly charge anddischarge capacitance.
Chapter 8 – Section 6 (5/2/04) Page 8.6-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Minimizing the Propagation Delay Time in ComparatorsFact:• The input signal is equal to Vin(min) for worst case
• Amplifiers have a step response with a negative argument in the exponential• Latches have a step response with a positive argument in the exponentialResult:Use a cascade of linear amplifier to quickly build up the signal level and apply thisamplified signal level to a latch for quick transition to the full binary output swing.Illustration of a preamplifier andlatch cascade:Minimization of tp:
Q. If the preamplifer consists of nstages of gain A having a single-pole response, what is the value ofn and A that gives minimumpropagation delay time?A. n = 6 and A = 2.62 but this is avery broad minimum and n isusually 3 and A ≈ 6-7 to save area.
t1
VXt2
voutVOH
VOL t
Latch
Preamplifier
Fig. 8.6-2
Chapter 8 – Section 6 (5/2/04) Page 8.6-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Fully Differential, Three-Stage Amplifier and Latch ComparatorCircuit:
+
- +
-
FB
FB
Reset
Cv1
Cv2
+
- +
-
FB
FB
Reset
Cv3
Cv4
+
- +
-
FB
FB
Reset
Cv5
Cv6
Latch
Reset
Reset
C1
C2
vout
+
-
Clock
+vin - Fig. 8.6-3
Comments:• Autozero and reset phase followed by comparison phase• More switches are needed to accomplish the reset and autozero of all preamplifierssimultaneously• Can run as high as 100Msps
Chapter 8 – Section 6 (5/2/04) Page 8.6-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Preamplifier and Latch CircuitsGain:
Av = - gm1gm3 = -
gm2gm4 = -
KN’(W1/L1)Kp’(W3/L3)
Dominant Pole:
|pdominant| = gm3C =
gm4C
where C is the capacitance seen from theoutput nodes to ground.
If (W1/L1)/(W3/L3) = 100 and thebias current is 100µA, then A = -3.85and the bandwidth is 15.9MHz if C =0.5pF.Comments:• If a buffer is used to reduce the output
capacitance, one must take into account the loss of the buffer.• The use of a preamplifier before the latch reduces the latch offset by the gain of the
preamplifier so that the offset is due to the preamplifier only.
VDD
VBias
FB
FB
Reset
LatchEnable
M1
M2
M3 M4
M5 M6
Q
Q
Preamplifier Latch
Fig. 8.6-4
Chapter 8 – Section 6 (5/2/04) Page 8.6-6
CMOS Analog Circuit Design © P.E. Allen - 2004
An Improved PreamplifierCircuit:
VDD
M1 M2
M3 M4M5 M6
M7 M8M10
M9
M11 M12
VBiasN
VBias
VBiasP VBiasP
vout+vout-
vin+ vin-
FB FB
Reset
Fig. 8.6-5
Gain:
Av = - gm1gm3 = -
KN’(W1/L1)I1KP’(W3/L3)I3 = -
KN’(W1/L1)KP’(W3/L3) 1+
I5I3
If I5 = 24I3, the gain is increased by a factor of 5
Chapter 8 – Section 6 (5/2/04) Page 8.6-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Charge Transfer PreamplifierThe preamplifier can be replaced by the charge transfer circuit shown.
vin=VREFVPR
S2
S1CT CO
vout
+
-
VPR
CT CO
vout
=VPR
+
-
vin-VT
vin = VREF+∆V
CT CO
vout =VPR -+
VREF-VT+∆V
CTCO
∆V
Charge transfer amplifier. Precharge phase. Amplification phase.Fig. 8.6-6
vin=VREF
Comments:• Only positive values of voltage will be amplified.• Large offset voltages result as a function of the subthreshold current.
Chapter 8 – Section 6 (5/2/04) Page 8.6-8
CMOS Analog Circuit Design © P.E. Allen - 2004
A CMOS Charge Transfer PreamplifierCircuit:
vin
VDD VDDVPR
CT
CTM1
M2S1
S2
CO
vout
S1
S3
S3
Fig. 8.6-7
Comments:• NMOS and PMOS allow both polarities of input• CMOS switches along with dummy switches reduce the charge injection• Switch S3 prevents the subthreshold current influence• Used as a preamplifier in a comparator with 8-bit resolution at 20Msps and a power
dissipation of less than 5µW
Chapter 8 – Section 6 (5/2/04) Page 8.6-9
CMOS Analog Circuit Design © P.E. Allen - 2004
A High-Speed ComparatorCircuit:
IBias
Preamp
Latch
Self-biaseddiff amp Output
Driver
voutvin
+
vin-
VDD
Fig. 8.6-8
Comments:• Designed to have a tp = 10ns with a 5pF load and a 10mV overdrive
• Not synchronous• Comparator gain is greater than 2000V/V and the quiescent current was 100µA
Chapter 8 – Section 7 (5/2/04) Page 8.7-1
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 8 - SUMMARYTypes of Comparators Presented• High-gain, open-loop• Improved high-gain, open-loop, comparators
HysteresisAutozeroing
• Regenerative comparators• Discrete-time comparatorsPerformance Characterization• Propagation delay time• Binary output swing• Input resolution and/or gain• Input offset voltage• Power dissipationImportant Principles• The speed of the comparator depends on the linear and slewing responses• The dc input offset voltage depends on the matching and is reduced by autozeroing.
Charge injection is the limit of autozeroing• The comparator gain should be large enough for a binary output when vin = Vin(min)• Cascaded comparators, the first stages should large GB and the last stages high SR
Chapter 9 – Switched Capacitor Circuits 5/2/04
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 9 – SWITCHED CAPACITOR CIRCUITSObjectiveThe objective of this presentation is:1.) Introduce the principles of switched capacitor circuits2.) Illustrate the application of switched capacitor circuits to filter designOutlineSection 9.0 - IntroductionSection 9.1 - Switched Capacitor CircuitsSection 9.2 - Switched Capacitor AmplifiersSection 9.3 - Switched Capacitor IntegratorsSection 9.4 - z-domain Models of Two-Phase, Switched Capacitor Circuits, SimulationSection 9.5 - First-order, Switched Capacitor CircuitsSection 9.6 - Second-order, Switched Capacitor CircuitsSection 9.7 - Switched Capacitor FiltersSection 9.8 - Summary
Chapter 9 – Section 1 (5/2/04) Page 9.0-1
CMOS Analog Circuit Design © P.E. Allen - 2004
9.0 - INTRODUCTIONOrganization
Chapter 9
Switched Capaci-tor Circuits
Chapter 6Simple CMOS &BiCMOS OTA's
Chapter 7High Performance
OTA's
Chapter 10D/
Chapter 11AnalogSystems
Chapter 3
CMOSModeling
Chapter 4
CMOS/BiCMOSSubcircuits
Chapter 5CMOS/BiCMOS
Amplifiers
Systems
Complex
Circuits
Devices
Simple
Chapter 2CMOS
Technology
Chapter 1Introduction to An-alog CMOS Design
Chapter 8CMOS/BiCMOS
Comparators
Chapter 10D/A and A/DConverters
Chapter 9 – Section 1 (5/2/04) Page 9.0-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Advantages of Switched Capacitor Circuits1.) Compatibility with CMOS technology2.) Good accuracy of time constants3.) Good voltage linearity4.) Good temperature characteristics
Disadvantages of Switched Capacitor Circuits1.) Experience clock feedthrough2.) Require a nonoverlapping clock3.) Bandwidth of the signal must be less than the clock frequency
Philosophical ViewpointThe implementation of switched capacitors in CMOS technology occurred in the early1970’s and represented a major step in implementing practical analog circuits andsystems in an integrated circuit technology.
Switched capacitor circuits are not new.James Clerk Maxwell used switches and a capacitor to measure the equivalentresistance of a galvanometer in the 1860’s.
Chapter 9 – Section 1 (5/2/04) Page 9.1-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 9.1 – SWITCHED CAPACITOR CIRCUITSRESISTOR EMULATION
Parallel Switched Capacitor Equivalent Resistor
i (t) i (t)2
v (t)1 v (t)2
1 Ri (t) i (t)2
Cv (t)1 v (t)2
1 1 2
v (t)C
Fig 9.1-01Two-Phase, Nonoverlapping Clock:
t
t
1
0
1
00 T/2 T 3T/2 2T
2
1
Fig. 9.1-02
Chapter 9 – Section 1 (5/2/04) Page 9.1-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Equivalent Resistance of a Switched Capacitor CircuitAssume that v1(t) and v2(t) are changing slowly with respect to the clock period.
The average current is,
i1(average) = 1T ⌡⌠
0
T
i1(t)dt = 1T ⌡⌠
0
T/2
i1(t)dt
Charge and current are related as,
i1(t) = dq1(t)
dtSubstituting this in the above gives,
i1(average) = 1T ⌡⌠
0
T/2
dq1(t) = q1(T/2)-q1(0)
T = CvC(T/2)-CvC(0)
T
However, vC(T/2) = v1(T/2) and vC(0) = v2(0). Therefore,
i1(average) = C [v1(T/2)-v2(0)]
T ≈ C [V1-V2]
T
For the continuous time circuit:
i1(average) = V1-V2
R ∴ R ≈ TC
For v1(t) ≈ V1 and v2(t) ≈ V2, the signal frequency must be much less than fc.
i (t) i (t)2
Cv (t)1 v (t)2
1 1 2
v (t)C
Fig. 9.1-03
i (t) i (t)2
v (t)1 v (t)2
1 R
Fig. 9.1-04
Chapter 9 – Section 1 (5/2/04) Page 9.1-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.1-1 - Design of a Parallel Switched Capacitor Resistor EmulationIf the clock frequency of parallel switched capacitor equivalent resistor is 100kHz,
find the value of the capacitor C that will emulate a 1MΩ resistor.Solution
The period of a 100kHz clock waveform is 10µsec. Therefore, using the previousrelationship, we get that
C = TR =
10-5
106 = 10pF
We know from previous considerations that the area required for 10pF capacitor is muchless than for a 1MΩ resistor when implemented in CMOS technology.
Chapter 9 – Section 1 (5/2/04) Page 9.1-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Power Dissipation in the Resistance EmulationIf the switched capacitor
circuit is an equivalentresistance, how is the powerdissipated?
Continuous Time Resistor:
Power = (V1 - V2)2
R
Discrete Time Resistor Emulation:If the switches have an ON resistance of Ron, then power dissipated/clock cycle is,
Power = i1(aver.)(V1-V2) where i1 (aver.) = (V1 -V2)
RonT ⌡⌠0
Te-t/(RonC)dt
∴ Power = (V1-V2)2
TRon ⌡⌠0
Te -t/(RonC)dt =
(V1-V2)2
(T/C) -e -T /(RonC) + 1 ≈ (V1-V2)2
(T/C) if T >> RonC
Thus, if R = T/C, then the power dissipation is identical in the continuous time anddiscrete time realizations.
i (t) i (t)2
v (t)1 v (t)2
1 Ri (t) i (t)2
Cv (t)1 v (t)2
1 1 2
v (t)C
Fig 9.1-01
Chapter 9 – Section 1 (5/2/04) Page 9.1-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Other SC Equivalent Resistance Circuits
Series
i (t)2
v (t)1 v (t)2
i (t)1 1 2
1S 2SC
v (t)C
Series-Parallel
i (t)2
Cv (t)1 v (t)2
i (t)1 1 2
1S 2S1
C2
v (t)C1 v (t)C2 1
1S i (t)2
v (t) v (t)2
i (t)1
1 2
2SC
121S 2S
Bilinear
v (t)C
Fig. 9.1-05
Series-Parallel:The current, i1(t), that flows during both the φ1 and φ2 clocks is:
i1(average) = 1T ⌡⌠
0
T
i1(t)dt = 1T
⌡⌠
0
T/2
i1(t)dt + ⌡⌠
T/2
T
i1(t)dt = q1(T/2)-q1(0)
T + q1(T)-q1(T/2)
T
Therefore, i1(average) can be written as,
i1(average) = C2 [vC2(T/2)-vC2(0)]
T +C1 [vC1(T)-vC1(T/2)]
T
The sequence of switches cause,vC2(0)=V2, vC2(T/2)=V1, vC1(T/2)=0, and vC1(T)= V1-V2.Applying these results gives
i1(average) = C2[V1-V2]
T + C1[V1-V2- 0]
T = (C1+C2)(V1-V2)
T
Equating the average current to the continuous time circuit gives: R = T
C1 + C2
Chapter 9 – Section 1 (5/2/04) Page 9.1-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.1-2 - Design of a Series-Parallel Switched Capacitor Resistor EmulationIf C1 = C2 = C, find the value of C that will emulate a 1MΩ resistor if the clock
frequency is 250kHz.Solution
The period of the clock waveform is 4µsec. Using above relationship we find that Cis given as,
2C = TR =
4x10-6
106 = 4pF
Therefore, C1 = C2 = C = 2pF.
Chapter 9 – Section 1 (5/2/04) Page 9.1-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of the Four Switched Capacitor Resistance CircuitsSwitched CapacitorResistor Emulation
Circuit
Schematic EquivalentResistance
Parallel Cv (t)1 v (t)2
1 2
TC
Series v (t)1 v (t)2
1 2
CTC
Series-ParallelC
v (t)1 v (t)2
1 2
1 C2
TC1 + C2
Bilinear1v (t) v (t)2
1 2
C
2 1
T4C
Chapter 9 – Section 1 (5/2/04) Page 9.1-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Accuracy of Switched Capacitor CircuitsConsider the following continuous time, first-order, lowpasscircuit:
The transfer function of this simple circuit is,
H(jω) = V2(jω)V1(jω) =
1jωR1C2 + 1 =
1jωτ1 + 1
where τ1 = R1C2 is the time constant of the circuit and determines the accuracy.Continuous Time AccuracyLet τ1 = τC. The accuracy of τC can be expressed as,
dτC
τC =
dR1
R1 +
dC2
C2 ⇒ 5% to 20% depending on the size of the components
Discrete Time Accuracy
Let τ1 = τD =
T
C1 C2 =
1
fcC1 C2. The accuracy of τD can be expressed as,
dτD
τD =
dC2
C2 -
dC1
C1 -
dfc
fc ⇒ 0.1% to 1% depending on the size of components
The above is the primary reason for the success of switched capacitor circuits in CMOStechnology.
R1
C21v v2
Fig. 9.1-06
Chapter 9 – Section 1 (5/2/04) Page 9.1-9
CMOS Analog Circuit Design © P.E. Allen - 2004
ANALYSIS OF SWITCHED CAPACITOR CIRCUITSAnalysis Methods for Two-Phase, Nonoverlapping ClocksSampled Data Voltage Waveforms for a Two-phase Clock:
0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5t/T
v(t)v*(t)
1 2 2 2 2 21 1 1 1
v (t)O
v (t)e
0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5t/T
v(t)
1 1 1 1 1
0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5t/T
v(t)
2 2 2 2 2
A sampled-datavoltage waveformfor a two-phaseclock.
A sampled-datavoltage waveformfor the odd-phaseclock.
A sampled-datavoltage waveformfor the even-phaseclock.
Fig. 9.1-065
Chapter 9 – Section 1 (5/2/04) Page 9.1-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Analysis Methods for Two-Phase, Nonoverlapping Clocks - Cont’d
Time-domain Relationships:The previous figure showed that,
v*(t) = vo(t) + ve(t) where the superscript o denotes the odd phase (φ1) and the superscript e denotes the
even phase (φ2).For any given sample point, t = nT/2, the above may be expressed as
v*
nT
2
n=1,2,3,4,5,6,··· = v o
nT
2
n=1,3,5,··· + v e
nT
2
n=2,4,5,···
z-domain Relationships:Consider the one-sided z-transform of a sequence, v(nT), defined as
V(z) = ∞Σ
n = 0 v(nT)z- n = v(0) + v(T)z- 1 + v(2T)z- 2 + ···
for all z for which the series V(z) converges.Now, this equation can be expressed in the z-domain as
V*(z) = Vo(z) + Ve(z) .
The z-domain format for switched capacitor circuits will allow the analysis of transferfunctions.
Chapter 9 – Section 1 (5/2/04) Page 9.1-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Transfer Function Viewpoint of Switched Capacitor Circuits
Input-output voltages of a general switched capacitor circuit in the z-domain.
SwitchedCapacitor
Circuit
1 2
V (z) = V (z) + V (z)io e
i i V (z) = V (z) + V (z)oo e
o o
Fig. 9.1-07
z-domain transfer functions:
H ij (z) = V
j o (z)
Vi i(z)
where i and j can be either e or o. For example, Hoe(z) represents Veo (z)/ V
oi (z) .
Also, a transfer function, H(z) can be defined as
H(z) = Vo(z)Vi(z) =
Veo(z) + V
oo(z)
Vei(z) + V
oi (z)
.
Chapter 9 – Section 1 (5/2/04) Page 9.1-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Approach for Analyzing Switched Capacitor Circuits1.) Analyze the circuit in the time-domain during a selected phase period.2.) The resulting equations are based on q = Cv.3.) Analyze the following phase period carrying over the initial conditions from the
previous analysis.4.) Identify the time-domain equation that relates the desired voltage variables.5.) Convert this equation to the z-domain.6.) Solve for the desired z-domain transfer function.
7.) Replace z by ejωT and examine the frequency response.
Chapter 9 – Section 1 (5/2/04) Page 9.1-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.1-3 - Analysis of a Switched Capacitor, First-order, Low pass FilterUse the above approach to find the z-domain transfer function of the first-order, low
pass switched capacitor circuit shown below. This circuit was developed by replacingthe resistor, R1, of the previous circuit with the parallel switched capacitor resistor circuit.The timing of the clocks is also shown. This timing is arbitrary and is used to assist theanalysis and does not change the result.
Switched capacitor, low pass filter.
2Cv 1 v 21
1 2
C
Clock phasing for this example.
tTn-1n-3
2 n-12 n+ 1
2n
1 12 2 2
n+1
Fig. 9.1-08
Solutionφ1: (n-1)T< t < (n-0.5)T
Equivalent circuit:
C2C1v (n-1)T1o v (n- )T3
2e2 v (n-1)To
2
Equivalent circuit.
C1
C2
v (n-1)T1o v (n- )T3
2e2 v (n-1)To
2
Simplified equivalent circuit.Fig. 9.1-09
The voltage at the output (across C2) is vo2(n-1)T = ve
2 (n-3/2)T (1)
Chapter 9 – Section 1 (5/2/04) Page 9.1-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.1-3 - Continuedφ2: (n-0.5)T< t < nT
Equivalent circuit:
C1
C2v (n-1/2)T1
e v (n- )T12
e2
v (n-1)To2v (n-1)To
1
C1
Fig. 9.1-10
The output of this circuit can be expressed as the superposition of two voltagesources, vo
1 (n-1)T and vo2 (n-1)T given as
ve2 (n-1/2)T =
C1
C1+C2 vo
1 (n-1)T +
C2
C1+C2 vo
2 (n-1)T. (2)
If we advance Eq. (1) by one full period, T, it can be rewritten as
vo2(n)T = ve
2 (n-1/2)T. (3)
Substituting, Eq. (3) into Eq. (2) yields the desired result given as
vo2 (nT) =
C1
C1+C2 vo
1 (n-1)T +
C2
C1+C2 vo
2 (n-1)T. (4)
Chapter 9 – Section 1 (5/2/04) Page 9.1-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.1-3 - Continuedz-domain Analysis:
The next step is to write the z-domain equivalent expression for Eq. (4). This can bedone term by term using the sequence shifting property given as
v(n-n1)T ↔ z-n1V(z) . (5)The result is
Vo2(z) =
C1
C1+C2 z
-1 Vo
1(z) +
C2
C1+C2 z
-1 Vo
2(z). (6)
Finally, solving for Vo2(z)/Vo
1(z) gives the desired z-domain transfer function for theswitched capacitor circuit of this example as
Hoo(z) = Vo
2(z)
Vo1(z) =
z-1
C1
C1+C2
1 - z-1
C2
C1+C2
= z-1
1 + α - αz-1 , where α = C2
C1 . (7)
Chapter 9 – Section 1 (5/2/04) Page 9.1-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Discrete-Frequency Domain AnalysisRelationship between the continuous and discrete frequency domains:
z = e jωT
Illustration:j
= ∞
= 0
= -∞
Continuoustime frequency
response
Continuous Frequency Domain
Imaginary Axis
RealAxis
+j1
-j1
+1-1
r = 1
Discretetime frequency
response
= -∞
= ∞ = 0
Discrete Frequency DomainFig. 9.1-11
Chapter 9 – Section 1 (5/2/04) Page 9.1-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.1-4 - Frequency Response of Example 9.1-3Use the results of the previous example to find the magnitude and phase of the
discrete time frequency response for the switched capacitor circuit of Example 3.Solution
The first step is to replace z in Hoo(z) of Ex. 3 by e jωT. The result is given below as
Hoo ejωΤ =
e-jωT
1+α-α e-jωT = 1
(1+α)ejωT- α = 1
(1+α)cos(ωT)- α + j(1+α)sin(ωT) (1)
where we have used Eulers formula to replace e jωT by cos(ωT)+jsin(ωT). The magnitudeof Eq. (1) is found by taking the square root of the square of the real and imaginarycomponents of the denominator to give
Hoo = 1
(1+α)2cos2(ωT) - 2α(1+α)cos(ωT) + α2 + (1+α)2sin2(ωT)
= 1
(1+α)2[cos2(ωT)+sin2(ωT)]+α2-2α(1+α)cos(ωT)
= 1
1+2α+α2 -2α(1+α)cos(ωT) = 1
1+2α(1+α)(1-cos(ωT)) . (2)
The phase shift of Eq. (1) is expressed as
Arg Hoo = - tan-1
(1+α)sin(ωT)
(1+α)cos(ωT)-α = - tan-1
sin(ωT)
cos(ωT) - α
1+α(3)
Chapter 9 – Section 1 (5/2/04) Page 9.1-18
CMOS Analog Circuit Design © P.E. Allen - 2004
The Oversampling AssumptionThe oversampling assumption is simply to assume that fsignal << fclock = fc.
This means that,
fsignal = f << 1T ⇒ 2πf = ω <<
2πT ⇒ ωT << 2π.
The importance of the oversampling assumption is that is permits the design of switchedcapacitor circuits that approximates the continuous time circuit until the signal frequencybegins to approach the clock frequency.
Chapter 9 – Section 1 (5/2/04) Page 9.1-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.1-5 - Design of Switched Capacitor Circuit and Resulting FrequencyResponse
Design the first-order, low pass, switched capacitor circuit of Ex. 3 to have a -3dBfrequency at 1kHz. Assume that the clock frequency is 20kHz Plot the frequencyresponse for the resulting discrete time circuit and compare with a first-order, low pass,continuous time filter.Solution
If we assume that ωT is less than unity, then cos(ωT) approaches 1 and sin(ωT)approaches ωT. Substituting these approximations into the magnitude response of Eq. (2)of Ex. 4 results in
Hoo(ejωT) ≈ 1
(1+α) -α + j(1+α)ωΤ = 1
1 + j(1+α)ωT . (1)
Comparing this equation to the simple, first-order, low pass continuous time circuitresults in the following relationship which permits the design of the circuit parameter α.
ωτ1 = (1+α)ωT (2)Solving for α gives
α = τ1
T - 1 = fcτ1 - 1 = fc
ω-3dB - 1 =
ωc
2πω-3dB - 1 . (3)
Using the values given, we see that α = (20/6.28)-1 =2.1831. Therefore, C2 = 2.1831C1.
Chapter 9 – Section 1 (5/2/04) Page 9.1-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.1-5 - Continued
Frequency Response of the First-order, Switched Capacitor, Low Pass Circuit:
0
0.2
0.4
0.6
0.8
1
0 0.2 0.4 0.6 0.8 1
Mag
nitu
de
0.707
|H(jω)|
|Hoo(ejωT)|
ω = 1/τ1
ω/ωc
-100
-50
0
50
100
0 0.2 0.4 0.6 0.8 1
Phas
e Sh
ift (
Deg
rees
)
ω/ωc
Arg[Hoo(ejωT)]
Arg[H(jω)]
ω = 1/τ1
Fig. 9.1-12
Better results would be obtained if fc > 20kHz.
Chapter 9 – Section 1 (5/2/04) Page 9.1-21
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• Resistance emulation is the replacement of continuous time resistors with switched
capacitor approximations
- Parallel switched capacitor resistor emulation
- Series switched capacitor resistor emulation
- Series-parallel switched capacitor resistor emulation
- Bilinear switched capacitor resistor emulation• Time constant accuracy of switched capacitor circuits is proportional to the
capacitance ratio and the clock frequency• Analysis of switched capacitor circuits includes the following steps:
1.) Analyze the circuit in the time-domain during a selected phase period.2.) The resulting equations are based on q = Cv.3.) Analyze the following phase period carrying over the initial conditions from the
previous analysis.4.) Identify the time-domain equation that relates the desired voltage variables.5.) Convert this equation to the z-domain.6.) Solve for the desired z-domain transfer function.
7.) Replace z by ejωT and examine the frequency response.
Chapter 9 – Section 2 (5/2/04) Page 9.2-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 9.2 – SWITCHED CAPACITOR AMPLIFIERSCONTINUOUS TIME AMPLIFIERS
Inverting and Noninverting Amplifiers
+-
R1 R2 vOUT
vIN +-
R1 R2 vOUTvIN
Fig. 9.2-01
Gain and GB = ∞:VoutVin =
R1+R2R1
VoutVin = -
R2 R1
Gain ≠ ∞, GB = ∞:
Vout(s)Vin(s) =
R1+R2
R1
Avd(0)R1R1+R2
1 + Avd(0)R1R1+R2
Vout(s)Vin(s) = -
R2
R1
R1Avd(0)R1+R2
1 + Avd(0)R1R1+R2
Gain ≠ ∞, GB ≠ ∞:
Vout(s)Vin(s) =
R1+R2
R1
GB·R1R1+R2
s + GB·R1R1+R2
=
R1+R2
R1 ωH
s+ωH Vout(s)Vin(s) =
- R2R1
GB·R1R1+R2
s + GB·R1R1+R2
=
- R2R1
ωHs+ωH
Chapter 9 – Section 2 (5/2/04) Page 9.2-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.2-1- Accuracy Limitation of Voltage Amplifiers due to a Finite VoltageGain
Assume that the noninverting and inverting voltage amplifiers have been designed fora voltage gain of +10 and -10. If Avd(0) is 1000, find the actual voltage gains for eachamplifier.Solution
For the noninverting amplifier, the ratio of R2/R1 is 9.
Avd(0)R1/(R1+R2) = 10001+9 = 100.
∴ VoutVin
= 10
100
101 = 9.901 rather than 10.
For the inverting amplifier, the ratio of R2/R1 is 10.Avd(0)R1R1+R2
= 10001+10 = 90.909
∴ VoutVin
= -(10)
90.909
1+90.909 = - 9.891 rather than -10.
Chapter 9 – Section 2 (5/2/04) Page 9.2-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.2-2 - -3dB Frequency of Voltage Amplifiers due to Finite Unity-Gainbandwidth
Assume that the noninverting and inverting voltage amplifiers have been designed fora voltage gain of +1 and -1. If the unity-gainbandwidth, GB, of the op amps are2πMrads/sec, find the upper -3dB frequency for each amplifier.Solution
In both cases, the upper -3dB frequency is given by
ωH = GB·R1R1+R2
For the noninverting amplifier with an ideal gain of +1, the value of R2/R1 is zero.∴ ωH = GB = 2π Mrads/sec (1MHz)
For the inverting amplifier with an ideal gain of -1, the value of R2/R1 is one.
∴ ωH = GB·11+1 =
GB2 = π Mrads/sec (500kHz)
Chapter 9 – Section 2 (5/2/04) Page 9.2-4
CMOS Analog Circuit Design © P.E. Allen - 2004
CHARGE AMPLIFIERSNoninverting and Inverting Charge Amplifiers
+
-
vIN
OUTvC1 C2
Noninverting Charge Amplifier
+
-
vINOUTv
Inverting Charge Amplifier
C1 C2
Gain and GB = ∞:VoutVin
= C1+C2
C2
VoutVin
= - C1C2
Gain ≠ ∞, GB = ∞:
Vout
Vin =
C1+C2
C2
Avd(0)C2C1+C2
1 + Avd(0)C2C1+C2
Vout
Vin =
-C1
C2
Avd(0)C2C1+C2
1 + Avd(0)C2C1+C2
Gain ≠ ∞, GB ≠ ∞:
Vout
Vin =
C1+C2
C2
GB·C2C1+C2
s + GB·C2C1+C2
Vout
Vin =
-C1
C2
GB·C2C1+C2
s + GB·C2C1+C2
Chapter 9 – Section 2 (5/2/04) Page 9.2-5
CMOS Analog Circuit Design © P.E. Allen - 2004
SWITCHED CAPACITOR AMPLIFIERSParallel Switched Capacitor Amplifier
1 2
+
-
1 2
voutinv
C1
2C
Inverting Switched Capacitor Amplifier
+-
vC1
vC2
+-
1 2
+
-
1
2C
C1
voutinv
Modification to prevent open-loop operation
vC1
vC2
+-
+-
Analysis:Find the even-odd and the even-even z-domain
transfer function for the above switched capacitorinverting amplifier.φ1: (n -1)T < t < (n -0.5)T
v oC1(n -1)T = v o
in (n -1)T
and
v oC2(n -1)T = 0
Clock phasing for this example.
tTn-1n-3
2 n-12 n+1
2n
1 12 2 2
n+1
Chapter 9 – Section 2 (5/2/04) Page 9.2-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Parallel Switched Capacitor Amplifier- Continuedφ2: (n -0.5)T < t < nT
Equivalent circuit:
From the simplifiedequivalent circuit wewrite,
v e out (n-1/2)T = -
C1
C2 v o
in (n-1)T
Converting to the z-domain gives,
z -1/2 V e out (z) = -
C1
C2 z -1 Vo
in (z)
Multiplying by z1/2 gives,
V e out (z) = -
C1
C2 z -1/ 2 Vo
in (z)
Solving for the even-odd transfer function, Hoe (z), gives, Hoe
(z) = V e
out (z)
Vo in (z)
= -
C1
C2 z -1/ 2
inv o
+
-2CC1
Simplified equivalent circuit.
vC1 vC2
+
-
+-+-
(n-1)T
= 0 = 0 vout (n-1/2)Te
Equivalent circuit at the moment φ2 closes.
+
-C1 inv
vC2
+-
(n-1)T
= 0
o
+-
2
t = 0 vout (n-1/2)Te
Chapter 9 – Section 2 (5/2/04) Page 9.2-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Parallel Switched Capacitor Amplifier- Continued
Solving for the even-even transfer function, Hee (z).
Assume that the applied input signal, voin (n-1)T, was unchanged during the previous
φ2 phase period(from t = (n-3/2)T to t = (n-1)T), then
voin (n-1)T = v
ein (n-3/2)T
which gives
Voin(z) = z -1/2 V
ein(z) .
Substituting this relationship into Hoe(z) gives
Ve
out(z) = -
C1
C2 z -1 V
ein(z)
or
Hee (z) = V
eout(z)
Vein(z)
= -
C1
C2 z -1
Chapter 9 – Section 2 (5/2/04) Page 9.2-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Response of Switched Capacitor AmplifiersReplace z by e jωT.
Hoe (e jωT) =
Ve
out( e jωT)
Ve
out( e jωT) = -
C1
C2 e -jωT/2
and
Hee (e jωT) =
Ve
out(e jωT)
Vo
out( e jωT) = -
C1
C2 e -jωT
If C1/C2 = R2/R1, then the magnitude response is identical to inverting unity gain amp.
However, the phase shift of Hoe(e jωT) is
Arg[Hoe(e jωT)] = ±180° - ωT/2
and the phase shift of Hee(e jωT) is
Arg[Hee(e jωT)] = ±180° - ωT.Comments:• The phase shift of the SC inverting amplifier has an excess linear phase delay.• When the frequency is equal to 0.5fc, this delay is 90°.
• One must be careful when using switched capacitor circuits in a feedback loopbecause of the excess phase delay.
Chapter 9 – Section 2 (5/2/04) Page 9.2-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Positive and Negative Transresistance Equivalent CircuitsTransresistance circuits are two-port networks where the voltage across one port
controls the current flowing between the ports. Typically, one of the ports is at zeropotential (virtual ground).Circuits:
Analysis (Negative transresistance realization):
RT = v1(t)i2(t) =
v1
i2(average)
If we assume v1(t) is ≈ constant over one period of the clock, then we can write
i2(average) = 1T ⌡⌠
T/2
T
i2(t)dt = q2(T) - q2(T/2)
T = CvC(T) - CvC(T/2)
T = -Cv1
T
Substituting this expression into the one above shows that RT = -T/C
Similarly, it can be shown that the positive transresistance is T/C.These circuits are insensitive to the parasitic capacitances shown as dotted capacitors.
Positive Transresistance Realization.
1
2 2
1C
vC(t)
v1(t)
i1(t) i2(t)
CP CP
Negative Transresistance Realization.
1
2
2
1C
vC(t)
v1(t)
i1(t) i2(t)
CP CP
Chapter 9 – Section 2 (5/2/04) Page 9.2-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Noninverting Stray Insensitive Switched Capacitor AmplifierAnalysis:φ1: (n -1)T < t < (n -0.5)T
The voltages across each capacitor can be written as
vo
C1(n -1)T = voin(n -1)T
and
vo
C2(n -1)T = vo
out(n -1)T = 0 .φ2: (n -0.5)T < t < nT
The voltage across C2 is
ve
out(n -1/2)T =
C1
C2 v
oin(n -1)T
Ve
out(z) =
C1
C2 z -1/2 V
oin(z) → Hoe(z) =
C1
C2 z-1/2
If the applied input signal, voin(n -1)T, was unchanged during the previous φ2 phase, then,
Ve
out(z) =
C1
C2 z-1 V
ein(z) → Hee(z) =
C1
C2 z-1
Comments:• Excess phase of H oe(e jωT) is -ωT/2 and for H ee(e jωT) is -ωT
Clock phasing for this example.
tTn-1n-3
2 n-12 n+1
2n
1 12 2 2
n+1
Noninverting Switched Capacitor Voltage Amplifier.
1 2
+
-
1
2C
voutinv vC2+-
121C
vC1(t)
Chapter 9 – Section 2 (5/2/04) Page 9.2-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Inverting Stray Insensitive Switched Capacitor AmplifierAnalysis:φ1: (n -1)T < t < (n -0.5)T
The voltages across each capacitor canbe written as
vo
C1(n -1)T = 0and
vo
C2(n -1)T = vo
out(n -1)T = 0 .φ2: (n -0.5)T < t < nT
The voltage across C2 is
ve
out(n -1/2)T = -
C1
C2 v
ein(n -1/2)T
Ve
out(z) = -
C1
C2V
ein(z) → H˚oe(z) = -
C1
C2
Comments: • The inverting switched capacitor amplifier has no excess phase delay. • There is no transfer of charge during φ1.
Inverting Switched Capacitor Voltage Amplifier.
1
2
+
-
1
2C
voutinv vC2+-
1
2
vC1(t)vC1(t)
1C
vC1(t)
Chapter 9 – Section 2 (5/2/04) Page 9.2-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.2-3 - Design of a Switched Capacitor Summing AmplifierDesign a switched capacitor summing
amplifier using the stray insensitive transresist-ance circuits to gives the output voltage duringthe φ2 phase period that is equal to 10v1 - 5v2,where v1 and v2 are held constant during a φ2-φ1period and then resampled for the next period.Solution
A possible solution is shown. Consideringeach of the inputs separately, we can write that
v eo1(n-1/2)T = 10vo
1(n-1)T (1)and
v eo2(n-1/2)T = -5ve
2(n-1/2)T . (2)
Because vo1(n-1)T = ve
1(n-3/2)T, Eq. (1) can be rewritten as
v eo1(n-1/2)T = 10ve
1(n-3/2)T . (3)
Combining Eqs. (2) and (3) gives
veo(n-1/2)T = v e
o1(n-1/2)T + v eo2(n-1/2)T = 10ve
1(n-3/2)T - 5ve2(n-1/2)T . (4)
orVe
o(z) = 10z-1Ve1(z) - 5Ve
2(z) . (5)
1 2
+
-
1
vo12
v1
1
2
1
2v2
C
10C
5C
Chapter 9 – Section 2 (5/2/04) Page 9.2-13
CMOS Analog Circuit Design © P.E. Allen - 2004
NONIDEALITIES OF SWITCHED CAPACITOR CIRCUITSSwitchesCovered in Chapter 4.CapacitorsCovered in Chapter 2.
Chapter 9 – Section 2 (5/2/04) Page 9.2-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.2-4 – Influence of Clock Feedthrough on a Noninverting SwitchedCapacitor AmplifierA noninverting, switchedcapacitor voltage amplifier isshown. The switch overlapcapacitors, COL are assumed tobe 100fF each and C1 = C2 =1pF. If the switches have a W= 1µm and L = 1µm and thenonoverlapping clock of 0 to 5Vamplitude has a rate of rise andfall of ±0.5x109 volts/second,find the actual value of theoutput voltage when a 1Vsignal is applied to the input.Solution
We will break this example into three time sequences. The first will be when φ1 turnsoff (φ1off), the second when φ2 turns on (φ2on), and the third when φ2 turns off (φ2off).
2
2C
voutinv vC2+-vC(t)
2
COL COL
1
COL
COL
1COL COL
COL
COL
1COL COL
M1
M3 M2
M4
M5
1C
+-
Fig. 9.2-9
Chapter 9 – Section 2 (5/2/04) Page 9.2-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.2-4 – Continuedφ1 turning off
M1:The value of VHT is given as
VHT = 5V-1V-0.7V = 3.3VTherefore, the value of βVHT2/2CL is found as
βVHT2
2CL =
110x10-6(3.3)2
2x10-12 = 0.599x109V/sec.
This corresponds to the slow transition mode. Using the previous model gives
Verror =
220x10-18+(0.5)(24.7)(10-16)
10-12 π109·10-12
2·110x10-6 - 220x10-18
10-12 (1+1.4+0)
= (0.001455)(3.779) - 220x10-6(2.4) = 5.498mV-0.528mV = 4.97mVM2:
The value of VHT for M2 is given asVHT = 5V-0V-0.7V = 4.3V
The value of βVHT2/2CL is found asβVHT2
2CL =
110x10-6(4.3)2
2x10-12 = 1.017x109V/sec.
2
2C
voutinv vC2+-vC(t)
2
COL COL
1
COL
COL
1COL COL
COL
COL
1COL COL
M1
M3 M2
M4
M5
1C
+-
Fig. 9.2-9
Chapter 9 – Section 2 (5/2/04) Page 9.2-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.2-4 – ContinuedTherefore, M2 is also in the slow transition mode. The error voltage is found as
Verror =
220x10-18+(0.5)(24.7)(10-16)
10-12 π109·10-12
2·110x10-6 - 220x10-18
10-12 (0+1.4+0)
= (0.001455)(3.779) - 220x10-6(1.4) = 5.498mV-0.308mV = 5.19mVTherefore, the net error on the C1 capacitor at the end of the φ1 phase is
vC1(φ1off) = 1.0 - 0.00497 + 0.00519 = 1.00022V
We see that the influence of vin ≠ 0V is to cause thefeedthrough from M1 and M2 not to cancelcompletely.M5:
We must also consider the influence of M5 turningoff. In order to use the previous model for M5, we willassume that feedthrough of M5 via a virtual ground is valid for the previous model givenfor feedthrough. Based on this assumption, M5 will have the same feedthrough as M2which is 5.19mV. This voltage error will left on C2 at the end of the φ1 and is
vC2(φ1off) = 0.00519V.
2
2C
voutinv vC2+-vC(t)
2
COL COL
1
COL
COL
1COL COL
COL
COL
1COL COL
M1
M3 M2
M4
M5
1C
+-
Fig. 9.2-9
Chapter 9 – Section 2 (5/2/04) Page 9.2-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.2-4 – Continuedφ2 turning on
During the turn-on part of φ2, M3 and M4 willfeedthrough onto C1 and C2. However, it is easy toshow that the influence of M3 and M4 will canceleach other for C1. Therefore, we need only considerthe feedthrough of M4 and its influence on C2.Interestingly enough, the feedthrough of M4 onto C2is exactly equal and opposite to the previous feedthrough by M5. As a result, the value ofvoltage on C2 after φ2 has stabilized is
vC2(φ2on) = 0.00519V-0.00519V + C1C2
vc1(φ1off) = 1.00022V
φ2 turning off
Finally, as switch M4 turns off, there will be feedthrough onto C2. Since, M4 has oneof its terminals at 0V, the feedthrough is the same as before and is 5.19mV. The finalvoltage across C2, and therefore the output voltage vout, is given as
vout(φ2off) = vC2(φ2off) = 1.00022V + 0.00519V = 1.00541V
It is interesting to note that the last feedthrough has the most influence.
2
2C
voutinv vC2+-vC(t)
2
COL COL
1
COL
COL
1COL COL
COL
COL
1COL COL
M1
M3 M2
M4
M5
1C
+-
Fig. 9.2-9
Chapter 9 – Section 2 (5/2/04) Page 9.2-18
CMOS Analog Circuit Design © P.E. Allen - 2004
NONIDEAL OP AMPS - FINITE GAINFinite Amplifier GainConsider the noninverting switched capacitor amplifier during φ2:
inv
+
-
2CC1
+
-
(n-1)T
vout (n-1/2)Te
ovout (n-1/2)T
e
Avd(0)+- Op amp with finite
value of Avd(0)Fig. 9.2-11
The output during φ2 can be written as,
ve
out(n -1/2)T =
C1
C2 v
oin(n -1)T +
C1+C2
C2 v
eout(n -1/2)T
Avd(0)
Converting this to the z-domain and solving for the Hoe(z) transfer function gives
Hoe(z) = V
eout(z)
Voin(z)
=
C1
C2 z-1/2
1
1 - C1 + C2
Avd(0)C2
.
Comments:• The phase response is unaffected by the finite gain• A gain of 1000 gives a magnitude of 0.998 rather than 1.0.
Chapter 9 – Section 2 (5/2/04) Page 9.2-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Nonideal Op Amps - Finite Bandwidth and Slew RateFinite GB:
• In general the analysis is complicated. (We will provide more detail for integrators.)• The clock period, T, should be equal to or less that 10/GB.• The settling time of the op amp must be less that T/2.
Slew Rate:• The slew rate of the op amp should be large enough so that the op amp can make a
full swing within T/2.
Chapter 9 – Section 2 (5/2/04) Page 9.2-20
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• Continuous time amplifiers are influenced by the gain and gainbandwidth of the op amp• Charge amplifiers are also influenced by the gain and the gainbandwidth of the op amp• Switched capacitor amplifiers replace the resistors of the continuous time amplifier with
switched capacitor equivalents• The transresistor SC amplifiers can be inverting and noninverting with the positive
input terminal of the op amp on ground• The nonidealities of the SC amplifier include:
- Switches
- Capacitors
- Op amp finite gain
- Op amp finite GB
Chapter 9 – Section 3 (5/2/04) Page 9.3-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 9.3 – SWITCHED CAPACITOR INTEGRATORSContinuous Time Integrators
-R1 C2 R R VoutVin
(a.)
+
-
+
-
Inverter
(b.)
R1 C2Vin Vout
+
-
(a.) Noninverting and (b.) inverting continuous time integrators.Ideal Performance:
Noninverting- Inverting-Vout(jω)Vin(jω) =
1jω R 1C2
= ωI
jω = -jωIω
Vout(jω)Vin(jω) =
-1jω R 1C2
= -ωI
jω = jωIω
Frequency Response:
90°
0°
Arg[Vout(jω)/Vin(jω)]
ωI log10ω
|Vout(jω)/Vin(jω)|
ωIωIωI100 10
10ωI 100ωI
log10ω
40 dB
20 dB
0 dB
-20 dB
-40 dB
(a.) (b.)
Chapter 9 – Section 3 (5/2/04) Page 9.3-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Continuous Time Integrators - Nonideal PerformanceFinite Gain:
Vout
Vin = -
1
sR1C2
Avd(s) sR1C2
sR1C2 + 1
1 + Avd(s) sR1C2
sR1C2+1
=
- ωI
s
Avd(s) (s/ωΙ) (s/ωΙ) + 1
1 + Avd(s) (s/ωΙ) (s/ωΙ) + 1
where Avd(s) = Avd(0)ωa
s+ωa =
GBs+ωa
≈ GBs
Case 1: s → 0 ⇒ Avd(s) = Avd(0) ⇒Vout
Vin ≈ - Avd(0) (1)
Case 2: s → ∞ ⇒ Avd(s) = GBs ⇒
Vout
Vin ≈ -
GB
s
ωI
s (2)
Case 3: 0 < s < ∞ ⇒ Avd(s) = ∞ ⇒ Vout
Vin ≈ -
ωI
s (3)
90°
0°
Arg[Vout(jω)/Vin(jω)]
log10ωωI
Avd(0)GB
180°
45°
135°
ωI10Avd(0) 10ωI
Avd(0)GB10
10GB
|Vout(jω)/Vin(jω)|
ωI log10ω0 dB GB
Avd(0) dBEq. (3)
Eq. (2)
Eq. (1)
ωIAvd(0)
ωx1 =
ωx2 =
Chapter 9 – Section 3 (5/2/04) Page 9.3-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.3-1 - Frequency Range over which the Continuous Time Integrator isIdeal
Find the range of frequencies over which the continuous time integratorapproximates ideal behavior if Avd(0) and GB of the op amp are 1000 and 1MHz,respectively. Assume that ωI is 2000π radians/sec.Solution
The “idealness” of an integrator is determined by how close the phase shift is to±90° (+90° for an inverting integrator and -90° for a noninverting integrator).The actual phase shift in the asymptotic plot of the integrator is approximately 6° above90° at the frequency 10ωI/Avd(0) and approximately 6° below 90° at GB /10.Assume for this example that a ±6° tolerance is satisfactory. The frequency range can befound by evaluating 10ωI/Avd(0) and GB/10.Therefore the range over which the integrator approximates ideal behavior is from 10Hzto 100kHz. This range will decrease as the phase tolerance is decreased.
Chapter 9 – Section 3 (5/2/04) Page 9.3-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Noninverting Switched Capacitor IntegratorAnalysis:φ1: (n -1)T < t < (n -0.5)T
The voltage across each capacitor is
voc1(n-1)T = v
oin(n-1)T
and
voc2(n-1)T = v
oout(n-1)T .
φ2: (n -0.5)T < t < n T
Equivalent circuit:
oinv
Simplified equivalent circuit.
2C
C1
vC1
+
++
(n-1)T
= 0
vC2 = 0
vout (n-1/2)Te
+--
-vout(n-1)To
-
+
-
Equivalent circuit at the moment the φ2 switches close.
C1 inv+
(n-1)T
vC2 =
o
vout(n-1)To
+2
t = 0 vout (n-1/2)Te
--
+
-
t = 02
2C
We can write that, ve
out(n -1/2)T =
C1
C2 v
oin(n -1)T + v
oout(n -1)T
Noninverting, stray insensitive integrator.
1 2
2C
voutinv vC2+-
12
1C
vC1(t)
+
-+ -
S1
S2 S3
S4
Chapter 9 – Section 3 (5/2/04) Page 9.3-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Noninverting Switched Capacitor Integrator - Continuedφ1: nT < t < (n + 0.5)T
If we advance one more phase period, i.e. t = (n)T to t = (n+1/2)T, we see that thevoltage at the output is unchanged. Thus, we may write
vo
out(n)T = ve
out(n-1/2)T .Substituting this relationship into the previous gives the desired time relationshipexpressed as
vo
out(n)T =
C1
C2 v
oin(n -1)T + v
oout(n -1)T .
Transferring this equation to the z-domain gives,
Vo
out(z) =
C1
C2 z-1V
oin(z) + z-1V
oout(z) → Hoo(z) =
Vo
out(z) V
oin(z)
=
C1
C2
z-1
1-z-1 =
C1
C2
1z-1
Replacing z by ejω Τ gives,
Hoo(e jωΤ) = V
oout( e jωΤ)
Voin( ejωΤ)
=
C1
C2
1 e jωΤ -1 =
C1
C2
e-jωΤ/2
e jωΤ/2 - e-jωΤ/2 Replacing ejωΤ/2 - e-jωΤ/2 by its equivalent trigonometric identity, the above becomes
Hoo(e jωΤ) = V
oout(e jωΤ)
Voin( e jωΤ)
=
C1
C2
e-jωΤ/2
j2 sin(ωT/2)
ωT
ωT =
C1
jωTC2
ωT/2
sin(ωT/2) e-jωΤ/2
Hoo(ejωT) = (Ideal)x(Magnitude error)x(Phase error) where ωI = C1/TC2 ⇒ Ideal = ωI/jω
Chapter 9 – Section 3 (5/2/04) Page 9.3-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.3-2 - Comparison of a Continuous Time and Switched CapacitorIntegrator
Assume that ωI is equal to 0.1ωc and plot the magnitude and phase response of thenoninverting continuous time and switched capacitor integrator from 0 to ωc.Solution
Letting ωI be 0.1ωc gives
H(jω) = 1
10jω/ωc and Hoo(e jωΤ) =
1
10jω/ωc
πω/ωc
sin(πω/ωc) e-jπω/ωc
Plots:
0
1
2
3
4
5
0 0.2 0.4 0.6 0.8 1
Magnitude
|Hoo(ejωT)|
|H(jω)|ω I
ω/ω c
-300
-250
-200
-150
-100
-50
0
0 0.2 0.4 0.6 0.8 1
Phase Shift (Degrees)
Arg[Hoo(ejωT)]
Arg[H(jω)]
ω I ω/ω c
Chapter 9 – Section 3 (5/2/04) Page 9.3-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Inverting Switched Capacitor IntegratorAnalysis:φ1: (n -1)T < t < (n -0.5)T
The voltage across each capacitor is
voc1(n -1)T = 0
and
voc2(n -1)T = v
oout(n -1)T = v
eout(n -
32)T.
φ2: (n -0.5)T < t < n T
Equivalent circuit:
einv
Simplified equivalent circuit.
2C
C1
vC1
++
+
(n-1/2)T
= 0
vC2 = 0
vout (n-1/2)Te
+--
-vout(n-3/2)Te
- +
-
Equivalent circuit at the moment the φ2 switches close.
vC2 =vout(n-3/2)Te
+2
t = 0 vout (n-1/2)Te
-
+
-
C1
vC1+ +
(n-1/2)T= 0
-
-
einv
2
t = 0
2C
Now we can write that,
ve
out(n-1/2)T = ve
out(n-3/2)T -
C1
C2 v
ein(n-1/2)T . (22)
Inverting, stray insensitive integrator.
1
2
2C
voutinv vC2+-
1
2
1C
vC1(t)
+
-S1
S2 S3
S4
Chapter 9 – Section 3 (5/2/04) Page 9.3-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Inverting Switched Capacitor Integrator - ContinuedExpressing the previous equation in terms of the z-domain equivalent gives,
Ve
out(z) = z-1Ve
out(z) -
C1
C2 V
ein(z) → Hee(z) =
Ve
out(z) V
ein(z)
= -
C1
C2
11-z-1 = -
C1
C2
zz-1
To get the frequency response, we replace z by ejωΤ giving,
Hee(e jωΤ) = V
eout( e jωΤ)
Vein( ejωΤ)
= -
C1
C2
e jωΤ
e jωΤ -1 = -
C1
C2
e jωΤ/2
e jωΤ/2 - e-jωΤ/2
Replacing ejωΤ/2 - e-jωΤ/2 by 2j sin(ωT/2) and simplifying gives,
Hee(e jωΤ) = V
eout(e jωΤ)
Vein( e jωΤ)
= -
C1
jωTC2
ωT/2
sin(ωT/2) e jωΤ/2
Same as noninverting integrator except for phase error.Consequently, the magnitude response is identical but the phase response is given as
Arg[Hee(e jωΤ)] = π2 +
ωΤ2 .
Comments: • The phase error is + for the inverting integrator and - for the noninverting integrator.• The cascade of an inverting and noninverting switched capacitor integrator has no
phase error.
Chapter 9 – Section 3 (5/2/04) Page 9.3-9
CMOS Analog Circuit Design © P.E. Allen - 2004
A Sign MultiplexerA circuit that changes the φ1 and φ2 of the leftmost switches of the stray insensitive,switched capacitor integrator.
1 2
VC
x
y
To switch connectedto the input signal (S1).
To the left most switchconnected to ground (S2).
VC
0
1
x y
1
12
2
Fig. 9.3-8
This circuit steers the φ1 and φ2 clocks to the input switch (S1) and the leftmost switchconnected to ground (S2) as a function of whether Vc is high or low.
Chapter 9 – Section 3 (5/2/04) Page 9.3-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Switched Capacitor Integrators - Finite Op Amp GainConsider the following circuit which is equivalentof the noninverting integrator at the beginning ofthe φ2 phase period.
The expression for ve
out (n-1/2)T can be written as
ve
out(n-1/2)T =
C1
C2 v
oin(n-1)T + v
oout(n-1)T -
vo
out(n-1)TAvd(0) +
ve
out(n-1/2)TAvd(0)
C1+C2
C2
Substituting vo
out(n)T = ve
out(n -0.5)T into this equation gives
vo
out(n)T =
C1
C2 v
oin(n-1)T + v
oout(n-1)T -
vo
out(n-1)TAvd(0) +
vo
out(n)TAvd(0)
C1+C2
C2
Using the previous approach to solve for the z-domain transfer function results in,
Hoo(z) = V
oout(z)
Voin(z)
= (C1/C2) z
-1
1 - z-1 + z-1
Avd(0) - C1
Avd(0)C2 z-1
z-1 + 1
Avd(0) z-1
z-1
or
Hoo(z) = V
oout(z)
Voin(z)
=
(C1/C2) z
-1
1 - z-1
1
1 - 1Avd(0) -
C1
Avd(0)C2(1-z-1) =
HI(z)
1 - 1
Avd(0) - C1
Avd(0)C2(1-z-1)
oinv
2C
C1
vC1
+
++
(n-1)T
= 0
vC2 = 0
vout (n-1/2)Te
+--
-
-
+
-
+-
vout (n-1/2)Te
Avd(0)
vout (n-1)T -o vout (n-1)T
o
Avd(0)
Fig. 9.3-10
Chapter 9 – Section 3 (5/2/04) Page 9.3-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Finite Op Amp Gain - ContinuedSubstitute the z-domain variable, z, with ejωT to get
Hoo(e jωT) = HI(e
jωT)
1 - 1
Avd(0)
1 + C1
2C2 - j
C1/C2
2Avd(0) tan
ωT
2
(1)
where now HI(e jωT) is the integrator transfer function for Avd(0) = ∞.
The error of an integrator can be expressed as
H(jω) = HI(jω)
[1-m(ω)] e-jθ(ω) where
m(ω) = the magnitude error due to Avd(0)θ(ω) = the phase error due to Avd(0)
If θ(ω) is much less than unity, then this expression can be approximated by
H(jω) ≈ HI(jω)
1 - m(ω) - jθ(ω) (2)
Comparing Eq. (1) with Eq. (2) gives m(ω) and θ(ω)due to a finite value of Avd(0) as
m(jω) = - 1
Avd(0)
1 + C1
2C2 and θ(jω) =
C1/C2
2Avd(0) tan(ωT/2)
Chapter 9 – Section 3 (5/2/04) Page 9.3-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.3-3 - Evaluation of the Integrator Errors due to a finite value of A v d (0)Assume that the clock frequency and integrator frequency of a switch capacitor
integrator is 100kHz and 10kHz, respectively. If the value of Avd(0) is 100, find the valueof m(jω) and θ(jω) at 10kHz.Solution
The ratio of C1 to C2 is found asC1
C2 = ωIT =
2π⋅10,000100,000 = 0.6283 .
Substituting this value along with that for Avd(0) into m(jω) and θ(jω) gives
m(jω) = -
1 + 0.6283
2 = -0.0131
and
θ(jω) = 0.6283
2⋅100⋅tan(18°) = 0.554° .
The “ideal” switched capacitor transfer function, HI(jω), will be multiplied by a value ofapproximately 1/1.0131 = 0.987 and will have an additional phase lag of approximately0.554°.In general, the phase shift error is more serious than the magnitude error.
Chapter 9 – Section 3 (5/2/04) Page 9.3-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Switched Capacitor Integrators - Finite Op Amp GBThe precise analysis of the influence of GB can be found elsewhere† . The results of
such an analysis can be summarized in the following table.
NoninvertingIntegrator
Inverting Integrator
m(ω) ≈ -e-k1
C2
C1+C2
θ(ω) ≈ 0
m(ω) ≈ -e-k1
1 -
C2
C1+C2 cos(ωT)
θ(ω) ≈ -e-k1
C2
C1+C2 cos(ωT)
k1 ≈ π
C2
C1+C2
GB
fc
If ωT is much less than unity, the expressions in table reduce to
m(ω) ≈ -2π
f
fc e-π(GB/f
c)
† K. Martin and A.S. Sedra, “Effects of the Op Amp Finite Gain and Bandwidth on the Performance of Switched-Capacitor Filters,” IEEE Trans. onCircuits and Systems, vol. CAS-28, no. 8, August 1981, pp. 822-829.
Chapter 9 – Section 3 (5/2/04) Page 9.3-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Switched Capacitor Circuits - kT/C NoiseSwitched capacitors generate aninherent thermal noise given bykT/C. This noise is verified asfollows.An equivalent circuit for a switchedcapacitor:The noise voltage spectral density of Fig. 9.3-11b is given as
e 2Ron = 4kTRon Volts2/Hz =
2kTRonπ Volt2/Rad./sec. (1)
The rms noise voltage is found by integrating this spectral density from 0 to ∞ to give
v 2Ron =
2kTRonπ ⌡
⌠
0
∞
ω12dω
ω12+ω2 =
2kTRonπ
πω1
2 = kTC Volts(rms)2 (2)
where ω1 = 1/(RonC). Note that the switch has an effective noise bandwidth of
fsw = 1
4RonC Hz (3)
which is found by dividing Eq. (2) by Eq. (1).
C voutvin
+
-
+
-
C voutvin
+
-
+
-
Ron
(a.) (b.)Figure 9.3-11 - (a.) Simple switched capacitor circuit. (b.) Approximation of (a.).
Chapter 9 – Section 3 (5/2/04) Page 9.3-15
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• The discrete time noninverting integrator transfer function is
Hoo(e jωΤ) = V
oout(e jωΤ)
Voin( e jωΤ)
=
C1
jωTC2
ωT/2
sin(ωT/2) e-jωΤ/2
• The discrete time inverting integrator transfer function is
Hee(e jωΤ) = V
eout(e jωΤ)
Vein( e jωΤ)
= -
C1
jωTC2
ωT/2
sin(ωT/2) ejωΤ/2
• In general the integrator transfer function can be expressed as
H(ejωT) = (Ideal)x(Magnitude error)x(Phase error)• Note that the cascade of an noninverting integrator with a inverting integrator has no
phase error• A capacitor C and a switch (or switches) has a thermal noise given as kT/C where T is
the clock period
Chapter 9 – Section 4 (5/2/04) Page 9.4-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 9.4 – z-DOMAIN MODELS OF TWO-PHASE SWITCHEDCAPACITOR CIRCUITS
IntroductionObjective:• Allow easy analysis of complex switched capacitor circuits• Develop methods suitable for simulation by computer• Will constrain our focus to two-phase, nonoverlapping clocksGeneral Two-Port Characterization of Switched Capacitor Circuits:
+-
vin(t) vout(t)
IndependentVoltageSource
SwitchedCapacitor
Circuit
UnswitchedCapacitor
DependentVoltageSource
Figure 9.4-1 - Two-port characterization of a general switched capacitor circuit.
Approach:• Four port - allows both phases to be examined• Two-port - simplifies the models but not as general
Chapter 9 – Section 4 (5/2/04) Page 9.4-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Independent Voltage Sources
0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5t/T
v(t)v*(t)
1 2 2 2 2 21 1 1 1
v (t)O
v (t)e
0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5t/T
v(t)
1 1 1 1 1
0 1/2 1 3/2 2 5/2 3 7/2 4 9/2 5t/T
v(t)
2 2 2 2 2
2 2 2 2 2
1 1 1 1 1
Ve(z)
Vo(z)
z-1/2Vo(z)
Vo(z)
Ve(z)
z-1/2Ve(z)
Phase DependentVoltage Source
Phase IndependentVoltage Source forthe Odd Phase
Phase IndependentVoltage Source forthe Even Phase
Chapter 9 – Section 4 (5/2/04) Page 9.4-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Switched Capacitor Four-Port Circuits And Z-Domain Models†
+
-V o
2
+
-V e
2
+
-V o
1
+
-V e
1
C
-Cz-
1/2
Cz-
1/2
-Cz-
1/2
C
+
-v1(t) v2(t)C
φ1 φ2
+
-
Parallel Switched Capacitor
+
-
+
-
Cz-1/2
V e2V o
1
Switched Capacitor, Two-Port Circuit Simplified, Two-Port z-domain Model
+
-v1(t) v2(t)
Cφ1 φ2
+
-
Negative SC Transresistance
φ2 φ1
+
-V o
2
+
-V e
2
+
-V o
1
+
-Ve
1
C
Cz-
1/2
-Cz-
1/2
Cz-
1/2
C
+
-
+
-
-Cz-1/2
V e2V o
1
+
-v1(t) v2(t)
C
φ1
φ2 +
-
Positive SC Transresistance
φ2φ1
+
-V o
2
+
-V e
2
+
-V o
1
+
-V e
1
C
+
-
+
-
C
V e2V e
1
+
-v1(t) v2(t)
Cφ2 +
-
Capacitor and Series Switch
+
-V o
2
+
-V e
2
+
-V o
1
+
-V e
1C(1-z-1)
+
-
+
-V e
2V e1
C(1-z-1)
Four-Port, z-domain Equivalent Model
Fig. 9.4-3
(Circuit connected betweendefined voltages)
(Circuit connected betweendefined voltages)
(Circuit connected betweendefined voltages)
(Circuit connected betweendefined voltages)
† K.R. Laker, “Equivalent Circuits for Analysis and Synthesis of Switched Capacitor Networks,” Bell System Technical Journal, vol. 58, no. 3,
March 1979, pp. 729-769.
Chapter 9 – Section 4 (5/2/04) Page 9.4-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Z-Domain Models for Circuits that must be Four-Port
+
-v1(t) v2(t)
C
+
-
+
-V o
2
+
-V e
2
+
-V o
1
+
-
Ve1
C
-Cz-
1/2
Cz-
1/2
C
-Cz-
1/2
Cz-
1/2
+
-V o
2
+
-V e
2
+
-V o
1
+
-Ve
1
C
-Cz-
1/2
C
-Cz-
1/2
+
-v1(t) v2(t)
C
φ1
+
-Capacitor and Shunt Switch
+
-V o
2
+
-V e
2
+
-V o
1
+
-V e
1
C
UnswitchedCapacitor
+
-V o
2
+
-V e
2
+
-V o
1
+
-V e
1
C
Switched Capacitor Circuit
Four-port z-domain Model Simplified Four-portz-domain Model
Fig. 9.4-4
Chapter 9 – Section 4 (5/2/04) Page 9.4-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Z-Domain Model for the Ideal Op Amp
+-
+
-vi(t)
+
-vo(t) = Avvi(t)
+
-Vi
o(z)
+
-
Vie(z)
+
-Vo
o(z) = AvVio(z)
+
-
Voe(z) = AvVi
e(z)
Figure 9.4-5 Time domain op amp model. z-domain op amp model
Chapter 9 – Section 4 (5/2/04) Page 9.4-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.4-1- Illustration of the Validity of the z-domain ModelsShow that the z-domain four-port model for the negative switched capacitor
transresistance circuit of Fig. 9.4-3 is equivalent to the two-port switched capacitorcircuit.Solution
For the two-port switched capacitor circuit, weobserve that during the φ1 phase, the capacitor C ischarged to v1(t). Let us assume that the time referencefor this phase is t - T/2 so that the capacitor voltage is
vC = v1(t - T/2).
During the next phase, φ2, the capacitor is inverted and v2 can be expressed as
v2(t) = -vC = -v1(t - T/2).
Next, let us sum the currents flowing away from the positive V e2 node of the four-
port z-domain model in Fig. 9.4-3. This equation is,
-Cz-1/2(V e2 - V
o1 ) + Cz-1/2V
e2 + CV
e2 = 0.
This equation can be simplified as V e2 = -z-1/2V
o1
which when translated to the time domain gives v2(t) = -vC = -v1(t - T/2).
Thus, the four-port z-domain model is equivalent to the time domain.
+
-V o
2
+
-V e
2
+
-V o
1
+
-Ve
1
C
Cz-
1/2
-Cz-
1/2
Cz-
1/2
C
Negative SC Transresistance Model
Chapter 9 – Section 4 (5/2/04) Page 9.4-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Z-Domain, Hand-Analysis of Switched Capacitor Circuits
General, time-variant,switched capacitor circuit.
Four-port, model of theabove circuit.
Simplification of the abovecircuit to a two-port, time-invariant model.
+-
vov1φ1
φ1φ2
φ2
v2 v3
+-
φ2
φ1φ1
φ2
v4
v1
Fig. 9.6-4a
+-
φ1
φ1φ2
φ2 φ2
φ1φ1
φ2
V4(z)
+-
+-
+-
o Vo(z)o
V3(z)oV2(z)o
V1(z)o
V4(z)e
Vo(z)eV3(z)eV2(z)e
V1(z)e
Fig9.4-6b
+-
φ1
φ1φ2
φ2 φ2
φ1φ1
φ2
V1(z)o
V2(z)e V4(z)e
Vo(z)e
V3(z)e
+-
Fig. 9.4-7
Chapter 9 – Section 4 (5/2/04) Page 9.4-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.4-2 - z-domain Analysis of the Noninverting SC Integrator
Find the z-domain transfer function V eo (z)/V oi (z) and
Voo(z)/Vo
i (z) of the noninverting switched capacitorintegrator using the above methods.Solution
First redraw Fig. 9.3-4a as shown in Fig. 9.4-8a.We have added an additional φ2 switch to help inusing Fig. 9.4-3. Because this circuit is time-invariant, we may use the two-port modelingapproach of Fig. 9.4-7. Note that C2 and theindicated φ2 switch are modeled by the bottom row,right column of Fig 9.4-3. The resulting z-domainmodel for Fig. 9.4-8a is shown in Fig. 9.4-8b.
Since z-domain models use admittance, we get
-C1z-1/2V oi (z) + C2(1-z-1)V
eo (z) = 0 → Hoe(z) = (V
eo (z)/V
oi (z)) =
C1z-1/2
C2(1-z-1) .
Hoo(z) is found by using the relationship that V oo (z) = z-1/2V
eo (z) to get
Hoo(z) = (V oo (z)/V
oi (z)) =
C1z-1
C2(1-z-1)
which is equal to z-domain transfer function of the noninverting SC integrator.
+-vi(t)
φ1
φ1φ2
φ2
+-
φ2
voC1 C2
Vi(z)
-C1z-1/2 C2(1-z-1)
o
Vo(z)e
Vo(z)o
z-1/2Vo(z)e
(a.)
(b.)Figure 9.4-8 - (a.) Modified equivalent circuit of Fig. 9.3-4a. (b.) Two-port, z-domain modelfor Fig. 9.4-8a.
Chapter 9 – Section 4 (5/2/04) Page 9.4-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.4-3 - z-domain Analysis of the Inverting Switched Capacitor Integrator
Find the z-domain transfer function V eo (z)/V
ei (z) and
V oo (z)/V
ei (z) of Fig. 9.3-4a using the above methods.
SolutionFig. 9.4-9a shows the modified equivalent
circuit of Fig. 9.3-4b. The two-port, z-domainmodel for Fig. 9.4-9a is shown in Fig. 9.4-9b.Summing the currents flowing to the inverting nodeof the op amp gives
C1V ei (z) + C2(1-z-1)V
eo (z) = 0
which can be rearranged to give
Hee(z) = V
eo (z)
V ei (z)
= -C1
C2(1-z-1) .
which is equal to inverting, switched capacitor integrator z-domain transfer function.
Heo(z) is found by using the relationship that V oo (z) = z-1/2V
eo (z) to get
Heo(z) = V
oo (z)
V ei (z)
= C1z-1/2
C2(1-z-1) .
+-vi(t)
φ2
φ1φ1
φ2
+-
φ2
voC1 C2
Vi(z)
C1 C2(1-z-1)
e
Vo(z)e
Vo(z)o
z-1/2Vo(z)e
(a.)
(b.)Figure 9.4-9 - (a.) Modified equivalent circuit of inverting SC integrator. (b.) Two-port, z-domain model for Fig. 9.4-9a
Chapter 9 – Section 4 (5/2/04) Page 9.4-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.4-4 - z-domain Analysis a Time-Variant Switched Capacitor Circuit
Find V oo (z) and V
eo (z) as function of V
o1 (z)
and V o2 (z) for the summing, switched capacitor
integrator of Fig. 9.4-10a.Solution
This circuit is time-variant because C3 ischarged from a different circuit for each phase.Therefore, we must use a four-port model. Theresulting z-domain model for Fig. 9.4-10a isshown in Fig. 9.4-10b.
+-v1(t)
φ1
φ1φ2
φ2
voC1 C3
v2(t)
φ1
φ2φ2
φ1
C1
Fig. 9.4-10a - Summing Integrator.
Chapter 9 – Section 4 (5/2/04) Page 9.4-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.4-4 - Continued
Summing the currents flowing away from the V oi (z) node
gives
C2V o2 (z) + C3V
oo (z) - C3z-1/2V
eo (z) = 0 (1)
Summing the currents flowing away from the V ei (z) node,
-C1z-1/2V o1 (z) - C3z-1/2V
oo (z) + C3V
eo (z) = 0 (2)
Multiplying (2) by z-1/2 and adding it to (1) gives
C2V o2 (z) + C3V
oo (z) - C1z-1V
o1 (z) - C3z-1V
oo (z) = 0 (3)
Solving for V oo (z) gives,
V oo (z) =
C1z-1V o1 (z)
C3(1-z-1) - C2V
o2 (z)
C3(1-z-1)
Multiplying Eq. (1) by z-1/2 and adding it to Eq. (2) gives
C2z-1/2V o2 (z) - C1z-1V
o1 (z) - C3z-1V
eo (z) + C3V
eo (z) = 0
Solving for V eo (z) gives,
V eo (z) =
C1z-1/2V o1 (z)
C3(1-z-1) - C2z-1/2V
o2 (z)
C3(1-z-1) .
+-
V1(z)
-C1z-1/2
C3o
Vo(z)o
V2(z)o
C2
-C3z-1/2
Vi(z)o
+-C3
Vo(z)eVi(z)e
Fig. 9.4-10b - Four-port, z-domainmodel for Fig. 9.4-10a.
-C3z-1/2
Chapter 9 – Section 4 (5/2/04) Page 9.4-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Domain Simulation of SC Circuits Using Spice Storistors†
A storistor is a two-terminal element that has a current flow that occurs at some timeafter the voltage is applied across the storistor.z-domain:
I(z) = ±Cz-1/2 [V1(z) - V2(z)]
Time-domain:
i(t) = ±C
v1
t - T2 - v2
t - T2
SPICE Primitives:
† B.D. Nelin, “Analysis of Switched-Capacitor Networks Using General-Purpose Circuit Simulation Programs,” IEEE Trans. on Circuits and Systems, pp. 43-48, vol. CAS-30,No. 1, Jan. 1983.
V1(z) V2(z)
I(z) I(z)
±Cz-1/2
Fig. 9.4-11a
+
- T2
+
-v1(t)
+ -v3(t)
+
-v2(t)
±Cv3(t)
Rin = ∞
Delay of T/2
i(t) i(t)
Fig. 9.4-11b
LosslessTrans-mission Line
TD = T/2, Z0 = R
1
V1-V2
2
±CV43 4
R
Fig. 9.4-11c
Chapter 9 – Section 4 (5/2/04) Page 9.4-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.4-5 - SPICE Simulation of A Noninverting SC IntegratorUse SPICE to obtain a frequency domain simulation of the noninverting, switched
capacitor integrator. Assume that the clock frequency is 100kHz and design the ratio ofC1 and C2 to give an integration frequency of 10kHz.
SolutionThe design of C1/C2 is accomplished from the ideal integrator transfer function.
C1C2
= ωIT = 2πfIfc
= 0.6283
AssumeC2 = 1F →C1 = 0.6283F.
Next we replace the switchedcapacitor C1 and the unswitchedcapacitor of integrator by the z-domain model of the second row ofFig. 9.4-3 and the first row of Fig.9.4-4 to obtain Fig. 9.4-12. Notethat in addition we used Fig. 9.4-5for the op amp and assumed that the op amp had a differential voltage gain of 106. Also,the unswitched C’s are conductances.
As the op amp gain becomes large, the important components are indicated by thedarker shading.
+
-V o
i
+
-Ve
i
C1
C1z
-1/2
-C1z
-1/2
C1z
-1/2
C1
+
-V o
o
+
-V e
o
C2
-C2z
-1/2
C2z
-1/2
-C2z
-1/2
C2z
-1/2
106V3
106V4
5
0
6
3
0
4
1
0
2
Figure 9.4-12 - z-domain model for noninverting switched capacitor integrator.
C2
Chapter 9 – Section 4 (5/2/04) Page 9.4-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.4-5 - ContinuedThe SPICE input file to perform a frequency domain simulation of Fig. 9.4-12 is shownbelow.
VIN 1 0 DC 0 AC 1R10C1 1 0 1.592X10PC1 1 0 10 DELAYG10 1 0 10 0 0.6283X14NC1 1 4 14 DELAYG14 4 1 14 0 0.6283R40C1 4 0 1.592X40PC1 4 0 40 DELAYG40 4 0 40 0 0.6283X43PC2 4 3 43 DELAYG43 4 3 43 0 1R35 3 5 1.0X56PC2 5 6 56 DELAYG56 5 6 56 0 1R46 4 6 1.0X36NC2 3 6 36 DELAY
G36 6 3 36 0 1X45NC2 4 5 45 DELAYG45 5 4 45 0 1EODD 6 0 4 0 -1E6EVEN 5 0 3 0 -1E6********************.SUBCKT DELAY 1 2 3ED 4 0 1 2 1TD 4 0 3 0 ZO=1K TD=5URDO 3 0 1K.ENDS DELAY********************.AC LIN 99 1K 99K.PRINT AC V(6) VP(6) V(5) VP(5).PROBE.END
Chapter 9 – Section 4 (5/2/04) Page 9.4-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.4-5 - ContinuedSimulation Results:
Mag
nitu
de
Frequency (kHz)20 40 60 80 1000
(a.)
Both H and Hoe oo
0
1
2
3
4
5
(b.)Frequency (kHz)
20 40 60 80 1000-200
-150
-100
-50
0
50
100
150
200
Phas
e Sh
ift (
Deg
rees
)
Phase of H (jw)oe
Phase of H (jw)oo
Comments:• This approach is applicable to all switched capacitor circuits that use two-phase,
nonoverlapping clocks.• If the op amp gain is large, some simplification is possible in the four-port z-domain
models.• The primary advantage of this approach is that it is not necessary to learn a new
simulator.
Chapter 9 – Section 4 (5/2/04) Page 9.4-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Simulation of Switched Capacitor Circuits Using SWITCAP†
IntroductionSWITCAP is a general simulation
program for analyzing linear switchedcapacitor networks (SCN’s) and mixedswitched capacitor/digital (SC/D)networks.Major Features1.) Switching Intervals - An arbitrary number of switching intervals per switching period
is allowed. The durations of the switching intervals may be unequal and arbitrary.2.) Network Elements - ON-OFF switches, linear capacitors, linear VCVS’s, and independent voltage sources. The independent voltage source waveforms may be continuous or piecewise-constant. The switches in the linear SCN’s are controlled by periodic clock waveforms only. A mixed SC/D network may contain comparators, logic gates such as AND, OR, NOT,
NAND, NOR, XOR, and XNOR. The ON-OFF switches in the SC/D network may becontrolled not only by periodic waveforms but also by nonperiodic waveforms fromthe output of comparators and logic gates.
† K. Suyama, Users’ Manual for SWITCAP2, Version 1.1, Dept. of Elect. Engr., Columbia University, New York, NY 10027, Feb. 1992.
SignalGenerators
SCN's or MixedSC/D Networks Outputs
Clocks
General Setup of SWITCAP
Chapter 9 – Section 4 (5/2/04) Page 9.4-17
CMOS Analog Circuit Design © P.E. Allen - 2004
SWITCAP - Major Features, Continued3.) Time-Domain Analyses of Linear SCN’s and Mixed SC/D Networks -
a.) Linear SCN’s only: The transient response to any prescribed input waveform fort ≥ 0 after computing the steady-state values for a set of dc inputs for t < 0.
b.) Both types of networks: Transient response without computing the steady-statevalues as initial conditions. A set of the initial condition of analog and digitalnodes at t = 0- may be specified by the user.
4.) Various Waveforms for Time Domain Analyses - Pulse, pulse train, cosine,exponential, exponential cosine, piecewise linear, and dc sources.5.) Frequency Domain Analyses of Linear SCN’s - A single-frequency sinusoidal inputcan produce a steady-state output containing many frequency components. SWITCAPcan determine all of these output frequency components for both continuous andpiecewise-constant input waveforms. z-domain quantities can also be computed.Frequency-domain group delay and sensitivity analyses are also provided.6.) Built-In Sampling Functions - Both the input and output waveforms may be sampledand held at arbitrary instants to produce the desired waveforms for time- and frequency-domain analyses of linear SCN’s except for sensitivity analysis. The output waveformsmay also be sampled with a train of impulse functions for z-domain analyses.
Chapter 9 – Section 4 (5/2/04) Page 9.4-18
CMOS Analog Circuit Design © P.E. Allen - 2004
SWITCAP - Major Features, Continued7.) Subcircuits - Subcircuits, including analog and/or digital elements, may be definedwith symbolic values for capacitances, VCVS gains, clocks, and other parameters.Hierarchical use of subcircuits is allowed.8.) Finite Resistances, Op Amp Poles, and Switch Parasitics - Finite resistance ismodeled with SCN’s operating at clock frequencies higher than the normal clock. These“resistors” permit the modeling of op amp poles. Capacitors are added to the switchmodel to represent clock feedthrough.
Chapter 9 – Section 4 (5/2/04) Page 9.4-19
CMOS Analog Circuit Design © P.E. Allen - 2004
SWITCAP - Mixed SC/D NetworksStructure of mixed SC/D networks as defined in SWITCAP2.
+-+-
+-
Threshold
...
...
Logic
+
-v
Av
SCN - Function Generation
Timing
Chapter 9 – Section 4 (5/2/04) Page 9.4-20
CMOS Analog Circuit Design © P.E. Allen - 2004
SWITCAP - ResistorsRQ RQ
RQRQ
Ceq
R = T4Ceq
RQ
RQ
t
t
The clock, RQ, for the resistor is run at a frequency, much higher than the system clock inorder to make the resistor model still approximate a resistor at frequencies near thesystem clock.
Chapter 9 – Section 4 (5/2/04) Page 9.4-21
CMOS Analog Circuit Design © P.E. Allen - 2004
SWITCAP - MOS SwitchesMOS Transistor Switch Model:
High Clock Voltage
MQ MQ
Cgd
D
G
RON
Cbd
Cgs
Cbs
S
MQMQ
MQ
FrequencyHigher thanMQ clock
D
G
S
MQ
More information:SWITCAP Distribution CenterColumbia University411 Low Memorial LibraryNew York, NY [email protected]
Chapter 9 – Section 4 (5/2/04) Page 9.4-22
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• Can replace various switch-capacitor combinations with a z-domain model• The z-domain model consists of:
- Positive and negative conductances
- Delayed conductances (storistor)
- Controlled sources
- Independent sources• These models permit SPICE simulation of switched capacitor circuits• The type of clock circuits considered here are limited to two-phase clocks
Chapter 9 – Section 5 (5/2/04) Page 9.5-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 9.5 – FIRST-ORDER SWITCHED CAPACITOR CIRCUITSIntroductionObjective:• Examine first-order SC circuits• Illustrate various design methods of SC circuitsApproach:• Low-pass: Design using oversampled assumption and direct z-domain design• High-pass: Design using oversampled assumption and direct z-domain design• All-pass: Design using oversampled assumption and direct z-domain design
Chapter 9 – Section 5 (5/2/04) Page 9.5-2
CMOS Analog Circuit Design © P.E. Allen - 2004
General, First-Order Transfer FunctionsA general first-order transfer function in the s-domain:
H(s) = sa1 ± a0s + b0
a1 = 0 ⇒ Low pass, a0 = 0 ⇒ High Pass, a0 ≠ 0 and a1 ≠ 0 ⇒ All pass
Note that the zero can be in the RHP or LHP.A general first-order transfer function in the z-domain:
H(z) = zA1 ± A0
z - B0 =
A1 ± A0z-1
1 - B0z-1
Chapter 9 – Section 5 (5/2/04) Page 9.5-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Noninverting, First-Order, Low Pass Circuit
+-
vi(t)
φ1
φ1φ2
φ2
φ2
vo(t)
C1
(a.) (b.)Figure 9.5-1 - (a.) Noninverting, first-order low pass circuit. (b.) Equivalent circuit of Fig. 9.5-1a.
φ1 φ1 φ2
+-
vi(t)
φ1
φ1φ2
φ2
φ2
vo(t)
φ2
φ1φ1vo(t)
α1C1
α2C1
α2C1
α1C1
C1
Transfer function:Summing currents flowing toward the inverting
op amp terminal gives
α2C1V eo (z) - α1C1z-1/2V
oi (z) + C1(1-z-1)V
eo (z) = 0
Solving for V oo (z)/V
oi (z) gives
V oo (z)
V oi(z)
= α1z-1
1 + α2 - z-1 =
α1z-1
1+α2
1 - z-1
1+α2Equating the above to H(z) of the previous page gives the design equations as
α1 = A0/B0 and α2 = (1-B0)/B0
+-Vi(z)
-C1α1z-1/2 C1(1-z-1) Vo(z)e
Vo(z)o
z-1/2Vo(z)e
Vo(z)
C1α2
o
e
Figure 9.5-2 - z-domain model of Fig. 9.5-1b.
Chapter 9 – Section 5 (5/2/04) Page 9.5-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Inverting, First-Order, Low Pass CircuitAn inverting low pass circuit can be obtained by reversing the phases of the leftmost twoswitches in Fig. 9.5-1a.
+-
vi(t)
φ2
φ1φ1
φ2
φ2
vo(t)
C1
Inverting, first-order low pass circuit. Equivalent circuit.
φ1 φ1 φ2
+-
vi(t)
φ2
φ1φ1
φ2
φ2
vo(t)
φ2
φ1φ1vo(t)
α1C1
α2C1
α2C1
α1C1
C1
It can be shown that,
V eo (z)
V ei(z)
= -α1
1 + α2 - z-1 =
-α11+α2
1 - z-1
1+α2
Equating to H(z) gives the design equations for the inverting low pass circuit as
α1 = -A1B0
and α2 =
1-B0
B0
Chapter 9 – Section 5 (5/2/04) Page 9.5-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.5-1 - Design of a Switched Capacitor First-Order CircuitDesign a switched capacitor first-order circuit that has a low frequency gain of +10
and a -3dB frequency of 1kHz. Give the value of the capacitor ratios α1 and α2. Use aclock frequency of 100kHz.Solution
Assume that the clock frequency, fc, is much larger than the -3dB frequency. In thisexample, the clock frequency is 100 times larger so this assumption should be valid.Based on this assumption, we approximate z-1 as
z-1 = e-sT ≈ 1- sT + ··· (1)Rewrite the z-domain transfer function as
V oo (z)
V oi (z)
= α1z-1
α2 + 1- z-1 (2)
Next, we note from Eq. (1) that 1-z-1 ≈ sT. Furthermore, if sT<<1, then z-1 ≈ 1.Making these substitutions in Eq. (2), we get
V oo (s)
V oi (s)
≈ α1
α2 + sT = α1/α2
1 + s(T/α2) (3)
Equating Eq. (3) to the specifications gives α1 = 10α2 and α2 = ω-3dB/fc∴ α2 = 6283/100,000 = 0.0628 and α1 = 0.6283
Chapter 9 – Section 5 (5/2/04) Page 9.5-6
CMOS Analog Circuit Design © P.E. Allen - 2004
First-Order, High Pass Circuit
Transfer function:Summing currents at theinverting input node of the opamp gives
α1(1-z-1)V eo (z) + α2V
eo (z) + (1-z-1)V
ei (z) = 0 (1)
Solving for the Hee(z) transfer function gives
Hee(z) = V
eo (z)
V ei (z)
= -α1(1-z-1)α2+1-z-1 =
α1α2+1 (1-z-1)
1 - 1
α2+1 z-1 (2)
Equating Eq. (2) to H(z) gives,
α1 = -A1B0
and α2 =
1-B0
B0
+-
vi(t)
φ2
vo(t)α1C
C
φ1 φ1 φ2α2C
+-
vi(t)
φ2
φ2
vo(t)
C
φ1 φ1 φ2
(a.) (b.)Figure 9.5-3 - (a.) Switched-capacitor, high pass circuit. (b.) Version of Fig. 9.5-3athat constrains the charging of C1 to the φ2 phase.
α1C
α2C
+-
Vi(z)
α1(1-z-1) (1-z-1) Vo(z)e
Vo(z)o
z-1/2Vo(z)e
α2
e
Figure 9.5-4 - z-domain model for Fig. 9.5-3.
Chapter 9 – Section 5 (5/2/04) Page 9.5-7
CMOS Analog Circuit Design © P.E. Allen - 2004
First-Order, Allpass Circuit
Transfer function:Summing the currentsflowing into theinverting input of theop amp gives
-α1z-1/2Vo i (z)+α3(1-z-1)Ve
i (z)+α2Ve o(z)+(1-z-1)Ve
o(z) = 0
Since Voi (z) = z-1/2Ve
i(z), then the above becomes
Veo(z) α2+1-z-1 = α1z-1Ve
i(z) - α3(1-z-1)Vei(z)
Solving for Hee(z) gives
Hee(z) = α1z-1-α3(1-z-1)α2+(1-z-1) =
-α3
α2+1 1-α1+α3α3
z-1
1-z-1
α2+1
⇒ α1 = A1+A0
B0 α2 =
1-B0
B0 and α3 =
- A0B0
+-
vi(t)
φ1
φ1φ2
φ2
φ2
vo(t)
C
(b.)
φ1 φ1 φ2
φ2
+-
vi(t)
φ1
φ1φ2
φ2
φ2
vo(t)
α1C C
(a.)
φ1 φ1 φ2α3C
Figure 9.5-5 - (a.) High or low frequency boost circuit. (b.) Modification of (a.) to simplifythe z-domain modeling
α2C α3C α2C
α1C
+-
Vi(z)
-α1z-1/2 (1-z-1) Vo(z)e
Vo(z)o
z-1/2Vo(z)e
α2
o
Figure 9.5-6 - z-domain model for Fig. 9.5-5b.
α3(1-z-1)
Vi(z)e
Chapter 9 – Section 5 (5/2/04) Page 9.5-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.5-2 - Design of a Switched Capacitor Bass Boost CircuitFind the values of the capacitor ratiosα1, α2,and α3 using a 100kHz clock for Fig. 9.5-5that will realize the asymptotic frequencyresponse shown in Fig. 9.5-7.Solution
Since the specification for the example isgiven in the continuous time frequencydomain, let us use the approximation that z-1 ≈ 1 and 1-z-1≈ sT, where T is the period ofthe clock frequency. Therefore, the allpass transfer function can be written as
Hee(s) ≈ -sTα3 + α1
sT + α2 = -
α1α2
sTα3/α1 - 1
sT/α2 + 1
From Fig. 9.5-7, we see that the desired response has a dc gain of 10, a right-halfplane zero at 2π kHz and a pole at -200π Hz. Thus, we see that the followingrelationships must hold.
α1α2
= 10 , α1Tα3
= 2000π , and α2T = 200π
From these relationships we get the desired values as
α1 = 2000π
fc, α2 =
200πfc
, and α3 = 1
dB
20
01kHz 10kHz10Hz 100Hz
FrequencyFigure 9.5-7 - Bass boost response for Ex. 9.5-2.
Chapter 9 – Section 5 (5/2/04) Page 9.5-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Practical Implementations of the First-Order Circuits
+-
vi(t)
φ1
φ1φ2
φ2
φ2
vo(t)C1
C
(a.) (b.)Figure 9.5-8 - Differential implementations of (a.) Fig. 9.5-1, (b.) Fig. 9.5-3, and (c.) Fig. 9.5-5.
φ1 φ1
φ2α2C
vo(t)
+-
C
φ1 φ1
φ2 φ2
φ1 φ2
+
-+-
vi(t)
φ2
φ2
vo(t)
C
φ1 φ1
φ2
vo(t)
+-
C
φ1 φ1
φ2 φ2
φ2
+
-+-
vi(t)
φ1
φ1φ2
φ2
φ2
vo(t)
C
(c.)
φ1 φ1φ2
vo(t)
+-
C
φ1 φ1
φ2 φ2
φ1 φ2
+
-
φ2
φ2α2C
α1C
α1C
α2C
α2C
α1C
α1C
α2C
α2C
α1C
α1C
α3C
α3C
Comments:• Differential operation reduces clock feedthrough, common mode noise sources and
enhances the signal swing.• Differential operation requires op amps or OTAs with differential outputs which in turn
requires a means of stabilizing the output common mode voltage.
Chapter 9 – Section 5 (5/2/04) Page 9.5-10
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• Examined first-order SC circuits (lowpass, highpass, allpass)• Illustrated design by assuming the clock frequency is higher than the signal frequency
(s-domain design)• Illustrated direct design by equating coefficients between the desired and design in the
z-domain (requires the specifications in the z-domain)
Chapter 9 – Section 6 (5/2/04) Page 9.6-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 9.6 – SECOND-ORDER SWITCHED CAPACITOR CIRCUITSWhy Second-Order Circuits?
They are fundamental blocks in switched capacitor filters.Switched Capacitor Filter Design Approaches • Cascade design
• Ladder designAlso uses first- and second-order circuits
There are also other applications of first- and second-order circuits:• Oscillators• Converters
First-OrderCircuit
Second-OrderCircuit
Second-OrderCircuit
Second-OrderCircuit
Stage 1 Stage 2 Stage n
Vin Vout
Second-OrderCircuit
Second-OrderCircuit
Stage 1 Stage 2 Stage n
Vin Vout
(a.)
(b.)Figure 9.6-1 - (a.) Cascade design when n is even. (b.) Cascade designwhen n is odd.
Chapter 9 – Section 6 (5/2/04) Page 9.6-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Biquad Transfer FunctionA biquad has two poles and two zeros.
Poles are complex and always in the LHP.The zeros may or may not be complex and may be in the LHP or the RHP.
Transfer function:
Ha(s) = Vout(s)Vin(s) =
-(K2s2+ K1s + K0)
s2 + ωoQ s+ ωo
2 = K
(s-z1)(s-z2)
(s-p1)(s-p2)
2Qωo
ωo
jω
σ
Low pass: zeros at ∞ Bandstop: zeros at ±jωo
High pass: zeros at 0 Allpass: Poles and zeros are complexBandpass: One zero at 0 and the other at ∞ conjugates
Chapter 9 – Section 6 (5/2/04) Page 9.6-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Low-Q, Switched Capacitor BiquadDevelopment of the Biquad:
Rewrite Ha(s) as:
s2Vout(s) + ωosQ Vout(s) + ωo
2Vout(s) = -(K2s2 + K1s + K0)Vin(s)
Dividing through by s 2 and solving for Vout(s), gives
Vout(s) = -1s
(K1 + K2s)Vin(s) + ωoQ Vout(s) +
1s (K0Vin(s) +ωo
2Vout(s))
If we define the voltage V1(s) as
V1(s) = -1s
K0
ωo Vin(s) + ωoVout(s) , then Vout(s) can be expressed as
Vout(s) = -1s
(K1 + K2s) Vin(s) + ωoQ Vout(s) - ωoV1(s)
Synthesizing the voltages V1(s)and Vout(s), gives
+-
Vout(s)
Vout(s)Vin(s)V1(s)
CA=1
ωo/K0
1/ωo
+-
Vout(s)
Vin(s)
V1(s)
CB=1
Q/ωo
-1/ωo
Vin(s)
1/K1
K2
Figure 9.6-2 - (a.) Realization of V1(s). (b.) Realization of Vout(s).(a.) (b.)
Chapter 9 – Section 6 (5/2/04) Page 9.6-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Low-Q, Switched Capacitor Biquad - ContinuedReplace the continuous time integrators with switched capacitor integrators to get:
+-
Vout(z) V1(z)C1
V1(s)
Figure 9.6-3 - (a.) Switched capacitor realization of Fig. 9.6-2a. (b.) Switchedcapacitor realization of Fig. 9.6-2b.
(a.)
(b.)
Vin(z)
e
e
φ1
φ1 φ1
φ2φ2
α1C1
α2C1
φ2
+-
Vout(z)
C2Vin(z)
e
e
φ1
φ2
φ1
φ2φ2
α5C2
α4C2
φ1
Vin(z)
φ1
α6C2
φ2
o
Vout(z)e
α3C2
e
e
From these circuits we can write that:
V e1(z) = -
α1
1-z-1 Vein(z) -
α2
1-z-1 Ve
out(z)
and
V eout(z) = -α3 V
ein(z) -
α4
1-z-1 Vein(z) +
α5z-1
1-z-1 Ve1(z) -
α6
1-z-1 Ve
out(z) .
Note that we multiplied the V o1 (z) input of Fig. 9.6-3b by z-1/2 to convert it to V
e1(z).
Chapter 9 – Section 6 (5/2/04) Page 9.6-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Low-Q, Switched Capacitor Biquad - ContinuedConnecting the two circuitsof Fig. 9.6-3 together givesthe desired, low-Q, biquadrealization.
If we assume that ωT<<1,
then 1-z-1 ≈ sT and Ve1(z)
andVe
out(z) can beapproximated as
V e1(s) ≈ -
α1sT V
ein(s) -
α2sT V
eout(s) =
-1s
α1
T Vein(s) +
α2T V
eout(s)
and
V eout(s) ≈
-1s
(α4T + sα3)V
ein(s) -
α5T V
e1(s) +
α6T V
eout(s) .
These equations can be combined to give the transfer function, Hee(s) as follows.
Hee(s) ≈ -
α3s2 + sα4T +
α1α5
T2
s2 + sα6T +
α2α5
T2
+-
V1(z)C1
Figure 9.6-4 - Low Q, switched capacitor, biquad realization.
Vin(z)e
φ1
φ1
φ1
φ2φ2
α2C1
α1C1φ2
+-
C2
φ2
α6C2
α4C2
φ2
α5C2
φ1
Vout(z)e
α3C2
e
φ1
Chapter 9 – Section 6 (5/2/04) Page 9.6-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Low-Q, Switched Capacitor Biquad - Continued
Equating Hee(s) to Ha(s) gives-
α3s2 + sα4T +
α1α5
T2
s2 + sα6T +
α2α5
T2
= -(K2s2+ K1s + K0)
s2 + ωoQ s+ ωo
2
which gives, α1 = K0Tωo
, α2 = |α5| = ωoT, α3 = K2, α4 = K1T, and α6 = ωoTQ .
Largest capacitor ratio:If Q > 1 and ωoT << 1, the largest capacitor ratio is α6.
For this reason, the low-Q, switched capacitor biquad is restricted to Q < 5.Sum of capacitance:
To find this value, normalize all of the capacitors connected or switched into theinverting terminal of each op amp by the smallest capacitor, αminC. The sum of thenormalized capacitors associated with each op amp will be the sum of the capacitanceconnected to that op amp. Thus,
ΣC = 1
αmin ∑i =1
nαi
where there are n capacitors connected to the op amp inverting terminal, including theintegrating capacitor.
Chapter 9 – Section 6 (5/2/04) Page 9.6-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.6-1- Design Of A Switched Capacitor, Low-Q, BiquadAssume that the specifications of a biquad are fo = 1kHz, Q = 2, K0 = K2 = 0, and K1 =
2πfo/Q (a bandpass filter). The clock frequency is 100kHz. Design the capacitor ratios ofFig. 9.6-4 and determine the maximum capacitor ratio and the total capacitance assumingthat C1 and C2 have unit values.
SolutionFrom the previous slide we have
α1 = K0Tωo
, α2 = |α5| = ωoT, α3 = K2, α4 = K1T, and α6 = ωoTQ .
Setting K0 = K2 = 0, and K1 = 2πfo/Q and letting fo = 1kHz, Q = 2 gives
α1 = α3 = 0, α2 = α5 = 0.0628, and α4 = α6 = 0.0314.
The largest capacitor ratio is α4 or α6 and is 1/31.83.
Σ capacitors connected to the input op amp = 1/0.0628 + 1 = 16.916.Σ capacitors connected to the second op amp = 0.0628/0.0314 + 1/0.0314 + 2 = 35.85.Therefore, the total biquad capacitance is 52.76 units of capacitance.(Note that this number will decrease as the clock frequency becomes closer to the signalfrequencies.)
Chapter 9 – Section 6 (5/2/04) Page 9.6-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Z-Domain Characterization of the Low-Q, BiquadCombining the following two equations,
V e1(z) = -
α1
1-z-1 Vein(z) -
α2
1-z-1 Ve
out(z)
and
V eout(z) = -α3 V
ein(z) -
α4
1-z-1 Vein(z) +
α5z-1
1-z-1 Ve1(z) -
α6
1-z-1 Ve
out(z) .
gives,
Ve
out(z)
Vein(z)
= Hee(z) = - (α3 + α4)z2 + (α1α5 - α4 - 2α3)z + α3
(1 + α6)z2 + (α2α5 - α6 - 2)z + 1
A general z-domain specification for a biquad can be written as
H(z) = - a2z2 + a1z + a0
b2z2 + b1˚z + 1
Equating coefficients givesα3 = a0, α4 = a2-a0, α1α5 = a2+a1+a0, α6 = b2-1, and α2α5 = b2+b1+1
Because there are 5 equations and 6 unknowns, an additional relationship can beintroduced. One approach would be to select α5 = 1 and solve for the remainingcapacitor ratios. Alternately, one could let α2 = α5 which makes the integrator frequencyof both integrators in the feedback loop equal.
Chapter 9 – Section 6 (5/2/04) Page 9.6-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Voltage ScalingIt is desirable to keep the amplitudes of the output voltages of the two op amps
approximately equal over the frequency range of interest. This can be done by voltagescaling.
If the voltage at the output node of an op amp in a switched capacitor circuit is tobe scaled by a factor of k, then all switched and unswitched capacitors connected to thatoutput node must be scaled by a factor of 1/k.
For example,
+-
+-
α1C1 C1 α2C2 C2v1
The charge associated with v1 is:
Q(v1) = C1v1 + α2C2v1
Suppose we wish to scale the value of v1 by k1 so that v1’ = k1v1. Therefore,
Q(v1’) = C1v1’ + α2C2v1’ = C1k1v1 + α2C2k1v1
But, Q(v1) = Q(v1’) so that C1’ = C1/k1 and C2’ = C2/k1.
This scaling is based on keeping the total charge associated with a node constant.The choice above of α2 = α5 results in a near-optimally scaled dynamic range realization.
Chapter 9 – Section 6 (5/2/04) Page 9.6-10
CMOS Analog Circuit Design © P.E. Allen - 2004
High-Q, Switched Capacitor BiquadDesired: A biquad capable of realizing higher values of Q without suffering largeelement spreads.Development of such a biquad:
Reformulate the equations for V1(s) and Vout(s) as follows,
Vout(s) = - 1s K2sVin - ωoV1(s)
and
V1(s) = - 1s
K0
ωo +
K1ωo
s Vin(s) +
ωo + sQ Vout(s)
Synthesizing these equations:
+-
Vout(s)
Vout(s)
Vin(s)
V1(s)
CA=1
ωo/K0
1/ωo
+-
Vout(s)
Vin(s)
V1(s)
CB=1
K1/ωo
-1/ωo
Vin(s)1/Q
K2
Realization of V1(s). Realization of Vout(s).
Chapter 9 – Section 6 (5/2/04) Page 9.6-11
CMOS Analog Circuit Design © P.E. Allen - 2004
High-Q, Switched Capacitor Biquad - ContinuedReplace the continuous time integrators with switched capacitor integrators to get:
+-
V1(z)C1
V1(s)
Figure 9.6-6 - (a.) Switched capacitor realization of Fig. 9.6-5a. (b.) Switchedcapacitor realization of Fig. 9.6-5b.
(a.) (b.)
Vin(z)
Vout(z)e
e
φ1
φ1 φ1
φ2φ2
α1C1
α2C1
φ2
+-
Vout(z)
C2Vin(z)
e
e
φ1
φ2α5C2
φ2
α6C2
φ1
o
Vout(z)e
α4C1
eα3C1Vin(z)e
From these circuits we can write that:
V e1(z) = -
α1
1-z-1 Vein(z) -
α2
1-z-1 Ve
out(z) - α3Vein(z) - α4V
eout(z)
and
V eout(z) = -α6 V
ein(z) +
α5z-1
1-z-1 Ve1(z) .
Note that we multiplied the V o1 (z) input of Fig. 9.6-6b by z-1/2 to convert it to V
e1(z).
Chapter 9 – Section 6 (5/2/04) Page 9.6-12
CMOS Analog Circuit Design © P.E. Allen - 2004
High-Q, Switched Capacitor Biquad - ContinuedConnecting the two circuitsof Fig. 9.6-6 together givesthe desired, high-Q biquadrealization.
If we assume that ωT<<1,
then 1-z-1 ≈ sT and Ve1(z)
andVe
out(z) can beapproximated as
V e1(s) ≈ -
1s
α1
T + sα3 Vein(s) -
1s
α2
T + sα4 Ve
out(s)and
V eout(s) ≈
-1s
(sα6)Vein(s) -
α5T V
e1(s) .
These equations can be combined to give the transfer function, Hee(s) as follows.
Hee(s) ≈ -
α6s2 + sα3α5
T + α1α5
T2
s2 + sα4α5
T + α2α5
T2
+-
V1(z)C1Vin(z)e
φ1 φ1
φ2
α1C1
α2C1
φ2
+-
C2
φ1
φ2
α5C2
φ2
α6C2
φ1
Vout(z)e
α4C1
e
α3C1
Figure 9.6-7 - High Q, switched capacitor, biquad realization.
φ1φ2
Chapter 9 – Section 6 (5/2/04) Page 9.6-13
CMOS Analog Circuit Design © P.E. Allen - 2004
High-Q, Switched Capacitor Biquad - ContinuedEquating Hee(s) to Ha(s) gives
-
α6s2 + sα3α5
T + α1α5
T2
s2 + sα4α5
T + α2α5
T2
= -(K2s2+ K1s + K0)
s2 + ωoQ s+ ωo
2
which gives,
α1 = K0Tωo
, α2 = |α5| = ωoT, α3 = K1ωo
, α4 =1Q, and α6 = K2 .
Largest capacitor ratio:If Q > 1 and ωoT << 1, the largest capacitor ratio is α2 (α5) or α4 depending on the
values of Q and ωoT.
Chapter 9 – Section 6 (5/2/04) Page 9.6-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.6-2 - Design of a Switched Capacitor, High-Q, BiquadAssume that the specifications of a biquad arefo = 1kHz, Q = 10, K0 = K2 = 0, and K1
= 2πfo/Q (a bandpass filter). The clock frequency is 100kHz. Design the capacitor ratiosof the high-Q biquad of Fig. 9.6-4 and determine the maximum capacitor ratio and thetotal capacitance assuming that C1 and C2 have unit values.
SolutionFrom the previous slide we have,
α1 = K0Tωo
, α2 = |α5| = ωoT, α3 = K1ωo
, α4 =1Q, and α6 = K2 .
Using fo = 1kHz, Q = 10 and setting K0 = K2 = 0, and K1 = 2πfo/Q (a bandpass filter) gives
α1 = α6 = 0, α2 = α5 = 0.0628, and α3 =α4 = 0.1.
The largest capacitor ratio is α2 or α5 and is 1/15.92.
Σ capacitors connected to the input op amp = 1/0.0628 + 2(0.1/0.0628) + 1 = 20.103.Σ capacitors connected to the second op amp = 1/0.0628 + 1 = 16.916.Therefore, the total biquad capacitance is 36.02 units of capacitance.
Chapter 9 – Section 6 (5/2/04) Page 9.6-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Z-Domain Characterization of the High-Q, BiquadCombining the following two equations,
V e1(z) = -
α1
1-z-1 Vein(z) -
α2
1-z-1 Ve
out(z) - α3Vein(z) - α4V
eout(z)
and
V eout(z) = -α6 V
ein(z) +
α5z-1
1-z-1 Ve1(z)
gives,
Ve
out(z)
Vein(z)
= H ee(z) = - α6z2 + (α3α5 - α1α5 - 2α6)z + (α6 - α3α5)
z2 + (α4α5 + α2α5 - 2)z + (1 - α4α5)
A general z-domain specification for a biquad can be written as
H(z) = - a2z2 + a1z + a0
b2z2 + b1˚z + 1 = - (a2/b2)z2 + (a1/b2)z + (a0/b2)
z2 + (b1/b2)z + (b0/b2)
Equating coefficients gives
α6 = a2b2
, α3α5 = a2-a0
b2, α1α5 =
a2+a1+a0b2
, α4α5 = 1- 1b2
and α2α5 = 1 + b1+1
2
Because there are 5 equations and 6 unknowns, an additional relationship can beintroduced. One approach would be to select α5 = 1 and solve for the remainingcapacitor ratios. Alternately, one could let α2 = α5 which makes the integrator frequencyof both integrators in the feedback loop equal.
Chapter 9 – Section 6 (5/2/04) Page 9.6-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Fleischer-Laker, Switched Capacitor Biquad†
+-
V1(s)D
Figure 9.6-8 - Fleischer-Laker, switched capacitor biquad.
Vin(z)e
φ1
φ2
φ1
φ2φ2
C
G
φ2
+-
B
φ2
F
I
φ2
A
φ1
Vout(z)ee
φ1φ1
φ2
J
H
L
K
φ1
E
φ2
Ve
out(z)
Vein(z)
= (DJ ^ - AH ^)z-2 - [D( I ^ + J ^) - AG ^]z - D I ^
(DB - AE)z-2 - [2DB - A(C + E) + DF]z-1 + D(B +F)
Ve1(z)
Vein(z)
= (EJ ^ - BH ^)z-2+[B(G ^+H ^) + FH ^ - E( I ^+J ^) - CJ ^]z-1 - [ I ^(C+E) - G ^(F+B)]
(DB - AE)z-2 - [2DB - A(C + E) + DF]z-1 + D(B +F)
where G ^ = G+L, H ^ = H+L , I ^ = I+K and J ^ = J+L
Chapter 9 – Section 6 (5/2/04) Page 9.6-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Z-Domain Model Of The Fleischer-Laker Biquad
+-
Vin(z)
-Az-1 B(1-z-1) Vout(z)e
F
e
I
E(1-z-1)
+-
G D(1-z-1) V1(z)e
CK(1-z-1)
-Hz-1
-Jz-1
L(1-z-1)
Figure 9.6-9 - z-domain equivalent circuit for the Fleischer-Laker biquad of Fig. 9.6-8.
Type 1E Biquad (F = 0)
Ve
out
Vein
= z-2(JD - HA) + z-1(AG - DJ - DI) + DI
z-2(DB - AE) + z-1(AC + AE - 2BD) + BD
and
Ve1
Vein
= z-2(EJ - HB) + z-1(GB + HB - IE - CJ - EJ) + (IC + IE - GB)
z-2(DB - AE) + z-1(AC + AE - 2BD) + BD
Chapter 9 – Section 6 (5/2/04) Page 9.6-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Z-Domain Model of the Fleischer-Laker Biquad - Continued
+-
Vin(z)
-Az-1 B(1-z-1) Vout(z)e
F
e
I
E(1-z-1)
+-
G D(1-z-1) V1(z)e
CK(1-z-1)
-Hz-1
-Jz-1
L(1-z-1)
Figure 9.6-9 - z-domain equivalent circuit for the Fleischer-Laker biquad of Fig. 9.6-8.
Type 1F Biquad (E = 0)
Ve
out
Vein
= z-2(JD - HA) + z-1(AG - DJ - DI) + DI
z-2DB + z-1(AC - 2BD - DF) + (BD + DF)
and
Ve1
Vein
= -z-2HB + z-1(GB + HB + HF - CJ) + (IC + GF - GB)
z-2DB + z-1(AC - 2BD - DF) + (BD + DF)
Chapter 9 – Section 6 (5/2/04) Page 9.6-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.6-3 - Design of a Switched Capacitor, Fleischer-Laker BiquadUse the Fleischer-Laker biquad to implement the following z-domain transfer
function which has poles in the z-domain at r = 0.98 and θ = ±6.2°.
H(z) = 0.003z-2 + 0.006z-1 + 0.0030.9604z-2 - 1.9485z-1 + 1
SolutionLet us begin by selecting a Type 1E Fleischer-Laker biquad. Equating the numerator
of Eq. (1) with the numerator of H(z) givesDI = 0.003 AG-DJ-DI = 0.006 → AG-DJ = 0.009 DJ-HA = 0.003
If we arbitrarily choose H = 0, we getDI = 0.003 JD = 0.003 AG = 0.012
Picking D = A = 1 gives I = 0.003, J = 0.003 and G = 0.012. Equating the denominatorterms of Eq. (1) with the denominator of H(z), gives
BD = 1 BD-AE = 0.9604 → AE = 0.0396AC+AE-2BD = -1.9485 → AC+AE = 0.0515 → AC = 0.0119
Because we have selected D = A = 1, we get B = 1, E = 0.0396, and C = 0.0119. If anycapacitor value was negative, the procedure would have to be changed by makingdifferent choices or choosing a different realization such as Type 1F.
Chapter 9 – Section 6 (5/2/04) Page 9.6-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 9.6-3 - ContinuedSince each of the alphabetic symbols is a capacitor, the largest capacitor ratio
will be D or A divided by I or J which gives 333. The large capacitor ratio is beingcaused by the term BD = 1. If we switch to the Type 1F, the term BD = 0.9604 will causelarge capacitor ratios. This example is a case where both the E and F capacitors areneeded to maintain a smaller capacitor ratio.
Chapter 9 – Section 6 (5/2/04) Page 9.6-21
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY• The second-order switched capacitor circuit is a very versatile circuit• The second-order switched capacitor circuit will be very useful in filter design• Low-Q biquad is good for Qs up to about 5 before the elements spreads become large• Design methods:
- Assume that fc>>fsig and using continuous time specifications and design
- Direct design – equate the z-domain transfer function to a z-domain specificationand solve for the capacitor ratios
Chapter 9 – Section 7 (5/2/04) Page 9.7-1
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
SECTION 9.7 – SWITCHED CAPACITOR FILTERSContinuous Time Filter Theory
Today’s switched capacitor filters are based on continuous time filters.Consequently, it is expedient to briefly review the subject of continuous time filters.
FilterSpecifications
→ ContinuousTime Filter
→ SwitchedCapacitor Filter
Ideal Filter:Magnitude
1.0
0.00 fcutoff =
fPassbandFrequency
Passband Stopband Phase
0° 0Frequency
Slope =-Time delay
This specification cannot be achieve by realizable filters because: • An instantaneous transition from a gain of 1 to 0 is not possible. • A band of zero gain is not possible.Therefore, we develop filter approximations which closely approximate the ideal filterbut are realizable.
Chapter 9 – Section 7 (5/2/04) Page 9.7-2
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Characterization of FiltersA low pass filter magnitude response.
T(jω)
T(j0)T(jωPB)
T(jωSB)
ωSBωPB0
0ω
T(jωPB)/T(j0)
T(jωSB)/T(j0)
ωSB/ωPB=Ωn
1
0
Tn(jωn)
1ωn0
(a.) (b.)Figure 9.7-1 - (a.) Low pass filter. (b.) Normalized, low pass filter.
Three basic properties of filters.1.) Passband ripple = |T(j0) - T(jωPB)|.
2.) Stopband frequency = ωSB.
3.) Stopband gain/attenuation = T(jωSB).
For a normalized filter the basic properties are:1.) Passband ripple = T(jωPB)/T(j0) = T(jωPB) if T(j0) = 1.
2.) Stopband frequency (called the transition frequency) = Ωn = ωSB/ωPB.
3.) Stopband gain = T(jωSB)/T(j0) = T(jωSB) if T(j0) = 1.
Chapter 9 – Section 7 (5/2/04) Page 9.7-3
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Filter Specifications in Terms of Bode Plots (dB)
T(jωPB)
T(jωSB)
Ωn10 log10(ωn)
A(jωPB)
A(jωSB)
Ωn0
Tn(jωn) dB
10
(a.) (b.)Figure 9.7-2 - (a.) Low pass filter of Fig. 9.7-1 as a Bode plot. (b.) Low pass filter ofFig. 9.7-2a shown in terms of attenuation (A(jω) = 1/T(jω)).
An(jωn) dB
log10(ωn)
Therefore,Passband ripple = T(jωPB) dB
Stopband gain = T(jωSB) dB or Stopband attenuation = A(jωPB)
Transition frequency is still = Ωn = ωSB/ωPB
Chapter 9 – Section 7 (5/2/04) Page 9.7-4
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Butterworth Filter ApproximationThis approximation is maximally flatin the passband.
Butterworth MagnitudeApproximation:
TLPn(jωn) =
1
1 + ε2 ω2Nn
where N is the order of theapproximation and ε is defined inthe above plot.The magnitude of the Butterworth filter approximation at ωSB is given as
TLPn
jωSB
ωPB = |TLPn(jΩn)| = TSB = 1
1 + ε2 Ω2Nn
This equation in terms of dB is useful for finding N given the filter specifications.
20 log10(TSB) = TSB (dB) = -10 log10
1 + ε2 Ω
2Nn
Normalized Frequency, ωn
0 0.5 1 1.5 2 2.5 30
0.2
0.4
0.6
0.8
1
A
N=5
N=3N=6
11+ε 2
|T LPn (jω )|n
N=8
N=10
N=4N=2
Chapter 9 – Section 7 (5/2/04) Page 9.7-5
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-1 - Determining the Order of A Butterworth Filter ApproximationAssume that a normalized, low-pass filter is specified as TPB = -3dB, TSB = -20 dB,
and Ωn = 1.5. Find the smallest integer value of N of the Butterworth filter approximationwhich will satisfy this specification.Solution
TPB = -3dB corresponds to TPB = 0.707 which implies that ε = 1. Thus, substituting ε= 1 and Ωn = 1.5 into the equation at the bottom of the previous slide gives
TSB (dB) = - 10 log10 1 + 1.52N Substituting values of N into this equation gives,
TSB = -7.83 dB for N = 2-10.93 dB for N = 3-14.25 dB for N = 4-17.68 dB for N = 5-21.16 dB for N = 6.
Thus, N must be 6 or greater to meet the filter specification.
Chapter 9 – Section 7 (5/2/04) Page 9.7-6
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Poles and Quadratic Factors of Butterworth FunctionsTable 9.7-1 - Pole locations and quadratic factors (sn
2 + a1sn + 1) of normalized, low passButterworth functions for ε = 1. Odd orders have a product (sn+1).
N Poles a1 coefficient2 -0.70711 ± j0.70711 1.414213 -0.50000 ± j0.86603 1.000004 -0.38268 ± j0.92388
-0.92388 ± j0.382680.765361.84776
5 -0.30902 ± j0.95106-0.80902 ± j0.58779
0.618041.61804
6 -0.25882 ± j0.96593 -0.96593 ± j0.25882-0.70711 ± j0.70711
0.51764 1.931861.41421
7 -0.22252 ± j0.97493 -0.90097 ± j0.43388-0.62349 ± j0.78183
0.44505 1.801941.24698
8 -0.19509 ± j0.98079 -0.83147 ± j0.55557-0.55557 ± j0.83147 -0.98079 ± j0.19509
0.39018 1.662941.11114 1.96158
9 -0.17365 ± j0.98481 -0.76604 ± j0.64279-0.50000 ± j0.86603 -0.93969 ± j0.34202
0.34730 1.532081.00000 1.87938
10 -0.15643 ± j0.98769 -0.89101 ± j0.45399-0.45399 ± j0.89101 -0.98769 ± j0.15643-0.70711 ± j0.70711
0.31286 1.782020.90798 1.975381.41421
Chapter 9 – Section 7 (5/2/04) Page 9.7-7
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-2 - Finding the Butterworth Roots and Polynomial for a given NFind the roots for a Butterworth approximation with ε =1 for N = 5.
SolutionFor N = 5, the following first- and second-order products are obtained from Table
9.7-1
TLPn(sn) = T1(sn)T2(sn)T3(sn) =
1
sn+1
1
s2n+0.6180sn+1
1
s2n+1.6180sn+1
Illustration of the individual magnitude contributions of each product of TLPn(sn).
0
0.5
1
1.5
2
0 0.5 1 1.5 2 2.5 3
T1(jωn)
T2(jωn)
T3(jωn)
(jωnTLPn )
Mag
nitu
de
Normalized Frequency, ωn
Chapter 9 – Section 7 (5/2/04) Page 9.7-8
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Chebyshev Filter ApproximationThe magnitude response of theChebyshev filter approximation forε = 0.5088.
The magnitude of the normalized,Chebyshev, low-pass, filterapproximation can be expressed as
TLPn(jωn) =1
1 + ε2 cos2[Ncos-1(ωn)] ,
ωn ≤ 1and
TLPn(jωn) = 1
1 + ε2 cosh2[Ncosh-1(ωn)] , ωn > 1
where N is the order of the filter approximation and ε is defined as
|TLPn(ωPB)| = |TLPn(1)| = TPB = 1
1+ε2 .
N is determined from 20 log10(TSB) = TSB (dB) = -10log101 + ε2cosh2[Ncosh-1(Ωn)]
0
0.2
0.4
0.6
0.8
1
0 0.5 1 1.5 2 2.5 3
TLPn(jωn)
A
N=5
N=2
N=4
N=3
1
1+ε2
Normalized Frequency, ωn
Chapter 9 – Section 7 (5/2/04) Page 9.7-9
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-3 - Determining the Order of A Chebyshev Filter ApproximationRepeat Ex. 9.7-1 for the Chebyshev filter approximation.
SolutionIn Ex. 9.7-2, ε = 1 which means the ripple width is 3 dB or TPB = 0.707. Now we
substitute ε = 1 into
20 log10(TSB) = TSB (dB) = -10log101 + ε2cosh2[Ncosh-1(Ωn)]
and find the value of N which satisfies TSB = - 20dB.For N = 2, → TSB = - 11.22 dB.For N =3, → TSB = -19.14 dB.For N = 4, → TSB = -27.43 dB.
Thus N = 4 must be used although N = 3 almost satisfies the specifications. This resultcompares with N = 6 for the Butterworth approximation.
Chapter 9 – Section 7 (5/2/04) Page 9.7-10
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Poles and Quadratic Factors of Chebyshev FunctionsTable 9.7-2 - Pole locations and quadratic factors (a0 + a1sn + sn
2) of normalized, low passChebyshev functions for ε = 0.5088 (1dB).
N Normalized PoleLocations
a0 a1
2 -0.54887 ± j0.89513 1.10251 1.097733 -0.24709 ± j0.96600
-0.494170.99420 0.49417
4 -0.13954 ± j0.98338-0.33687 ± j0.40733
0.986500.27940
0.279070.67374
5 -0.08946 ± j0.99011-0.23421 ± j0.61192
-0.28949
0.988310.42930
0.178920.46841
6 -0.06218 ± j0.99341-0.16988 ± j0.72723-0.23206 ± j0.26618
0.990730.557720.12471
0.124360.339760.46413
7 -0.04571 ± j0.99528-0.12807 ± j0.79816-0.18507 ± j0.44294
-0.20541
0.992680.653460.23045
0.091420.256150.37014
Chapter 9 – Section 7 (5/2/04) Page 9.7-11
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-4 - Finding the Chebyshev Roots for a given NFind the roots for the Chebyshev approximation with ε =1 for N = 5.
SolutionFor N = 5, we get the following quadratic factors which give the transfer function as
TLPn(sn) = T1(sn)T2(sn)T3(sn) =
0.2895
sn+0.2895
0.9883
s2n+0.1789sn+0.9883
0.4293
s2n+0.4684sn+0.4293
.
Chapter 9 – Section 7 (5/2/04) Page 9.7-12
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Other ApproximationsThomson Filters - Maximally flat magnitude and linear phase1
Elliptic Filters - Ripple both in the passband and stopband, the smallest transition regionof all filters.2
An excellent collection of filter approximations and data is found in A.I. Zverev,Handbook of Filter Synthesis, John Wiley & Sons, Inc., New York, 1967.
1 W.E. Thomson, “Delay Networks Having Maximally Flat Frequency Characteristics,” Proc. IEEE, part 3, vol. 96, Nov. 1949, pp. 487-490.2 W. Cauer, Synthesis of Linear Communication Networks, McGraw-Hill Book Co., New York, NY, 1958.
Chapter 9 – Section 7 (5/2/04) Page 9.7-13
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
GENERAL APPROACH FOR CONTINUOUS AND SC FILTER DESIGNApproach
Low-Pass,NormalizedFilter with a passband of 1 rps and an impedance of 1 ohm.
Denormalize the Filter
Realization
Cascade of First- and/or Second-Order
Stages
First-OrderReplacement
of LadderComponents
Frequency Transform the Roots to HP,
BP, or BS
Frequency Transform the L's and C's to HP, BP, or BS
Normalized LP Filter
RootLocations
Normalized Low-Pass
RLC Ladder Realization
All designs start with a normalized, low pass filter with a passband of 1 radian/second andan impedance of 1Ω that will satisfy the filter specification.1.) Cascade approach - starts with the normalized, low pass filter root locations.2.) Ladder approach - starts with the normalized, low pass, RLC ladder realizations.
Chapter 9 – Section 7 (5/2/04) Page 9.7-14
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
A Design Procedure for the Low Pass, SC Filters Using the Cascade Approach
1.) From TPB, TSB, and Ωn (or APB, ASB, and Ωn) determine the required order of thefilter approximation, N.
2.) From tables similar to Table 9.7-1 and 9.7-2 find the normalized poles of theapproximation.
3.) Group the complex-conjugate poles into second-order realizations. For odd-orderrealizations there will be one first-order term.
4.) Realize each of the terms using the first- and second-order blocks of the previouslectures.
5.) Cascade the realizations in the order from input to output of the lowest-Q stage first(first-order stages generally should be first).
More information can be found elsewhere1,2,3,4.
1 K.R. Laker and W.M.C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw Hill, New York, 1994.2 P.E. Allen and E. Sanchez-Sinencio, Switched Capacitor Circuits, Van Nostrand Reinhold, New York, 1984.3 R. Gregorian and G.C. Temes, Analog MOS Integrated Circuits for Signal Processing, John Wiley & Sons, New York, 1987.4 L.P. Huelsman and P.E. Allen, Introduction to the Theory and Design of Active Filters, McGraw Hill Book Company, New York, 1980.
Chapter 9 – Section 7 (5/2/04) Page 9.7-15
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-5 - Fifth-order, Low Pass, SC Filter using the Cascade ApproachDesign a cascade, switched capacitor realization for a Chebyshev filter approximation
to the filter specifications of TPB = -1dB, TSB = -25dB, fPB = 1kHz and fSB = 1.5kHz. Givea schematic and component value for the realization. Also simulate the realization andcompare to an ideal realization. Use a clock frequency of 20kHz.SolutionFirst we see that Ωn = 1.5. Next, recall that when TPB = -1dB that this corresponds to ε =0.5088. We find that N = 5 satisfies the specifications (TSB = -29.9dB). Using the resultsof previous lecture, we may write TLPn(sn) as
TLPn(sn) =
0.2895
sn+0.2895
0.9883
s2n+0.1789sn+0.9883
0.4293
s2n+0.4684sn+0.4293
(1)
Next, we design each of the three stagesindividually.Stage 1 - First-order Stage
Let us select the first-order stage shown. We willassume that fc is much greater than fBP (i.e. 100) and usetransfer function shown below to accomplish the design.
T1(s) ≈ α11/α21
1 + s(T/α21) (2)
+-φ1
φ1φ2
φ2
φ2
φ1
α11C11α21C11
C11
Vin(ejω)
Stage 1
V2(ejω)
Chapter 9 – Section 7 (5/2/04) Page 9.7-16
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-5 - ContinuedNote that we have used the second subscript 1 to denote the first stage. Before we
can use this equation we must normalize the sT factor. This normalization isaccomplished by
sT =
s
ωPB · (ωPBT) = snTn . (3)
Therefore, Eq. (2) can be written as
T1(sn) ≈ α11/α21
1 + sn(Tn/α21) = α11/Tn
sn + α21/Tn (4)
where α11 = C11/C and α21 = C21/C.
Equating Eq. (4) to the first term in TLPn(sn) gives the design of first-order stage as
α21 = α11 = 0.2895Tn = 0.2895·ωPB
fc =
0.2895·2000π20,000 = 0.0909
The sum of capacitances for the first stage is
First-stage capacitance = 2 + 1
0.0909 = 13 units of capacitance
Chapter 9 – Section 7 (5/2/04) Page 9.7-17
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-5 - ContinuedStage 2 – 2nd-order, high-Q StageThe next product of TLPn(sn) is
0.9883
s 2n + 0.1789sn + 0.9883
= T(0)ω 2n
s2n +
ωnQ sn + ω 2n
(5)
where T(0) = 1, ωn = 0.9941 and Q = (0.9941/0.1789) = 5.56. Therefore, select the low-pass version of the high-Q biquad. First, apply the normalization of Eq. (3) to get
T2(sn) ≈
-
α62s 2n + snα32α52
Tn +
α12α52
T 2n
s 2n + snα42α52
Tn +
α22α52
T 2n
. (6)
To get a low pass realization, select α32 = α62 = 0 to get
T2(sn) ≈ -(α12α52/T 2n )
s 2n + snα42α52
Tn +
α22α52
T 2n
. (7)
+-φ2
φ1φ1
φ2
α12C12
C12
+-φ1
φ1φ2
φ2
φ2
φ1
α52C22
α22C12
C22
α42C12
V3(ejω)V2(ejω)
Stage 2
Chapter 9 – Section 7 (5/2/04) Page 9.7-18
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-5 - ContinuedEquating Eq. (7) to the middle term of TLPn(sn) gives
α12α52 = α22α52 = 0.9883T2n =
0.9883·ωPB2
fc2 =
0.9883·4π2
400 = 0.09754
and
α42α52 = 0.1789Tn = 0.1789·ωPB
fc =
0.1789·2π20 = 0.05620
Choose a12 = a22 = α52 to get optimum voltage scaling. Thus we get, α12 = α22 = α52 =0.3123 and α42 = 0.05620/0.3123 = 0.1800. The second-stage capacitance is
Second-stage capacitance = 1 + 3(0.3123)
0.1800 + 2
0.1800 = 17.316 units of capacitance
Stage 3 - Second-order, Low-Q StageThe last product of TLPn(sn) is
0.4293
s2n + 0.4684sn + 0.4293
= T(0)ω 2n
s 2n + (ωn/Q)sn + ω 2n (8)
where we see that T(0) = 1, ωn = 0.6552 and Q = (0.6552/0.4684) = 1.3988. Therefore,select the low pass version of the low-Q biquad. Apply the normalization of Eq. (3) to get
+-φ2
φ1φ1
φ2
α13C13
C13
+-φ1
φ1φ2
φ2
φ2
φ1
α53C23α21C13
C23
α63C23
Stage 3
V3(ejω)Vout(ejω)
Chapter 9 – Section 7 (5/2/04) Page 9.7-19
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-5 - Continued
T3(sn) ≈
-
α33s 2n + snα43
Tn +
α13α53
T 2n
s 2n + snα63
Tn +
α23α53
T 2n
. (9)
To get a low pass realization, select α33 = α43 = 0 to get
T3(sn) ≈ - (α13α53/T 2n )
s 2n + snα63
Tn +
α23α53
T 2n
. (10)
Equating Eq. (10) to the last term of TLPn(sn) gives
α13α53 = α23α53 = 0.4293T 2n = 0.4293·ωPB
2
fc2 =
0.4293·4π2
400 = 0.04184
andα63 = 0.4684Tn = (0.4684·ωPB/fc) = (0.4684·2π/20) = 0.1472
Choose a13 = a23 = α53 to get optimum voltage scaling. Thus , α13 = α23 = α53 = 0.2058and α63 = 0.1472. The third-stage capacitance is
3rd-stage capacitance = 1+(3(0.2058)/0.1472)+(2/0.1472) =18.78 units of capacitanceThe total capacitance of this design is 13 + 17.32 + 18.78 = 49.10 units of capacitance.
Chapter 9 – Section 7 (5/2/04) Page 9.7-20
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-5 - ContinuedFinal design with stage 3 second to maximize the dynamic range.
+-φ1
φ1φ2
φ2
φ2
φ1
α11C11α21C11
C11
+-φ2
φ1φ1
φ2
α13C13
C13
+-φ1
φ1φ2
φ2
φ2
φ1
α53C23α23C13
C23
α63C23
+-φ2
φ1φ1
φ2
α12C12
C12
+-φ1
φ1φ2
φ2
φ2
φ1
α52C22
α22C12
C22
α42C12
Vin(ejω)
Vout(ejω)
Stage 1
Stage 3
Stage 2
Figure 9.7-7 - Fifth-order, Chebyshev, low pass, switched capacitor filterof Example 9.7-5.
Chapter 9 – Section 7 (5/2/04) Page 9.7-21
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-5 - ContinuedSimulated Frequency Response:
-70
-60
-50
-40
-30
-20
-10
0
0 500 1000 1500 2000 2500 3000 3500Frequency (Hz)
Mag
nitu
de (d
B)
Stage 1 Output
Stage 3 Output
Stage 2 Output(Filter Output)
Figure 9.7-8a - Simulated magnitude response of Ex. 9.7-5Frequency (Hz)
-200
-150
-100
-50
0
50
100
150
200
0 500 1000 1500 2000 2500 3000 3500
Phas
e (D
egre
es)
Stage 2 Phase Shift(Filter Output)
Stage 1 Phase Shift
Stage 3 Phase Shift
Figure 9.7-8b - Simulated phase response of Ex. 9.7-5
Comments:• There appears to be a sinx/x effect on the magnitude which causes the passband
specification to not be satisfied. This can be avoided by prewarping the specificationsbefore designing the filter.
• Stopband specifications met• None of the outputs of the biquads exceeds 0 dB (Need to check internal biquad nodes)
Chapter 9 – Section 7 (5/2/04) Page 9.7-22
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-5 – Continued
SPICE Input File: ******** 08/29/97 13:17:44 ****************PSpice 5.2 (Jul 1992) ********
*SPICE FILE FOR EXAMPLE 9.7-5*EXAMPLE 9-7-5: nodes 5 is the output*of 1st stage, node 13 : second stage (in*the figure it is second while in design it *isthird, low Q stage), and node 21 is the*final output of the *filter.
**** CIRCUIT DESCRIPTION ****
VIN 1 0 DC 0 AC 1
*.PARAM CNC=1 CNC_1=1 CPC_1=1
XNC1 1 2 3 4 NC1XUSCP1 3 4 5 6 USCPXPC1 5 6 3 4 PC1XAMP1 3 4 5 6 AMPXPC2 5 6 7 8 PC2XUSCP2 7 8 9 10 USCPXAMP2 7 8 9 10 AMPXNC3 9 10 11 12 NC3XAMP3 11 12 13 14 AMPXUSCP3 11 12 13 14 USCPXPC4 13 14 11 12 PC4XPC5 13 14 7 8 PC2XPC6 13 14 15 16 PC6XAMP4 15 16 17 18 AMPXUSCP4 15 16 17 18 USCP
XNC7 17 18 19 20 NC7XAMP5 19 20 21 22 AMPXUSCP5 19 20 21 22 USCPXUSCP6 21 22 15 16 USCP1XPC8 21 22 15 16 PC6
SUBCKT DELAY 1 2 3ED 4 0 1 2 1TD 4 0 3 0 ZO=1K TD=25USRDO 3 0 1K.ENDS DELAY
.SUBCKT NC1 1 2 3 4RNC1 1 0 11.0011XNC1 1 0 10 DELAYGNC1 1 0 10 0 0.0909XNC2 1 4 14 DELAYGNC2 4 1 14 0 0.0909XNC3 4 0 40 DELAYGNC3 4 0 40 0 0.0909RNC2 4 0 11.0011.ENDS NC1
.SUBCKT NC3 1 2 3 4RNC1 1 0 4.8581XNC1 1 0 10 DELAYGNC1 1 0 10 0 0.2058XNC2 1 4 14 DELAYGNC2 4 1 14 0 0.2058XNC3 4 0 40 DELAYGNC3 4 0 40 0 0.2058RNC2 4 0 4.8581Ends NC3
Chapter 9 – Section 7 (5/2/04) Page 9.7-23
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-5 - Continued
Spice Input File-Continued
.SUBCKT NC7 1 2 3 4RNC1 1 0 3.2018XNC1 1 0 10 DELAYGNC1 1 0 10 0 0.3123XNC2 1 4 14 DELAYGNC2 4 1 14 0 0.3123XNC3 4 0 40 DELAYGNC3 4 0 40 0 0.3123RNC2 4 0 3.2018.ENDS NC7
.SUBCKT PC1 1 2 3 4RPC1 2 4 11.0011.ENDS PC1
.SUBCKT PC2 1 2 3 4RPC1 2 4 4.8581.ENDS PC2
.SUBCKT PC4 1 2 3 4RPC1 2 4 6.7980.ENDS PC4
.SUBCKT PC6 1 2 3 4RPC1 2 4 3.2018.ENDS PC6
.SUBCKT USCP 1 2 3 4R1 1 3 1R2 2 4 1XUSC1 1 2 12 DELAYGUSC1 1 2 12 0 1XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 1XUSC3 3 2 32 DELAYGUSC3 2 3 32 0 1XUSC4 3 4 34 DELAYGUSC4 3 4 34 0 1.ENDS USCP
.SUBCKT USCP1 1 2 3 4R1 1 3 5.5586R2 2 4 5.5586XUSC1 1 2 12 DELAYGUSC1 1 2 12 0 0.1799XUSC2 1 4 14 DELAYGUSC2 4 1 14 0 .1799XUSC3 3 2 32 DELAYGUSC3 2 3 32 0 .1799XUSC4 3 4 34 DELAYGUSC4 3 4 34 0 .1799.ENDS USCP1
.SUBCKT AMP 1 2 3 4EODD 3 0 1 0 1E6EVEN 4 0 2 0 1E6.ENDS AMP
.AC LIN 100 10 3K
.PRINT AC V(5) VP(5) V(13)VP(13) V(21) VP(21).PROBE.END
Chapter 9 – Section 7 (5/2/04) Page 9.7-24
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-5 - Continued
Spice Input File-Continued
.SUBCKT NC7 1 2 3 4RNC1 1 0 3.2018XNC1 1 0 10 DELAYGNC1 1 0 10 0 0.3123XNC2 1 4 14 DELAYGNC2 4 1 14 0 0.3123XNC3 4 0 40 DELAYGNC3 4 0 40 0 0.3123RNC2 4 0 3.2018.ENDS NC
.SUBCKT PC1 1 2 3 4RPC1 2 4 11.0011.ENDS PC1
.SUBCKT PC2 1 2 3 4RPC1 2 4 4.8581.ENDS PC2
.SUBCKT PC4 1 2 3 4RPC1 2 4 6.7980.ENDS PC4
.SUBCKT PC6 1 2 3 4RPC1 2 4 3.2018.ENDS PC6
.SUBCKT USCP 1 2 3 4R1 1 3 1R2 2 4 1XUSC1 1 2 12 DELAYGUSC1 1 2 12 0 1XUSC2 1 4 14 DELAY
GUSC2 4 1 14 0 1XUSC3 3 2 32 DELAYGUSC3 2 3 32 0 1XUSC4 3 4 34 DELAYGUSC4 3 4 34 0 1.ENDS USCP
.SUBCKT USCP1 1 2 3 4R1 1 3 5.5586R2 2 4 5.5586XUSC1 1 2 12 DELAYGUSC1 1 2 12 0 0.1799XUSC2 1 4 14 DELAYGUSC2 4 1 14 0 .1799XUSC3 3 2 32 DELAYGUSC3 2 3 32 0 .1799XUSC4 3 4 34 DELAYGUSC4 3 4 34 0 .1799.ENDS USCP1
.SUBCKT AMP 1 2 3 4EODD 3 0 1 0 1E6EVEN 4 0 2 0 1E6.ENDS AMP
.AC LIN 100 10 3K
.PRINT AC V(5) VP(5) V(13)VP(13) V(21) VP(21).PROBE.END
Chapter 9 – Section 7 (5/2/04) Page 9.7-25
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-5 - ContinuedSwitcap2 Input File (The exact same results were obtained as for SPICE)
TITLE: EXAMPLE 9-7-5
OPTIONS; NOLIST; GRID; END;
TIMING; PERIOD 50E-6; CLOCK CLK 1 (0 25/50); END;
SUBCKT (1 100) STG1; S1 (1 2) CLK; S2 (2 0) #CLK; S3 (3 4) #CLK; S4 (3 0) CLK; S5 (5 100) #CLK; S6 (5 0) CLK; CL11 (2 3) 0.0909; CL21 (3 5) 0.0909; E1 (100 0 0 4)1E6; END;
SUBCKT (200 300) STG2; S1 (200 2) #CLK; S2 (2 0) CLK; S3 (3 0) CLK; S4 (3 4) #CLK; S5 (6 5) CLK;
S6 (6 0) #CLK; S7 (7 0) CLK; S8 (7 8) #CLK; S9 (300 9) #CLK; S10 (9 0) #CLK; CL12 (2 3) 0.3123; CL22 (3 9) 0.3123; CL42 (4 300) 0.1799; C12 (4 5) 1; CL52 (6 7) 0.3123; C22 (8 300) 1; E1 (5 0 0 4) 1E6; E2 (300 0 0 8)1E6 END;
SUBCKT (100 200) STG3; S1 (100 2) #CLK; S2 (2 0) CLK; S3 (3 0) CLK; S4 (3 4) #CLK; S5 (6 5) CLK; S6 (6 0) #CLK; S7 (7 0) CLK; S8 (7 8) #CLK; S9 (200 9) #CLK; S10 (9 0) #CLK; CL13 (2 3) 0.2058; CL23 (3 9) 0.2058; CL63 (9 7) 0.1471; C13 (4 5) 1;
CL53 (6 7) 0.2058; C23 (8 200) 1; E1 (5 0 0 4) 1E6; E2 (200 0 0 8)1E6 END;
CIRCUIT; X1 (1 100) STG1; X2 (100 200) STG3; X3 (200 300) STG2; V1 (2 0); END;
ANALYZE SSS; INFREQ 1 3000 LIN 150; SET V1 AC 1.0 0.0; PRINT vdb(100) vp(100); PRINT vdb(200) vp(200); PRINT vdb(300) vp(300); PLOT vdb(300); END;
END;
Chapter 9 – Section 7 (5/2/04) Page 9.7-26
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Using the Cascade Approach for Other Types of FiltersOther types of filters are developed based on the low pass approach.
(a.) (b.)
(c.) (d.)
0 ωSBωPB
1
0 ω (rps)
TLP(jω)
TPB
TSB
TransitionRegion
A
B
One possiblefilter realization
ωPB
THP(jω)
1
00
ω (rps)
TPB
TSB
ωSB
TransitionRegionA
BOne possiblefilter realization
1
00
ω (rps)
TBP(jω)
ωPB1ωPB2 ωSB2ωSB1
TPB
TSB A
B C
D
One possiblefilter realizationLower
TransitionRegion Upper Transi-
tion Region
0ω (rps)
TBS(jω)
1
00
ω (rps)ωPB1 ωPB2ωSB2ωSB1
TPB
TSB
A
B
C
D
One possiblefilter realization
LowerTransition
Region
Upper Transi-tion Region
Practical magnitude responses of (a.) low pass, (b.) high pass, (c.) bandpass, and (d.)bandstop filter.
We will use transformations from the normalized, low pass filter to the normalizedhigh pass, bandpass or bandstop to achieve other types of filters.
Chapter 9 – Section 7 (5/2/04) Page 9.7-27
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
High Pass, SC Filters Using the Cascade ApproachNormalized, low pass to normalized high pass transformation:
sln = 1
shn
where shn is the normalized, high-pass frequency variable.A general form of the normalized, low-pass transfer function is
TLPn(sln) = p1lnp2lnp3ln···pNln
(sln+p1ln)(sln+p2ln)(sln+p3ln)···(sln+pNln)
where pkln is the kth normalized, low-pass pole.Applying the normalized, low-pass to high-pass transformation toTLPn(sln) gives
THPn(shn) = p1lnp2lnp3ln···pNln
1
shn+p1ln
1
shn+p2ln
1
shn+p3ln ···
1
shn+pNln
= s
Nhn
shn+1
p1ln
shn+1
p2ln
shn+1
p3ln···
shn+1
pNln
= s
Nhn
shn+p1hn shn+p2hn shn+p3hn ··· shn+pNhn
where pkhn is the kth normalized high-pass pole.Use high pass switched capacitor circuits to achieve the implementation.
Ωn is defined for the high pass normalized filter as: Ωn = 1Ωhn
= ωPBωSB
Chapter 9 – Section 7 (5/2/04) Page 9.7-28
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-6 - Design of a Butterworth, High-Pass FilterDesign a high-pass filter having a -3dB ripple bandwidth above 1 kHz and a gain of
less than -35 dB below 500 Hz using the Butterworth approximation. Use a clockfrequency of 100kHz.Solution
From the specification, we know that TPB = -3 dB and TSB = -35 dB. Also, Ωn = 2(Ωhn = 0.5). ε = 1 because TPB = -3 dB. Therefore, find that N = 6 will give TSB = -36.12dB which is the lowest, integer value of N which meets the specifications.
Next, the normalized, low-pass poles are found from Table 9.7-1 asp1ln, p6ln = -0.2588 ± j 0.9659p2ln, p5ln = -0.7071 ± j 0.7071
andp3ln, p4ln = -0.9659 ± j 0.2588
Inverting the normalized, low-pass poles gives the normalized, high-pass poles which are
p1hn, p6hn = -0.2588 -+ j 0.9659
p2hn, p5hn = -0.7071 -+ j 0.7071and
p3hn, p4hn = -0.9659 -+ j 0.2588 .
We note the inversion of the Butterworth poles simply changes the sign of the imaginarypart of the pole.
Chapter 9 – Section 7 (5/2/04) Page 9.7-29
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-6 - ContinuedThe next step is to group the poles in second-order products, since there are no first-
order products. This result gives the following normalized, high-pass transfer function.THPn(shn) = T1(shn)T2(shn)T3(shn)
=
s2hn
(shn+p1hn)(shn+p6hn)
s2hn
(shn+p2hn)(shn+p5hn)
s2hn
(shn+p3hn)(shn+p4hn)
=
s
2hn
s2hn+0.5176shn+1
s
2hn
s2hn+1.4141shn+1
s
2hn
s2hn+1.9318shn+1
.
Now we are in a position to do the stage-by-stage design. We see that the Q’s ofeach stage are Q1 = 1/0.5176 = 1.932, Q2 = 1/1.414 = 0.707, and Q3 = 1/1.9318 = 0.5176.Therefore, we will choose the low-Q biquad to implement the realization of this example.The low-Q biquad design equations are:
α1 = (K0Tn/ωon) , α2 = |α5| = ωonTn, α3 = K2, α4 = K1Tn, and α6 = (ωonTn/Q) .For the high pass,
K0=K1=0 and K2=1, so that α1=α4=0 and α2=|α5| = ωonTn, α3 = K2 and α6 = ωonTn
Q .Stage 1
α21=α51=(ωPB/fc)=(2π·103/105)=0.06283, α31 = 1,and α61 = (ωPB/Qfc) = (0.06283/1.932) = 0.03252
Chapter 9 – Section 7 (5/2/04) Page 9.7-30
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-6 - ContinuedStage 2
α22 = α52 = ωPBfc
= 2π·103
105 = 0.06283,
α32 = 1, and
α62 = ωPBQfc =
0.062830.707 = 0.08884
Stage 3
α23 = α53 = ωPBfc
= 2π·103
105 = 0.06283,
α33 = 1, and
α63 = ωPBQfc =
0.062830.5176 = 0.1214
Realization →Lowest Q stages are first in the cascade
realization.Σ capacitances = 104.62 units of capacitance
+-
C23Vin(z)e
φ1
φ1
φ2 α23C13
φ2
+-
C13
φ2
α63C23
φ2
α53C23
φ1
V3(z)eα33C23
φ1
φ1φ2
+-
C21 Vout(z)e
φ1
φ1
φ2 α21C11
φ2
+-
C11
φ2
α61C21
φ2
α51C21
φ1
α31C21
φ1
φ1φ2
V2(z)e
φ1φ1
φ2
α21C12 φ2C12
α62C22
φ2
α52C22
α32C22
φ1
φ1
φ2
+-
C22
+-
φ1φ2
Stage 3
Stage 2
Stage 1
Chapter 9 – Section 7 (5/2/04) Page 9.7-31
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Bandpass, SC Filters Using the Cascade Approach1.) Define the passband and stopband as
BW = ωPB2 - ωPB1 and SW = ωSB2 - ωSB1where ωPB2 (ωPB1) is the larger (smaller) passband of the bandpass filter. ωSB2 (ωSB1) isthe larger (smaller) stopband frequency.2.) Geometrically centered bandpass filters have the following relationship:
ωr = ωPB1ωPB2 = ωSB2ωSB1 3.) Define a normalized low-pass to unnormalized bandpass transformation as
sln = 1
BW
sb
2 + ωr2
sb =
1BW
sb + ωr
2
sb .
4.) A normalized low-pass to normalized bandpass transformation is achieved bydividing the bandpass variable, sb, by the geometric center frequency, ωr, to get
sln =
ωr
BW
sb
ωr + 1
(sb/ωr) =
ωr
BW
sbn + 1
sbn where sbn =
sbωr .
5.) Multiply by BW/ωr and define yet a further normalization as
sln' =
BW
ωr sln = Ωbsln = Ωb
sl
ωPB =
sbn + 1
sbn where Ωb =
BWωr .
6.) Solve for sbn in terms of sln' from the following quadratic equation.
s2bn - sln' sbn + 1 = 0 → sbn =
sln' /2 ±
sln' /2 2 - 1 .
Chapter 9 – Section 7 (5/2/04) Page 9.7-32
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Illustration of the Above Approach
(a.) (b.)
0 ωbn (rps)
1
00
TPBn(jωb)
ωr-ωr
BW BW
ωb (rps)(c.)(d.)
Bandpass Normalization
Normalized low-pass to normalized bandpass
transformation
BandpassDenormalization
1
00-1 1
TLPn(jωln )
ωln (rps)ωrωPB
1
00
1Ωb-Ωb
TLPn(jωln' )
ωln' (rps)
sln'
2 ±
sln'
2
2
- 1
↓sbn
1
0
TBPn(jωbn )
ΩbΩb
1-1
sb ← Ωbsbn = BWωr
sbn
Ωbsln = BWωr
sln → sln'
Figure 9.7-10 - Illustration of the development of a bandpass filter from a low-pass filter.(a.) Ideal normalized, low-pass filter. (b.) Normalization of (a.) for bandpasstransformation. (c.) Application of low-pass to bandpass transformation. (d.)Denormalized bandpass filter.
Chapter 9 – Section 7 (5/2/04) Page 9.7-33
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Bandpass Design Procedure for the Cascade Approach1.) The ratio of the stop bandwidth to the pass bandwidth is defined as
Ωn = SWBW =
ωSB2 - ωSB1
ωPB2 - ωPB1.
2.) From TPB, TSB, and Ωn, find the order N or the filter.
3.) Find the normalized, low-pass poles, p‘ kln.
4.) The normalized bandpass poles can be found from the normalized, low pass poles, p‘ kln
using
pkbn = p‘
kln2 ±
p ‘
kln2
2 - 1 .
For each pole of the low-pass filter, two polesresult for the bandpass filter.
Figure 9.7-11 - Illustration of how thenormalized, low-pass, complex conjugatepoles are transformed into two normalized,bandpass, complex conjugate poles.
pjln'
pkln'
= pjln' *
pkbn*
pjbn*
pjbn
pkbn
jωln'
σln' σbn
jωbn
Low-pass PolesNormalized by ωPBωr
BWNormalized
Bandpass Poles
Chapter 9 – Section 7 (5/2/04) Page 9.7-34
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Bandpass Design Procedure for the Cascade Approach - Continued5.) Group the poles and zeros into second-order products having the following form
Tk(sbn) = Kk sbn
(sbn + pkbn)(sbn + pjbn* ) =
Kk sbn(sbn+σkbn+jωkbn)(sbn+σkbn-jωkbn)
= Kk sbn
sbn2 +(2σkbn)sbn+(σbn
2 +ωkbn2 ) =
Tk(ωkon)
ωkon
Qksbn
sbn2 +
ωkon
Qksbn + ωkon
2
where j and k corresponds to the jth and kth low-pass poles which are a complexconjugate pair, Kk is a gain constant, and
ωkon = σkbn2 +ωkbn
2 and Qk = σbn
2 +ωkbn2
2σbn .
6.) Realize each second-order product with a bandpass switched capacitor biquad andcascade in the order of increasing Q.
Chapter 9 – Section 7 (5/2/04) Page 9.7-35
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-7 - Design of a Cascade Bandpass Switched Capacitor FilterDesign a bandpass, Butterworth filter having a -3dB ripple bandwidth of 200 Hz
geometrically centered at 1 kHz and a stopband of 1 kHz with an attenuation of 40 dB orgreater, geometrically centered at 1 kHz. The gain at 1 kHz is to be unity. Use a clockfrequency of 100kHz.Solution
From the specifications, we know that TPB = -3 dB and TSB = -40 dB. Also, Ωn =1000/200 = 5. ε = 1 because TPB = -3 dB. Therefore, we find that N = 3 will give TSB = -41.94 dB which is the lowest, integer value of N which meets the specifications.
Next, we evaluate the normalized, low-pass poles from Table 9.7-1 asp1ln, p3ln = -0.5000 ± j0.8660 and p2ln = -1.0000 .
Normalizing these poles by the bandpass normalization of Ωb = 200/1000 = 0.2 givesp1ln’, p3ln’= -0.1000 ± j 0.1732 and p2ln’= -0.2000 .
Each one of the pkln’will contribute a second-order term. The normalized bandpass
poles are found by using sbn =
sln' /2 ±
sln' /2 2 - 1 which results in 6 poles given as,
For p1ln’= -0.1000 + j0.1732 → p1bn, p2bn = -0.0543 + j1.0891, -0.0457 - j0.9159.For p2ln’= -0.1000 - j0.1732 → p3bn, p4bn = -0.0457 + j0.9159, -0.543 - j 1.0891.For p3ln’= -0.2000 → p5bn, p6bn = -0.1000 ± j 0.9950.
Chapter 9 – Section 7 (5/2/04) Page 9.7-36
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-7 - ContinuedThe normalized low-pass pole locations, pkln, the bandpass normalized, low-pass polelocations, pkln' , and the normalized bandpass poles, pkbn are shown below. Note that thebandpass poles have very high pole-Qs if BW < ωr.
p1ln
p2ln
p3ln
p3ln'
p2ln'p1ln
'
j1
-j1
-1σln
'
jωln'
(b.)(a.)
-1
j1
-j1
-0.5000
j0.8660
-j0.8660
jωln
σln
p1ln
p2ln
p3ln
σbn
p1bn
p2bn
p3bn
p4bn
p5bn
p6bn
jωbn
j1
-1
-j1
(c.)
3 zerosat ±j∞
Pole locations for Ex. 9.7-8. (a.) Normalized low-pass poles. (b.) Bandpassnormalized low-pass poles. (c.) Normalized bandpass poles.
Chapter 9 – Section 7 (5/2/04) Page 9.7-37
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-7 - ContinuedGrouping the complex conjugate bandpass poles gives the following second-order
transfer functions.
T1(sbn) = K1sbn
(s+p1bn)(s+p4bn) =
K1sbn(sbn+0.0543+j1.0891)(sbn+0.0543-j1.0891)
=
1.0904
10.0410 sbn
sbn2 +
1.0904
10.0410 sbn+1.09042
T2(sbn) = K2sbn
(s+p2bn)(s+p3bn) =
K2sbn(sbn+0.0457+j0.9159)(sbn+0.0457-j0.9159)
=
0.9170
10.0333 sbn
sbn2 +
0.9170
10.0333 sbn+0.91592 .
and
T3(sbn) = K3sbn
(s+p5bn)(s+p6bn) = K3sbn
(sbn+0.1000+j0.9950)(sbn+0.1000-j0.9950)
=
1.0000
5.0000 sbn
sbn2 +
1.0000
5.0000 sbn+1.00002 .
Chapter 9 – Section 7 (5/2/04) Page 9.7-38
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-7 - ContinuedNow we can begin the stage-by-stage design. Note that the Q’s of the stages are Q1
= 10.0410, Q2 = 10.0333, and Q3 = 5.0000. Therefore, use the high-Q biquad whosedesign equations are:
α1 = K0Tnωon
, α2 = |α5| = ωonTn , α3 = K1ωon
, α4 =1Q, and α6 = K2 .
For the bandpass realization K0 = K2 = 0 and K1 = ωon/Q, so that the design equationssimplify to
α1 = 0, α2 = |α5| = ωon,Tn = ωon·ωr
fc , α3 =
K1ωon
= ωon/Qωon =
1Q , α4 =
1Q, and α6 = 0
Stage 1
α11=α61=0, α21=|α51|=ωo1fc
= 1.0904·2πx103
105 =0.06815, α31=0.09959, and α41 =0.09959
Stage 2
α12=α62=0, α22=|α52|=ωo2fc
= 0.9159·2πx103
105 =0.05755, α32=0.09967, and α42 =0.09967
Stage 3
α13=α63=0, α23=|α53|=ωo3fc
= 1.0000·2πx103
105 = 0.06283, α31 = 0.2000, and α41 = 0.2000
Chapter 9 – Section 7 (5/2/04) Page 9.7-39
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-7 - ContinuedRealization:
+-
C11
φ2α21C11
φ1
+-
C21
φ1
φ2
α51C21
φ2
φ1 Vout(z)e
α41C11
α31C11
φ1φ2
+-
C13Vin(z)e
φ2α23C13
φ1
+-
C23
φ1
φ2
α53C23
φ2
φ1V3(z)
e
α43C13
α33C13
φ1φ2
+-
C12
φ2α22C12
φ1
+-
C22
φ1
φ2
α52C22
φ2
φ1
α42C12
α32C12
φ1φ2
V2(z)e
Stage 3
Stage 2
Stage 1
Chapter 9 – Section 7 (5/2/04) Page 9.7-40
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Higher Order Switched Capacitor Filters - Ladder ApproachThe ladder approach to filter design starts from RLC realizations of the desired filterspecification.These RLC realizations are called prototype circuits.Advantage: • Less sensitive to capacitor ratios.Disadvantage: • Design approach more complex • Requires a prototype realizationSingly-terminated RLC prototype filters:
(a.)
(b.)
1
+
-
+
-
L2nLN,n
CN-1,n C3n C1nVin(sn) Vout(sn)
1
+
-
+
-
C2nCN-1,n
LN,n L3n L1n
Vin(sn) Vout(sn)
Figure 9.7-12 - Singly-terminated, RLC prototype filters. (a.) N even. (b.) N odd.
Chapter 9 – Section 7 (5/2/04) Page 9.7-41
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Formulation of the State Variables of a Prototype CircuitState Variables:The state variables of a circuit are the current through an element or the voltage across it.
The number of state variables to solve a circuit= number of inductors and capacitors - inductor cutsets and capacitor loops.
An inductor cutset is a node where only inductors are connected.A capacitor loop is a loop where only capacitors are in series.
The approach: • Identify the “correct” state variables and formulate each state variable as function of
itself and other state variables. • Convert this function to a form synthesizable by switched capacitor.
A low pass example:
The state variables are I1 , V2, I3, V4, and I5.
(The “correct” state variables will be the currents in the series elements and the voltageacross the shunt elements.)
+
-
C2n
L3nL1n
Vout(sn)+
-
Vin(sn) C4n
L5nR0n
R6n+
-
+
-
I1 I3 I5
V2 V4
Chapter 9 – Section 7 (5/2/04) Page 9.7-42
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Writing the State Equations for a RLC Prototype CircuitAlternately use KVL and KCL for a loop and a node, respectively.
I1: Vin(s) - I1(s)R0n - sL1nI1(s) - V2(s) = 0
V2: I1(s) - sC2nV2(s) - I3(s) = 0
I3: V2(s) - sL3nI3(s) - V4(s) = 0
V4: I3(s) - sC4nV4(s) - I5(s) = 0
andI5: V4(s) - sL5nI5(s) - R6nI5n(s) = 0
However, we really would prefer Vout as a state variable instead of I5. This is achievedusing Ohm’s law to get for the last two equations:
V4: I3(s) - sC4nV4(s) - Vout(s)
R6n= 0
and
Vout: V4(s) - sL5nVout(s)
R6n - Vout = 0
Chapter 9 – Section 7 (5/2/04) Page 9.7-43
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Voltage Analogs of CurrentA voltage analog, Vj’, of a current Ij is defined as
Vj’ = RIj
where R’is an arbitrary resistance (normally 1 ohm).Rewriting the five state equations using voltage analogs for current gives:
V1’: Vin(s) -
V1’(s)
R (R0n + sL1n) - V2(s) = 0
V2:
V1’(s)
R - sC2nV2(s) -
V3’(s)
R = 0
V3’: V2(s) - sL3n
V3’(s)
R - V4(s) = 0
V4:
V3’(s)
R - sC4nV4(s) - Vout(s)
R6n = 0
and
Vout: V4(s) - sL5nVout(s)
R6n - Vout = 0
Chapter 9 – Section 7 (5/2/04) Page 9.7-44
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
The State Variable FunctionsSolve for each of the state variables a function of itself and other state variables.
V ' 1 (s) = R'
sL1n
Vin(s) - V2(s) -
R0n
R' V ' 1 (s)
V2(s) = 1
sR'C2n [V' 1 (s) - V' 3 (s) ]
V ' 3 (s) = R'
sL3n [V2(s) - V4(s)]
V4(s) = 1
sR'C4n [V' 3(s) -
R'
R6n Vout(s)]
Vout(s) = R6nsL5n
[V4(s) - Vout(s)]
Note that each of these functions is the integration of voltage variables and is easilyrealized using switched capacitor integrators.
Chapter 9 – Section 7 (5/2/04) Page 9.7-45
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
General Design Procedure for Low Pass, SC Ladder Filters1.) From TBP, TSB, and Ωn (or APB, ASB, and Ωn) determine the required order of the filterapproximation.2.) From tables similar to Table 9.7-3 and 9.7-2 find the RLC prototype filterapproximation.3.) Write the state equations and rearrange them so each state variable is equal to theintegrator of various inputs.4.) Realize each of rearranged state equations by switched capacitor integrators.
Chapter 9 – Section 7 (5/2/04) Page 9.7-46
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-8 - Fifth-order, Low Pass, Switched Capacitor Filter using the LadderApproach
Design a ladder, switched capacitor realization for a Chebyshev filter approximationto the filter specifications of TBP = -1dB, TSB = -25dB, fPB = 1kHz and fSB = 1.5 kHz. Givea schematic and component value for the realization. Also simulate the realization andcompare to an ideal realization. Use a clock frequency of 20 kHz. Adjust your design sothat it does not suffer the -6dB loss in the pass band. (Note that this example should beidentical with Ex. 1.)Solution
From previous work, we know that a 5th-order, Chebyshev approximation willsatisfy the specification. The corresponding low pass, RLC prototype filter is
1 Ω
+
-
+
-
Vin(sn) Vout(sn)1 Ω
C4n=1.0911 F
C2n=1.0911 F
L1n=2.1349 HL5n=2.1349 H L3n=3.0009 H
Next, we must find the state equations and express them in the form of an integrator.Fortunately, the above results can be directly used in this example.
Finally, use switched-capacitor integrators to realize each of the five state functionsand connect each of the realizations together.
Chapter 9 – Section 7 (5/2/04) Page 9.7-47
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-8 – Continued
L1n: V ' 1 (sn) = R'
sn L1n
Vin(sn) - V2(sn) -
R0n
R' V ' 1 (sn) (1)
This equation can be realized by the switched capacitorintegrator of Fig. 9.7-17 which has one noninverting inputand two inverting inputs. Therefore,
V’1(z) =
1z-1
α11Vin(z) - α21zV2(z) - α31zV‘1(z) (2)
However, since fPB < fc, replace z by 1 and z-1 by sT.
V‘1(sn) ≈
1snTn
α11Vin(s) - α21V2(s) - α31V‘1(s) (3)
Equating Eq. (1) to Eq. (3) gives the capacitor ratios for the first integrator as
α11 = α21 = R’TnL1n
= R’ωPBfcL1n
= 1·2000π
20,000·2.1349 = 0.1472
and
α31 = R0nTnL1n
= R0nωPBfcL1n
= 1·2000π
20,000·2.1349 = 0.1472
Assuming that R0n = R’ = 1Ω. Also, double the value of α11 (α11 = 0.2943) in order to get0dB gain. The total capacitance of the first integrator is
First integrator capacitance = 2 + 2(0.1472)
0.1472 + 1
0.1472 = 10.79 units of capacitance.
V2(ejω)+-
V'1(ejω)
C1Vin(ejω)
φ2
φ1
φ1
φ2φ1
α21C1
α11C1
φ2
φ1
α31C1
φ2
V'1(ejω)
Figure 9.7-17 - Realization of V1'.
Chapter 9 – Section 7 (5/2/04) Page 9.7-48
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-8 – Continued
C2n: V2(sn) = 1
sn R'C2n [V' 1 (sn) - V' 3 (sn)] (4)
This equation can be realized by the switchedcapacitor integrator of Fig. 9.7-18 which has onenoninverting input and one inverting input. As beforewe write that
V2(z) = 1
z-1
α12V‘1 (z) - α22zV
‘3(z) . (5)
Simplifying as above gives
V2(sn) ≈ 1
snTn
α12V‘1 (sn) - α22V
‘3(sn) . (6)
Equating Eq. (4) to Eq. (6) yields the design of the capacitor ratios for the secondintegrator as
α12 = α22 = Tn
R’C2n =
ωPBR’fcC2n
= 2000π
1·20,000·1.0911 = 0.2879.
The second integrator has a total capacitance of
Second integrator capacitance = 1
0.2879 + 2 = 5.47 units of capacitance.
V'3(ejω)+-
V'1(ejω)C2
φ2
φ1 φ1
φ2φ1
α22C2
α12C2
φ2
V2(ejω)
Figure 9.7-18 - Realization of V2.
Chapter 9 – Section 7 (5/2/04) Page 9.7-49
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-8 – Continued
L3n: V ' 3 (sn) = R'
sn L3n [V2(sn) - V4(sn)] (7)
Eq. (7) can be realized by the switched capacitorintegrator of Fig. 9.7-19 which has one noninvertinginput and one inverting input. For this circuit we get
V‘3(z) =
1z-1 α13V2 (z) - α23zV4(z) . (8)
Simplifying as above gives
V‘3(sn) ≈
1snTn
α13V2(sn) - α23V4(sn) . (9)
Equating Eq. (7) to Eq. (9) yields the capacitor ratios for the third integrator as
α13 = α23 = R’TnL3n
= R’ωPBfcL3n
= 1·2000π
20,000·3.0009 = 0.1047.
The third integrator has a total capacitance of
Third integrator capacitance = 1
0.1047 + 2 = 11.55 units of capacitance
V4(ejω)+-
V2(ejω)C3
φ2
φ1 φ1
φ2φ1
α23C3
α13C3
φ2
V'3(ejω)
Figure 9.7-19 - Realization of V3'.
Chapter 9 – Section 7 (5/2/04) Page 9.7-50
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-8 – Continued
C4n: V4(sn) = 1
sn R'C4n [V' 3( sn)-
R'
R6nVout(sn)] (10)
Eq. (10) can be realized by the switched capacitorintegrator of Fig. 9.7-20 with one noninverting andone inverting input. As before we write that
V4(z) = 1
z-1
α14V‘3 (z) - α24zVout(z) . (11)
Assuming that fPB < fc gives
V4(sn) ≈ 1
snTn
α14V‘3 (sn) - α24Vout(sn) . (12)
Equating Eq. (10) to Eq. (12) yields the design of the capacitor ratios for the fourthintegrator as
α14 = α24 = Tn
R’C4n =
ωPBR’fcC4n
= 2000π
1·20,000·1.0911 = 0.2879.
if R’ = R0n. In this case, we note that fourth integrator is identical to the second integratorwith the same total integrator capacitance.
Vout(ejω)+-
V'2(ejω)C4
φ2
φ1 φ1
φ2φ1
α24C4
α14C4
φ2
V4(ejω)
Figure 9.7-20 - Realization of V4.
Chapter 9 – Section 7 (5/2/04) Page 9.7-51
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-8 – Continued
L5n: Vout(sn) = R6n
snL5n [V4(sn) - Vout(sn)] (13)
The last state equation, Eq. (13), can be realized bythe switched capacitor integrator of Fig. 9.7-21 whichhas one noninverting input and one inverting input.For this circuit we get
Vout(z) = 1
z-1 α15V4 (z) - α25zVout(z) . (14)
Simplifying as before gives
Vout(sn) ≈ 1
snTn α15V4(sn) - α25Vout(sn) . (15)
Equating Eq. (13) to Eq. (15) yields the capacitor ratios for the fifth integrator as
α15 = α25 = R6nTnL3n
= R6nωPBfcL3n
= 1·2000π
20,000·2.1349 = 0.1472
where R6n = 1Ω.
Fifth integrator capacitance = 1
0.1472 + 2 = 8.79 units of capacitance
We see that the total capacitance of this filter is 10.79 + 5.47 + 11.53 + 5.47 + 8.79 =42.05. We note that Ex. 1 which used the cascade approach for the same specificationrequired 49.10 units of capacitance.
Vout(ejω)+-
V4(ejω)C5
φ2
φ1 φ1
φ2φ1
α25C5
α15C5
φ2
Vout(ejω)
Figure 9.7-21 - Realization of Vout.
Chapter 9 – Section 7 (5/2/04) Page 9.7-52
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-8 – ContinuedFinal realization of Ex. 9.7-8.
V2(ejω)
C1
Vin(ejω)
φ2
φ1
α21C1
2α11C1
α31C1
V'1(ejω)
C2
α22C2
α12C2
+-
+-
φ1
φ2
φ2
φ2
φ1
φ1
φ1
φ1
φ1
φ1
φ2 φ2
φ2C3
φ2
φ1
α23C3
α13C3
V'3(ejω)+-
φ1
φ2
φ1
V4(ejω)
C4
α24C4
α14C2
+-
φ1 φ1
φ2 φ2
φ2φ1
φ2
φ2
α25C5 Vout(ejω)+-
φ1
φ2
φ1
φ2
C5α15C5
Chapter 9 – Section 7 (5/2/04) Page 9.7-53
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-8 – ContinuedSimulated Frequency Response:
Frequency (Hz)
-70
-60
-50
-40
-30
-20
-10
0
10
0 500 1000 1500 2000 2500 3000 3500
Mag
nitu
de (d
B)
V1' Output
V2 Output
V3' Output
V4 Output
Filter Output
-200
-150
-100
-50
0
50
100
150
200
0 500 1000 1500 2000 2500 3000 3500
Phas
e Sh
ift (
Deg
rees
)
Frequency (Hz)
V1' Phase
V2 Phase
V3' Phase
V4 Phase
Filter Phase
Comments:• Both passband and stopband specifications satisfied.• Some of the op amp outputs are exceeding 0 dB (need to voltage scale for maximum dynamic range)
Chapter 9 – Section 7 (5/2/04) Page 9.7-54
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-8 – ContinuedSPICE Input File:
******* 08/29/97 13:12:51 ***************PSpice 5.2 (Jul 1992) ********
**** CIRCUIT DESCRIPTION ****
*SPICE FILE FOR EXAMPLE 9.7_5*Example 9.7-8 : ladder filter*Node 5 is the output at V1'*Node 7 is the output at V2*Node 9 is the output of V3'*Node 11 is the output of V4*Node 15 is the final output
VIN 1 0 DC 0 AC 1
*************************** V1' STAGEXNC11 1 2 3 4 NC11XPC11 7 8 3 4 PC1XPC12 5 6 3 4 PC1XUSC1 5 6 3 4 USCPXAMP1 3 4 5 6 AMP***************************V2 STAGEXNC21 5 6 19 20 NC2XPC21 9 10 19 20 PC2XUSC2 7 8 19 20 USCPXAMP2 19 20 7 8 AMP***************************V3' STAGEXNC31 7 8 13 14 NC3XPC31 11 12 13 14 PC3XUSC3 9 10 13 14 USCP
XAMP3 13 14 9 10 AMP***************************V4 STAGEXNC41 9 10 25 26 NC2XPC41 15 16 25 26 PC2XUSC4 11 12 25 26 USCPXAMP4 25 26 11 12 AMP***************************VOUT STAGEXNC51 11 12 17 18 NC1XPC51 15 16 17 18 PC1XUSC5 15 16 17 18 USCPXAMP5 17 18 15 16 AMP*************************
.SUBCKT DELAY 1 2 3ED 4 0 1 2 1TD 4 0 3 0 ZO=1K TD=25USRDO 3 0 1K.ENDS DELAY
.SUBCKT NC1 1 2 3 4RNC1 1 0 6.7934XNC1 1 0 10 DELAYGNC1 1 0 10 0 .1472XNC2 1 4 14 DELAYGNC2 4 1 14 0 .1472XNC3 4 0 40 DELAYGNC3 4 0 40 0 .1472RNC2 4 0 6.7934.ENDS NC1
Chapter 9 – Section 7 (5/2/04) Page 9.7-55
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-8 – ContinuedSPICE Input File:
.SUBCKT NC11 1 2 3 4RNC1 1 0 3.3978XNC1 1 0 10 DELAYGNC1 1 0 10 0 .2943XNC2 1 4 14 DELAYGNC2 4 1 14 0 .2943XNC3 4 0 40 DELAYGNC3 4 0 40 0 .2943RNC2 4 0 3.3978.ENDS NC11
.SUBCKT NC2 1 2 3 4RNC1 1 0 3.4730XNC1 1 0 10 DELAYGNC1 1 0 10 0 .2879XNC2 1 4 14 DELAYGNC2 4 1 14 0 0.2879XNC3 4 0 40 DELAYGNC3 4 0 40 0 0.2879RNC2 4 0 3.4730.ENDS NC2
.SUBCKT NC3 1 2 3 4RNC1 1 0 9.5521XNC1 1 0 10 DELAYGNC1 1 0 10 0 0.1047XNC2 1 4 14 DELAYGNC2 4 1 14 0 0.1047XNC3 4 0 40 DELAY
GNC3 4 0 40 0 0.1047RNC2 4 0 9.5521.ENDS NC3
.SUBCKT NC4 1 2 3 4RNC1 1 0 3.4730XNC1 1 0 10 DELAYGNC1 1 0 10 0 .2879XNC2 1 4 14 DELAYGNC2 4 1 14 0 .2879XNC3 4 0 40 DELAYGNC3 4 0 40 0 .1472RNC2 4 0 6.7955.ENDS NC4
.SUBCKT PC1 1 2 3 4RPC1 2 4 6.7934.ENDS PC1
.SUBCKT PC2 1 2 3 4RPC1 2 4 3.4730.ENDS PC2
.SUBCKT PC3 1 2 3 4RPC1 2 4 9.5521.ENDS PC3
Chapter 9 – Section 7 (5/2/04) Page 9.7-56
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-8 - ContinuedSwitcap2 Input File (The results are exactly the same as for the SPICE simulation)
TITLE: EXAMPLE 9-7-11
OPTIONS; NOLIST; GRID; END;
TIMING; PERIOD 50E-6; CLOCK CLK 1 (0 25/50); END;
SUBCKT (1 4) NC (P:CAP); S1 (1 2) CLK; S2 (2 0) #CLK; S3 (3 0) CLK; S4 (3 4) #CLK; C11 (2 3) CAP; END;
SUBCKT (1 4) PC (P:CAP1); S1 (1 2) #CLK; S2 (2 0) CLK; S3 (3 0) CLK; S4 (3 4) #CLK; C21 (2 3) CAP1; END;
CIRCUIT
/***** V1’ STAGE ****/ X11 (1 2) NC (0.2943); X12 (3 2) PC (0.1472); X13 (4 2) PC (0.1472); E11 (4 0 0 2) 1E6; C11 (2 4) 1;
/***** V2 STAGE ****/ X21 (1 2) NC (0.2879); X22 (3 2) PC (0.2879); E21 (3 0 0 6) 1E6; C21 (6 3) 1;
/***** V3’ STAGE ****/ X31 (3 8) NC (0.1047); X32 (7 8) PC (0.1047); E31 (5 0 0 8) 1E6; C31 (8 5) 1;
/***** V4 STAGE ****/ X41 (5 9) NC (0.2879); X42 (100 9) PC
(0.2879); E41 (7 0 0 9) 1E6; C41 (9 7) 1;
/***** VOUT STAGE****/ X51 (7 10) NC (0.1472); X52 (100 10) PC
(0.1472); E51 (100 0 0 10) 1E6; C51 (10 100) 1; V1 (1 0); END;
ANALYZE SSS; INFREQQ 20 3000 LOG 80; SET V1 AC 1.0 0.0; PRINT VDB(4) VP(4)VDB(3); PRINT VP(3) VDB(7) VP(7); PRINT VDB(100) VP(100); PLOT VDB(100); END;
END;
Chapter 9 – Section 7 (5/2/04) Page 9.7-57
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
High Pass Switched Capacitor Filters Using the Ladder ApproachHigh pass, switched capacitor filters using the ladder approach are achieved by
applying the following normalized, low pass to normalized, high pass transformation onthe RLC prototype circuit.
sln = 1
shn
This causes the following transformationon the inductors and capacitors of theRLC prototype:
Design Procedure:1.) Identify the appropriate RLC
prototype, low pass circuit to meetthe specifications.
2.) Transform each inductor and capacitor by the normalized, low pass to high passtransformation.
3.) Choose the state variables and write the state functions.4.) Realize the state functions using switched capacitor circuits.The problem: The realizations are derivative circuits.
sln → 1shn
Normalized Low-Pass Network
Normalized High-Pass Network
Lln
ClnLhn = 1
Cln
Chn = 1Lln
Chapter 9 – Section 7 (5/2/04) Page 9.7-58
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Switched Capacitor Derivative Circuit
+-
Vin(z) C2
φ2
φ1C1 Vout(z)
Figure 9.7-26 - (a.) Switched capacitor differentiatior circuit. (b.) Stray insensitive version of (a.). (c.) Modification to keep op amp output from being discharged to ground during φ1.
+-
Vin(z)
C2φ2
φ1
C1 Vout(z)
φ2
C2
(a.) (b.)
+-
C1
C1
φ1 φ1
φ1
φ2φ2
φ2Vout(z)Vin(z)
(c.)
Transfer function:φ1: (n-1)T < t < (n -0.5)T
v oc1(n -0.5)T = v
ein(n -1)T and v
oc2(n -0.5)T = 0
φ2: (n-0.5)T < t < (n )T
v e
out(n )T = - C1C2
v ein(n )T +
C1C2
v ein(n -1)T
∴ V e
out(z) = C1C2
V ein(z) - z-1
C1C2
V ein(z) = -
C1C2
(1-z-1)V ein(z) Hee(z) =
V e
out(z)
V ein(z)
= - C1C2
(1-z-1)
+-vin(n)
C1 C2
e
vin(n-1)e
vout(n)e
Chapter 9 – Section 7 (5/2/04) Page 9.7-59
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Frequency Response of the Derivative CircuitReplace z by ejωT to get,
Hee(ejωT) = - C1C2
1 - e-jωT = - C1C2
ejωT/2 - e-jωT/2
ejωT/2 = - C1C2
2jω sin(ωT/2) e-jωT/2
or
= - jωTC1
C2
sin(ωΤ/2)
ωΤ/2 (ε-jωΤ/2) =
-jω
ωo
sin(ωΤ/2)
ωΤ/2 e-jωT/2
= (Ideal)x(Mag. Error)x(Phase Error)where ωo = C2/(C1T).
Frequency Response for C2 = 0.2πC1:
|Hee(ejωT)
5
10
10
0 ωo= ωc2
ωc10
ωc
ContinuousTime
DiscreteTime
π
ω
Phase
-90°
-180°
-270°
0ωc2
ωcω
ContinuousTime
DiscreteTime
Chapter 9 – Section 7 (5/2/04) Page 9.7-60
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-9 - High Pass, Switched Capacitor Ladder FilterDesign a high pass, switched capacitor ladder filter starting from a third-order,
normalized, low pass Butterworth prototype filter. Assume the cutoff frequency is 1kHzand the clock frequency is 100kHz. Use the doubly terminated structure.SolutionA third-orderprototype filtertransformed to thenormalized highpass filter is shown.State Variable Eqs:
Vin=I1R0n+I1
snC1hn+V2 → I1 = snC1hn [Vin - I1R0n - V2] → V1’ = snC1hnR [Vin -
R0nR V1’-V2]
I1 = V2
snL2hn + I3 =
V2snL2hn
+ VoutR4n
→ V2 = snL2hn [I1 - VoutR4n
]→ V2 = snL2hn[ V1’R -
VoutR4n
]
V2 = I3
snC3hn + I3R4n → I3 = snC3hn [V2 - I3R4n] → Vout = snR4nC3hn [V2 - Vout]
Problem! Derivative circuit only has inverting inputs. Solution?1.) Use inverters.2.) Rearrange the eqs. to get integrators where possible.3.) Redefine the polarity of the voltages at internal nodes (180° phase reversal).
Vin
R0n=1Ω
L1n=1H
L3n=1H
C2n=2F
R4n=1Ω
+
-Vout
sln = shn1
Vin
R0n=1Ω
C1hn=1F
C3hn=1F
L2hn=0.5H
R4n=1Ω
+
-VoutI1
I3
+
-V2
Chapter 9 – Section 7 (5/2/04) Page 9.7-61
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-9 - ContinuedMake the first eq. into an integrator, reverse the sign of V2 and V1’, and use one inverter.
Note that V '1 = - V '1 andV2 = - V2 . Therefore the rewrite the first state equation as:
V '1=snC1hnR [Vin-R0nR V '1-V2] →V '1=
-V1’snC1hnR0n
+R
R0n(Vin -V2) → V '1 =
- V1’snC1hnR0n
-R
R0n(Vin+ V2 )
V2 = snL2hn[ V1’R -
VoutR4n
] → V2 = -snL2hn[- V1’
R - VoutR4n
] → V2 =-snL2hn
V1’
R + VoutR4n
Vout = snR4nC3hn [- V2 - Vout]C1hn:
This state equation can be realized by the SCintegrator shown with two inverting unswitched inputs.
∴ V1’ (z) = -α11zz -1 V1’ (z) - α21Vin(z) - α31 V2 (z)
Assuming that z -1 ≈ sT and z ≈ 1, we write that
V1’ (s) ≈ -α11sT V1’ (s) - α21Vin(s) - α31 V2 (s)
Normalizing this equation gives,
V '1 (sn) ≈ -α11snTn
V '1 (sn)-α21Vin(sn)-α31 V2 (sn) → α11=Tn
R0nC1hn =
2π·103
1·105 =0.06283, α21=α31=1
+-
α11C1
φ1 φ1
α21C1
α31C1
C1
V1'
V2
Vin V1'
φ2 φ2
Chapter 9 – Section 7 (5/2/04) Page 9.7-62
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-9 - ContinuedL2hn:
This state eq. can be realized by the SCdifferentiator circuit shown with two inputs.
∴ V2(z) = -(1-z-1)[α12 V1’ (z) + α22Vout(z)]
V2(s) ≈ -sT [α12 V1’ (s) + α22Vout(s)]
Normalizing T by ωPB gives V2(sn) = -snTn
[α12 V1’ (sn) + α22Vout(sn)]
∴ α12 = α22 = L2hnTn
= 0.5·105
2π·103 = 7.9577 if R = R0n = 1Ω.
L2hn:
This state equation can be realized by the SCdifferentiator circuit shown with two inputs.
∴ Vout(z) = -(1-z-1)[α13 V2 (z) + α23Vout(z)]
Vout(s) ≈ -sT [α13 V2 (s) + α23Vout(s)]
Normalizing T by ωPB gives Vout(sn) = -snTn [α13 V2 (sn) + α23Vout(sn)]
∴ α13 = α23 = R4nC3hn
Tn =
1·105
2π·103 = 15.915 if R4n = 1Ω. Σ capacitances =100.49 units of C
+-
C2
φ1 φ1
φ1
φ2
φ2
φ2
V2
Voutα22C2
φ2
α12C2
V1'
+-
C C V2
+-
C3
φ1 φ1
φ1
φ2
φ2
φ2
Vout
Voutα23C3
φ2
α13C3
V2
Chapter 9 – Section 7 (5/2/04) Page 9.7-63
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Bandpass Switched Capacitor Filters Using the Ladder ApproachBandpass switched capacitor ladder filters are obtained from low pass RLC prototypecircuits by applying the normalized, low pass to normalized bandpass transformationgiven as
sln =
ωr
BW
sb
ωr + 1
(sb/ωr) =
ωr
BW
sbn + 1
sbn
This causes the followingtransformation on the inductors andcapacitors of the RLC prototype:
Design Procedure:1.) Identify the appropriate RLCprototype, low pass circuit to meetthe specifications.2.) Transform each inductor and capacitor by the normalized, low pass to bandpasstransformation.3.) Choose the state variables and write the state functions.4.) Realize the state functions using switched capacitor circuits.
In this case, the state functions will be second-order, bandpass functions which canbe realized by switched-capacitor biquads.
NormalizedLow-PassNetwork
Lln
Cln sn → ωrBW
sbn + 1sbn
Normalized Bandpass Network
Lbn= ωrBW
Lln Cbn= BWωr
1Lln
Lbn= BWωr
1Cln
Cbn = ωrBW
Cln
Chapter 9 – Section 7 (5/2/04) Page 9.7-64
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-10 - Design of a 4th-Order, Butterworth Bandpass, SC Ladder FilterDesign a fourth-order, bandpass, switched capacitor ladder filter. The filter is to have acenter frequency (ωr) of 3kHz and a bandwidth (BW) of 600 Hz. fc = 128kHz.
SolutionThe low pass normalized prototype
filter is shown (Note that this form is slightlydifferent than the form used in Table 9.7-4)
Applying the lowpass-bandpasstransformation on the elementsgives,
The state equations for thiscircuit can be written as illustrated below.
Vin(s) =
I2(s) + V1(s)Z1bn R0n + V1(s) → V1(s) =
Z1bnR0n [Vin(s) - I2(s)R0n - V1(s)]
where Z1bn = sL1bn(1/sC1bn)
sL1bn + (1/sC1bn) = s/C1bn
s 2 + (1/L1bnC1bn) =
s/C1bn
s 2+1
∴ V1(s) = s/R0nC1bn
s2 + 1
Vin(s) - R0nR V2’(s) - V1’(s) (1)
+
-
C1n
L2n
Vout(sn)+
-
Vin(sn)
R0n
R5n+
-
=1Ω
0.7659F=
=1.8478H
C3n1.8478F
=
L =0.7659H4n
=1Ω
C1bn = C1lnωr
BW
L1bn =1/C1bn
+
-V1
R0n
Vin(sn)
L2bn = L2lnωr
BWC2bn =1/L2bn
I2 C3bn = C3lnBW
L3bn =1/C3bn
+
-V3
L4bn = L4lnωr
BWC4bn =1/L4bn
I4ωr
+
-Vout(sn)R5n
Ex.6-B
Chapter 9 – Section 7 (5/2/04) Page 9.7-65
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-10 - Continued
I2(s) = Y2bn[V1(s) - V3(s)]→ V2’(s) =
sR/L2bn
s 2+1[V1(s) - V3(s)] (2)
V3(s)=Z3bn(I2(s)-I4(s))=Z3bn
V2’(s)
R -Vout(s)
R5n → V3(s)=s/RC3bn
s 2+1
V2’(s)-
R
R5n Vout (3)
andI4(s) =Y4bn[V3(s)-Vout(s)] → Vout(s) = R5nY4bn[V3(s)-Vout(s)]
or Vout(s) = sR5n/L4bn
s 2+1 [V3(s)-Vout(s)] (4)
How to realize? Consider the bandpass form of the low-Q and high-Q biquads:
+-
V1(z)C1
Low Q, switched capacitor, biquad BP realization.
Vin(z)e
φ1 φ1φ2
φ2
α2C1
α4C2
φ2
+-
C2
φ2
α6C2
φ2
α5C2
φ1
Vout(z)ee
φ1φ1+-
V1(z)C1Vin(z)e
φ1φ2
α2C1
+-
C2
φ1
φ2
α5C2
φ2
φ1
Vout(z)e
α4C1
eα3C1
High Q, switched capacitor, biquad realization.
φ1φ2
Chapter 9 – Section 7 (5/2/04) Page 9.7-66
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-10 - ContinuedNote that the high-Q biquad can only have inverting inputs. Therefore, we shall use thelow-Q biquad to realize the above state equations because it can have both inverting andnoninverting inputs (α4C2).
For the low-Q biquad, if we let α1 = α3 = α6 = 0, we get
Hee(s) ≈ -(α4s/T)
s 2˚+ (α2α5/T˚2)Normalizing by Ωn gives
→ Hee(sn) ≈ - (α4sn/Tn)
sn2˚+ (α2α5/Tn2)
All the α2’s and α5’s will be given as: α2α5 = Tn2 = Ωn2T 2 = ωr2/fc2 = (2π)2(fr/fc)2
Therefore, let α2 = |α5| = 2π·fr
fc = 2π·3x103
128x105 = 0.1473
Now all that is left is to design α4 for each stage (assuming R0n = R5n = R = 1Ω).Also, the sum of capacitances per stage will be:
Σ capacitances/stage = α2αmin +
|α5|αmin +
2αmin +
α4αmin x (no. of inputs)
Chapter 9 – Section 7 (5/2/04) Page 9.7-67
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-10 - ContinuedStage 1
α41Tn =
1R0nC1bn → α41 =
TnR0nC1bn =
ωr·BWfc·ωr·C1ln =
2π·600128x103·0.7658
= 0.03848
There will be one noninverting input (Vin) and two inverting inputs (V2’ and V1).
Σ capacitances = 2(0.1437)0.03848 +
20.03848 + 3 = 62.44 units of capacitance
Stage 2α42Tn =
RL2bn → α42 =
Tn·BWωrL2ln =
ωr·BWfc·ωr·L2ln =
2π·600128x103·1.8478
= 0.01594
There will be one noninverting input (V1) and one inverting input (V3).
Σ capacitances = 2(0.1437)0.01594 +
20.01594 + 2 = 145.50 = units of capacitance
Stage 3Same as stage 2. α43 = 0.01594There will be one noninverting input (V2’) and one inverting input (Vout).Σ capacitances = 145.50 units of capacitance
Stage 4Same as stage 1 except Σ capacitances = 61.44 units of capacitance. α44 = 0.03848.There will be one noninverting input (V3) and one inverting input (Vout).
Chapter 9 – Section 7 (5/2/04) Page 9.7-68
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-10 - ContinuedTotal capacitance of this example is 414.88 units of capacitance.Realization:
Using this simplification gives:
φ2
φ1 α C41 21
φ1φ2
α C41 21
α 21 =α 51=
0.1473
φ2
α C41 21
φ1
φ1
φ2 α C42 22
α 22 =α 52 =
0.1473
V1
V'2
φ2
φ1α C43 23
α 23 =α 53 =
0.1473
φ2α C42 22 φ1
φ1
φ2 α C44 42V3
φ2
α C43 23
φ1
α C44 42 φ1
φ2
α 24 =α 52 =
0.1473
VoutVin
+-
+-
α2C1C1
C2
φ1φ1
φ2φ2
α5C2
φ2φ1
φ1
φ2
α2,α5
Ex.9.7-13B
Chapter 9 – Section 7 (5/2/04) Page 9.7-69
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
General Approach to Designing Switched Capacitor Ladder Filters
ChooseState
Variables
WriteState
Equations
Use SC Integrators toDesign Each
State Equation
Low PassSwitchedCapacitor
Filter
Use SC BP Ckts. to
Design EachState Equation
BandpassSwitchedCapacitor
Filter
Normalized LPto Normalized
BandpassTransformation
Use SC Differentiatorsto Design EachState Equation
High PassSwitchedCapacitor
Filter
Normalized LPto Normalized
BandpassTransformation
Use SC BS Ckts. toDesign Each
State Equation
BandstopSwitchedCapacitor
Filter
EliminateL-cutsets
and C-loops
Low passPrototypeRLC Ckt.
ChooseState
Variables
WriteState
Equations
Normalized LPto Normalized
High passTransformation
ChooseState
Variables
WriteState
Equations
Normalized LPto Normalized
High passTransformation
ChooseState
Variables
WriteState
Equations
Chapter 9 – Section 7 (5/2/04) Page 9.7-70
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
ANTI-ALIASING IN SWITCHED CAPACITOR FILTERSA characteristic of circuits that sample the signal (switched capacitor circuits) is that
the signal passbands occur at each harmonic of the clock frequency including thefundamental.
T(jω)
T(j0)T(jωPB)
ωPB
00
ω
Figure 9.7-28 - Spectrum of a discrete-time filter and a continuous-time anti-aliasing filter.
-ωPB ωc 2ωc
ωc+ωPBωc-ωPB 2ωc-ωPB 2ωc+ωPB
Anti-Aliasing Filter
Baseband
The primary problem of aliasing is that there are undesired passbands that contributeto the noise in the desired baseband.
Chapter 9 – Section 7 (5/2/04) Page 9.7-71
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Noise Aliasing in Switched Capacitor CircuitsIn all switched capacitor circuits, a noise aliasing occurs from the passbands that
occur at the clock frequency and each harmonic of the clock frequency.
f0.5fc fcfBfsw-fB
fc-fsw
fc+fBfc-fB
fc+fsw
Magnitude
0
Noise Aliasing
From higher bands
Baseband
Figure 9.7-31 - Illustration of noise aliasing in switched capacitor circuits.
It can be shown that the aliasing enhances the baseband noise voltage spectral density bya factor of 2fsw/fc. Therefore, the baseband noise voltage spectral density is
eBN2 =
kT/C
fsw x
2fsw
fc =
2kTfcC volts2/Hz
Multiplying this equation by 2fB gives the baseband noise voltage in volts(rms)2.Therefore, the baseband noise voltage is
vBN2 =
2kT
fcC 2fB = 2kTC
2fB
fc =
2kT /COSR volts(rms)2
where OSR is the oversampling ratio.
Chapter 9 – Section 7 (5/2/04) Page 9.7-72
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Simulation of Noise in Switched Capacitor FiltersThe noise of switched capacitor filters can be simulated using the above concepts.
1.) Convert the switched capacitor filter to a continuous time equivalent filter byreplacing each switched capacitor with a resistor whose value is 1/(fcC).
2.) Multiply the noise of this resistance by 2fB/fc, to make the resulting noise toapproximate that of the switched capacitor filter.Unfortunately, simulators like SPICE do not permit the multiplication of the thermal
noise. Another approach is to assume that the resistors are noise-free and build a noisegenerator that represents the effect of the noise of vBN
2.
1.) Put a zero dc current through a resistor identical to the one being modeled.2.) A voltage source that is dependent on the voltage across this resistor can be placed at
the input of an op amp to implement vBN2. The gain of the voltage dependent source
should be 2fB/fc.
3.) Model all resistors that represent switched capacitors in the same manner.The resulting noise source model along with the normal noise sources of the op amp willserve as a reasonable approximation to the noise in a switched capacitor filter.
Chapter 9 – Section 7 (5/2/04) Page 9.7-73
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
CONTINUOUS TIME ANTI-ALIASING FILTERSSallen and Key, Unity Gain, Low Pass Filter
VoltageAmplifier
Vout(s)Vin(s) K=1R1 R3
C2
C4
(a.) (b.)
K=1
Transfer function:
Vout(s)Vin(s) =
KR1R3C2C4
s 2 + s
1
R3C4 +
1R1C2
+ 1
R3C2 -
KR3C4
+ 1
R1R3C2C4
= TLP(0) ωo
2
s 2 +
ωo
Q s + ωo2
We desire K = 1 in order to not influence the passband gain of the SCF. With K = 1,
Vout(s)Vin(s) =
1R1R3C2C4
s 2 + s
1
R1C2 +
1R3C2
+ 1
R1R3C2C4
= 1/mn(RC)2
s 2 + (1/RC)[(n+1)/n]s + 1/mn(RC)2
where R3 = nR1 = nR and C4 = mC2 = mC.
Chapter 9 – Section 7 (5/2/04) Page 9.7-74
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Design Equations for The Unity Gain, Sallen and Key Low Pass FilterEquating Vout(s)/Vin(s) to the standard second-order low pass transfer function, we
get two design equations which are
ωo = 1
mnRC
1Q = (n +1)
mn
The approach to designing the components of Fig. 9.7-29a is to select a value of mcompatible with standard capacitor values such that
m ≤ 1
4Q 2 .
Then, n, can be calculated from
n =
1
2mQ 2 - 1 ± 1
2mQ 2 1-4mQ 2 .
This equation provides two values of n for any given Q and m. It can be shown thatthese values are reciprocal. Thus, the use of either one produces the same elementspread.Incidentally, these filters have excellent linearity because the op amp is in unity gain.
Chapter 9 – Section 7 (5/2/04) Page 9.7-75
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-11 - Application of the Sallen-Key Anti-Aliasing Filter Use the above design approach to design a second-order, low-pass filter using Fig.9.7-7a if Q = 0.707 and fo = 1 kHzSolution
We see that m should be less than 0.5 for this example. Let us choose m = 0.5.m = 0.5 → n = 1.
These choices guarantee that Q = 0.707.
Now, use ωo = 1
mnRC to find the RC product → RC = 0.225x10-3.
At this point, one has to try different values to see what is best for the given situation(typically the area required).Let us choose C = C2 = 500pF.
This gives R = R1 = 450kΩ. Thus, C4 = 250pF and R3 = 450kΩ.
It is readily apparent that the anti-aliasing filter will require considerable area toimplement.
Chapter 9 – Section 7 (5/2/04) Page 9.7-76
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
A Negative Feedback, Second-Order, Low Pass Anti-Aliasing FilterAnother continuous-time filter suitable for anti-aliasing filtering is shown in Fig. 9.7-
30. This filter uses frequency-dependent negative feedback to achieve complex conjugatepoles.
+-
C5=C
C4=4Q2(1+|TLP(0)|)C
R1= 12|TLP(0)|ωoQC
R2= 12ωoQC
R3=1
2(1+|TLP(0)|)ωoQC
Vin Vout
Figure 9.7-30 - A negative feedback realization of a second-order, low pass filter.
This gain of this circuit in the passband is determined by the ratio of R2/R1.
Chapter 9 – Section 7 (5/2/04) Page 9.7-77
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
Example 9.7-12 - Design of A Negative Feedback, Second-Order, Low-Pass ActiveFilter
Use the negative feedback, second-order, low-pass active filter of Fig. 9.7-30 todesign a low-pass filter having a dc gain of -1, Q = 1/ 2 , and fo = 10kHz.Solution
Let us use the design equations given on Fig. 9.7-30. Assume that C5 = C = 100pF.Therefore, we get C4 = (8)(0.5)C = 400pF. The resistors are
R1 = 2
(2)(1)(6.2832)(10-6) = 112.54 kΩ
R2 = 2
(2)(6.2832)(10-6) = 112.54 kΩ
and
R3 = 2
(2)(6.2832)(2)(10-6) = 56.27 kΩ
Unfortunately we see that again because of the passive element sizes that anti-aliasing filters will occupy a large portion of the chip.
Chapter 9 – Section 8 (5/2/04) Page 9.8-1
ECE 6414 - Analog Integrated Systems Design © P.E. Allen - 2002
SUMMARY• Switched capacitor circuits have reached maturity in CMOS technology.• The switched capacitor circuit concept was a pivotal step in the implementation of
analog signal processing circuits in CMOS technology.• The accuracy of the signal processing is proportional to the capacitor ratios.• Switched capacitor circuits have been developed for:
AmplificationIntegrationDifferentiationSummationFilteringComparisonAnalog-digital conversion
• Approaches to switched capacitor circuit design:Oversampled approach – clock frequency is much greater than the signal frequencyz-domain approach – the specifications are converted to the z-domain and directly
realized. Such circuits can operate to within half of the clock frequency.• SPICE or SWITCAP permits frequency domain simulation of switched capacitor ckts.• Clock feedthrough and kT/C noise represent the lower limit of the dynamic range of
switched capacitor circuits.
Chapter 10 – Digital-Analog and Analog-Digital Converters 5/2/04
CMOS Analog Circuit Design © P.E. Allen - 2004
CHAPTER 10 – DIGITAL-ANALOG AND ANALOG-DIGITALCONVERTERS
Section 10.0 - IntroductionSection 10.1 - Characterization of Digital-Analog ConvertersSection 10.2 - Parallel Digital-Analog ConvertersSection 10.3 - Extending the Resolution of Parallel Digital-Analog ConvertersSection 10.4 - Serial Digital-Analog ConvertersSection 10.5 - Characterization of Analog-Digital ConvertersSection 10.6 - Serial Analog-Digital ConvertersSection 10.7 - Medium Speed Analog-Digital ConvertersSection 10.8 - High Speed Analog-Digital ConvertersSection 10.9 - Oversampling ConvertersSection 10.10 - Summary
Chapter 10 – Introduction (5/2/04) Page 10.0-1
CMOS Analog Circuit Design © P.E. Allen - 2004
10.0 - INTRODUCTIONOrganization
Chapter 9
Switched Capaci-tor Circuits
Chapter 6Simple CMOS &BiCMOS OTA's
Chapter 7High Performance
OTA's
Chapter 10D/
Chapter 11AnalogSystems
Chapter 3
CMOSModeling
Chapter 4
CMOS/BiCMOSSubcircuits
Chapter 5CMOS/BiCMOS
Amplifiers
Systems
Complex
Circuits
Devices
Simple
Chapter 2CMOS
Technology
Chapter 1Introduction to An-alog CMOS Design
Chapter 8CMOS/BiCMOS
Comparators
Chapter 10D/A and A/DConverters
Chapter 10 – Introduction (5/2/04) Page 10.0-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Importance of Data Converters in Signal Processing
PRE-PROCESSING(Filtering and analog to digital conversion)
DIGITAL PROCESSOR
(Microprocessor)
POST-PROCESSING (Digital to analog
conversion and filtering)
ANALOGSIGNAL(Speech,sensors,radar,etc.)
ANALOGOUTPUTSIGNAL
CONTROL
ANALOG A/D D/ADIGITAL ANALOG
Chapter 10 – Introduction (5/2/04) Page 10.0-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Digital-Analog Converters in Signal Processing Applications
Digital SignalProcessing
SystemMicroprocessorsCompact disksRead only memoryRandom access memoryDigital transmissionDisk outputsDigital sensors
DIGITAL-ANALOG
CONVERTERFilter Amplifier
AnalogOutput
Reference Fig. 10.1-01
Chapter 10 – Introduction (5/2/04) Page 10.0-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Asynchronous Versus Synchronous Digital-Analog Converters
Asynchronous
Digital-Analog
Converter
b0
b1b2
bN-1
vOUT
VREF
Synchronous
Digital-Analog
Converter
b0
b1b2
bN-1
VOUT*Latch
Sampleand
Hold
Clock
VREF
Fig. 10.1-02
(Asterisk represents a sample and held signal.)
Chapter 10 – Introduction (5/2/04) Page 10.0-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Block Diagram of a Digital-Analog Converter
VREF DVREF vOUT =KDVREF
OutputAmplifier
ScalingNetwork
VoltageReference
Binary Switches
b0b1 b2 bN-1Figure 10.1-3
b0 is the most significant bit (MSB)
The MSB is the bit that has the most (largest) influence on the analog output
bN-1 is the least significant bit (LSB)
The LSB is the bit that has the least (smallest) influence on the analog output
Chapter 10 – Section 1 (5/2/04) Page 10.1-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 10.1 - CHARACTERIZATION OF DIGITAL-ANALOGCONVERTERS
STATIC CHARACTERISTICSOutput-Input CharacteristicsIdeal input-output characteristics of a 3-bit DAC
1.000
0.875
0.750
0.625
0.500
0.375
0.250
0.125
0.000
Ana
log
Out
put V
alue
Nor
mal
ized
to V
RE
F
000 001 010 011 100 101 110 111Digital Input Code
Vertical ShiftedCharacteristic
Infinite ResolutionCharacteristic
1 LSB
Fig. 10.1-4
Chapter 10 – Section 1 (5/2/04) Page 10.1-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Definitions• Resolution of the DAC is equal to the number of bits in the applied digital input word.• The full scale (FS):
FS = Analog output when all bits are 1 - Analog output all bits are 0
FS = (VREF - VREF
2N ) - 0 = VREF
1 - 1
2N
• Full scale range (FSR) is defined as
FSR = lim
N→∞FS = VREF• Quantization Noise is the inherent uncertainty in digitizing an analog value with a finite
resolution converter.
DigitalInput Code
0LSB
0.5LSB
1LSB
-0.5LSB
000 001 010 011 100 101 110 111
Quantization Noise
Fig. 10.1-5
Chapter 10 – Section 1 (5/2/04) Page 10.1-3
CMOS Analog Circuit Design © P.E. Allen - 2004
More Definitions• Dynamic Range (DR) of a DAC is the ratio of the FSR to the smallest difference that
can be resolved (i.e. an LSB)
DR = FSR
LSB change = FSR
(FSR/2N) = 2N
or in terms of decibels DR(dB) = 6.02N (dB)
• Signal-to-noise ratio (SNR) for the DAC is the ratio of the full scale value to the rmsvalue of the quantization noise.
rms(quantization noise) = 1T ⌡
⌠
0
T
LSB2
t
T - 0.5 2dt = LSB
12 = FSR
2N 12
∴ SNR = vOUT(rms)
(FSR/ 12 2N)• Maximum SNR (SNRmax) for a sinusoid is defined as
SNRmax = vOUTmax(rms)
(FSR/ 12 2N) = FSR/(2 2)
FSR/( 12 2N) = 6 2N
2
or in terms of decibels
SNRmax(dB) = 20log10
62N
2 = 10 log10(6)+20 log10(2N)-20 log10(2) = 1.76 + 6.02N dB
Chapter 10 – Section 1 (5/2/04) Page 10.1-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Even More Definitions• Effective number of bits (ENOB) can be defined from the above as
ENOB = SNRActual - 1.76
6.02
where SNRActual is the actual SNR of the converter.
Comment:The DR is the amplitude range necessary to resolve N bits regardless of the amplitudeof the output voltage.However, when referenced to a given output analog signal amplitude, the DR requiredmust include 1.76 dB more to acount for the presence of quantization noise.Thus, for a 10-bit DAC, the DR is 60.2 dB and for a full-scale, rms output voltage, thesignal must be approximately 62 dB above whatever noise floor is present in the outputof the DAC.
Accuracy Requirements of the i-th Bit
Weighting factor of the i-th bit = VREF2i+1
2n
2n = 2n-i-1 LSBs
Accuracy of the i-th bit = ±0.5 LSB2n-i-1 LSB =
12n-i =
1002n-i %
Result: The highest accuracy requirements is always the MSB (i = 1). The LSB bit only needs ±50% accuracy.
Chapter 10 – Section 1 (5/2/04) Page 10.1-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Offset and Gain ErrorsAn offset error is a constant difference between the actual finite resolution
characteristic and the ideal finite resolution characteristic measured at any vertical jump.A gain error is the difference between the slope of the actual finite resolution and the
ideal finite resolution characteristic measured at the right-most vertical jump.
Gain Error in a 3-bit DACOffset Error in a 3-bit DAC
Ana
log
Out
put V
alue
Nor
mal
ized
to V
RE
F000 001 010 011 100 101 110 111
Digital Input Code
Ideal 3-bitResolution
Characteristic
1
7/8
6/8
5/8
4/8
3/8
2/8
1/8
0
Actual Characteristic
GainError
InfiniteResolution
Characteristic
Ana
log
Out
put V
alue
Nor
mal
ized
to V
RE
F
000 001 010 011 100 101 110 111Digital Input Code
OffsetError
1
7/8
6/8
5/8
4/8
3/8
2/8
1/8
0
Actual Characteristic
InfiniteResolution
Characteristic
Ideal 3-bitResolution
Characteristic
Fig. 10.1-6
Chapter 10 – Section 1 (5/2/04) Page 10.1-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Integral and Differential Nonlinearity• Integral Nonlinearity (INL) is the maximum difference between the actual finite
resolution characteristic and the ideal finite resolution characteristic measured vertically(% or LSB).
• Differential Nonlinearity (DNL) is a measure of the separation between adjacent levelsmeasured at each vertical jump (% or LSB).
DNL = Vcx – Vs =
Vcx - Vs
Vs Vs =
Vcx
Vs -1 LSBs
where Vcx is the actual voltage change on a bit-to-bit basis and Vs is the ideal LSBchange of (VFSR/2N)
Example of a 3-bit DAC:
000 001 010 011 100 101 110 111
1808
28
38
48
58
68
78
88
Ana
log
Out
put V
olta
ge
Digital Input Code
Ideal 3-bit Characteristic
Actual 3-bit Characteristic
Infinite Resolution Characteristic
+1.5 LSB INL
-1 LSB INL
+1.5 LSB DNL
A-1.5 LSB DNL
Nonmonotonicity
Fig. 10.1-7
Chapter 10 – Section 1 (5/2/04) Page 10.1-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Example of INL and DNL of a Nonideal 4-Bit DacFind the ±INL and ±DNL for the 4-bit DAC shown.
15/16
14/16
13.16
12/16
11/16
10/16
9/16
8/16
7/16
6/16
5/16
4/16
3/16
2/16
1/16
0/160 10 0 0 0 0 0 0 1 1 1 1 1 1 10 0 0 0 1 1 1 1 0 0 0 0 1 1 1 10 0 1 1 0 0 1 1 0 0 1 1 0 0 1 10 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
b0b1b2b3
Ana
log
Out
put (
Nor
mal
ized
to F
ull S
cale
)
Digital Input Code
-1.5 LSB INL
-2 LSB DNL
Actual 4-bit DACCharacteristic
+1.5 LSB DNL
+1.5 LSB INL
Ideal 4-bit DACCharacteristic
-2 LSB DNL
Fig. 10.1-8
Chapter 10 – Section 1 (5/2/04) Page 10.1-8
CMOS Analog Circuit Design © P.E. Allen - 2004
DYNAMIC CHARACTERISTICS OF DIGITAL-ANALOG CONVERTERSDynamic characteristics include the influence of time.
Definitions• Conversion speed is the time it takes for the DAC to provide an analog output when the
digital input word is changed.Factor that influence the conversion speed:
Parasitic capacitors (would like all nodes to be low impedance)Op amp gainbandwidthOp amp slew rate
• Gain error of an op amp is the difference between the desired and actual output voltageof the op amp (can have both a static and dynamic influence)
Actual Gain = Ideal Gain x
Loop Gain
1 + Loop Gain
Gain error = Ideal Output-Actual Output = Ideal Gain-Actual Gain
Ideal Gain = 1
1+Loop Gain
Chapter 10 – Section 1 (5/2/04) Page 10.1-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Example of Influence of Op Amp Gain Error on DAC PerformanceAssume that a DAC using an op amp in the inverting configuration with C1 = C2 and
Avd(0) = 1000. Find the largest resolution of the DAC if VREF is 1V and assuming worstcase conditions.Solution
The loop gain of the inverting configuration is LG = C2
C1+C2 Avd(0) = 0.5⋅1000 = 500.
The gain error is therefore 1/501 ≈ 0.002. The gain error should be less than thequantization noise of ±0.5LSB which is expressed as
Gain error = 1
501 ≈ 0.002 ≤ VREF2N+1
Therefore the largest value of N that satisfies this equation is N = 7.
Chapter 10 – Section 1 (5/2/04) Page 10.1-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Influence of the Op Amp GainbandwidthSingle-pole response:
vout(t) = ACL[1 - e-ωHt]vin(t)
whereACL = closed-loop gain
ωH = GB
R1
R1+R2 or GB
C2
C1+C2
To avoid errors in DACs (and ADCs), vout(t) must be within ±0.5LSB of the final value bythe end of the conversion time.Multiple-pole response:
Typically the response is underdamped like the following (see Appendix C of text).
+-
Settling Time
Final Value
Final Value + ε
Final Value - ε
ε
ε
vOUT(t)
t00
vOUTvIN
Ts
Upper Tolerance
Lower Tolerance
Fig. 6.1-7
Chapter 10 – Section 1 (5/2/04) Page 10.1-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Example of the Influence of GB and Settling Time on DAC PerformanceAssume that a DAC uses a switched capacitor noninverting amplifier with C1 = C2
and GB = 1MHz. Find the conversion time of an 8-bit DAC if VREF is 1V.
SolutionFrom the analysis in Secs. 9.2 and 9.3, we know that
ωH =
C2
C1+C2 GB = (2π)(0.5)(106) = 3.141x106
and ACL = 1. Assume that the ideal output is equal to VREF. Therefore the value of theoutput voltage which is 0.5LSB of VREF is
1 - 1
2N+1 = 1 - e-ωH T
or2N+1 = eωH T
Solving for T gives
T =
N+1
ωH ln(2) = 0.693
N+1
ωH =
9
3.141 0.693 = 1.986µs
Chapter 10 – Section 1 (5/2/04) Page 10.1-12
CMOS Analog Circuit Design © P.E. Allen - 2004
TESTING OF DACsInput-Output TestTest setup:
N-bitDACunder test
ADC withmore resolution
than DAC(N+2 bits)
DigitalSubtractor(N+2 bits)
DigitalWordInput
(N+2 bits)
Vout
ADCOutput Digital
ErrorOutput
(N+2 bits)
Fig. 10.1-9
Comments:Sweep the digital input word from 000...0 to 111...1.The ADC should have more resolution by at least 2 bits and be more accurate than theerrors of the DACINL will show up in the output as the presence of 1’s in any bit.
If there is a 1 in the Nth bit, the INL is greater than ±0.5LSBDNL will show up as a change between each successive digital error output.The bits which are greater than N in the digital error output can be used to resolve theerrors to less than ±0.5LSB
Chapter 10 – Section 1 (5/2/04) Page 10.1-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Spectral TestTest setup:
Comments:Digital input pattern is selected to
have a fundamental frequency whichhas a magnitude of at least 6N dBabove its harmonics.
Length of the digital sequencedetermines the spectral purity of thefundamental frequency.
All nonlinearities of the DAC (i.e. INL and DNL) will cause harmonics of thefundamental frequency
The THD can be used to determine the SNR dB range between the magnitude of thefundamental and the THD. This SNR should be at least 6N dB to have an INL of less than±0.5LSB for an ENOB of N-bits.
Note that the noise contribution of VREF must be less than the noise floor due tononlinearities.
If the period of the digital pattern is increased, the frequency dependence of INL can bemeasured.
N-bitDACunder test
DigitalPattern
Generator(N bits)
Vout
Clock
DistortionAnalyzer
Vout
t
|Vout(jω)|
ωfsig
SpectralOutput
1000
0
1000
1
1001
1
1111
1
Noise floordue to non-linearities
VREF
Fig. 10.1-10
Chapter 10 – Section 2 (5/2/04) Page 10.2-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 10.2 - PARALLEL DIGITAL-ANALOG CONVERTERS
Classification of Digital-Analog Converters
Parallel
Voltage ChargeCurrent
Serial
Charge
Digital-Analog Converters
Voltage and Charge
Slow Fast Fig. 10.2-1
Chapter 10 – Section 2 (5/2/04) Page 10.2-2
CMOS Analog Circuit Design © P.E. Allen - 2004
CURRENT SCALING DIGITAL-ANALOG CONVERTERSGeneral Current Scaling DACs
+
-
I0
I1
I2
IN-1
RFvOUTCurrent
ScalingNetwork
Digital Input Word
VREF
Fig. 10.2-2
The output voltage can be expressed as
VOUT = -RF(I0 + I1 + I2 + ··· + IN-1)
where the currents I0, I1, I2, ... are binary weighted currents.
Chapter 10 – Section 2 (5/2/04) Page 10.2-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Binary-Weighted Resistor DACCircuit:
+
-
R
S0I0
VREF
2R
S1I1
4R
S2I2
2N-1R
SN-1
IN-1
IO
RF = K(R/2)
+
-
vOUT
Fig. 10.2-3RLSBRMSB
Comments:1.) RF can be used to scale the gain of the DAC. If RF = KR/2, then
vOUT = -RFIO = -KR
2
b0
R + b12R +
b24R +···+
bN-12N-1R VREF ⇒ vOUT = -K
b0
2 + b14 +
b28 +···+
bN-12N VREF
where bi is 1 if switch Si is connected toVREF or 0 if switch Si is connected to ground.
2.) Component spread value = RMSBRLSB
= R
2N-1R = 1
2N-1
3.) Attributes:Insensitive to parasitics ⇒ fast Large component spread valueTrimming required for large values of N Nonmonotonic
Chapter 10 – Section 2 (5/2/04) Page 10.2-4
CMOS Analog Circuit Design © P.E. Allen - 2004
R-2R Ladder Implementation of the Binary Weighted Resistor DACUse of the R-2R concept toavoid large element spreads:
How does the R-2R ladder work?“The resistance seen to the rightof any of the vertical 2R resistorsis 2R.”
Attributes: • Not sensitive to parasitics (currents through the resistors never change as Si is varied)
• Small element spread. Resistors made from same unit (2R consist of two in series or Rconsists of two in parallel)
• Not monotonic
+
-
R
S0
I0
VREF
2R I1 I2 IN-1
IO
RF = KR
+
-
vOUT
R
S1
2R
S2
2R
SN-1
2R
2R
Fig. 10.2-4
2R
R 2R
2R2R
RVREF
I
I
2I
2I
4I
4I
8I
Fig. 10.2-4(2R-R)
Chapter 10 – Section 2 (5/2/04) Page 10.2-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Current Scaling Using Binary Weighted MOSFET Current SinksCircuit:
+
-2N-1I 2I4I I
S0 SN-3 SN-2 SN-1R2
2N-1 matched FETs 4 matched FETs 2 matched FETs
TransistorArray
+
-
vOUT
IREF =I
VA+
-
A1
VA
+
-
b0 bN-3 bN-2 bN-1
Fig. 10.2-5
VDD
+ -A 2
Operation:vOUT = R2(bN-1·I + bN-2·2I + bN-3·4I + ··· + b0·2N-1·I)
If I = IREF = VREF
2NR2,
then
vOUT =
b0
2 + b14 +
b28 + ··· +
bN-32N-2 +
bN-22N-1 +
bN-12N VREF
Attributes: Fast (no floating nodes) and not monotonic Accuracy of MSB greater than LSBs
Chapter 10 – Section 2 (5/2/04) Page 10.2-6
CMOS Analog Circuit Design © P.E. Allen - 2004
VOLTAGE SCALING DIGITAL-ANALOG CONVERTERSGeneral Voltage Scaling Digital Analog Converter
vOUT
VoltageScalingNetwork
Digital Input Word
VREFDecoder
Logic
V1
V2
V3
V2N
Fig. 10.2-6
Operation:Creates all possible values of the analog output then uses a decoding network to
determine which voltage to select based on the digital input word.
Chapter 10 – Section 2 (5/2/04) Page 10.2-7
CMOS Analog Circuit Design © P.E. Allen - 2004
3-Bit Voltage Scaling Digital-Analog Converter
The voltage at any tap can be expressed as: vOUT = VREF
8 (n − 0.5) = VREF16 (2n − 1)
Attributes:• Guaranteed
monotonic• Compatible with
CMOStechnology
• Large area if N islarge
• Sensitive toparasitics
• Requires a buffer• Large current can
flow through theresistor string.
b2 b1 b0b2 b1 b0
VREF
R/2
R/2
8
7
6
5
4
3
2
1
R
R
R
R
R
R
R
vOUT
000 001 010 011 100 101 110 111
VREF8
2VREF8
3VREF8
4VREF8
5VREF8
6VREF8
7VREF8
VREF
0
Digital Input Code
v OU
T
(a.) (b.)
Figure 10.2-7 - (a.) Implementation of a 3-bit voltage scaling DAC. (b.) Input-output characteristics of Fig. 10.2-7(a.)
1116 VREF
Input = 101
Chapter 10 – Section 2 (5/2/04) Page 10.2-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Alternate Realization of the 3-Bit Voltage Scaling DAC
b2 b1 b0
VREF
R/2
R/2
8
7
6
5
4
3
2
1
R
R
R
R
R
R
R
vOUT
3-to-8 Decoder
Fig. 10.2-8
Chapter 10 – Section 2 (5/2/04) Page 10.2-9
CMOS Analog Circuit Design © P.E. Allen - 2004
INL and DNL of the Voltage Scaling DACFind an expression for the INL and DNL of the voltage scaling DAC using a worst-caseapproach. For an n-bit DAC, assume there are 2n resistors between VREF and groundand that the resistors are numbered from 1 to 2n beginning with the resistor connected to
VREF and ending with the resistor connected to ground.
Integral NonlinearityThe voltage at the i-th resistor from the top is,
vi = (2n-i)R
(2n-i)R + iR VREF
where there are i resistors above vi and 2n-i below.For worst case, assume that i = 2n-1 (midpoint).
Define Rmax = R + ∆R and Rmin = R - ∆R.
The worst case INL isINL = v2n-1(actual) - v2n-1(ideal)
Therefore,
INL = 2n-1(R+∆R)VREF
2n-1(R+∆R) + 2n-1(R-∆R) - VREF
2 = ∆R2R VREF
INL=2n
2n
∆R
2R VREF=2n-1
∆R
R
VREF
2n =2n-1
∆R
R LSBs
Differential NonlinearityThe worst case DNL can
be found asDNL = vstep(act) - vstep(ideal)
Substituting the actual andideal steps gives,
= (R±∆R)VREF
2nR - R VREF
2nR
=
R±∆R
R - RR
VREF2n
= ±∆R
R VREF
2n Therefore,
DNL = ±∆R
R LSBs
VREF
R1
R2
R3
Ri-1
Ri
Ri+1
R2n
2n-1
1
2
3
i-2
i-1
i
i+1
2n-2
2n-1
2n
Vi
Fig. 10.2-085
Chapter 10 – Section 2 (5/2/04) Page 10.2-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.2-1 - Accuracy Requirements of a Voltage-Scaling digital-analogConverter
If the resistor string of a voltage scaling digital-analog converter is a 5 µm widepolysilicon strip having a relative accuracy of ±1%, what is the largest number of bits thatcan be resolved and keep the worst case INL within ±0.5 LSB? For this number of bits,what is the worst case DNL?
SolutionFrom the previous page, we can write that
2n-1
∆R
R = 2n-1
1
100 ≤ 12
This inequality can be simplified2n ≤ 100
which has a solution of n = 6. The value of the DNL for n = 6 is found from the previous page as
DNL = ±1
100 LSBs = ±0.01LSBs
(This is the reason the resistor string is monotonic.)
Chapter 10 – Section 2 (5/2/04) Page 10.2-11
CMOS Analog Circuit Design © P.E. Allen - 2004
CHARGE SCALING DIGITAL-ANALOG CONVERTERSGeneral Charge Scaling Digital-Analog Converter
vOUT
ChargeScalingNetwork
Digital Input Word
VREF
Fig. 10.2-9
General principle is to capacitively attenuate the referencevoltage. Capacitive attenuation is simply:
Calculate as if the capacitors were resistors. For example,
Vout =
1C2
1C1 +
1C2
VREF = C1
C1 + C2 VREF
C1
C2VREF
+
-
Vout
Fig. 10.2-9b
Chapter 10 – Section 2 (5/2/04) Page 10.2-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Binary-Weighted, Charge Scaling DACCircuit:
Operation:1.) All switches
connected to groundduring φ1.
2.) Switch Si closes to VREF if bi = 1 or to ground if bi = 0.Equating the charge in the capacitors gives,
VREFCeq = VREF
b0C + b1C
2 + b2C22 + ... +
bN-1C2N−1 = Ctot vOUT = 2C vOUT
which givesvOUT = [b02-1 + b12-2 + b22-3 + ... + bN-12-N]VREF
Equivalent circuit of the binary-weighted, chargescaling DAC is:Attributes:
• Accurate• Sensitive to parasitics• Not monotonic• Charge feedthrough occurs at turn on of switches
+
-
VREF
φ1
C2 2N-2 2N-1C
4C C C
2N-1C
φ2
S0
φ2 φ2 φ2 φ2
S1 S2 SN-2 SN-1
vOUT
TerminatingCapacitor
Fig. 10.2-10
+
-
VREF
Ceq.
2C - Ceq. vOUT
Fig. 10.2-11
Chapter 10 – Section 2 (5/2/04) Page 10.2-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Integral Nonlinearity of the Charge Scaling DACAgain, we use a worst case approach. Assume an n-bit charge scaling DAC with the
MSB capacitor of C and the LSB capacitor of C/2n-1 and the capacitors have a toleranceof ∆C/C.
The ideal output when the i-th capacitor only is connected to VREF is
vOUT (ideal) = C/2i-1
2C VREF = VREF
2i
2n
2n = 2n
2i LSBs
The maximum and minimum capacitance is Cmax = C + ∆C and Cmin = C - ∆C.Therefore, the actual worst case output for the i-th capacitor is
vOUT(actual) = (C±∆C)/2i-1
2C VREF = VREF
2i ± ∆C·VREF
2iC = 2n
2i ± 2n∆C2iC LSBs
Now, the INL for the i-th bit is given as
INL(i) = vOUT(actual) - vOUT(ideal) = ±2n∆C
2iC = 2n-i∆C
C LSBs
Typically, the worst case value of i occurs for i = 1. Therefore, the worst case INL is
INL = ± 2n-1∆CC LSBs
Chapter 10 – Section 2 (5/2/04) Page 10.2-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Differential Nonlinearity of the Charge Scaling DACThe worst case DNL for the binary weighted capacitor array is found when the MSB
changes. The output voltage of the binary weighted capacitor array can be written as
vOUT = Ceq.
(2C-Ceq.) + Ceq. VREF
where Ceq are capacitors whose bits are 1 and (2C - Ceq) are capacitors whose bits are 0.
The worst case DNL can be expressed as
DNL = vstep(worst case)
vstep(ideal) - 1 =
vOUT(1000....) - vOUT(0111....)LSB - 1 LSBs
The worst case choice for the capacitors is to choose C1 larger by ∆C and the remainingcapacitors smaller by ∆C giving,
C1=C+∆C, C2 = 12(C-∆C),...,Cn-1=
12n-2(C-∆C), Cn=
12n-1(C-∆C), and Cterm=
12n-1(C-∆C)
Note that nΣCii=2
+ Cterm = C2+ C3+···+ Cn-1+ Cn+ Cterm = C-∆C
Chapter 10 – Section 2 (5/2/04) Page 10.2-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Differential Nonlinearity of the Charge Scaling DAC - Continued
∴ vOUT(1000...) =
C+∆C
(C+∆C)+(C-∆C) VREF =
C+∆C
2C VREF
and
vOUT(0111...) =
(C-∆C) -Cterm
(C+∆C)+(C-∆C) VREF = (C-∆C) -
12n-1(C-∆C)
(C+∆C)+(C-∆C) VREF
=
C-∆C
2C
1 - 22n VREF
∴ vOUT(1000...) - vOUT(0111...)
LSB -1 LSBs = 2n
C+∆C
2C -2n
C-∆C
2C
1-22n -1 = (2n-1)
∆CC LSBs
Therefore, DNL = (2n - 1) ∆CC LSBs
Chapter 10 – Section 2 (5/2/04) Page 10.2-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.2-2 - DNL and INL of a Binary Weighted Capacitor Array DACIf the tolerance of the capacitors in an 8-bit, binary weighted, charge scaling DAC are
±0.5%, find the worst case INL and DNL.Solution
For the worst case INL, we get from above thatINL = (27)(±0.005) = ±0.64 LSBs
For the worst case DNL, we can write thatDNL = (28-1)(±0.005) = ±1.275 LSBs
Chapter 10 – Section 2 (5/2/04) Page 10.2-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.2-3 - Influence of Capacitor Ratio Accuracy on Number of Bits
Use the data of Fig. 2.4-2 to estimate the number of bits possible for a charge scalingDAC assuming a worst case approach for INL and that the worst conditions occur at themidscale (1 MSB). Solution
Assuming an INL of ±0.5 LSB, we can write that
INL = ±2N-1 ∆CC ≤ ±
12 →
∆C
C = 1
2N .
From the data presented in Chapter 2, it is reasonable to assume that the relativeaccuracy of the capacitor ratios will decrease with the number of bits. Let us assume aunit capacitor of 50 µm by 50 µm and a relative accuracy of approximately ±0.1%.Solving for N in the above equation gives approximately 10 bits. However, the ±0.1%figure corresponds to ratios of 16:1 or 4 bits. In order to get a solution, we estimate therelative accuracy of capacitor ratios as
∆CC ≈ 0.001 + 0.0001N
Using this approximate relationship, a 9-bit digital-analog converter should berealizable.
Chapter 10 – Section 2 (5/2/04) Page 10.2-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Binary Weighted, Charge Amplifier DAC
+
-b0
VREF
2N-1
CF = 2NC/K
+
-
vOUT
C2C
φ1
φ1
+
-
b0 b1φ1 b1 b2φ1 b2 bN-1φ1 bN-1
Fig. 10.2-12
C
bN-2φ1 bN-2
2N-2C 2N-3C
Attributes: • No floating nodes which implies insensitive to parasitics and fast • No terminating capacitor required
• With the above configuration, charge feedthrough will be ∆Verror ≈ -(COL/2CN)∆V
• Can totally eliminate parasitics with parasitic-insensitive switched capacitor circuitrybut not the charge feedthrough
Chapter 10 – Section 2 (5/2/04) Page 10.2-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of the Parallel DAC Performance
DAC Type Advantage DisadvantageCurrentScaling
Fast, insensitive toswitch parasitics
Large element spread,nonmonotonic
VoltageScaling
Monotonic, equalresistors
Large area, sensitiveto parasiticcapacitance
ChargeScaling
Fast, good accuracy Large element spread,nonmonotonic
Chapter 10 – Section 3 (5/2/04) Page 10.3-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 10.3 - EXTENDING THE RESOLUTION OF PARALLELDIGITAL-ANALOG CONVERTERS
BackgroundTechnique:
Divide the total resolution N into k smaller sub-DACs each with a resolution of Nk .
Result:Smaller total area.More resolution because of reduced largest to smallest component spread.
Approaches:• Combination of similarly scaled subDACs
Divider approach (scale the analog output of the subDACs)Subranging approach (scale the reference voltage of the subDACs)
• Combination of differently scaled subDACs
Chapter 10 – Section 3 (5/2/04) Page 10.3-2
CMOS Analog Circuit Design © P.E. Allen - 2004
COMBINATION OF SIMILARLY SCALED SUBDACsAnalog Scaling - Divider ApproachExample of combining a m-bitand k-bit subDAC to form am+k-bit DAC.
vOUT =
b0
2 + b14 + ··· +
bm-12m VREF +
1
2m
bm
2 + bm+1
4 + ··· + bm+k-1
2k VREF
vOUT =
b0
2 + b14 + ··· +
bm-12m +
bm2m+1 +
bm+12m+2 + ··· +
bm+k-12m+k VREF
Accuracy?
Weighting factor of the i-th bit = VREF2i+1
2n
2n = 2n-i-1 LSBs
Accuracy of the i-th bit = ±0.5 LSB2n-i-1 LSB =
12n-i =
1002n-i %
m-MSBbits
k-LSBbits
m-bitMSBDAC
k-bitLSBDAC
÷ 2m
VREF
VREF
Σ++
vOUT
Fig. 10.3-1
Chapter 10 – Section 3 (5/2/04) Page 10.3-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.3-1 - Illustration of the Influence of the Scaling FactorAssume that m = 2 and k = 2 in Fig. 10.3-1 and find the transfer characteristic of this
DAC if the scaling factor for the LSB DAC is 3/8 instead of 1/4. Assume that VREF = 1V.What is the ±INL and ±DNL for this DAC? Is this DAC monotonic or not?
Solution
The ideal DAC output is given as
vOUT = b02 +
b14 +
14
b2
2 + b34 =
b02 +
b14 +
b28 +
b316 .
The actual DAC output can be written as
vOUT(act.) = b02 +
b14 +
3b216 +
3b332 =
16b032 +
8b132 +
6b232 +
3b332
The results are tabulated in Table 10.3-1 for this example.
Chapter 10 – Section 3 (5/2/04) Page 10.3-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.3-1 - Continued Table 10.3-1
Ideal and Actual Analog Output for the DAC in Ex. 10.3-1,
Table 10.3-1 contains allthe information we areseeking. An LSB for thisexample is 1/16 or 2/32.The fourth column gives the+INL as 1.5LSB and the -INL as 0LSB. The fifthcolumn gives the +DNL as-0.5LSB and the -DNL as-1.5LSB. Because the -DNLis greater than -1LSB, thisDAC is not monotonic.
InputDigitalWord
vOUT(act.) vOUT vOUT(act.)- vOUT
Change invOUT(act) -
2/320000 0/32 0/32 0/32 -0001 3/32 2/32 1/32 1/320010 6/32 4/32 2/32 1/320011 9/32 6/32 3/32 1/320100 8/32 8/32 0/32 -3/320101 11/32 10/32 1/32 1/320110 14/32 12/32 2/32 1/320111 17/32 14/32 3/32 1/321000 16/32 16/32 0/32 -3/321001 19/32 18/32 1/32 1/321010 22/32 20/32 2/32 1/321011 25/32 22/32 3/32 1/321100 24/32 24/32 0/32 -3/321101 27/32 26/32 1/32 1/321110 30/32 28/32 2/32 1/321111 33/32 30/32 3/32 1/32
Chapter 10 – Section 3 (5/2/04) Page 10.3-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.3-2 - Tolerance of the Scaling Factor to Prevent Conversion ErrorsFind the worst case tolerance of the scaling factor (x = 1/2m = 1/4) in the above
example that will not cause a conversion error in the DAC.Solution
Because the scaling factor only affects the LSB DAC, we need only consider the twoLSB bits. The worst case requirement for the ideal scaling factor of 1/4 is given as
b22 x ± ∆x +
b34 x ± ∆x ≤
xb22 +
xb34 ±
132
or
∆x
b2
2 + ∆x
b3
4 = ∆x
b2
2 + b34 ≤
132 .
The worst case value of ∆x occurs when both b2 and b3 are 1. Therefore, we get
∆x
3
4 ≤ 1
32 → ∆x ≤ 1
24 .
The scaling factor, x, can be expressed as
x ± ∆x = 14 ±
124 =
624 ±
124
Therefore, the tolerance required for the scaling factor x is 5/24 to 7/24. This correspondsto an accuracy of ±16.7% which is less than the ±25% (±100%/2k) because of theinfluence of the LSB bits. It can be shown that the INL will be equal to ±0.5LSB or less(see Problem 10.3-6 of text).
Chapter 10 – Section 3 (5/2/04) Page 10.3-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Reference Scaling - Subranging ApproachExample of combining a m-bit and k-bit subDAC to form a m+k-bit DAC.
m-MSBbits
k-LSBbits
m-bitMSBDAC
k-bitLSBDAC
VREF
VREF/2m
Σ++
vOUT
Fig. 10.3-2
vOUT =
b0
2 + b14 + ··· +
bm-12m VREF +
bm
2 + bm+1
4 + ··· + bm+k-1
2k
VREF
2m
vOUT =
b0
2 + b14 + ··· +
bm-12m +
bm2m+1 +
bm+12m+2 + ··· +
bm+k-12m+k VREF
Accuracy considerations of this method are similar to the analog scaling approach.
Chapter 10 – Section 3 (5/2/04) Page 10.3-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Current Scaling Dac Using Two SubDACsImplementation:
+
-
I16
I8
I4
I2
I16
I8
I4
I2
15R
RLSB MSB
RF vOUTioi2i1
MSB subDACLSB subDAC
b0b1b2b3b4b5b6b7
CurrentDivider
Fig. 10.3-3
vOUT = RFI
b0
2 + b14 +
b28 +
b316 +
116
b4
2 + b54 +
b68 +
b716
Chapter 10 – Section 3 (5/2/04) Page 10.3-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Charge Scaling DAC Using Two SubDACsImplementation:
+
-
VREF
φ1
C2C
4C
φ2
b7
φ2 φ2 φ2 φ2
b6 b5 b1 b0
vOUT
C
φ2
b48
C8
φ2
b3
φ2
b2
C2C
4CC
8
Cs
Scal
ing
Cap
acito
r
LSB Array MSB ArrayTerminatingCapacitor
Fig. 10.3-4
Design of the scaling capacitor, Cs:
The series combination of Cs and the LSB array must terminate the MSB array orequal C/8. Therefore, we can write
C8 =
11Cs
+ 1
2C or
1Cs
= 8C -
12C =
162C -
12C =
152C .
Chapter 10 – Section 3 (5/2/04) Page 10.3-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Equivalent Circuit of the Charge Scaling Dac Using Two SubDACsSimplified equivalent circuit:
where the Thevenin equivalent voltageof the MSB array is
V1 =
1
15/8 b0 +
1/2
15/8 b1 +
1/4
15/8 b2 +
1/8
15/8 b3 VREF = 1615
b0
2 + b14 +
b28 +
b316 VREF
and the Thevenin equivalent voltage of the LSB array is
V2 =
1/1
2 b4 +
1/2
2 b5 +
1/4
2 b6 +
1/8
2 b7 VREF =
b4
2 + b54 +
b68 +
b816 VREF
Combining the elements of the simplified equivalent circuit above gives
vOUT=
1
2 +152
12 +
152 +
815
V1+
8
1512 +
152 +
815
V2 =
15+15·15
15+15·15+16 V1+
16
15+15·15+16 V2 = 1516V1+
116V2
vOUT =
b0
2 + b14 +
b28 +
b316 +
b432 +
b564 +
b6128 +
b7256 VREF =
7Σi=0
biVREF
2i+1
+
-
Cs = 2C/15
C + 7C/8 = 15C/8
V1V2
2CvOUT
Fig. 10.3-5
Chapter 10 – Section 3 (5/2/04) Page 10.3-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Charge Amplifier DAC Using Two Binary Weighted Charge Amplifier SubDACsImplementation:
VREF
+
-
vOUT
+
-
C
b4 φ1
b4
C/2
b5 φ1
b5
b6 φ1
b6
b7 φ1
b7
C/4
C/8
+
-2C
φ1
VREF+
-
C
b0 φ1
b0
C/2
b1 φ1
b1
b2 φ1
b2
b3 φ1
b3
C/4
C/8
+
-2C
φ1
C/8
A1 A2
LSB Array MSB Array
vO1
Fig. 10.3-6
Attributes:• MSB subDAC is not dependent upon the accuracy of the scaling factor for the LSB
subDAC.• Insensitive to parasitics, fast• Limited to op amp dynamics• No ICMR problems with the op amp
Chapter 10 – Section 3 (5/2/04) Page 10.3-11
CMOS Analog Circuit Design © P.E. Allen - 2004
COMBINATION OF DIFFERENTLY SCALED SUBDACsVoltage Scaling MSB SubDAC And Charge Scaling LSB SubDACImplementation:
Ck =2k-1C
Sk-1,A
SF
SF
Bus A
Bus B
Sk,A
Sk,B
Ck-1 =2k-2C
Sk-1,B
C2
=2CC1
=CC
vOUT
S2A
S2B
S1A
S1B
m-to-2m Decoder A
m-to-2m Decoder BVREF
R1 R2 R3 R2m-2 R2m-1 R2m
m-MSB bits
m-MSB bits
m-bit, MSB voltagescaling subDAC
k-bit, LSB chargescaling subDAC
Fig. 10.3-7
Operation:1.) Switches SF and S1B through Sk,B discharge all capacitors.
2.) Decoders A and B connect Bus A and Bus B to the top and bottom, respectively, ofthe appropriate resistor as determined by the m-bits.3.) The charge scaling subDAC divides the voltage across this resistor by capacitivedivision determined by the k-bits.Attributes:• MSB’s are monotonic but the accuracy is poor • Accuracy of LSBs is good
Chapter 10 – Section 3 (5/2/04) Page 10.3-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Voltage Scaling MSB SubDAC And Charge Scaling LSB SubDAC - ContinuedEquivalent circuit of the voltage scaling (MSB) and charge scaling (LSB) DAC:
Ck =2k-1C
Sk-1,A
Bus A
Bus B
Sk,A
Sk,B
Ck-1 =2k-2C
Sk,B
C2
=2CC1
=CC
vOUTS2A
S2B
S1A
S1B
2-mVREF
V'REF
2-mVREF
V'REF
vOUT
Ceq.
2kC - Ceq.
Bus A
Bus B
v'OUT
Fig. 10.3-8
where,
V’REF = VREF
b0
21 + b122 + ··· +
bm-22m-1 +
bm-12m
and
v’OUT = VREF2m
bm
2 + bm+122 + ··· +
bm+k2k-1 +
bm+k-12k = VREF
bm
2m+1 + bm+12m+2 + ··· +
bm+k2m+k-1 +
bm+k-12m+k
Adding V’REF and v’OUT gives the DAC output voltage as
vOUT = V’REF+v’OUT = VREFb021 +
b122 +···+
bm-22m-1 +
bm-12m +
bm2m+1 +
bm+12m+2 +···+
bm+k2m+k-1 +
bm+k-12m+k
which is equivalent to an m+k bit DAC.
Chapter 10 – Section 3 (5/2/04) Page 10.3-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Charge Scaling MSB SubDAC and Voltage Scaling LSB SubDAC
vOUT =
b0
21 + b122 +···+
bm-22m-1 +
bm-12m VREF +
vk2m where vk =
bm
21 + bm+122 +···+
bm+k2k-1 +
bm+k-12k VREF
∴ vOUT =
b0
21 + b122 + ··· +
bm-22m-1 +
bm-12m +
bm2m+1 +
bm+12m+2 + ··· +
bm+k2m+k-1 +
bm+k-12m+k VREF
Attributes:• MSBs have good accuracy• LSBs are monotonic, have poor accuracy - require trimming for good accuracy
C1 =2mC
S2,AS1,A
S1,B
C2 =2m-1C
S2,B
Cm-1
=21CCm
=CCm=C
vOUTSm-2A
Sm-2B
Sm-1A
Sm-1BVREF
k-to-2k
Decoder
k-LSB bits
R1
R2
R3
R2k-2
R2k-1
R2k
VREF
m-bit, MSB charge scaling subDAC
k-bit,LSB
voltage scaling
subDAC
vk
Fig. 10.3-9A
Chapter 10 – Section 3 (5/2/04) Page 10.3-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Tradeoffs in SubDAC Selection to Enhance Linearity PerformanceAssume a m-bit MSB subDAC and a k-bit LSB subDAC.
MSB Voltage Scaling SubDAC and LSB Charge Scaling SubDAC (n = m+k)INL and DNL of the m-bit MSB voltage-scaling subDAC:
INL(R) = 2m-1
2n
2m ∆RR = 2n-1
∆RR LSBs and DNL(R) =
±∆RR
2n
2m = 2k ±∆R
R LSBs
INL and DNL of the k-bit LSB charge-scaling subDAC:
INL(C) = 2k-1 ∆CC LSBs and DNL(C) = (2k-1)
∆CC LSBs
Combining these relationships:
INL = INL(R) + INL(C) =
2n-1 ∆RR + 2k-1
∆CC LSBs
and DNL = DNL(R) + DNL(C) =
2k ∆RR + (2k-1)
∆CC LSBs
MSB Charge Scaling SubDAC and LSB Voltage Scaling SubDAC
INL = INL(R) + INL(C) =
2k-1 ∆RR + 2n-1
∆CC LSBs
and DNL = DNL(R) + DNL(C) =
∆R
R + (2n-1) ∆CC LSBs
Chapter 10 – Section 3 (5/2/04) Page 10.3-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.3-3 - Design of a DAC using Voltage Scaling for MBSs and ChargeScaling for LSBs
Consider a 12-bit DAC that uses voltage scaling for the MSBs charge scaling for theLSBs. To minimize the capacitor element spread and the number of resistors, choose m =5 and k = 7. Find the tolerances necessary for the resistors and capacitors to give an INLand DNL equal to or less than 2 LSB and 1 LSB, respectively.
Solution
Substituting n = 12 and k = 7 into the previous equations gives
2 = 211 ∆RR + 26
∆CC and 1 = 27
∆RR + (27-1)
∆CC
Solving these two equations simultaneously gives∆CC =
25-2211 - 26 - 25 = 0.0154 →
∆CC = 1.54%
and∆RR =
2 - 26(0.0154)211 = 0.0005 →
∆RR = 0.05%
We see that the capacitor tolerance will be easy to meet but that the resistortolerance will require resistor trimming to meet the 0.05% requirement. Because of the2n-1 multiplying ∆R/R in the relationship, it will not do any good to try different values ofm and k. This realization will consist of 32 equal value resistors and 7 binary-weightedcapacitors with an element spread of 64.
Chapter 10 – Section 3 (5/2/04) Page 10.3-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.3-4 - Design of a DAC using Charge Scaling for MBSs and VoltageScaling for LSBs
Consider a 12-bit DAC that uses charge scaling for the MSBs voltage scaling for theLSBs. To minimize the capacitor element spread and the number of resistors, choose m =7 and k = 5. Find the tolerances necessary for the resistors and capacitors to give an INLand DNL equal to or less than 2 LSB and 1 LSB, respectively.Solution
Substituting the values of this example into the relationships developed on a previousslide, we get
2 = 24 ∆RR + 211
∆CC and 1 =
∆RR + (212-1)
∆CC
Solving these two equations simultaneously gives∆CC =
24-2216-211-24 = 0.000221 →
∆CC = 0.0221% and
∆RR ≈
325-1 = 0.0968 →
∆RR = 9.68%
For this example, the resistor tolerance is easy to meet but the capacitor tolerance willbe difficult. To achieve accurate capacitor tolerances, we should decrease the value of mand increase the value of k to achieve a smaller capacitor value spread and therebyenhance the tolerance of the capacitors. If we choose m = 5 and k = 7, the capacitortolerance remains about the same but the resistor tolerance becomes 2.36% which is stillreasonable. The largest to smallest capacitor ratio is 16 rather than 64 which will help tomeet the capacitor tolerance requirements.
Chapter 10 – Section 3 (5/2/04) Page 10.3-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Extended Resolution Dacs
• DAC resolution can be achieved by combining several subDACs with smaller resolution
• Methods of combining include scaling the output or the reference of the non-MSBsubDACs
• SubDACs can use similar or different scaling methods
• Tradeoffs in the number of bits per subDAC and the type of subDAC allow minimizationof the INL and DNL
Chapter 10 – Section 4 (5/2/04) Page 10.4-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 10.4 - SERIAL DIGITAL-ANALOG CONVERTERSSerial DACs• Typically require one clock pulse to convert one bit• Types considered here are:
Charge-redistributionAlgorithmic
Charge Redistribution DACImplementation:
VREF
S2
S3
S1
S4C2C1 vC2
Fig. 10.4-1Operation:
Switch S1 is the redistribution switch that parallels C1 and C2 sharing their chargeSwitch S2 precharges C1 to VREF if the ith bit, bi, is a 1Switch S3 discharges C1 to zero if the ith bit, bi, is a 0Switch S4 is used at the beginning of the conversion process to initially discharge C2Conversion always begins with the LSB bit and goes to the MSB bit.
Chapter 10 – Section 4 (5/2/04) Page 10.4-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.4-1 - Operation of the Serial, Charge Redistribution Digital-AnalogConverter
Assume that C1 = C2 and thatthe digital word to be convertedis given as b0 = 1, b1 = 1, b2 = 0,and b3 = 1. Follow through thesequence of events that result inthe conversion of this digitalinput word.Solution1.) S4 closes setting vC2 = 0.2.) b3 = 1, closes switch S2 causing vC1 = VREF.3.) Switch S1 is closed causing vC1 = vC2 = 0.5VREF.4.) b2 = 0, closes switch S3, causing vC1 = 0V.5.) S1 closes, the voltage across both C1 and C2 is 0.25VREF.6.) b1 = 1, closes switch S2 causing vC1 = VREF.7.) S1 closes, the voltage across both C1 and C2 is (1+0.25)/2VREF = 0.625VREF.8.) b0 = 1, closes switch S2 causing vC1 = VREF.9.) S1 closes, the voltage across both C1 and C2 is (0.625 + 1)/2VREF = 0.8125VREF =
(13/16)VREF.
0 1 2 3 4 5 6 7 8
1
3/4
1/2
1/4
0
t/T
v C1/
VR
EF
0 1 2 3 4 5 6 7 8
1
3/4
1/2
1/4
0
t/T
v C2/
VR
EF13/16 13/16
Fig. 10.4-2
Chapter 10 – Section 4 (5/2/04) Page 10.4-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Pipeline DACImplementation:
Σ z-11/2
bN-1 = ±1
Σ z-11/2
bN-2 = ±1
Σ z-11/2
b0 = ±1
0
VREF
vOUT
Fig. 10.4-3
Vout(z) = [b0z-1 + 2-1b1z-2 + ··· + 2-(N-2)bN-2z-(N-1) + bN-1z-N]VREF
where bi is either ±1 if the ith bit is high or low.
Attributes:• Takes N+1 clock cycles to convert the digital input to an analog output• However, a new analog output is converted every clock after the initial N+1 clocks
Chapter 10 – Section 4 (5/2/04) Page 10.4-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Algorithmic (Iterative) DACImplementation:
ΣSample
andhold
+1
+1
12
+VREF A
B-VREF
vOUT
FIG. 10.4-4
Closed form of the previous series expression is,
Vout(z) = biz-1VREF1 - 0.5z-1
Operation:Switch A is closed when the ith bit is 1 and switch B is closed when the ith bit is 0.Start with the LSB and work to the MSB.
Chapter 10 – Section 4 (5/2/04) Page 10.4-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.4-2 - Digital-Analog Conversion Using the Algorithmic MethodAssume that the digital word to be converted is 11001 in the order of MSB to LSB.
Find the converted output voltage and sketch a plot of vOUT/VREF as a function of t/T,where T is the period for one conversion.Solution1.) The conversion starts by zeroing the
output (not shown on Fig. 10.4-4).2.) The LSB = 1, switch A is closed and
VREF is summed with zero to give anoutput of +VREF.
3.) The next LSB = 0, switch B is closed andvOUT = -VREF+0.5VREF = -0.5VREF.
4.) The next LSB = 0, switch B is closed andvOUT = -VREF+0.5(-0.5VREF) = -1.25VREF.
5.) The next LSB = 1, switch A is closed and vOUT = VREF+0.5(-1.25VREF) = 0.375VREF.
6.) The MSB = 1, switch A is closed and vOUT = VREF + 0.5(0.375VREF) = 1.1875VREF =(19/16)VREF. (Note that because the actual VREF of this example if ±VREF or 2VREF,the analog value of the digital word 11001 is 19/32 times 2VREF or (19/16)VREF.)
0 1 2 3 4 5
2.0
19/161.0
0
-1/2
3/8
-1.0-5/4
-2.0
vOUT/VREF
t/T
Fig. 10.4-5
Chapter 10 – Section 4 (5/2/04) Page 10.4-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Serial DACSTable 10.4-1 - Summary of the Performance of Serial DACs
Serial DAC Figure Advantage DisadvantageSerial, ChargeRedistribution
10.4-1 Simple,minimum area
Slow, requires complexexternal circuitry,precise capacitor ratios
Serial,algorithmic
10.4-3 Simple,minimum area
Slow, requires complexexternal circuitry,precise capacitor ratios
Chapter 10 – Section 4 (5/2/04) Page 10.4-7
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY OF THE PERFORMANCE OF DIGITAL-ANALOG CONVERTERSDAC Figure Primary Advantage Primary Disadvantage
Current-scaling, binaryweighted resistors
10.2-3 Fast, insensitive to parasitic capacitance Large element spread, nonmonotonic
Current-scaling, R-2R ladder 10.2-4 Small element spread, increased accuracy Nonmonotonic, limited to resistoraccuracy
Current-scaling, activedevices
10.2-5 Fast, insensitive to switch parasitics Large element spread, large area
Voltage-scaling 10.2-7 Monotonic, equal resistors Large area, sensitive to parasiticcapacitance
Charge-scaling,binary weighted capacitors
10.2-10 Best accuracy Large area, sensitive to parasiticcapacitance
Binary weighted, chargeamplifier
10.2-12 Best accuracy, fast Large element spread, large area
Current-scaling subDACsusing current division
10.3-3 Minimizes area, reduces element spreadwhich enhances accuracy
Sensitive to parasitic capacitance, dividermust have –0.5LSB accuracy
Charge-scaling subDACsusing charge division
10.3-4 Minimizes area, reduces element spreadwhich enhances accuracy
Sensitive to parasitic capacitance, slower,divider must have –0.5LSB accuracy
Binary weighted chargeamplifier subDACs
10.3-6 Fast, minimizes area, reduces elementspread which enhances accuracy
Requires more op amps, divider musthave –0.5LSB accuracy
Voltage-scaling (MSBs),charge-scaling (LSBs)
10.3-7 Monotonic in MSBs, minimum area,reduced element spread
Must trim or calibrate resistors forabsolute accuracy
Charge-scaling (MSBs),voltage-scaling (LSBs)
10.3-8 Monotonic in LSBs, minimum area,reduced element spread
Must trim or calibrate resistors forabsolute accuracy
Serial, charge redistribution 10.4-1 Simple, minimum area Slow, requires complex external circuitsPipeline, algorithmic 10.4-3 Repeated blocks, output at each clock
after N clocksLarge area for large number of bits
Serial, iterative algorithmic 10.4-4 Simple, one precise set of components Slow, requires additional logic circuitry
Chapter 10 – Section 5 (5/2/04) Page 10.5-1
CMOS Analog Circuit Design © P.E. Allen - 2004
10.5 - CHARACTERIZATION OF ANALOG-DIGITAL CONVERTERSALL YOU EVER WANTED TO KNOW ABOUT A/D CONVERTERS†
† From The Institute, September 1989, page 5
Chapter 10 – Section 5 (5/2/04) Page 10.5-2
CMOS Analog Circuit Design © P.E. Allen - 2004
General Block Diagram of an Analog-Digital Converter
DigitalProcessor
Prefilter Sample/Hold Quantizer Encoder
x(t) y(kTN)
Fig.10.5-1
• Prefilter - Avoids the aliasing of high frequency signals back into the baseband of theADC
• Sample-and-hold - Maintains the input analog signal constant during conversion• Quantizer - Finds the subrange that corresponds to the sampled analog input• Encoder - Encoding of the digital bits corresponding to the subrange
Chapter 10 – Section 5 (5/2/04) Page 10.5-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Nyquist Frequency Analog-Digital ConvertersThe sampled nature of the ADC places a practical limit on the bandwidth of the input
signal. If the sampling frequency is fS, and fB is the bandwidth of the input signal, thenfB < 0.5fS
which is simply the Nyquistrelationship which states thatto avoid aliasing, thesampling frequency must begreater than twice thehighest signal frequency.
fB-fB 0 f
fB-fB 0 fSfS-fB fS+fB 2fS2fS-fB 2fS+fBf
-fB 0 fS 2fSf
AntialiasingFilter
fS2
fB-fB 0f
fS2
fS2
fS
fS
Continuous time frequency response of the analog input signal.
Sampled data equivalent frequency response where fB < 0.5fS.
Case where fB > 0.5fS causing aliasing.
Use of an antialiasing filter to avoid aliasing.
Fig. 10.5-2
Chapter 10 – Section 5 (5/2/04) Page 10.5-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Classification of Analog-Digital ConvertersAnalog-digital converters can be classified by the relationship of fB and 0.5fS and by theirconversion rate.• Nyquist ADCs - ADCs that have fB as close to 0.5fS as possible.
• Oversampling ADCs - ADCs that have fB much less than 0.5fS.
Table 10.5-1 - Classification of Analog-to-Digital Converter Architectures
ConversionRate
Nyquist ADCs Oversampled ADCs
Slow Integrating (Serial) Very high resolution >14 bits
MediumSuccessive
Approximation1-bitPipeline Algorithmic
Moderate resolution >10 bits
FastFlash Multiple-bit
Pipeline Folding andinterpolating
Low resolution > 6 bits
Chapter 10 – Section 5 (5/2/04) Page 10.5-5
CMOS Analog Circuit Design © P.E. Allen - 2004
STATIC CHARACTERIZATION OF ANALOG-TO-DIGITAL CONVERTERSDigital Output Codes
Table 10.5-2 - Digital Output Codes used for ADCs
Decimal Binary Thermometer Gray Two’sComplement
0 000 0000000 000 0001 001 0000001 001 1112 010 0000011 011 1103 011 0000111 010 1014 100 0001111 110 1005 101 0011111 111 0116 110 0111111 101 0107 111 1111111 100 001
Chapter 10 – Section 5 (5/2/04) Page 10.5-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Input-Output CharacteristicsIdeal input-output characteristics of a 3-bit ADC
Analog Input Value Normalized to VREF
000
001
010
011
100
101
110
111
Dig
ital O
utpu
t Cod
e
Ideal 3-bitCharacteristic
Figure 10.5-3 Ideal input-output characteristics of a 3-bit ADC.
Infinite ResolutionCharacteristic
1 LSB
18
28
38
48
58
68
08
78
1 LSB
vinVREF
0.5
1.0
0.0-0.5Q
uant
izat
ion
Noi
se L
SBs
88
Chapter 10 – Section 5 (5/2/04) Page 10.5-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Definitions• The dynamic range, signal-to-noise ratio (SNR), and the effective number of bits
(ENOB) of the ADC are the same as for the DAC• Resolution of the ADC is the smallest analog change that distinguishable by an ADC.• Quantization Noise is the ±0.5LSB uncertainty between the infinite resolution
characteristic and the actual characteristic.• Offset Error is the difference between the ideal finite resolution characteristic and
actual finite resolution characteristic• Gain Error is the
difference betweenthe ideal finiteresolution charact-eristic and actualfinite resolutioncharacteristicmeasured at full-scale input. Thisdifference isproportional to theanalog inputvoltage.
000
001
010
011
100
101
110
111
vinVREF
Dig
ital O
utpu
t Cod
e
Offset = 1.5 LSBs
000
001
010
011
100
101
110
111
08
18
28
38
48
58
68
78
88
vinVREF
Dig
ital O
utpu
t Cod
e
Gain Error = 1.5LSBs
(a.) (b.)Figure 10.5-4 - (a.) Example of offset error for a 3-bit ADC. (b.) Example of gainerror for a 3-bit ADC.
IdealCharacteristic
IdealCharacteristic
08
18
28
38
48
58
68
78
88
ActualCharacteristic
Chapter 10 – Section 5 (5/2/04) Page 10.5-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Integral and Differential NonlinearityThe integral and differential nonlinearity of the ADC are referenced to the vertical
(digital) axis of the transfer characteristic.• Integral Nonlinearity (INL) is the maximum difference between the actual finite
resolution characteristic and the ideal finite resolution characteristic measured vertically(% or LSB)
• Differential Nonlinearity (DNL) is a measure of the separation between adjacent levelsmeasured at each vertical step (% or LSB).
DNL = (Dcx - 1) LSBs
where Dcx is the size of the actual vertical step in LSBs.
Note that INL and DNL of an analog-digital converter will be in terms of integers incontrast to the INL and DNL of the digital-analog converter. As the resolution of theADC increases, this restriction becomes insignificant.
Chapter 10 – Section 5 (5/2/04) Page 10.5-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Example of INL and DNL
000
001
010
011
100
101
110
111
08
18
28
38
48
58
68
78
88
vinVREF
Dig
ital O
utpu
t Cod
e
Example of INL and DNL for a 3-bit ADC.) Fig.10.5-5
IdealCharacteristic
ActualCharacteristic
INL =+1LSB
INL =-1LSB
DNL =+1LSB
DNL =0 LSB
Chapter 10 – Section 5 (5/2/04) Page 10.5-10
CMOS Analog Circuit Design © P.E. Allen - 2004
MonotonicityA monotonic ADC has all vertical jumps positive. Note that monotonicity can only be
detected by DNL.Example of a nonmonotonic ADC:
000
001
010
011
100
101
110
111
08
18
28
38
48
58
68
78
88
vinVREF
Dig
ital O
utpu
t Cod
e
DNL =-2 LSB
ActualCharacteristic
IdealCharacteristic
Fig. 10.5-6L
If a vertical jump is 2LSB or greater, missing output codes may result.If a vertical jump is -1LSB or less, the ADC is not monotonic.
Chapter 10 – Section 5 (5/2/04) Page 10.5-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.5-2 - INL and DNL of a 3-bit ADC
Find the INL and DNL for the 3-bit ADC shown on the previous slide.SolutionWith respect to the digital axis:1.) The largest value of INL for this 3-bit ADC occurs between 3/16 to 5/16 or 7/16 to
9/16 and is 1LSB. 2.) The smallest value of INL occurs
between 11/16 to 12/16 and is-2LSB.
3.) The largest value of DNL occurs at3/16 or 6/8 and is +1LSB.
4.) The smallest value of DNL occursat 9/16 and is -2LSB which iswhere the converter becomesnonmonotonic.
000
001
010
011
100
101
110
111
08
18
28
38
48
58
68
78
88
vinVREF
Dig
ital O
utpu
t Cod
e
DNL =-2 LSB
ActualCharacteristic
IdealCharacteristic
Fig. 10.5-6DL
INL =+1LSB
INL =-2LSB
DNL =+1 LSB
Chapter 10 – Section 5 (5/2/04) Page 10.5-12
CMOS Analog Circuit Design © P.E. Allen - 2004
DYNAMIC CHARACTERISTICSThe dynamic characteristics of ADCs are influenced by:
• Comparators• Sample-hold circuits• Circuit parasitics• Logic propagation delay
Chapter 10 – Section 5 (5/2/04) Page 10.5-13
CMOS Analog Circuit Design © P.E. Allen - 2004
ComparatorThe comparator is the quantizing unit of ADCs.
Open-loop model:
+
-Av(s)ViVi
VOS
Ri
RoVo
V1
V2Comparator Fig.10.5-7
Nonideal aspects:• Input offset voltage, VOS (a static characteristic)
• Propagation time delay- Bandwidth (linear)
Av(s) = Av(0)sω c
+ 1 =
Av(0)sτc + 1
- Slew rate (nonlinear)
∆T = C·∆V
I (I is constant)
Chapter 10 – Section 5 (5/2/04) Page 10.5-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Linear Propagation Time Delay (Small input changes)If VOH and VOL are the maximum and minimum output voltages of the comparator,
then minimum input to the comparator (resolution) is
vin(min) = VOH - VOL
Av(0)
If the propagation time delay, tp, is the time required to go from VOH or from VOL toVOH+VOL
2 , then if vin(min) is applied to the comparator, the tp is,
VOH - VOL2 = Av(0) [1- e-tp/τc] vin(min) = Av(0) [1- e-tp/τc]
VOH - VOL
Av(0)
Therefore, tp is
tp(max) = τc ln(2) = 0.693τc
If vin is greater than vin(min), i.e. vin = kvin(min), then
tp = τc ln
2k
2k -1Illustration of these results:
+
-
VOH
VOL
tp(max)0t0
VOH+VOL2
vin > vin(min)
vin = vin(min)
vin
vout
vout
Fig.10.5-8tp
Chapter 10 – Section 5 (5/2/04) Page 10.5-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Nonlinear Propagation Time Delay (Large input changes)The output rises or falls with a constant rate as determined by the slew rate, SR.
∴ tp = ∆T = ∆VSR =
VOH - VOL2·SR
(If the rate of the output voltage of the comparator never exceeds SR , then thepropagation time delay is determined by the previous expression.)
Chapter 10 – Section 5 (5/2/04) Page 10.5-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.5-2 - Propagation Delay Time of a Comparator (Large input changes)Find the propagation delay time of an open loop comparator that has a dominant pole
at 103 radians/sec, a dc gain of 104, a slew rate of 1V/µs, and a binary output voltageswing of 1V. Assume the applied input voltage is 10mV.Solution
The input resolution for this comparator is 1V/104 or 0.1mV. Therefore, the 10mVinput is 100 times larger than vin(min) giving a k of 100. From the previous work,
tp = 1
103 ln
2·100
2·100-1 = 10-3 ln
200
199 = 5.01µs
If the output is slew-rate limited, then
tp = 1
2·1x106 = 0.5µs
Therefore, the propagation delay time for this case is the larger or 5.01µs.Note that the maximum slope of the linear response is
Max
dvout
dt = ddt
Av(0)[1-e-t/τc](0.01V) =
Av(0)τc e-t/τc(0.01V) =
Av(0)100τc
= 104·103
100 = 0.1V/µs
Since the maximum rate of the linear response is less than the slew rate, the response islinear and the propagation time delay is 5.01µs.
Chapter 10 – Section 5 (5/2/04) Page 10.5-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Sample-and-Hold CircuitWaveforms of a sample-and-hold circuit:
Definitions:• Acquisition time (ta) = time requiredto acquire the analog voltage• Settling time (ts) = time required tosettle to the final held voltage to withinan accuracy tolerance
∴ Tsample = ta + ts → Maximum sample rate = fsample(max) = 1
Tsample
Other consideratons:• Aperture time= the time required for the sampling switch to open after the S/Hcommand is initiated• Aperture jitter = variation in the aperture time due to clock variations and noiseTypes of S/H circuits:• No feedback - faster, less accurate• Feedback - slower, more accurate
ta ts
Hold Sample HoldS/H Command
vin*(t)
vin*(t)vin(t)
vin(t)
Time
Am
plitu
de
Fig.10.5-9
Output of S/Hvalid for ADC
conversion
Chapter 10 – Section 5 (5/2/04) Page 10.5-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Open-Loop, Buffered S/H CircuitCircuit:
+-
φvin(t)vout(t)
CHSwitchClosed
(sample)
SwitchOpen(hold)
SwitchClosed
(sample)
vin(t)vout(t)
vin(t), vout(t) vin(t), vout(t)
Time
Am
plitu
de
Fig.10.5-10
Attributes:• Fast, open-loop• Requires current from the input to charge CH
• DC voltage offset of the op amp and the charge feedthrough of the switch will create dcerrors
Chapter 10 – Section 5 (5/2/04) Page 10.5-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Settling TimeAssume the op amp has a dominant pole at -ωa and a second pole at -GB.
The unity-gain response can be approximated as, A(s) ≈ GB2
s2 + GB·s + GB2
The resulting step response is, vout(t) = 1 -
4
3 e-0.5GB·t sin
3
4 GB·t + φ
Defining the error as the difference between the final normalized value and vout(t), gives,
Error(t) = ε = 1 - vout(t) = 43 e-0.5GB·t
In most ADCs, the error is equal to ±0.5LSB. Since the voltage is normalized,
12N+1 =
43 e-0.5GB·ts → e0.5GB·ts =
43 2N
Solving for the time, ts, required to settle with ±0.5LSB from the above equation gives
ts = 2
GB ln
4
3 2N = 1
GB [1.3863N + 1.6740]
Thus as the resolution of the ADC increases, the settling time for any unity-gain bufferamplifiers will increase. For example, if we are using the open-loop, buffered S/H circuitin a 10 bit ADC, the amount of time required for the unity-gain buffer with a GB of 1MHzto settle to within 10 bit accuracy is 2.473µs.
Chapter 10 – Section 5 (5/2/04) Page 10.5-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Open-Loop, Switched-Capacitor S/H CircuitCircuit:
+-
φ1dφ1φ2
vin(t) vout (t)C
+-
φ1dφ1φ2
vin(t) vout (t)
C
+-
C
φ2 φ1
φ1d
+
-
+
-
Fig.10.5-11
Switched capacitor S/H circuit. Differential switched-capacitor S/H
• Delayed clock used to remove input dependent feedthrough.• Differential version has lower PSRR, cancellation of even harmonics, and reduction of
charge injection and clock feedthrough
Chapter 10 – Section 5 (5/2/04) Page 10.5-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Open-Loop, Diode Bridge S/H CircuitCircuit:
Attributes:• Fast• Clock feedthrough is signal independent• Sample uncertainty caused by the finite slope of the clocks is minimized• During the hold phase the feedthrough from input to hold node is minimized because of
D5 and D6
IB
IB
Clock
Clock
VDD
VSS
CH
vout(t)vin(t)D1 D2
D3 D4
IB IB
VDD
VSS
CH
vout(t)vin(t)
D1 D2
D3 D4 +-
2IB
D5
D6SampleHold
M1 M2
Fig.10.5-12Diode bridge S/H circuit. Practical implementation of the diode bridge S/H.
Chapter 10 – Section 5 (5/2/04) Page 10.5-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Closed-Loop S/H CircuitCircuit:
+-
+-
φ1
φ1
φ2
CH
vout(t)
vin(t)
+- +
-φ1
φ2
CH
vout(t)vin(t)
Fig.10.5-13
Closed-loop S/H circuit. φ1 is the sample phase and φ2 is the hold phase.
An improved version.
Attributes:• Accurate• First circuit has signal-dependent feedthrough• Slower because of the op amp feedback loop
Chapter 10 – Section 5 (5/2/04) Page 10.5-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Closed-Loop, Switched Capacitor S/H CircuitsCircuit:
+- vout(t)vin(t) φ1dφ1
φ2
CH +-
φ2
φ1 φ2dφ1d
φ2 φ1d
φ2d
φ1d
φ2d
φ1d φ2
φ1
φ2φ1
CH
CH
CH
CH
CH
CH
vout(t)vin(t)
+
-
+
-
φ1 φ2d
-+
Fig.10.5-14
Switched capacitor S/H circuitwhich autozeroes the op ampinput offset voltage.
A differential version that avoids large changes at the op amp output
Attributes:• Accurate• Signal-dependent feedthrough eliminated by a delayed clock• Differential circuit keeps the output of the op amps constant during the φ1 phase
avoiding slew rate limits
Chapter 10 – Section 5 (5/2/04) Page 10.5-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Current-Mode S/H CircuitCircuit:
VDD
IB
CH
φ1φ1
φ2
iin iout
Fig.10.5-15
Attributes:• Fast• Requires current in and out• Good for low voltage implementations
Chapter 10 – Section 5 (5/2/04) Page 10.5-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Aperature Jitter in S/H CircuitsIllustration:
If we assume that vin(t) =Vpsinωt, then themaximum slope is equal toωVp.
Therefore, the value of ∆Vis given as
∆V =
dvin
dt ∆t = ωVp∆t .
The rms value of this noise is given as
∆V(rms) =
dvin
dt ∆t = ωVp∆t
2 .
The aperature jitter can lead to a limitation in the desired dynamic range of an ADC. Forexample, if the aperature jitter of the clock is 100ps, and the input signal is a full scalepeak-to-peak sinusoid at 1MHz, the rms value of noise due to this aperature jitter is111µV(rms) if the value of VREF = 1V.
Analog-DigitalConverter
Clock
AnalogInput
DigitalOutput ∆V
t
vin
Aperature Jitter = ∆tFigure10.5-14 - Illustration of aperature jitter in an ADC.
vin(to)
to
Chapter 10 – Section 5 (5/2/04) Page 10.5-26
CMOS Analog Circuit Design © P.E. Allen - 2004
TESTING OF ADCsInput-Output Test for an ADCTest Setup:
N-bitADCunder test
DAC withmore resolution
than ADC(N+2 bits)
DigitalWord
Output(N bits)
Fig.10.5-17
Vin Σ-
+
Vin'Qn =
Vin-Vin'
The ideal value of Qn should be within ±0.5LSB
Can measure:• Offset error = constant shift above or below the 0 LSB line• Gain error = contant increase or decrease of the sawtooth plot as Vin is increased
• INL and DNL (see following page)
Chapter 10 – Section 5 (5/2/04) Page 10.5-27
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of the Input-Output Test for a 4-Bit ADC
016
116
216
316
416
516
616
716
816
916
1016
1116
1216
1316
1416
1516
1616
0.0 LSB
0.5 LSB
1.0 LSB
1.5 LSB
2.0 LSB
-0.5 LSB
-1.0 LSB
-1.5 LSB
-2.0 LSB
Qua
ntiz
atio
n N
oise
(L
SBs)
Analog Input Normalized to VREF
+2LSBDNL
-2LSBINL
+2LSBINL
-2LSBDNL
Fig.10.5-18
Chapter 10 – Section 5 (5/2/04) Page 10.5-28
CMOS Analog Circuit Design © P.E. Allen - 2004
Measurement of Nonlinearity Using a Pure SinusoidThis test applies a pure sinusoid to the input of the ADC. Any nonlinearity will
appear as harmonics of the sinusoid. Nonlinear errors will occur when the dynamic range(DR) is less than 6N dB where N = number of bits.
N-bitADCunder test
Harmonicfree
sinusoid
Clock
Distortionor
SpectrumAnalyzer
t
|Vout(jω)|
ωfsig
SpectralOutput
1000
0
1000
1
1001
1
1111
1
Noise floordue to non-linearities
VREF
Fig. 10.5-19A
DR
N-bitDAC
with N+2bits
resolution
Vout(DAC)
Vout(DAC)
t
VREF
Vin
Vin
fsig
Comments:• Input sinusoid must have less distortion that the required dynamic range• DAC must have more accuracy than the ADC
Chapter 10 – Section 5 (5/2/04) Page 10.5-29
CMOS Analog Circuit Design © P.E. Allen - 2004
FFT Test for an ADCTest setup:
Analog-Digital
Converter
Fast RAM Buffer
FFTPost-
processor
PureSinusoidalInput, fin
Clockfc
FrequencySpectrum
Fig.10.5-19B
Comments:• Stores the digital output codes of the ADC in a RAM buffer• After the measurement, a postprocessor uses the FFT to analyze the quantization noise
and distortion components• Need to use a window to eliminate measurement errors (Raised Cosine or 4-term
Blackmann-Harris are often used)• Requires a spectrally pure sinusoid
Chapter 10 – Section 5 (5/2/04) Page 10.5-30
CMOS Analog Circuit Design © P.E. Allen - 2004
Histogram Test for an ADCThe number of occurances of each digital output code is plotted as a function of the digitaloutput code.Illustration:
Comments:• Emphasizesthe time spent at a given level and can show DNL and missing codes• DNL
DNL(i) = Width of the bin as a fraction of full scale
Ratio of the bin width to the ideal bin width -1 = H(i)/Nt
P(i) -1
whereH(i) = number of counts in the ith binNt = total number of samples
P(i) = ratio of the bin width to the ideal bin width• INL is found from the cumulative bin widths
0 MidScale
FullScale
Num
ber
of
Occ
uran
ces
Sinusoidal InputTriangular Input
OutputCode0
Fig.10.5-20
Chapter 10 – Section 5 (5/2/04) Page 10.5-31
CMOS Analog Circuit Design © P.E. Allen - 2004
Comparison of the Tests for Analog-Digital ConvertersOther Tests• Sinewave curve fitting (good for ENOB)• Beat frequency test (good for a qualitative measure of dynamic performance)Comparison
Test → Error↓
Histogramor
Code TestFFT Test
SinewaveCurve
Fit Test
BeatFrequency
TestDNL Yes (spikes) Yes (Elevated
noise floor)Yes Yes
Missing Codes Yes (Bin counts withzero counts)
Yes (Elevatednoise floor)
Yes Yes
INL Yes (Triangle inputgives INL directly)
Yes (Harmonics inthe baseband)
Yes Yes
AperatureUncertainty
No Yes (Elevatednoise floor)
Yes No
Noise No Yes (Elevatednoise floor)
Yes No
BandwidthErrors
No No No Yes (Measuresanalog bandwidth)
Gain Errors Yes (Peaks indistribution)
No No No
Offset Errors Yes (Offset ofdistribution average)
No No No
Chapter 10 – Section 5 (5/2/04) Page 10.5-32
CMOS Analog Circuit Design © P.E. Allen - 2004
Bibliography on ADC Testing1.) D. H. Sheingold, Analog-Digital Conversion Handbook, Analog Devices, Inc.,
Norwood, MA 02062, 1972.2.) S.A. Tretter, Introduction to Discrete-Time Signal Processing, John Wiley & Sons,
New York, 1976.3.) J. Doernberg, H.S. Lee, and D.A. Hodges, “Full-Speed Testing of A/D Converters,”
IEEE J. of Solid-State Circuits, Vol. SC-19, No. 6, December 1984, pp. 820-827.4.) “Dynamic performance testing of A to D converters,” Hewlett Packard Product Note
5180A-2.
Chapter 10 – Section 6 (5/2/04) Page 10.6-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 10.6 - SERIAL ANALOG-DIGITAL CONVERTERSIntroduction
Serial ADCs typically require 2NT for conversion where T = period of the clockTypes:• Single-slope• Dual-slope
Single-Slope ADCBlock diagram:
Attributes:• Simplicity of operation• Subject to error in the ramp generator• Long conversion time ≤ 2NT
RampGenerator vT
vT
vin*
vin*
nTt0
0
VREF
IntervalCounter
t
t
Clock
f =1/T
T
OutputCounter
nT
nT
Output
Reset
+-
Fig.10.6-1
n ≤ N
Chapter 10 – Section 6 (5/2/04) Page 10.6-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Dual-Slope ADCBlock diagram: Waveforms:
PositiveIntegrator
1
2
DigitalControl
Counter
vin*
-VREF
vint
Vth
CarryOutput Binary
Output
+-
Fig.10.6-2
Operation:1.) Initially vint = 0 and vin is sampled and held (vIN* > 0).2.) Reset the positive integrator by integrating a positive voltage until vint (0) = Vth.3.) Integrate vin* for NREF clock cycles to get,
vint(t1) = K ⌡⌠
0
NREFT
vin* dt + vint(0) = KNREFTvin* + Vth
4.) After NREF counts, the carry output of the counter closes switch 2 and-VREF isapplied to the positive integrator. The output of the integrator at t = t1+t2 is,
vint(t1+t2) = vint(t1)+K ⌡⌠
t1
NoutT
(−VREF)dt =Vth → KNREFTvin*+Vth -KNoutTVREF = Vth
5.) Solving for Nout gives, Nout = NREF (vin*/VREF)Comments: Conversion time ≤ 2(2N)T and the operation is independent of Vth and K.
vin
VREF+Vth
Vth0
0t
vin'''
vin''
vin'
Reset t0(start)
t1 = NREFT
t2' t2''t2'''
t2= NoutT
NREFT
Fig.10.6-3
vin''' > vin'' > vin'.
Chapter 10 – Section 7 (5/2/04) Page 10.7-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 10.7 - MEDIUM SPEED ANALOG-DIGITAL CONVERTERSIntroductionSuccessive Approximation Algorithm:1.) Start with the MSB bit and work toward the LSB bit.2.) Guess the MSB bit as 1.3.) Apply the digital word 10000.... to a DAC.4.) Compare the DAC output with the sampled analog input voltage.5.) If the DAC output is greater, keep the guess of 1. If the DAC output is less, changethe guess to 0.6.) Repeat for the next MSB.If the number of bits is N, the time for conversion will be NT where T is the clock period.Illustration:
vguessVREF
0.50VREF
00 1 2 3 4 5 6
tT
Fig.10.7-2
0.75VREF
0.25VREF
Chapter 10 – Section 7 (5/2/04) Page 10.7-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Block Diagram of a Successive Approximation ADC††
OutputRegister
Digital-AnalogConverter
Conditional
ShiftRegister Clock
Output
VREF
Vin*+-
Comparator
Fig.10.7-1 Gates
† R. Hnatek, A User's Handbook of D/A and A/D Converters, JohnWiley and Sons, Inc., New York, NY, 1976.
Chapter 10 – Section 7 (5/2/04) Page 10.7-3
CMOS Analog Circuit Design © P.E. Allen - 2004
5-Bit Successive Approximation ADC
AnalogSwitch
5
0 1FF5
R RD S
LSB
G5
AnalogSwitch
4
0 1FF4
R RD S
G4
VREF
LSB
AnalogSwitch
3
0 1FF3
R RD S
G3
AnalogSwitch
2
0 1FF2
R RD S
G2
AnalogSwitch
1
0 1FF1
R RD S
G1
MSB
5-bit Digital-Analog Converter
MSB
Shift Register
1SR5
1SR4SR3SR2SR1
111
Delay
-1
+ -
AnalogIn
Comp-arator
vIA vOA
Gate
Delay
Clock pulses
Start pulseThe delay allows for the circuit transients to settle before the comparator output is sampled. Fig.10.7-3
Chapter 10 – Section 7 (5/2/04) Page 10.7-4
CMOS Analog Circuit Design © P.E. Allen - 2004
m-Bit Voltage-Scaling, k-Bit Charge-Scaling Successive Approximation ADCImplementation:Operation:1.) With the two SFswitches closed, allcapacitors are paralleledand connected to Vin*
which autozeros thecomparator offsetvoltage.2.) With all capacitorsstill in parallel, a suc-cessive approximationsearch is performed tofind the resistor segmentin which the analogsignal lies.3.) Finally, a successive approximation search is performed on charge scaling subDAC toestablish the analog output voltage.
Ck =2k-1C
Sk-1,A
SBSF
Bus A
Bus B
Sk,A
Sk,B
Ck-1=2k-2C
Sk-1,B
C2=2C
C1=C
C
Vin*
S2A
S2B
S1A
S1B
m-to-2m Decoder A
m-to-2m Decoder BVREF
R1 R2 R3 R2m-2 R2m-1 R2m
m-MSB bits
m-MSB bits
m-bit, MSB voltagescaling subDAC
k-bit, LSB chargescaling subDAC
+-SF
m-MSB bits
ClockCapacitor Switches
(m+k) bit output of ADC Start
Successive approximationregister & switch control logic
Fig.10.7-4
Chapter 10 – Section 7 (5/2/04) Page 10.7-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Voltage-Scaling, Charge-Scaling Successive Approximation ADC - ContinuedAutozero Step
Removes the influence of the offset voltage of thecomparator.
The voltage across the capacitor is given as,vC = Vin* - VOS
Successive Approximation Search on the Resistor StringThe voltage at the comparator input is
vcomp = VRi - Vin*
If vcomp > 0, then VRi > Vin*, if vcomp < 0, then VRi < Vin*
Successive Approx. Search on the Capacitor SubDACThe input to the comparator is written as,
vcomp = (VRi+1 - V*in)
Ceq2kC + (VRi - V*
in) 2kC-Ceq
2kCHowever, VRi+1 = VRi + 2-mVREF
Combining gives,
vcomp = (VRi + 2-mVREF -V *IN)
Ceq2kC + (VRi-V *
IN) 2kC-Ceq
2kC
= VRi - V *IN + 2-mVREF
Ceq2kC
+-
Vin*+
-VOS
+ -vC
2kC
VOS
Fig.10.7-5
+
-VRi=V'REF
vcomp
2kC
Busses A and B
V*in
+ -
Fig.10.7-6a
Fig.10.7-6b
+
-
2-mVREF
VRi=V'REF
vcompCeq.
2kC - Ceq.
Bus A
Bus B
V*in
VRi+1
+ -
V*in
+ -+
-
Chapter 10 – Section 7 (5/2/04) Page 10.7-6
CMOS Analog Circuit Design © P.E. Allen - 2004
A Successive Approximation ADC Using a Serial DACImplementation:
Conversion Sequence:Digital-analog
Conversion
Digital-analog Input Word Comparator
Numberof
ChargingNumber d1 d2 d3 ... dN-1 dN Output Steps
1 1 aN 2
2 1 aN aN-1 4
3 1 aN-1 aN d1 aN-2 6
. . . . . . . .
. . . . . . . .N 1 a2 a3 ... aN-1 aN a1 2N
Total number of charging steps = N(N+1)
+-
Data storageregister
DAC controlregisterSerial
DAC(Fig.
10.4-1)
Vin*
1
S2 precharge
S3 discharge
S1 charge share
S4 reset
Sequence and control logic
Start
Clock
VDAC
VREF
Fig.10.7-7
Chapter 10 – Section 7 (5/2/04) Page 10.7-7
CMOS Analog Circuit Design © P.E. Allen - 2004
A Successive Approximation ADC Using a Serial DAC - ContinuedExample:Analog input is 13/16.
1xxx 11xx 111x 1101
0 1 2 0 1 2 3 4 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8
0.75
0.50
1.00
0.25
0.00
v c1/
VR
EF
t/T
1 bit 2 bits 3 bits 4 bits
0 1 2 0 1 2 3 4 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8
0.75
0.50
1.00
0.25
0.00
v c2/
VR
EF
t/T
13/16
Fig.10.7-8
Digital word out is b0 = 1, b1 = 1, b2 = 0, and b3 = 1.
Chapter 10 – Section 7 (5/2/04) Page 10.7-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Pipeline Analog-Digital Algorithmic ConverterImplementation:
Operation:• Each stage muliplies its input by 2 and adds or subtracts VREF depending upon the signof the input.• i-th stage,
Vi = 2Vi-1 - biVREF
where bi is given as
bi = +1 if Vi-1>0-1 if Vi-1<0
+ -
Σ z-12
±1Vin*
VREF
+ -
ΣVi-12
±1z-1
+ -
ΣVi2
±1z-1
+ -
i-th stage
MSB LSB
Fig.10.7-9Stage 1 Stage 2 Stage N
z-1
Vi/VREF1.0
-1.0
0 0.5 1.0-1.0 -0.50
bi+1=+1
bi+1=-1
bi = -1 bi = +1
Vi-1/VREF
[bi,bi+1] [0,0] [0,1] [1,0] [1,1] Fig.10.7-10
Chapter 10 – Section 7 (5/2/04) Page 10.7-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.7-1 - Illustration of the Operation of the Pipeline Algorithmic ADCAssume that the sampled analog input to a 4-bit pipeline algorithmic analog-digitalconverter is 2.00 V. If VREF is equal to 5 V, find the digital output word and the analogequivalent voltage.Solution
Stage No. Input to the ith stage, Vi-1 Vi-1 > 0? Bit i1 2V Yes 12 (2V·2) - 5 = -1V No 03 (-1V·2) + 5 = 3V Yes 14 (3V·2) - 5 = 1V Yes 1
Illustration:
Vanalog = 5
1
2 − 14 +
18 +
116
= 5(0.4375) = 2.1875
where bi = +1 if the ith-bit is 1
and bi = -1 if the ith bit is 0
-1
-0.8
-0.6
-0.4
-0.2
0
0.2St
age
Oup
uts
norm
aliz
ed to
V
0.4
0.6
0.8
1
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
RE
F
Stage 1
Stage 2
Stage 3
Stage 4
V in*/VREF
Chapter 10 – Section 7 (5/2/04) Page 10.7-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Achieving the High Speed Potential of the Pipeline Algorithmic ADCIf shift registers are used to store the output bits and align them in time, the pipeline ADCcan output a digital word at every clock cycle with a latency of NT.Illustration:
+ -
Σ z-12
±1Vin*
VREF
+ -
ΣVi-12
±1z-1
+ -
ΣVi2
±1z-1
+ -
i-th stage
MSB
LSB
Fig.10.7-9BStage 1 Stage 2 Stage N
z-1
SR
SR
SR
SR
i-th Bit
SR
SR
SR
MSB-1SR
Digital Ouput Word
Chapter 10 – Section 7 (5/2/04) Page 10.7-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Errors in the Pipeline Algorithmic ADCThe output voltage for the N-th stage can be written as,
VN = ∏N
i=1AiVin -
N-1Σ
i=1
∏
j = i+1
NAj bi-1 + bN-1 VREF
where Ai (Aj) is the actual gain of 2 for the i-th ( j-th) stage.
Errors include:1.) Gain errors - x2 amplifier or summing junctions2.) Offset errors - comparator or summing junctions
i-th stage including errors,Vi = AiVi-1 + VOSi - biAsiVREF
bi = = +1 if Vi-1>VOCi= -1 if Vi-1<VOCi
whereAi is the gain of “2” amplifier for the i-th stage
VOSi is the system offset errors of the i-th stage
Asi is the gain of “1” summer for the i-th stage
VOCi is the comparator offset voltage of the i-th stage
Chapter 10 – Section 7 (5/2/04) Page 10.7-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Errors in the Pipeline Algorithmic ADC - ContinuedIllustration ofthe errors
Example of an error analysis for a 4-bit pipeline algorithmic ADCThe output of the 4th stage can be written as,
V4 = 24·Vin - (23·b0+22·b1+21·b2+20·b3)VREF
The difference between the actual, V4’, and the ideal, V4, can be written as,|V4’-V4| = 23·∆A1Vin
An error will occur in the output of stage 4 if |V4’-V4| > VREF.
∴ ∆A1 ≤ VREF23Vin
The smallest value of ∆A1 occurs when Vin = VREF which gives ∆A1/A1 ≤ 1/24.It can be shown that the tolerance of A2 will be half of the tolerance of A1, and so forth.Generally, ∆A1/A1 ≤ 1/2N , VOS1 ≤ VREF/2N , and VOC1 ≤ VREF/2N
2∆Ai
Vo/VREF
Vi/VREF2∆Ai
1
1
-1
-1
00
2VOSi
Vo/VREF
Vi/VREF1
1
-1
-1
00
System offset error, VOSi. 2VOSi
Vo/VREF
Vi/VREF1
1
-1
-1
00
Comparator offset error, VOCi.2VOCi
Fig.10.7-12
Gain error, Ai.
Chapter 10 – Section 7 (5/2/04) Page 10.7-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.7-2 - Accuracy requirements for a 5-bit pipeline algorithmic ADCShow that if Vin = VREF, that the pipeline algorithmic ADC will have an error in the 5th bitif the gain of the first stage is 2-(1/8) =1.875 which corresponds to when an error willoccur. Show the influence of Vin on this result for Vin of 0.65VREF and 0.22VREF.Solution
For Vin = VREF, we get the results shown below. The input to the fifth stage is 0Vwhich means that the bit is uncertain. If A1 was slightly less than 1.875, the fifth bitwould be 0 which is in error. This result assumes that all stages but the first are ideal.
i Vi(ideal) Bit i (ideal) Vi(A1=1.875) Bit i (A1=1.875)1 1 1 1.000 12 1 1 0.875 13 1 1 0.750 14 1 1 0.500 15 1 1 0.000 ?
Now let us repeat the above results for Vin = 0.65VREF. The results are shown below.
i Vi(ideal) Bit i (ideal) Vi(A1=1.875) Bit i (A1=1.875)1 +0.65 1 0.6500 12 +0.30 1 0.2188 13 -0.40 0 -0.5625 04 +0.20 1 -0.1250 05 -0.60 0 0.7500 1
Chapter 10 – Section 7 (5/2/04) Page 10.7-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.7-2 - ContinuedNext, we repeat for the results for Vin = 0.22VREF. The results are shown below. We
see that no errors occur.
i Vi(ideal) Bit i (ideal) Vi(A1=1.875) Bit i (A1=1.875)1 +0.22 1 0.2200 12 -0.56 0 -0.5875 03 -0.12 0 -0.1750 04 +0.76 1 0.6500 15 +0.52 1 0.3000 1
Note the influence of Vin in the fact that an error occurs for A1= 1.875 for Vin =0.65VREF but not for Vin = 0.22VREF. Why? Note on the plot for the output of eachstage, that for Vin = 0.65VREF, the output of the fourth stage is close to 0V so any smallerror will cause problems. However, for Vin = 0.22VREF, the output of the fourth stage isat 0.65VREF which is further away from 0V and is less sensitive to errors.
∴ The most robust values of Vin will be near -VREF , 0 and +VREF. orwhen each stage output is furthest from the comparator threshold, 0V.
Chapter 10 – Section 7 (5/2/04) Page 10.7-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Iterative (Cyclic) Algorithmic Analog-Digital ConverterThe pipeline algorithmic ADC can be reduced to a single stage that cycles the outputback to the input.Implementation:
+-
ΣSample
andHold
x2
+VREF
-VREF
Voi
+1 +1
+-
ΣSampleand
Hold
x2
VREF
Va
+1+1
S1
Vb
Vo
Vin*
-VREF
Vo ="1"
Vo ="0"
Iterative algorithm ADC Different version of iterative algorithm ADC implementationFig. 10.7-13
Operation:
1.) Sample the input by connecting switch S1 to Vin*.
2.) Multiply Vin * by 2.
3.) If Va > VREF, set the corresponding bit = 1 and subtract VREF from Va. If Va < VREF, set the corresponding bit = 0 and add zero to Va.
4.) Repeat until all N bits have been converted.
Chapter 10 – Section 7 (5/2/04) Page 10.7-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.7-3 - Conversion Process of an Iterative, Algorithmic Analog-DigitalConverter
The iterative, algorithmic analog-digital converter is to be used to convert an analogsignal of 0.8VREF. The figure below shows the waveforms for Va and Vb during theprocess. T is the time for one iteration cycle.1.) The analog input of 0.8VREF givesVa = 1.6VREF and Vb = 0.6VREF and the MSB as 1.2.) Vb is multiplied by two to give Va = 1.2VREF. The next bit is also 1 and Vb = 0.2VREF.3.) The third iteration givesVa = 0.4VREF, making the next bit is 0 and Vb = 0.4VREF .
4.) The fourth iteration gives Va = 0.8VREF, giving Vb = 0.8VREF and the fourth bit as 0.5.) The fifth iteration gives Va = 1.6VREF, Vb = 0.6VREF and the fifth bit as 1.The digital word after the fifth iteration is 11001 and is equivalent to an analog voltage of0.78125VREF.
0.0
0.4
0.8
1.2
1.6
2.0
0 1 2 3 4 5t/T
Va/VREF
0.0
0.4
0.8
1.2
1.6
2.0
0 1 2 3 4 5t/T
Vb/VREF
Fig. 10.7-14.
Chapter 10 – Section 7 (5/2/04) Page 10.7-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Self-Calibrating Analog-Digital ConvertersSelf-calibration architecture for a m-bit charge scaling, k-bit voltage scaling successiveapproximation ADC
+-
C1
VREF
C2 C3 Cm-1
Successive Approximation
Register
Cm
k-bits
m+k-bits
Cm
m-bit subDAC
k-bitsubDAC
m+2-bitCalibration
DAC
S1
ControlLogic
Register
Adder
Data Register
Vε1 Vε2
To SuccessiveApproximationRegister
Data Output
m control lines
Fig.10.7-15
Comments:• Self-calibration can be accomplished during a calibration cycle or at start-up• In the above scheme, the LSB bits are not calibrated• Calibration can extend the resolution to 2-4 bits more that without calibration
Chapter 10 – Section 7 (5/2/04) Page 10.7-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Self-Calibrating Analog-Digital Converters - ContinuedSelf-calibration procedure starting with the MSB bit:1.) Connect C1 to VREF and theremaining capacitors (C2+C3+···+Cm+Cm = C1 ) to ground and close SF.
2.) Next, connect C1 to ground andC1 to VREF.
3.) The result will be Vx1 =
C1 -C1
C1 + C1 VREF. If C1 = C1 , then Vx1 = 0.
4.) If Vx1 ≠ 0, then the comparator output will be either high or low. Depending on thecomparator output, the calibration circuitry makes a correction through the calibrationDAC until the comparator output changes. At this point the MSB is calibrated and theMSB correction voltage, Vε1 is stored.
5.) Proceed to the next MSB with C1 out of the array and repeat for C2 and C2 . Storethe correction voltage, Vε2, in the data register.6.) Repeat for C3 with C1 and C2 out of the array. Continue until all of the capacitors ofthe MSB DAC have been corrected.Note that for any combination of MSB bits the calibration circuit adds the correctcombined correction voltage during normal operation.
C1
VREF C1
C1
VREF
C1
Vx1
Fig.10.7-16
+-
+-
VREF
Connection of C1 to VREF. Connection of C1 to VREF.
Chapter 10 – Section 7 (5/2/04) Page 10.7-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Medium Speed Analog-Digital ConvertersMedium speed ADCs generally use some form of successive approximation.
Type of ADC Advantage DisadvantageVoltage-scaling,charge-scalingsuccessiveapproximation ADC
High resolution Requires considerabledigital controlcircuitry
Successiveapproximation using aserial DAC
Simple Slow
Pipeline algorithmicADC
Fast after initiallatency of NT
Accuracy depends oninput
Iterative algorithmicADC
Simple Requires other digitalcircuitry
Successive approximation ADCs also can be calibrated extending their resolution 2-4 bitsmore than without calibration.
Chapter 10 – Section 8 (5/2/04) Page 10.8-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 10.8 - HIGH SPEED ANALOG-DIGITAL CONVERTERSCharacteristics of High-Speed ADCsConversion time is T where T is a clock period.Types:• Parallel or Flash ADCs• Interpolating ADCs• Folding ADCs• Speed-Area Tradeoffs
- Multiple-Bit, Pipeline ADCs- Digital Error Correction
• Time-Interleaved ADCs• Examples of High-Speed ADCs
Chapter 10 – Section 8 (5/2/04) Page 10.8-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Parallel or Flash Analog-Digital ConverterA 3-bit, parallel ADC:
Comments:• Fast, in the first phase of the clock the
analog input is sampled and applied to thecomparators. In the second phase, thedigital encoding network determines thecorrect output digital word.
• Number of comparator required is 2N-1• Can put a sample-hold at the input or canused clocked comparators• Typical sampling frequencies can be ashigh as 400MHz for 6-bits in sub-micronCMOS technology.
1R+-
1R+-
0R+-
0R+-
0R+-
0R+-
0R+-
VREF Vin*=0.7VREF
R
2N-1to N
encoder
OutputDigitalWord101
0.875VREF
0.750VREF
0.625VREF
0.500VREF
0.375VREF
0.250VREF
0.125VREF
Fig.10.8-1
Chapter 10 – Section 8 (5/2/04) Page 10.8-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.8-1 - Influence of the Comparator Offset on the ADC PerformanceTwo comparators are shown of
an N-bit flash ADC. Comparators1 and 2 have an offset voltageindicated as VOS1 and VOS2,respectively. A portion of the idealtransfer function of the converter isalso shown. (a.) When do thecomparator offsets cause a missingcode? Express this condition interms of VOS1, VOS2, N, and VREF.(b.) Assume all offsets are identicaland express the magnitude of INL in terms of VOS1(=VOS2), N, and VREF. (c.) Express theDNL in terms of VOS1, VOS2, N, and VREF.
Solution(a.) We note that comparator 1 changes from a 0 to 1 when Vin(1) > VR1-VOS1 andcomparator 2 changes from a 0 to 1 when Vin(2) > VR2-VOS2. A missing code will occur ifVin(2) < Vin(1). Therefore,
VR2 - VOS2 > VR1 - VOS1 → VR2 - VR1 > VOS2 - VOS`But,
VR2 - VR1 = VREF2N → |VOS2 - VOS1| <
VREF2N .
+ -VOS2
+ -VOS1 Encoder
R
R
R
VR2
VR1
VREF Vin
VR1 VR2Vin
1 LSBVOS1
VOS2
Fig.10.8-2.
+-
+-
2
1
Chapter 10 – Section 8 (5/2/04) Page 10.8-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.8-1 - Continued(b.) If all offsets are alike and equal to VOS, we can write that the INL is given as theworst case deviation about each VRi
INL = |VOS|VLSB
= |VOS|
VREF/2N = 2N |VOS|VREF
.
(c.) The DNL can be expressed as the worst case difference between the offset deviationsgiven as
DNL = (VR2 - VOS2) - (VR1 - VOS1) - VLSB
VLSB =
VLSB + VOS2 - VOS1 - VLSBVLSB
= |VOS2 - VOS1|
VLSB =
2N |VOS2 - VOS1|VREF
Chapter 10 – Section 8 (5/2/04) Page 10.8-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Physical Consequences of High Speed ConvertersAssume that clocked comparators are used in a 400MHz sampling frequency ADC of
6-bits. If the input frequency is 200MHz with a peak-to-peak value of VREF, the clockaccuracy must be
∆t ≤ ∆VωVp
= VREF/2N+1
2πf(0.5VREF) = 1
27·π·f = 12.5ps
Since electrical signals travel at approximately 1ps/µm for metal on an IC, the length ofthe metal path from the clock to each comparator must be equal to within 12.5µm.
Therefore, must use careful layout to avoid ADC inaccuracies at high frequencies.Equal-delay,clock distribution system for a 4-bit parallel ADC:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ClockGenerator
Fig.10.8-2BComparators
Chapter 10 – Section 8 (5/2/04) Page 10.8-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.8-2 - Comparator Bandwidth Limitations on the Flash ADCThe comparators of a 6-bit, flash ADC have a dominant pole at 103 radians/sec, a dc
gain of 104 a slew rate of 3V/µs, and a binary output voltage of 1V and 0V. Assume thatthe conversion time is the time required for the comparator to go from its initial state tohalfway to its final state. What is the maximum conversion rate of this ADC if VREF =5V? Assume the resistor ladder is ideal.Solution:
The output of the i-th comparator can be found by taking the inverse Laplacetransform of,
L -1
Vout(s) =
Ao
(s/103) + 1 ·
Vin*-VRi
s → vout(t) = Ao(1 - e-103t)(Vin* - VRi).
The worst case occurs whenVin*-VRi = 0.5VLSB = VREF/27 = 5/128
∴ 0.5V = 104(1 - e-103T)(5/128) → 64/5x104 = 1- e-103T
or, e103T = 1 - 64
50,000 = 0.99872 → T = 10-3 ln(1.00128) = 1.2808µs
∴ Maximum conversion rate = 1
1.2808µs = 0.781x106 samples/second
Checking the slew rate shows that it does not influence the maximum conversion rate.
SR = 3V/µs → ∆V∆T = 3V/µs → ∆V = 3V/µs(1.2808µs) = 3.84V > 1V
Chapter 10 – Section 8 (5/2/04) Page 10.8-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Other Errors of the Parallel ADC• Resistor string error - if current is drawn from the taps to the resistor string this will
create a “bowing” effect on the voltage. This can be corrected by applying the correctvoltage to various points of the resistor string.
• Input common mode range of the comparators - the comparators at the top of the stringmust operate with the same performance as the comparators at the bottom of the string.
• Kickback or flashback - influence of rapid transition changes occuring at the input of acomparator. Can be solved by using a preamplifier or buffer in front of the comparator.
• Metastability - uncertainty of the comparator output causing the transition of thethermometer code to not be distinct.
Chapter 10 – Section 8 (5/2/04) Page 10.8-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Interpolating Analog-Digital ConvertersA 3-bit interpolating ADC using a factor of 4 interpolation:
Comments:• Loading of the input is reduced from 8 comparators to two amplifiers.• The comparators no longer need a large ICMR• V1 and V2, are interpolated through the resistor string and applied to the comparators.
• Because of the amplification of the input amplifiers and a single threshold, thecomparators can be simple and are often replaced by a latch.
• If the dots in Fig. 10.8-4 are not equally spaced, INL and DNL will result.
VDD
Vth
VREF0
0
V2a
V2
V2bV2c
V1aV1
V1b
V1c
0.5VREFVin
Volts
ComparatorThreshold
1 2 3 4 5 6 7 8
Fig.10.8-4
VDD
+-
V28R
+-
V2a7R
+-
V2b6R
+-
V2c5RV1 +
-4R+-
V1a3R
+-
V1b2R
+-
V1c1R
VREFVth
8 to 3encoder
Vin
R
R
VREF
2
3-bitdigitaloutput
+-VDD
+-A1
A2
Fig.10.8-3
Chapter 10 – Section 8 (5/2/04) Page 10.8-9
CMOS Analog Circuit Design © P.E. Allen - 2004
A 3-Bit Interpolating ADC with Equalized Comparator DelaysOne of the problems in voltage (passive) interpolation is that the delay from the amplifieroutput to each comparator can be different due to different source resistance.Solution:
VDD
+-
V28R
+-
V2a7R
+-
V2b6R
+-
V2c5RV1 +
-4R+-
V1a3R
+-
V1b2R
+-
V1c1R
VREFVth
8 to 3encoder
Vin
R
R
VREF
2
3-bitdigitaloutput
+-VDD
+-A1
A2
Fig.10.8-6
R
R/4
R/4
R
R/4
R/4
Chapter 10 – Section 8 (5/2/04) Page 10.8-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Folding Analog-Digital Converters
Allows the number of comparators to be reduced below the value of 2N-1.Architecture for a folded ADC:
PreprocessorCoarse
Quantizer
Folding Preprocessor
FineQuantizer
EncodingLogicVin
DigitalOutput
n1bits
n2bits
n1+n2bits
Fig.10.8-7
Operation:The input is split into two or more parallel paths.
• First path uses a coarse quantizer to quantize the signal into 2n1 values
• The second path maps all of the 2n1 subranges onto a single subrange and applies thisanalog signal to a fine quantizer of 2n2 subranges.
Thus, the total number of comparators is 2n1-1 + 2n2-1 compared with 2n1+n2-1 for aparallel ADC.I.e., if n1 = 2 and n2 = 4, the folding ADC requires 3 + 15 = 18 compared with 63comparators.
Chapter 10 – Section 8 (5/2/04) Page 10.8-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Folding PreprocessorIllustration:
FS/2
-FS/2
FS/F2n1
subranges2n2
subranges
Fig.10.8-8
Comments:• Folding is done simultaneously or in parallel so that only one clock cycle is needed forconversion.• Folding will tend to increase the bandwidth of the analog input by a factor of F.• Folding can reduce the power consumption and require less chip area.
Chapter 10 – Section 8 (5/2/04) Page 10.8-12
CMOS Analog Circuit Design © P.E. Allen - 2004
Example of a Folding PreprocessorFolding characteristic for n1 = 2 and n2 = 3.
832
NoFolding
Folding
Analog Input
Aft
er A
nalo
gPr
epro
cess
ing
MSBs = 00 01 10 11
n1 = 2n2 = 3
VREF
VREF4
00 VREF
Fig.10.8-9
Problems:• The sharp discontinuities of the folder are difficult to implement at high speeds.• Fine quantizer must work at voltages ranging from 0 to VREF/4 (subranging).
Chapter 10 – Section 8 (5/2/04) Page 10.8-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Modified Folding PreprocessorsThe above problems can be removed by the following folding preprocessors:
Vin
Vout
Multiple folders allow a single value quantizer (comparator).
Vin
VoutVREF
80
-VREF8
VREF8
0-VREF
8
VREF
VREF
0
0
Fig.10.8-10.
Folder that removes discontinuity problem.
Chapter 10 – Section 8 (5/2/04) Page 10.8-14
CMOS Analog Circuit Design © P.E. Allen - 2004
A 5-Bit Folding ADC Using 1-Bit Quantizers (Comparators)Block diagram:
CoarseMSBs(n1=2)
Folder 1
+-
Folder 2
+-
Folder 7
+-
Dec
oder
Vin
2 bits
3 bitsLSBs
Comparators
5-bitdigitaloutput
Fig.10.8-11
Comments:• Number of comparators is 7 for the fine quantizer and 3 for the course quantizer• The zero crossings of the folders must be equally spaced to avoid linearity errors• The number of folders can be reduced and the comparators simplified by use of
interpolation
Chapter 10 – Section 8 (5/2/04) Page 10.8-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Folding CircuitsImplementation ofa times 4 folder:
Comments:• Horizontal shifting isachieved by modifyingthe topmost andbottom resistors of theresistor string• Folding andinterpolation ADCsoffer the mostresolution at highspeeds (≈8 bits at200MHz)
V1 V2 V8
VDD
FoldingOutputs
Vin
+VREF
V1
V2
V7
V8 Vout-+
Vout
V1 V2 V3 V4 V6V5 V7
V7
Vin
I I I I
RL RLR
R
R
R
0
+IRL
-IRL
VREF
Fig. 10.8-12A
I
V8
Chapter 10 – Section 8 (5/2/04) Page 10.8-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Interpolating and Folding ADCsAdvantages of Interpolation:• Large area and power reduction• Input capacitance reduced• Folder offset errors are averaged among interpolated signalsComments on Resistive Interpolation:• Low resistance is required for high speed implies high drive required from previous
folding circuit• Guaranteed monotonicity of phase shiftComments on Active Interpolation:• Subject to additional offsets (fine active interpolation not recommended)• Lower drive necessary from initial folding circuits than for resistive interpolation
Chapter 10 – Section 8 (5/2/04) Page 10.8-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Use of a S/H in Front of the Folding ADCBenefit of a S/H:• With no S/H, the folding circuit acts as an amplitude-dependent frequency multiplier.
BW of ADC ≥ BW of Folding Circuit• With S/H, all inputs to the folding circuit arrive at the same time.
- The folding circuit is no longer an amplitude-dependent frequency multiplier - BW of the ADC is now limited by the BW of the S/H circuit - Settling time of the folding and interpolating preprocessor is critical
Single S/H versus Distributed S/H:• Single S/H requires high dynamic range for low THD• Dynamic range requirement for distributed S/H reduced by the number of S/H stages• If the coarse quantizer uses the same distributed S/H signals as the fine preprocessor,
the coarse/fine synchronization is automatic• The clock skew between the distributed S/H stages must be small. The clock jitter will
have a greater effect on the distributed S/H approach.
Chapter 10 – Section 8 (5/2/04) Page 10.8-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Use of a Preamplifier in the S/H CircuitIncluding a Preamplifier in the S/H circuit:• Reduces the effect of folding circuit input offset and comparator input offset• For a S/H distributed over D stages, then:
- The preamp linear range requirement is the input range/D - The preamp input common mode range is the input range
- The preamp output common mode range is small which implies the switchnonlinearity is not dependent on input signal amplitude
Chapter 10 – Section 8 (5/2/04) Page 10.8-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Error Sources and Limitations of a Basic Folding ADCError Sources:• Offsets in reference voltages due to resistor mismatch• Preamp offset (reduced by large W/L for low VGS-VT, with common-centroid geometry)• vin feedthrough to reference ladder via Cgs of input pairs places a maximum value on
ladder resistance which is dependent on the input frequency.• Folder current-source mismatches (gives signal-dependent error ⇒ distortion)• Comparator kickback (driving nodes should be low impedance)• Comparator metastability condition (uncertainty of comparator output)• Misalignment between coarse and fine quantization outputs (large code errors possible)Sampling Speed Limitations:• Folding output settling time• Comparator settling time• Clock distribution and layout• Clock jitterInput Bandwidth Limitations:• Maximum folding signal frequency ≥ (F/2)·fin, unless a S/H is used• Distortion due to limited preamplifier linear range and frequency dependent delay• Distortion due to the limited linear range and frequency dependent delay of the folder• Parasitic capacitance of routing to comparators
Chapter 10 – Section 8 (5/2/04) Page 10.8-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Multiple-Bit, Pipeline Analog-Digital ConvertersA compromise between speed and resolution is to use a pipeline ADC with multiplebits/stage.i-th stage of a k-bit per stage pipeline ADC with residue amplification:
k-bitADC
k-bitDAC
k-bits
S/HVREF VREF
Σ
Av =2k
+-
i-th stage
Vi-1
Clock
Vi
Fig.10.8-13
Residue
Residue voltage = Vi-1 -
b0
2 + b1
22 + ··· + bk-22k-1 +
bk-12k VREF
Chapter 10 – Section 8 (5/2/04) Page 10.8-21
CMOS Analog Circuit Design © P.E. Allen - 2004
A 3-Stage, 3-Bit Per Stage Pipeline ADCIllustration of the operation:
000001
011010
100101110111
000001
011010
100101110111
000001
011010
100101110111
Clock 1
Stage 1
Clock 2
Stage 2
Clock 3
Stage 3
Digital output = 011 111 001
MSB LSB Fig.10.8-14
VREF
VREF2
0 Time
Vol
tage
Converted word is 011 111 001Comments:• Only 21 comparators are required for this 9-bit ADC• Conversion occurs in three clock cycles• The residue amplifier will cause a bandwidth limitation,
GB = 50MHz → f-3dB = 50MHz
23 ≈ 6MHz
Chapter 10 – Section 8 (5/2/04) Page 10.8-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Subranging, Multiple-Bit, Pipeline ADCs
The residue amplifier can be replaced by dividing VREF to the next stage by 2k if thestage has k-bits.Illustration of a 2-stage, 2-bits/stage pipeline ADC:
Comments:• Resolution of the
comparators for thefollowing stages increasesbut fortunately, thetolerance of each stagedecreases by 2k for everyadditional stage.
• Removes the frequencylimitation of the amplifier
00011011
11
VREF
0
Stage 2Stage 1
Time
Vol
tage
0.5000VREF
0.7500VREF
0.2500VREF
0.3750VREF0.3125VREF
0.4375VREF
Clock 1 Clock 2Digital output word = 01 10 Fig.10.8-15
00
10
01
Chapter 10 – Section 8 (5/2/04) Page 10.8-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Implementation of the DAC in the Multiple-Bit, Pipeline ADCCircuit: Comments:
• A good compromise between area and speed• The ADC does not need to be a flash or
parallel if speed is not crucial• Typical performance is 10 bits at 50Msamples/sec+
-
+-
+-
+-
R
R
R
R 0
1
1
0
0
0
0
0
1
OFF
OFF
OFF
ON
AnalogOut VREF Vin*
Fig.10.8-16
Chapter 10 – Section 8 (5/2/04) Page 10.8-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.8-3 - Examination of error in subranging for a 2-stage, 2-bits/stagepipeline ADCThe stages of the 2-stage,2-bits/stage pipeline ADCshown below are ideal.However, the secondstage divides VREF by 2rather than 4. Find the±INL and ±DNL for this ADC.SolutionExamination of the first stage shows that its output, Vout(1) changes at
Vin(1)VREF
= 14,
24,
34, and
44 .
The output of the first stage will beVout(1)VREF
= b02 +
b14 .
The second stage changes atVin(2)VREF
= 18,
28,
38, and
48
whereVin(2) = Vin(1) - Vout(1).
The above relationships permit the infomation given in Table 10.8-1.
2-bitADC
2-bitDAC Σ
VREF VREFb0 b1
Vin(1)
Vout(1)
2-bitADC
2-bitDAC
VREF VREFb2 b3
Vin(2)
Vout(2)
2 2 Fig.10.8-17
Chapter 10 – Section 8 (5/2/04) Page 10.8-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.8-3 - ContinuedTable 10.8-1 Output digital word for Ex. 10.8-3
Vin(1)
VREF b0 b1
Vout(1)
VREF Vin(2)
VREF b2 b3
Ideal Ouputb0 b1 b2 b2
0 0 0 0 0 0 0 0 0 0 01/16 0 0 0 1/16 0 0 0 0 0 12/16 0 0 0 2/16 0 1 0 0 1 03/16 0 0 0 3/16 0 1 0 0 1 14/16 0 1 4/16 0 0 0 0 1 0 05/16 0 1 4/16 1/16 0 0 0 1 0 16/16 0 1 4/16 2/16 0 1 0 1 1 07/16 0 1 4/16 3/16 0 1 0 1 1 18/16 1 0 8/16 0 0 0 1 0 0 09/16 1 0 8/16 1/16 0 0 1 0 0 1
10/16 1 0 8/16 2/16 0 1 1 0 1 011/16 1 0 8/16 3/16 0 1 1 0 1 112/16 1 1 12/16 0 0 0 1 1 0 013/16 1 1 12/16 1/16 0 0 1 1 0 114/16 1 1 12/16 2/16 0 1 1 1 1 015/16 1 1 12/16 3/16 0 1 1 1 1 1
Comparing the actual digital output word with the ideal output word gives the following:+INL = 0LSB, -INL = 0111-0101 = -2LSB, +DNL = (1000-0101) - 1LSB = +2LSB, and -DNL = (0101-0100) - 1LSB = 0LSB.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1616 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Analog Input Voltage
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Dig
ital O
utpu
t Cod
e
Ideal Finite Characteristic
-INL=2LSB
+DNL=2LSB
INL=0LSB
-DNL=0LSB
Chapter 10 – Section 8 (5/2/04) Page 10.8-26
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 10.8-4 – Amplifier accuracy for 2-stage, 2-bits/stage pipeline ADCFor ADC shown, assume that the2-bit ADC’s and the 2-bit DACfunction ideally and VREF = 1V. Ifthe ideal value of the scaling factor,k, is 4, find the maximum andminimum value of k that will notcause an error in the 4-bit ADC.Solution
The input to the second ADC is vin(2) = k
vin(1) -
b0
2 + b14 . If v’in(2) is vin(2) when k = 4,
then the |vin(2) - v’in(2)| must be less than ±1/8 or the LSB bits will be in error.
Therefore, vin(2) - v’in(2) =
k vin(1) - k
b0
2 + b14 - 4 vin(1) + 4
b0
2 + b14 ≤
18
If k = 4+∆k, then
4 vin(1) + ∆k vin(1) - 4
b0
2 + b14 - ∆k
b0
2 + b14 - 4 vin(1) + 4
b0
2 + b14 ≤
18
or ∆k
vin(1)-
b0
2 +b14 ≤
18 where the largest value of
vin(1)-
b0
2 +b14 is 1/4 for any vin(1).
Therefore,∆k4 ≤
18 ⇒ ∆k ≤ 1/2. The tolerance of k is
∆kk =
±12·4 =
±18 ⇒ ±12.5%
2-bitADC
VREFVREF
Σ2-bitDAC
+
-2-bitADC
VREF
b0 b1 b2 b3
kvin(1)
vin(2)
vout(1)
Fig.10.8-18
Chapter 10 – Section 8 (5/2/04) Page 10.8-27
CMOS Analog Circuit Design © P.E. Allen - 2004
Example of a Multiple-Bit, Pipeline ADCTwo-stages with 5-bits per stage resulting in a 10-bit ADC with a sampling rate of5Msamples/second.Architecture:
S/HMSBADC
DACIncrement
by 1
LSBADC
DAC
MSBs
LSBs
Vr1
Vr2
Vin Vin*
Fig.10.8-21
Features:
• Requires only 2n/2-1 comparators• LSBs decoded using 31 preset charge redistribution capacitor arrays• Reference voltages used in the LSBs are generated by the MSB ADC• No op amps are used
Chapter 10 – Section 8 (5/2/04) Page 10.8-28
CMOS Analog Circuit Design © P.E. Allen - 2004
Example of a Multiple-Bit, Pipeline ADC - ContinuedMSB Conversion:
Operation:1.) Sample Vin* on
each 32Ccapacitanceautozeroing thecomparators
2.) Connect eachcomparator to anode of the resistorstring generating athermometer code.
+-
Vin*
+-
Vin*
VREF
R32
R31
+-
Vin*
+-
Vin*
LatchBankand
BinaryEncoder
32C
32C
32C
32C
Vin*+ -
Vin*+ -
Vin*+ -
Vin*+ -
R30
Ri
R2
R1
AnalogMUX
Vr2
Vr1VRi
VRi -Vin*
MSBOutput
Fig.10.8-22MSBs
DAC
Chapter 10 – Section 8 (5/2/04) Page 10.8-29
CMOS Analog Circuit Design © P.E. Allen - 2004
Example of a Multiple-Bit, Pipeline ADC - ContinuedLSB Conversion: Operation:
1.) MSB comparators are preset to eachof the 31 possible digital codes.
2.) Vr1 and Vr2 are derived from theMSB conversion.
3.) Preset comparators will produce athermometer code to the encoder.
Comments:• Requires two full clock cycles• Reuses the comparators• Accuracy limited by resistor string and
its dynamic loading• Accuracy also limited by the capacitor
array• Comparator is a 3-stage, low-gain,
wide-bandwidth, using internalautozeroing
LatchBankand
BinaryEncoder
LSBOutput
ADC set to Code 11111
Vr1
Vr2
Vin*
ADC set to Code 11110
Vr1
Vr2
Vin*
ADC set to Code 00010
Vr1
Vr2
Vin*
ADC set to Code 00001
Vr1
Vr2
Vin*
+-
2C C4C8C16C
Vr1
Vr2Switches
set to"Code" Fig.10.8-23
C
Chapter 10 – Section 8 (5/2/04) Page 10.8-30
CMOS Analog Circuit Design © P.E. Allen - 2004
Digital Error CorrectionThe multiple-bit, pipeline ADC architecture permits the correction of digital errors thatoccur in the previous stage.Problem (1st stage comparator is in error): Solution (use an additional bit for correction):
For an input of0.4VREF theoutput shouldbe 0110.
Comments:• Add a cor-
recting bit tothe followingstage tocorrect forerrors in theprevious stage.
• The subranging or amplification of the next stage does not include the correcting bit.• Correction can be done after all stages of the pipeline ADC have converted or after each
individual stage.
1011
100101
Fig.10.8-19
-010001
100101110111
001010011
01
11
101011
0001
Vin* = 0.4VREF
Digital output word = 10 00
00
Stage 2Stage 1
Clock 1 Clock 2Time
VREF
0
0.50VREF
0.75VREF
0.25VREF
Error01
11
10
01 10
00
Stage 2Stage 1
Clock 1 Clock 2Time
VREF
0
0.50VREF
0.75VREF
0.25VREF
-10000Vin* = 0.4VREF
Digital output word =
Chapter 10 – Section 8 (5/2/04) Page 10.8-31
CMOS Analog Circuit Design © P.E. Allen - 2004
Example of a Pipeline ADC with Digital Error CorrectionADC uses 4 stages of 4-bits each and employs a successive approximation ADC to get13-bit resolution at 250 ksamples/sec.Block diagram of a 13-bit pipeline ADC:
S/H+
-
S/H+
-
ADC-N1 bit DAC-N1 bit
S/H+
-
ADC-N2 bit DAC-N2 bit ADC-N3 bit DAC-N3 bit
Vin
2N2 2N32N1
S/H
N1 bit REG
N3 bit REG
N2 bit REG
N1 bit REG
N2 bit REG
N1 bit REG
0.5 LSB offset 0.5 LSB offset
VREF
3 bits
3 bits
3 bits
4 bits
Comments:• The ADC of the first stage uses 16 equal capacitors instead of 4 binary weighted for
more accuracy• One bit of the last three stages is used for error correction.
Chapter 10 – Section 8 (5/2/04) Page 10.8-32
CMOS Analog Circuit Design © P.E. Allen - 2004
12-Bit Pipeline ADC with Digital Error Correction & Self-Calibration†
Digital ErrorCorrection:• Avoids saturation
of the next stage• Reduces the
number ofmissing codes
• Relaxedspecifications forthe comparators
• Compensates forwrong decisionsin the coarsequantizers
Self-Calibration:• Can calibrate the effects of the DAC nonlinearity and gain error• Can be done by digital or analog methods or both
† J. Goes, et. al., CICC’96
DAC
ADC
S/Hvin
3 bits
DAC
ADC
3 bits
DAC
ADC
3 bits
DAC
ADC
3 bits
ADC
4 bits
12 bits
Digital Error Correction Logic
Clock
Fig. 11-30
Chapter 10 – Section 8 (5/2/04) Page 10.8-33
CMOS Analog Circuit Design © P.E. Allen - 2004
Time-Interleaved Analog-Digital ConvertersSlower ADCs are used in parallel.Illustration:
Comments:• Can get the same throughput with less chip area• If M = N, then a digital word is converted at every clock cycle• Multiplexer and timing become challenges at high speeds
S/H N-bit ADC No. 1
T1
S/H
T2
S/H
TM
Vin
Digitalwordout
T1 T2 TM T1+TCt
T2+TC TM+TC
N-bit ADC No. 2
N-bit ADC No. M
N-bit ADC No. 1N-bit ADC No. 2
N-bit ADC No. MT=TC
M
Fig.10.8-20
Chapter 10 – Section 8 (5/2/04) Page 10.8-34
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of Reported High-Speed ADCs
Architecture[paper reference]
SamplingFreq.
(Msps)
SignalFreq.
(MHz)
ENOB1
(bits)
Power(mW)
ActiveArea
(mm2)
Feature
Size2(µm)
Vin
(Vp-p)VDD
(V)
Folding+Interpolating [1]
70 8 5.5 110 0.7 0.8 2.0 5.0
Flash [2] 200 100 5.0 400 2.7 0.6 - -Flash [3] 200 20 6.0 110 1.6 0.5 0.3 3.0Flash w. pre-processing [4]
175 84 4.0 160 12.0 0.7 1.2 3.3
Folding+Interpolating [5]
125 10 5.5 225 4.0 1.0 - 5.0
Folding+Interpolating [6]
80 75 5.8 80 0.3 0.5 1.6 3.3
Subranging+Interleaving [7]
95 50 8.0 1100 50.0 1.0 2.0 5.0
Chapter 10 – Section 8 (5/2/04) Page 10.8-35
CMOS Analog Circuit Design © P.E. Allen - 2004
References for Recently Published High-Speed CMOS ADCs
[1] B. Nauta and A. Venes, “A 70Ms/s 110mW 8-b CMOS Folding and InterpolatingA/D Converter, IEEE J. of Solid-State Circuits, vol. 30, no. 12, Dec. 1995, pp. 1302-1308.
[2] J. Spalding and D. Dalton, “A 200 Msample/s 6b Flash ADC in 0.6µm CMOS,”Proc. of ISSCC, paper SA19.5, 1996.
[3] S. Tsukamoto, I. Dedic, et. al., “A CMOS 6b 200Msamples/s 3V-supply A/Dconverter for a PRML Read Channel LSI,” Proc. of ISSCC, paper TP4.5, 1996.
[4] R. Roovers and M. Steyaert, “A 175Ms/s, 6-b, 160mW, 3.3V CMOS A/DConverter,” IEEE J. of Solid-State Circuits, vol. 31, no. 7, July 1996, pp. 938-944.
[5] M. Flynn and D. Allstot, “CMOS Folding A/D Converters with Current-ModeInterpolation,” IEEE J. of Solid-State Circuits, vol. 31, no. 9, Sept. 1996, pp. 1248-1257.
[6] A. Venes and R. van de Plassche, “An 80 MHz, 80mW, 8-b CMOS Folding A/DConverter with Distributed Track-and-Hold Preprocessing,” IEEE J. of Solid-StateCircuits, vol. 31, no. 12, Dec. 1996, pp. 1846-1853.
[7] K. Kim, N. Kusayanagi, and A. Abidi, “A 10-b, 100-Ms/s CMOS A/D Converter,”IEEE J. of Solid-State Circuits, vol. 32, no. 3, Mar. 1997, pp. 302-311.
Chapter 10 – Section 8 (5/2/04) Page 10.8-36
CMOS Analog Circuit Design © P.E. Allen - 2004
Summary of High-Speed Analog-Digital Converters
Type of ADC Primary Advantage Primary DisadvantageFlash or parallel Fast Area is large if N > 6Interpolating Fast Requires accurate
interpolationFolding Fast Bandwidth increases if
no S/H usedMultiple-Bit,Pipeline
Increased number of bits Slower than flash
Time-interleaved
Small area with largethroughput
Precise timing and fastmultiplexer
Typical Performance:• 6-8 bits• 500-2000 Msamples/sec.• The ENOB at the Nyquist frequency is typically 1-2 bits less that the ENOB at low
frequencies.• Power is approximately 0.3 to 1W
Chapter 10 – Section 9 (5/2/04) Page 10.9-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 10.9 - EXAMPLES OF HIGH-SPEED CMOS DIGITAL-ANALOG CONVERTERS
Outline• Introduction
Example 1 - 10 Bit, 120 Msps, Time-Interleaved ADC with Digital BackgroundCalibration
Example 2 - 8 Bit, 150 Msps Pipelined ADCExample 3 - 6 Bit, 400 Msps Folding and Interpolating ADCExample 4 - 6 Bit, 1600 Msps Flash ADC using Averaging and Averaging
Termination• Objective
Present examples of high-speed digital-analog and analog-digital converters compatiblewith CMOS technology.
Chapter 10 – Section 9 (5/2/04) Page 10.9-2
CMOS Analog Circuit Design © P.E. Allen - 2004
EXAMPLE 1 - 10 BIT, 120 MSPS, TIME-INTERLEAVED ADC WITH DIGITALBACKGROUND CALIBRATION†
• Principle - Multiple ADCs time interleaved
ADC0
ADC1
ADCM-1
DigitalMultiplexer
AnalogMultiplexer
fs/M
x(t)
fs fs=1/T
x(nT)
FigEx1-01
• Problems- Offset mismatch of interleaved channels- Gain mismatch of interleaved channels- Aperture error between channels
• Solutions - Digital-background calibration is used to overcome the offset, gain, andsample-time errors between channels. Digital-background calibration is a tradeoff inoverhead versus enhanced performance.
Only two channels are given in this example to illustrate the method. † S. Jamal, D. Fu, C.J. Chang, P. Hurst and S. Lewis, “A 10-b, 120-Msample/s Time-Interleaved Analog-to-Digital Converter With Digital
Background Calibration”, IEEE J. of Solid-State Circuits, vol. 37, no. 12, Dec. 2002, pp. 1618-1627.
Chapter 10 – Section 9 (5/2/04) Page 10.9-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Random Chopper-Based Offset CalibrationCalibration system forone channel:
C[m] is a pseudo-random binary signal = ±1 where m is the discrete time index. C[m] iswhite with zero mean.VOS models the input-referred offset of the sample-hold amplifier and the ADC.
How does it work?1.) The chopped analog signal is sampled and digitized by the ADC producing S[m].2.) A variable offset, V[m], is subtracted from S[m] and the result multiplied by C[m] to
produce the channel output, a[m].3.) Since the analog signal has been chopped twice, it is unaffected by the chopping.4.) Because of the chopping process, the only dc component in the accumulator is due to
differences between the analog offset from the SHA and the ADC in the channel andthe accumulator output V[m].
5.) In steady state, the negative feedback forces the average of the accumulator input to bezero. µo controls the bandwidth of the notch, the speed of convergence, and thevariance of V[m] at convergence.
Sample-HoldAmplifier
ADC
Accumulator
Vin(t)
C[m] VOS
Chopping SHA
S[m]
V[m]
+
-
C[m]
a[m]
µo
Fig. Ex1-01
Chapter 10 – Section 9 (5/2/04) Page 10.9-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Gain CalibrationADC output spectrum for two time-interleaved channels with a sinusoidal input at fo anda gain mismatch between channels.
f
Y(f) = Output
fs2
fi = fo
Input
Image
fs2
-fof
YC(f) = ChoppedOutput
fs2
fi = fo
Chopped Input
Chopped Image
fs2
-foFig Ex1-03
The image amplitude is proportional to the gain mismatch between the two channels.How does it work?1.) The ADC output is chopped by multiplying it by a signal that alternates at the channel
sampling rate.2.) This multiplication causes the image to shift to fo and the input to fi.
3.) Next, the output and chopped output signals are multiplied in the time domain.4.) The result has a dc component that is proportional to the gain mismatch between the
two channels.
Chapter 10 – Section 9 (5/2/04) Page 10.9-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Gain Calibration - ContinuedBlock diagram of the gain-calibration scheme:
Operation:1.) a1[m] and a2[m] are upsampled by a factor of two by inserting zero samples to
produce a signal at the ADC sample rate of fs.2.) a2[m] is delayed so that β1[n]β2[n] = 0.3.) At the input of the gain-error detector the signal is passed through a short FIR filter.4.) The output of the FIR filter is y[n] which is chopped to produce yc[n].5.) The image at 0.5fs -fo turns out to be in phase with the input at fo.6.) Therefore, multiplying y[n] with yc[n] produces a signal with a dc component that is
proportional to the gain mismatch.7.) µg scales the product of y[n] and yc[n] to produce the accumulator output.8.) The feedback on the lower ADC channel causes the accumulator input to converge to
zero in the steady state eliminating the gain mismatch between the channels. The FIR filter is used notch out fs/4 to prevent generation of unwanted dc component.
Accumulator
y[n]
a2[m]µg
Fig. Ex1-04
G[n]
a1[m]
2 z-1β2[n]
2β1[n]
SampleTime
Calibration1+z-2
(-1)n
yc[n]
Gain-error Detector
Chapter 10 – Section 9 (5/2/04) Page 10.9-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Sample Time CalibrationBlock diagram of the aadaptive sampling-timecalibration system:
Operation:1.) β1 goes through a fixed delay that equals the delay through the adaptive FIR filter
when ∆t= 0.2.) The sum of β1 and β2 are applied to a phase detector.
3.) Except for the unit delay in the phase detector, the same method of calculating thecorrelation between the input and the image can be used in the time calibration.
4.) The feedback system is designed to adjust the delay of the adaptive filter so that thedelays experience by both β1 and β2 are identical
Based on simulations, a 21-tap FIR filter with 10-b coefficients is sufficient to correct anytiming error between ±200ps to 10-bit accuracy for frequencies as high as 54 MHz.
Accumulator
y
µt
Fig. Ex1-05
β2
β1
1+z-2
(-1)n
yc
Phase DetectorAdaptive FIR
Fixed Delay
Calculate orLook-up
Coefficients
z-1
∆t
Chapter 10 – Section 9 (5/2/04) Page 10.9-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Implementation of the ADCBlock diagram of the pipelined ADC in each channel.
2 S/H
1.5-bitDAC
1.5-bitADC
Code (Di)
Vm,i Vout,i
Stagei
Stage13
Stage1
InputS/H
1.5 bits 1.5 bits 1.5 bits
Output Registers
14 bits
Input
Fig. Ex1-06
1.5 bit stages permit digital error correction for every stage after the first.
Chapter 10 – Section 9 (5/2/04) Page 10.9-8
CMOS Analog Circuit Design © P.E. Allen - 2004
Implementation - ContinuedCircuits:
Chopping Amplifier Op Amp
+
-+
-
φc
φc
φc φc
Chopper
Vin
Vip
φ2
CI
CI
BIAS4 VCM
BIAS4 VCM
Voutp
Voutn
φ2
φ2
φ1
φ1
φ1
φ1''
φ1''
φ1'
C[m]=1 gives φc = φ1 and φc = 0.
C[m]=-1 gives φc = 0 and φc = φ1.
VB3
Vop
VB2
VB1
VDD
VB5 VB5
Von
Vip VinM1 M2
M3 M4
M5 M6
M7 M8
M9 M10
M11 M12M13
M14VCMFB
Fig. Ex1-07
CF
CF
Stage capacitors:First three stages CI = 0.5pF, remaining stages CI = 0.125pF
Op Amp:50dB gain and settling time of ≈ 7ns
Chapter 10 – Section 9 (5/2/04) Page 10.9-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Experimental ResultsADC output spectrum (fs = 120 Msps, SNDR versus Input AmplitudeVin = 3Vpp, and fo = 0.99MHz) (fs = 120 Msps, and fo = 0.99MHz)
Chapter 10 – Section 9 (5/2/04) Page 10.9-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Experimental Results – ContinuedSNDR versus Amplitude SNDR versus Input Frequency, fo(fs = 120 Msps, and fo = 9.9MHz ) (fs = 120 Msps)
Chapter 10 – Section 9 (5/2/04) Page 10.9-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Performance Summary
Without Calibration With Calibration
Process 0.35µm double-poly CMOS 0.35µm double-poly CMOS
Resolution 10 bits 10 bits
Sampling Rate 120 Megasamples/s 120 Megasamples/s
Active area 5.2 mm2 5.2 mm2
Power Dissipation (Analog/Total) 171 mW/234 mW 171 mW/234 mW + External
Full-Scale Input 3V peak-to-peak 3V peak-to-peak
µo = µg=µt 0 2-22
DNL (fo = 0.99MHz) +0.75/-0.41 LSB +0.44/0.36 LSB
THD (fo = 0.99MHz) -62.4 dB -62.4 dB
SNDR (fo = 0.99MHz) 42.5 dB 56.8 dB
SFDR (fo = 0.99MHz) 46.6 dB 70.2 dB
PSRR (fo = 0.05MHz) 67.0 dB 67.0 dB
CMRR (fo = 0.99MHz) 68.0 dB 68.0 dB
Dynamic Range (fo = 0.99MHz) 43.1 dB 61.5 dB
Chapter 10 – Section 9 (5/2/04) Page 10.9-12
CMOS Analog Circuit Design © P.E. Allen - 2004
EXAMPLE 2 – AN 8–BIT, 150 MHZ CMOS A/D CONVERTER†
IntroductionThis ADC uses a 5-stage pipelined and interleaved ADC that only uses open-loop
circuits such as a differential amplifier or source followers to achieve a high conversionrate.Techniques employed include:• Sliding interpolation to avoid the exponential growth of power and area• Interstage distributed sampling to perform pipelining with using op amps• Dual-channel interleaving to increase the conversion rate• Punctured interpolation to reduce the integral nonlinearity
A clock edge reassignment technique is also introduced to suppress timingmismatches in the interleaved channels.
† Yun-Ti Wang and Behzad Razavi, “An 8-Bit 150-MHz CMOS A/D Converter, “ J. of Solid-State Circuits, vol. 35, no. 3, March 2000, pp. 308-317.
Chapter 10 – Section 9 (5/2/04) Page 10.9-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Traditional Active 2x Interpolation
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
VR,j+1
VR,j
Vin Preamplifiers Interpolating Amplifiers
Aj+1
Aj
Vy
Vx Vo1
Vo3
Vo2
2 21+1 22+1
VinVR,j+1
VR,j Vy
Vx
VinVR,j+1
VR,j
Vo1Vo2
Vo3
VinVR,j+1
VR,j
2
21+1
22+1
Fig. E2-01
Problem with this scheme is the exponential growth of power and hardware.
Chapter 10 – Section 9 (5/2/04) Page 10.9-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Sliding Interpolation SchemeIf Vin lies between VR,j and VR,j+1, the only the outputs of Aj anAj+1 are of interest and theremaining preamplifiers do not provide any additional information.
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
VR,j+1
VR,j
Vin PreamplifiersInterpolating Amplifiers
Aj+1
Aj
Vy
Vx Vo1
Vo3
Vo2
MUX
Sub-ADC
+
-
+
-
+
-
+
-
+
-
+
-
SlidingStage
Vmax
Vmin
VR,j+2
VR,j-1
Vin
Stage 1 Stage 2 Stage 3
Fig. E2-02
In this example, the first stage employs 16 preamplifiers to generate 16 zero crossings.If the analog input lies between VR,j and VR,j+1, then a 4-bit coarse ADC and a 16-to-4MUX route the outputs of the preamplifiers sensing VR,j-1,…, VR,j+2 to the nextinterpolating stageThe sub-ADC detects 4-bits, 2 of which are used for subsequent digital error correction.
Chapter 10 – Section 9 (5/2/04) Page 10.9-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Multistage ADC ArchitectureDetailed block diagram:
First stage has 16 preamplifierswhile each of the following 5 stagesrequires 7 amplifiers each for a totalof 51. The reduction in “differentialpairs” is approximately 500 to 50.
The five sub-ADCs use 15comparators for the first stage and 3comparators each for the following5 stages for a total of 28comparators.
Chapter 10 – Section 9 (5/2/04) Page 10.9-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Embedded PipeliningWhere to apply the pipelining?
Interfacing the stages atthe input of the MUX hastwo advantages.1.) Multiplexing switchescan function as the samplingswitches.2.) The interconnectcapacitance serves as theS/H capacitors.
Note that each stage in the pipeline operates in the sample mode for half of the clockperiod and in the hold mode for the other half. Since the sub-ADC only operatesduring the hold mode, the possibility of interleaving exists to increase the throughput.
Chapter 10 – Section 9 (5/2/04) Page 10.9-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Interleaving
The multiplexers, distributedsampling circuits, and 2x-interpolation amplifiersare duplicated for the evenand the odd channelswhereas the front-endbuffer, the preamplifiers, andall of the sub-ADCs areshared between the 2channels.
Difficulties with the first sub-ADC:1.) Kickback noise disturbs the analog signals at the inputs of the multiplexers.2.) Sub-ADC must wait until the front-end SHA, the buffer, and the preamplifiers have settled.3.) Sub-ADC is in the critical delay path.
Chapter 10 – Section 9 (5/2/04) Page 10.9-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Interleaving – Continued
A replica front-end SHA has beenadded and its output directly drives thesub-ADC.• The scaled-down replica device
dimensions and current avoid thekickback problem.
• The replica signal experiences ashorter delay than that in the mainbecause of the smaller capacitances.
Note that one bit of overlap and digital correction suppress errors due to mismatchesbetween the main path and replica path.
Chapter 10 – Section 9 (5/2/04) Page 10.9-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Clock Edge Reassignment
Ideal clock generation for interleaving. Use of a single clock for both SHAs.
Clock scheme which provides both rising and falling edges for sample and holdoperations.
Chapter 10 – Section 9 (5/2/04) Page 10.9-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Punctured Interpolation
In this scheme, the original inputs (VA1, VA2 and VA3) are used to generate a second set ofinterpolated outputs (VB1and VB2). If the offset components of the adjacent VA’s areuncorrelated, then the standard deviation of the offsets of the corresponding VB’s are,
B1 = A1+A2
2 ⇒ σB1 = σ 2
A1 + σ 2A2
2 = σoriginal
2
Implementation of punctured interpolation. Error plot of the puncturedinterpolation scheme.
Chapter 10 – Section 9 (5/2/04) Page 10.9-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Circuits
Realization of a slice of the signal path in thefirst stage.
Dual-channel interleaved SHA
Chapter 10 – Section 9 (5/2/04) Page 10.9-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Circuits – Continued
Triple-channel interleaved SHA circuit. Clocks used for interleaving.
Comparator used in the first stage.
Chapter 10 – Section 9 (5/2/04) Page 10.9-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Layout Floorplan
Chapter 10 – Section 9 (5/2/04) Page 10.9-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Experimental PerformanceFFT at fin = 1.76 MHz:SNDR and SFDR at fsample = 150 MHz:
Chapter 10 – Section 9 (5/2/04) Page 10.9-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Experimental Performance – ContinuedDNL and INL at fin =1.8 MHz and fsample = 150MHz
Technology 0.6µm,1-p, 3-m CMOS
Resolution 8-bits
DNL 0.62 LSB
INL 1.24 LSB
Sampling Rate 150 MHz
SNDR @ fin = 1.8MHzfin = 70MHz
43.7 dB40 dB
Analog Input Swing 1.6 Vp-p
Input Capacitance 1.5 pF
Active Chip Area 1.2 mm2
Supply Voltage 3.3V
Power Consumption Analog Digital Reference Ladder Total
330 mW53 mW12 mW395 mW
Chapter 10 – Section 9 (5/2/04) Page 10.9-26
CMOS Analog Circuit Design © P.E. Allen - 2004
EXAMPLE 3 – A 400-MSAMPLE/S, 6-BIT CMOS FOLDING ANDINTERPOLATING ADC†
IntroductionThis ADC uses folding and interpolating to achieve a performance of 400 Msamples/s
with an accuracy of 6-bits.Techniques employed in this ADC:• Low impedance, current mode operation• Current-division interpolation• Short aperature comparator (do not need S/H for signal frequencies < 0.25 sample rate)Folding Review:
A three-bit example.
† M. P. Flynn and B. Sheahan, “A 400-Msample/s, 6-b CMOS Folding and Interpolating ADC, IEEE J. of Solid-State Circuits, vol. 33, no. 12, Dec.
1998, pp. 1932-1938.
Chapter 10 – Section 9 (5/2/04) Page 10.9-27
CMOS Analog Circuit Design © P.E. Allen - 2004
ADC ArchitectureBlock diagram:
A folding factor of 4 is chosen requiring 16 folders that produce 16 offset folding signalsand drive 16 comparators. A separate 1-bit coarse ADC determines the MSB.
Chapter 10 – Section 9 (5/2/04) Page 10.9-28
CMOS Analog Circuit Design © P.E. Allen - 2004
FolderFolder block:
The first stage (preamplifier) of the folder uses resistive loads for better speed andlinearity.The outputs of the second stage are current that permits the current mode operation.
Chapter 10 – Section 9 (5/2/04) Page 10.9-29
CMOS Analog Circuit Design © P.E. Allen - 2004
InterpolationIntepolation is used to eliminate half or more of the folder blocks.
Current mode interpolation:
• The output from one folder is fed into the “split-in-4” blocks.• A quarter of the folder 1 output is added to a quarter of the folder 2 output to give F2R’• Two quarters of folder 1 output are summed to form F1R’ and so forth.
If four parallel MOSFETs are used, a quarter of the current flows through eachdevice. This causes two problems, 1.) adds an extra node in the signal path and 2.) itdoes not allow low supply voltages.
Chapter 10 – Section 9 (5/2/04) Page 10.9-30
CMOS Analog Circuit Design © P.E. Allen - 2004
Modified Folder to Include Current Division
The resulting ADC uses:8 folders16 comparators1 coarse ADCEncoder
Chapter 10 – Section 9 (5/2/04) Page 10.9-31
CMOS Analog Circuit Design © P.E. Allen - 2004
ComparatorsTracking Latching
Comparator advantages:• Because the currents are summed to drive the latching devices, the input signal has very
little effect after latching begins.• Since there is always a path for the current to flow, the folders are not disturbed when
the comparators change from tracking to latching.• Since the output voltage swing is small, the comparator is fast.
Chapter 10 – Section 9 (5/2/04) Page 10.9-32
CMOS Analog Circuit Design © P.E. Allen - 2004
Folding and Interpolating ADCBlock diagram with detail of coarse ADC and coarse ADC waveforms.
A cyclic thermometer code is used which is more complex than a flash thermometer code.• The cyclic code along with the decoding logic can surpress the “bubbles” in the cyclic
code.• The reduced number of comparators does not cause a size penalty for using the cyclic
code.
Chapter 10 – Section 9 (5/2/04) Page 10.9-33
CMOS Analog Circuit Design © P.E. Allen - 2004
Test ResultsFFT for 1 MHz sinusoid sampled at SNDR versus input frequency400 Msamples/s (decimated). at 400 Msamples/s
Performance summary:Technology 0.5µm BiCMOS (CMOS only)SNDR (1MHz sinusoid) 33.6 dB @ 400 Msamples/s
32.9 dB @ 450 Msamples/sSupply voltage 3.2VPower 200mWArea 0.6mm2
Input capacitance 1.4 pF
Chapter 10 – Section 9 (5/2/04) Page 10.9-34
CMOS Analog Circuit Design © P.E. Allen - 2004
EXAMPLE 4 – A 6-BIT, 1.6-GSAMPLE/S ADC IN 0.18µm CMOS USINGAVERAGING TERMINATION†
IntroductionThis ADC uses folding and interpolating to achieve a performance of 1600
Msamples/s with an accuracy of 6-bits.Techniques employed in this ADC:• Resistance averaging to reduce offsets and nonlinearity• Termination of the averaging circuits to enhance the averaging• Derivation of expressions to relate the INL, DNL, and the number of over-range
amplifiers necessary as a function of averaging.• Distributed track-and-hold
This example represents one of the fastest CMOS ADC published.
† P.C.S. Scholtens and M. Vertregt, “A 6-b 1.6-Gsample/s Flash ADC in 0.18 µm CMOS Using Averaging Termination, IEEE J. of Solid-State
Circuits, vol. 37, no. 12, Dec. 2002, pp. 1599-1609.
Chapter 10 – Section 9 (5/2/04) Page 10.9-35
CMOS Analog Circuit Design © P.E. Allen - 2004
What is Averaging?Averaging is a technique that connects the outputs of adjacent amplifiers to obtain moreaccuracy and more speed.
Res
isto
r Ave
ragi
ng
Res
isto
r Ave
ragi
ng
T/HVin+
Vin-
Fig. Ex4-01
Clock
DigitalEncodingNetwork
DigitalOutput
ClockClock
Preamplifiers Comparators
Results:1.) With no averaging, the standard deviation of the offset voltage is 11mV.2.) With averaging of the preamplifiers, the standard deviation is 9mV.3.) With averaging of the preamplifiers and comparators, the standard deviation is 3.7mV.
Chapter 10 – Section 9 (5/2/04) Page 10.9-36
CMOS Analog Circuit Design © P.E. Allen - 2004
The Influence of Averaging on Bandwidth†
Another important advantage of averaging is an increase in bandwidth.
The standard deviation of the offset is inversely proportional to the Transistor Area .
∴ σVOS ≈ A
(W·L)input
It can be shown that averaging will reduce the value of σVOS by approximately 3.
Therefore, the transistors can be made 9 times smaller to achieve the same σVOS.
This means that the capacitances are reduced by a factor of 9 while the resistances areonly increased by a factor of 3. As a result, we find that,
BWsingle = 1
RO·(Cwire + Cload + Cj))
and
BWaveraging = 1
3RO·
Cwire
9 + Cload + Cj9 + Cnetwork
Therefore, BWaveraging
BWsingle ≈ 3
† M. Choi and A. Abidi, “A 6-b, 1.3-Gsamples/s A/D Converter in 0.35µm CMOS,” IEEE J. of Solid-State Circuits, vol. 36, no. 12, Dec. 2001, pp.
1847-1858.
Chapter 10 – Section 9 (5/2/04) Page 10.9-37
CMOS Analog Circuit Design © P.E. Allen - 2004
Some Useful Monte Carlo Simulation ResultsMost mismatch analyses can be expressed in terms of the standard deviations of
threshold and W mismatch. Using 0.35µm CMOS technology, the following standarddeviations have been derived from Monte Carlo simulations performed on a two-stageaveraging resistor network.
σVth,NMOS = 10.6mV·µm
W·L σVth,PMOS = 8.25mV·µm
W·L
and
σ
∆W
W NMOS = 0.0056·µm
W·L σ
∆W
W PMOS = 0.0011·µm
W·L
The above results suggest that PMOS devices would be better matched than NMOSdevices in this technology.
Chapter 10 – Section 9 (5/2/04) Page 10.9-38
CMOS Analog Circuit Design © P.E. Allen - 2004
Averaging TerminationIn addition to the above concepts of averaging, by applying the concept of averaging
termination, the number of over-range amplifiers can be reduced leading to reducedpower consumption.
The over-range amplifiers are the amplifiers which are outside the usable voltagerange for the purposes of making the averaging network look like an infinite array.Some results:
No averaging termination: Averaging termination:
R1 = the source resistance of each amplifierR2 = the averaging resistance used to connect the outputs of each amplifiern = number of level of quantization
Chapter 10 – Section 9 (5/2/04) Page 10.9-39
CMOS Analog Circuit Design © P.E. Allen - 2004
Analog Front End of the ADC
Chapter 10 – Section 9 (5/2/04) Page 10.9-40
CMOS Analog Circuit Design © P.E. Allen - 2004
Experimental ResultsENOB versus fsample: ENOB versus fsignal: Measured linearity:
Summary of results:
Measured Quantity ValueENOB
fsample = 1.6Gsamples/s, fsignal = 263 MHzfsample = 1.5Gsamples/s, fsignal = 300 MHzfsample = 1.6Gsamples/s, fsignal = 660 MHz
5.6 bits5.7 bits5.0 bits
Power consumption (1.95V analog and 2.25V digital)At 1.6 Gsamples/s the digital is increased to 2.35V
328mW340mW
Chapter 10 – Section 9 (5/2/04) Page 10.9-41
CMOS Analog Circuit Design © P.E. Allen - 2004
SUMMARY OF HIGH-SPEED ADC EXAMPLES• CMOS technology is capable of 6-bit, 1.5 Gsample/s ADC with less than 0.5mW of
power consumption• Key techniques for high-speed performance include:
- Digital background calibration- Time interleaving (frequency interleaving?)- Sliding interpolation- Punctured interpolation to reduce the INL- Current mode operation and current-division interpolation- Resistor averaging and resistor averaging termination
• Challenges- Increase the resolution at high speeds- Minimize the power dissipation- Move signal frequency bandwidth up to RF applications (1-3 GHz)
Chapter 10 – Section 10 (5/2/04) Page 10.10-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 10.10 - OVERSAMPLING CONVERTERSIntroductionWhat is an oversampling converter?
An oversampling converter uses a noise-shaping modulator to reduce the in-bandquantization noise to achieve a high degree of resolution.
What is the possible performance of an oversampled converter?The performance can range from 16 to 18 bits of resolution at bandwidths up to 50kHzto 8 to 10 bits of resolution at bandwidths up to 5-10MHz.
What is the range of oversampling?The oversampling ratio, called M, is a ratio of the clock frequency to the Nyquistfrequency of the input signal. This oversampling ratio can vary from 8 to 256.• The resolution of the oversampled converter is proportional to the oversampled ratio.• The bandwidth of the input signal is inversely proportional to the oversampled ratio.
What are the advantages of oversampling converters?Very compatible with VLSI technology because most of the converter is digitalHigh resolutionSingle-bit quantizers use a one-bit DAC which has no INL or DNL errorsProvide an excellent means of trading precision for speed
What are the disadvantages of oversampling converters?Difficult to model and simulateLimited in bandwidth to the clock frequency divided by the oversampling ratio
Chapter 10 – Section 10 (5/2/04) Page 10.10-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Nyquist Versus Oversampled ADCsConventional Nyquist ADC Block Diagram:
Fig.10.9-01
DigitalProcessor
y(kTN)x(t)
Filtering Sampling Quantization Digital Coding
Oversampled ADC Block Diagram:
Fig.10.9-02
DecimationFilter
y(kTN)x(t)
Filtering Sampling Quantization Digital Coding
Modulator
Components:• Filter - Prevents possible aliasing of the following sampling step.• Sampling - Necessary for any analog-to-digital conversion.• Quantization - Decides the nearest analog voltage to the sampled voltage (determines
the resolution).• Digital Coding - Converts the quantizer information into a digital signal.
Chapter 10 – Section 10 (5/2/04) Page 10.10-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Spectrum of Nyquist and Oversampled ConvertersDefinitions:
fB = analog signal bandwidthfN = Nyquist frequency (two times fB)fS = sampling or clock frequency
M = fSfN =
fS2fB = oversampling ratio
Frequency spectrums:
Fig.10.9-03
0.5fN = 0.5fSfB fS =fN0
0
Am
plitu
de
f
fB = 0.5fN
0.5fS fS =MfN0
0
Am
plitu
de
ffN
Anti-aliasing filter
Anti-aliasing filter
Signal Bandwidth
Signal Bandwidth
Transition band
Transition band
Conventional ADC with fB≈ 0.5fN=0.5fS.
Oversampled ADC with fB≈ 0.5fN<<fS.
Chapter 10 – Section 10 (5/2/04) Page 10.10-4
CMOS Analog Circuit Design © P.E. Allen - 2004
Quantization Noise of a Conventional (Nyquist) ADCMultilevel Quantizer:
The quantized signal y can be represented as,
y = Gx + ewhere
G = gain of the ADC, normally 1e = quantization error
The mean square value of the quantization error is
e 2rms = SQ = 1∆ ⌡⌠
-∆/2
∆/2 e(x)2dx =
∆212
Fig.10.9-04
Output, y
Input, x
5
1
3
-1
-3
-5
2 4 6
-2-4-6
Ideal curve
Input, x
Quantization error, e1
-1
∆
∆
Chapter 10 – Section 10 (5/2/04) Page 10.10-5
CMOS Analog Circuit Design © P.E. Allen - 2004
Quantization Noise of a Conventional (Nyquist) ADC - ContinuedSpectral density of the sampled noise:
When a quantized signal is sampled at fS (= 1/τ), then all of its noise power folds intothe frequency band from 0 to 0.5fS. Assuming that the noise power is white, the spectraldensity of the sampled noise is,
E(f) = erms2fS = erms 2τ
where τ = 1/fS and fS = sampling frequency
The inband noise energy no is
no2 = ⌡⌠
0
fB E2(f)df = e
2rms (2fBτ) = e
2rms
2fB
fS = e
2rms M ⇒ no =
erms
M
What does all this mean? • One way to increase the resolution of an ADC is to make the bandwidth of the signal,
fB, less than the clock frequency, fS. In otherwords, give up bandwidth for precision.
• However, it is seen from the above that a doubling of the oversampling ratio M, onlygives a decrease of the inband noise, no, of 1/ 2 which corresponds to -3dB decrease oran increase of resolution of 0.5 bits
The conclusion is that reduction of the oversampling ratio is not a very good method ofincreasing the resolution of a Nyquist analog-digital converter.
Chapter 10 – Section 10 (5/2/04) Page 10.10-6
CMOS Analog Circuit Design © P.E. Allen - 2004
Oversampled Analog-Digital ConvertersClassification of oversampled ADCs:1.) Straight-oversampling - The quantization noise is assumed to be equally distributed
over the entire frequency range of dc to 0.5fS. This type of converter is representedby the Nyquist ADC.
2.) Predictive oversampling - Uses noise shapingplus oversampling to reduce the inband noise toa much greater extent than the straight-oversampling ADC. Both the signal and noisequantization spectrums are shaped.
3.) Noise-shaping oversampling - Similar to thepredictive oversampling except that only thenoise quantization spectrum is shaped whilethe signal spectrum is preserved.
The noise-shaping oversampling ADCs are also known as delta-sigma ADCs. We willonly consider the delta-sigma type oversampling ADCs.
Fig.10.9-05
-
+
LoopFilter
QuantizerInput Output
fS
Fig.10.9-06
-
+ LoopFilter Quantizer
Input Output
fS
Chapter 10 – Section 10 (5/2/04) Page 10.10-7
CMOS Analog Circuit Design © P.E. Allen - 2004
Oversampling Analog-Digital Converters - ContinuedGeneral block diagram of an oversampled ADC:
Fig.10.9-07
∆Σ Modulator(Analog)
Decimator(Digital)
Lowpass Filter(Digital)
fS fD<fS
AnalogInputx(t)
fB 2fB DigitalPCM
Components of the Oversampled ADC:1.) ∆Σ Modulator - Also called the noise shaper because it can shape the quantizationnoise and push the majority of the inband noise to higher frequencies. It modulates theanalog input signal to a simple digital code, normally a one-bit serial stream using asampling rate much higher than the Nyquist rate.2.) Decimator - Also called the down-sampler because it down samples the highfrequency modulator output into a low frequency output and does some pre-filtering onthe quantization noise.3.) Digital Lowpass Filter - Used to remove the high frequency quantization noise and topreserve the input signal.Note: Only the modulator is analog, the rest of the circuitry is digital.
Chapter 10 – Section 10 (5/2/04) Page 10.10-8
CMOS Analog Circuit Design © P.E. Allen - 2004
First-Order, Delta-Sigma ModulatorBlock diagram of a first-order, delta-sigmamodulator:
Components:• Integrator (continuous or discrete time)• Coarse quantizer (typically two levels)
- A/D which is a comparator for two levels- D/A which is a switch for two levels
First-order modulator output for a sinusoidal input:
Fig.10.9-09
-1.5
-1
-0.5
0
0.5
1
1.5
0 50 100 150 200 250
Vol
ts
Tme (Units of T, clock period)
Fig.10.9-08
-
+Integrator A/D
D/A
x
u
v y
Quantizer
fS
Chapter 10 – Section 10 (5/2/04) Page 10.10-9
CMOS Analog Circuit Design © P.E. Allen - 2004
Sampled-Data Model of a First-Order ∆∆∆∆ΣΣΣΣ Modulator
Writing the following relationships,y[nTs] = q[nTs] +v[nTs]
v[nTs] = w[(n-1)Ts] + v[(n-1)Ts]
∴ y[nTs] = q[nTs]+w[(n-1)Ts]+v[(n-1)Ts] = q[nTs]+x[(n-1)Ts]-y[(n-1)Ts]+v[(n-1)Ts]
But the first equation can be written asy[(n-1)Ts] = q[(n-1)Ts] +v[(n-1)Ts] → q[(n-1)Ts] = y[(n-1)Ts] - v[(n-1)Ts]
Substituting this relationship into the above gives,y[nTs] = x[(n-1)Ts] + q[nTs] - q[(n-1)Ts]
Converting this expression to the z-domain gives,
Y(z) = z-1X(z) + (1-z-1)Q(z)Definitions:
Signal Transfer Function = STF = Y(z) X(x) = z-1
Noise Transfer Function = NT F= Y(z) Q(x) = 1-z-1
+
+
-
+Delay
+Integrator
Quan-tizer
x[nTs] v[nTs]
q[nTs]
y[nTs]
Fig. 10.9-10
w[nTs]
Chapter 10 – Section 10 (5/2/04) Page 10.10-10
CMOS Analog Circuit Design © P.E. Allen - 2004
Higher-Order ∆∆∆∆ΣΣΣΣ ModulatorsA second-order, ∆Σ modulator:
Fig.10.9-11
+
+
-
+Delay
+Integrator 2
Quan-tizer
q[nTs]
y[nTs]x[nTs]
+
+
-
+Delay
Integrator 1
It can be shown that the z-domain output is,
Y(z) = z-2X(z) + (1-z-1)2Q(z)The general, L-th order ∆Σ modulator has the following form,
Y(z) = z-LX(z) + (1-z-1)LQ(z)Note that noise tranfer function, NTF, has L-zeros at the origin resulting in a high-passtransfer function.This high-pass characteristic reduces the noise at low frequencies.
Chapter 10 – Section 10 (5/2/04) Page 10.10-11
CMOS Analog Circuit Design © P.E. Allen - 2004
Noise Transfer FunctionThe noise transfer function can be written as,
NTFQ (z) = (1-z-1)L
Evaluate (1-z-1) by replacing z by ejωTs to get
(1-z-1)= 1 - e-jωTs x 2j2j x
ejπf/fs
ejπf/fs =
ejπf/fs - e-jπf/fs
2j 2j e-jπf/fs = sin(πf/Ts) 2j e-jπf/fs
|1-z-1| = (2sinπfTs) → |NTFQ(f)| = (2sinπfTs)L
Magnitude of the noise transferfunction,
Note: Single-loop modulatorshaving noise shaping charac-teristics of the form (1-z-1)Lare unstable for L>2 unless anL-bit quantizer is used.
Fig.10.9-12
LPF
0
2
4
6
8
10
Mag
nitu
de o
f no
ise
shap
ing
func
tion
Frequency0
L = 1
L = 2
L = 3
fb fs/2
Chapter 10 – Section 10 (5/2/04) Page 10.10-12
CMOS Analog Circuit Design © P.E. Allen - 2004
In-Band Rms Noise of Single-Loop ∆∆∆∆ΣΣΣΣ ModulatorAssuming noise power is white, the power spectral density of the ∆Σ modulator, SE(f), is
SE(f) = |NTFQ(f)|2 |SQ(f)|
fs
Next, integrate SE(f) over the signal band to get the inband noise power using SQ = ∆212
∴ SB = 1fs ⌡
⌠
-fb
fb
(2sinπfTs)2L ∆212df ≈
π2L
2L+1
1
M2L+1
∆2
12 where sinπfTs ≈ πfTs for M>>1.
Therefore, the in-band, rms noise is given as
n0 = SB =
πL
2L+1
1
ML+0.5
∆
12 =
πL
2L+1
1
ML+0.5 erms
Note that as the ∆Σ is a much more efficient way of achieving resolution by increasing M.
n0 ∝ erms
ML+0.5 ⇒ Doubling of M leads to a 2L+0.5 decrease in in-band noise
which leads to an extra L+0.5 bits of resolution!∴ The increase of the oversampling ratio is an excellent method of increasing the
resolution of a ∆Σ oversampling analog-digital converter.
Chapter 10 – Section 10 (5/2/04) Page 10.10-13
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of RMS Noise Versus Oversampling Ratio for Single Loop ∆∆∆∆ΣΣΣΣModulatorsPlotting n0/erms gives,
n0 erms
=
πL
2L+1
1
ML+0.5
Fig.10.9-15
-100
-80
-60
-40
-20
0
1 8 32 128 1024Oversampling Ratio, M
2 4 16 64 512
L=0
L=1
L=2
L=3
n0 erms (dB)
L=4
Chapter 10 – Section 10 (5/2/04) Page 10.10-14
CMOS Analog Circuit Design © P.E. Allen - 2004
Dynamic Range of ∆∆∆∆ΣΣΣΣ Analog-Digital ConvertersOversampled ∆Σ Converter:The dynamic range, DR, for a 1 bit-quantizer with level spacing ∆ =VREF, is
DR2 = Maximum signal power
SB(f) =
∆
2 22
π2L
2L+1
1
M2L+1
∆2
12
= 32
2L+1π2L M2L+1
Nyquist Converter:The dynamic range of a N-bit Nyquist rate ADC is (now ∆ becomes ≈VREF for large N),
DR2 = Maximum signal power
SQ =
(VREF/2 2)2
∆2/12 = 32 22N → DR = 1.5 2N
Expressing DR in terms of dB (DRdB) and solving for N, gives
N = DRdB - 1.7609
6.0206 or DRdB = (6.0206N + 1.7609) dB
Example: A 16-bit ∆Σ ADC requires about 98dB of dynamic range. For a second-ordermodulator, M must be 153 or 256 since we must use powers of 2.Therefore, if the bandwidth is 20kHz, then the clock frequency must be 10.24MHz.
Chapter 10 – Section 10 (5/2/04) Page 10.10-15
CMOS Analog Circuit Design © P.E. Allen - 2004
Multibit QuantizersA single-bit quantizer:
∆ = VREF
Advantage is that the DAC is linear.
Multi-bit quantizer:Consists of an ADC and DAC of B-bits.
∆ = VREF2B-1
Disadvantage is that the DAC is no longer perfectly linear.
Dynamic range of a multibit ∆Σ ADC:
DR2 = 32
2L+1π2L M2L+1 2B-1 2
+-
yv
uv<0
v>0
Fig. 10.9-13
VREF2
VREF2
Fig. 10.9-14
A/D
D/A
v
Quantizer
fS
u
y
VREF ∆
Fig. 10.9-135
Chapter 10 – Section 10 (5/2/04) Page 10.10-16
CMOS Analog Circuit Design © P.E. Allen - 2004
Example 1 - Tradeoff Between Signal Bandwidth and Accuracy of ∆∆∆∆ΣΣΣΣ ADCsFind the minimum oversampling ratio, M, for a 16-bit oversampled ADC which uses
(a.) a 1-bit quantizer and third-order loop, (b.) a 2-bit quantizer and third-order loop, and(c.) a 3-bit quantizer and second-order loop. For each case, find the bandwidth of theADC if the clock frequency is 10MHz.
Solution
We see that 16-bit ADC corresponds to a dynamic range of approximately 98dB. (a.) Solving for M gives
M =
2
3 DR2
2L+1 π2L
(2B-1)21/(2L+1)
Converting the dynamic range to 79,433 and substituting into the above equation gives aminimum oversampling ratio of M = 48.03 which would correspond to an oversamplingrate of 64. Using the definition of M as fc/2fB gives fB as 10MHz/2·64 = 78kHz.
(b.) and (c.) For part (b.) and (c.) we obtain a minimum oversampling rates of M = 32.53and 96.48, respectively. These values correspond to oversampling rates of 32 and 128,respectively. The bandwidth of the converters is 312kHz for (b.) and 78kHz for (c.).
Chapter 10 – Section 10 (5/2/04) Page 10.10-17
CMOS Analog Circuit Design © P.E. Allen - 2004
Z-Domain Equivalent CircuitsThe modulator structures are much easier to analyze and interpret in the z-domain.
Fig.10.9-16
+
+
-
+Delay
+Integrator
Quan-tizer
x[nTs] v[nTs]
q[nTs]
y[nTs]w[nTs]
+
+
-
+z-1 +
Integrator
Quan-tizer
X(z) V(z)
Q(z)
Y(z)W(z)
-
+ z-1 +X(z)
Q(z)
Y(z)
1-z-1
Y(z) = Q(z) +
z-1
1-z-1 [X(z) - Y(z)] → Y(z)
1
1-z-1 = Q(z) +
z-1
1-z-1 X(z)
∴ Y(z) = (1-z-1)Q(z) + z-1X(z) → NTFQ (z) = (1-z-1) for L = 1
Chapter 10 – Section 10 (5/2/04) Page 10.10-18
CMOS Analog Circuit Design © P.E. Allen - 2004
Alternative Modulator ArchitecturesSince the single-loop architecture with order higher than 2 are unstable, it is necessary tofind alternative architectures that allow stable higher order modulators.Cascaded ∆Σ Modulator-Second-Order
Y1(z) = (1-z-1)Q1(z) + z-1X(z)
X2(z) =
z-1
1-z-1 (X(z) -Y1(z)
=
z-1
1-z-1 X(z) -
z-1
1-z-1 [(1-z-
1)Q1(z) + z-1X(z)]
Y2(z) = (1-z-1)Q2(z) + z-1X2(z) = (1-z-1)Q2(z) +
z-2
1-z-1 X(z) - z-2Q1(z) -
z-2
1-z-1 X(z)
= (1-z-1)Q2(z) - z-2Q1(z)
Y(z) = Y2(z) - z-1Y2(z) + z-2Y1(z) = (1-z-1)Y2(z) + z-2Y1(z)
= (1-z-1)2Q2(z) - (1-z-1)z-2Q1(z) + (1-z-1)z-2Q1(z) + z-3X(z) = (1-z-1)2Q2(z) + z-3X(z)
∴ Y(z) = (1-z-1)2Q2(z) + z-3X(z)
Fig.10.9-17
-
+ z-1 +
Q1(z)
Y1(z)
1-z-1
-
+ z-1 +
X(z)
Q2(z)
Y(z)
1-z-1
z-1-
+ z-1 +
X2(z)
Y2(z)
+
Chapter 10 – Section 10 (5/2/04) Page 10.10-19
CMOS Analog Circuit Design © P.E. Allen - 2004
Alternative Modulator Architectures - ContinuedMASH Architecture - Third Order
It can be shown that
Y(z) = X(z) + (1-z-1)3Q3(z)
Comments:• The above structures that eliminate the noise of all quantizers except the last are called
MASH or multistage architectures.• Digital error cancellation logic is used to remove the quantization noise of all stages,
except that of the last one.
1-z-11
z-1
X(z) +
-
Q1(z)
+ -
+ +
1-z-11
z-1
Q2(z)
+ -
+ +1-z-1
Y1(z)
Y2(z)
+- +
+
+
+
1-z-11
z-1
Q3(z)
+ +1-z-1
Y3(z)
+-
1-z-1
Y(z)
Fig. 10.9-17A
-Q1(z)
-Q2(z)
Chapter 10 – Section 10 (5/2/04) Page 10.10-20
CMOS Analog Circuit Design © P.E. Allen - 2004
Alternative Modulator Architectures - ContinuedDistributed Feedback ∆Σ Modulator - Fourth-Order
Fig.10.9-20
a1z-1
1-z-1-
+X a2z-1
1-z-1a3z-1
1-z-1a4z-1
1-z-1+
+ 1-bitA/D
1-bitD/A
Q
Y
++
++
Y1 Y2 Y3 Y4
Amplitude of integrator outputs:
0.00
0.25
0.50
0.75
1.00
1.25
1.50
am
plit
ud
e
of
inte
gra
tor
ou
tpu
t /
VR
EF
- 1 .00 -0.60 -0.20 0.20 0.60 1.00input signal amplitude / VREF
fourth order distributed feedback modulatora1=0.1, a2=0.1, a3=0.4, a4=0.4
y 1y 2
y 3y 4
Chapter 10 – Section 10 (5/2/04) Page 10.10-21
CMOS Analog Circuit Design © P.E. Allen - 2004
Alternative Modulator Architectures - ContinuedDistributed Feedback ∆Σ Modulator - Fourth-Order
Fig.10.9-20
a1z-1
1-z-1-
+X a2z-1
1-z-1a3z-1
1-z-1a4z-1
1-z-1+
+ 1-bitA/D
1-bitA/D
Q
Y
++
++
Y1 Y2 Y3 Y4
Amplitude of integrator outputs:
0.00
0.25
0.50
0.75
1.00
1.25
1.50
-1.00
am
plit
ud
e
of
inte
gra
tor
ou
tpu
ts
- 0 .60 -0.20 0.20 0.60 1.00input signal amplitude / VREF
fourth order feedforward modulatora1=0.5, a2=0.4, a3=0.1, a4=0.1
y 1
y 2
y 3
y 4
Chapter 10 – Section 10 (5/2/04) Page 10.10-22
CMOS Analog Circuit Design © P.E. Allen - 2004
Alternative Modulator Architectures - ContinuedCascaded of a Second-Order Modulator with a First-Order Modulator
Fig.10.9-21
a1z-1
1-z-1-
+ a2z-1
1-z-1-
+
+
X +
α
a3z-1
1-z-1-
+ +β
q1
q2
+
+
Dig
ital e
rror
can
cella
tion
circ
uit
Y
Comments:• The stability is guaranteed for cascaded structures• The maximum input range is almost equal to the reference voltage level for the
cascaded structures• All structures are sensitive to the circuit imperfection of the first stages• The output of cascaded structures is multibit requiring a more complex digital
decimator
Chapter 10 – Section 10 (5/2/04) Page 10.10-23
CMOS Analog Circuit Design © P.E. Allen - 2004
Integrator Circuits for ∆∆∆∆ΣΣΣΣ ModulatorsFundamental block of the ∆Σ modulator:
Fig.10.9-22+
+z-1
Vi(z) az-1
1-z-1
Vo(z) Vi(z) Vo(z)a
Fully-Differential, SwitchedCapacitor Implementation:
It can be shown (Chapter 9) that,
Vout(z)Vin(z) =
Cs
Ci
z-1
1-z-1 ⇒ V
oout(e jωΤ)
Voin( e jωΤ)
=
C1
C2
e-jωΤ/2
j2 sin(ωT/2)
ωT
ωT =
C1
jωTC2
ωT/2
sin(ωT/2) e-jωΤ/2
V
oout(e jωΤ)
Voin( e jωΤ)
= (Ideal)x(Magnitude error)x(Phase error) where ωI = C1
TC2 ⇒ Ideal =
ωIjω
Fig.10.9-23
+
-+
-vin+
-vout+
-
φ2
φ2
φ2
φ2
φ1
φ1
φ1
φ1
Cs
φ1
Cs
Ci
Ci
Chapter 10 – Section 10 (5/2/04) Page 10.10-24
CMOS Analog Circuit Design © P.E. Allen - 2004
Power Dissipation Vs. Supply Voltage And Oversampling RatioThe following is based on the above switched-capacitor integrator:1.) Dynamic range:
The noise in the band [-fs,fs] is kT/C while the noise in the band [-fs/2M,fs/2M] iskT/MC. We must multiply this noise by 4; x2 for the sampling and integrating phases andx2 for differential operation.
∴ DR = VDD2/24kT/MCs
= V
2DDMCs8kT
2.) Lower bound on the sampling capacitor, Cs:
Cs = 8kT·DR
V2
DDM
3.) Static power dissipation of the integrator:Pint = IbVDD
4.) Settling time for a step input of Vo,max:
Ib = Ci Vo,maxTsettle
=
Ci
Tsettle
Cs
CiVDD =
CsVDDTsettle
= CsVDD(2fs) = 2MfNCsVDD
∴ Pint = 2MfNCsVDD2 = 16kT·DR·fNBecause of additional feedback to the first integrator, the maximum voltage can be 2VDD.
P1st-int = 32kT·DR·fN
Chapter 10 – Section 10 (5/2/04) Page 10.10-25
CMOS Analog Circuit Design © P.E. Allen - 2004
Implementation of ∆∆∆∆ΣΣΣΣ ModulatorsMost of today’s delta-sigma modulators use fully differential switched capacitorimplementations.Advantages are:• Doubles the signal swing and increases the dynamic range by 6dB• Common-mode signals that may couple to the signal through the supply lines and
substrate are canceled• Charge injected by the switches are canceled to a first-orderExample:
First integratordissipates themost power andrequires the mostaccuracy.
Fig.10.9-24
YB
Y
-
+ 0.5z-11 - z-1
-
+ 0.5z-11 - z-1
++X Y
Q1
+
-
VRef+
φ1dφ1d
Y YB
φ2φ2
VRef+ VRef
-
VRef-
2C
2C
C
Cφ1dφ1d
YYB
VRef+
Y YB
VRef-
φ1
φ1
VRef+ VRef
-
YYB
+
-φ2φ2
2C
2C
C
C
φ1
φ1
φ1
Chapter 10 – Section 10 (5/2/04) Page 10.10-26
CMOS Analog Circuit Design © P.E. Allen - 2004
Example - 1.5V, 1mW, 98db ∆∆∆∆ΣΣΣΣ Analog-Digital Converter†
a1z - 1Σ
b1
Σ Σa2
z - 1
b2
a3z - 1
a4z - 1
Σ
1-bitA/D
1-bitD/A
α E
y4Y
y3y2y1
X
(6-1)
where a1 = 1/3, a2 = 3/25, a3 = 1/10, a4 = 1/10, b1= 6/5, b2= 1 and α = 1/6
Advantages: • The modulator combines the advantages of both DFB and DFF type modulators:
Only four op amps are required. The 1st integrator’s output swing is between ±VREFfor large input signal amplitudes (0.6VREF), even if the integrator gain is large (0.5).
• A local resonator is formed by the feedback around the last two integrators to furthersuppress the quantization noise.
• The modulator is fully pipelined for fast settling.
† A.L. Coban and P.E. Allen, “A 1.5V, 1mW Audio ∆Σ Modulator with 98dB Dynamic Range, “Proc. of 1999 Int. Solid-State Circuits Conf., Feb.1999, pp. 50-51.
Chapter 10 – Section 10 (5/2/04) Page 10.10-27
CMOS Analog Circuit Design © P.E. Allen - 2004
1.5V, 1mW, 98dB ∆∆∆∆ΣΣΣΣ Analog-Digital Converter - ContinuedIntegrator power dissipation vs. integrator gain
DR = 98 dBBW = 20 kHzCs = 5 pF0.5 µm CMOS
Chapter 10 – Section 10 (5/2/04) Page 10.10-28
CMOS Analog Circuit Design © P.E. Allen - 2004
1.5V, 1mW, 98db ∆∆∆∆ΣΣΣΣ Analog-Digital Converter - ContinuedModulator power dissipation vs. oversampling ratio
Suppy Voltage (V)DR = 98 dBBW = 20 kHzIntegrator gain = 1/30.5µm CMOS
OSR = 64
OSR = 32OSR = 16
OSR = 8
Chapter 10 – Section 10 (5/2/04) Page 10.10-29
CMOS Analog Circuit Design © P.E. Allen - 2004
1.5V, 1mW, 98dB ∆∆∆∆ΣΣΣΣ Analog-Digital Converter - ContinuedCircuit Implementation:
Capacitor Values
Capacitor Integrator 1 Integrator 2 Integrator 3 Integrator 4
Cs 5.00pF 0.15pF 0.30pF 0.10pF
Ci 15.00pF 1.25pF 3.00pF 1.00pF
Ca - - 0.05pF -
Cb1 - - - 0.12pF
Cb2 - - - 0.10pF
Fig.10.9-25
1
1d
2
2d
Chapter 10 – Section 10 (5/2/04) Page 10.10-30
CMOS Analog Circuit Design © P.E. Allen - 2004
1.5V, 1mW, 98dB ∆∆∆∆ΣΣΣΣ Analog-Digital Converter - ContinuedMicrophotograph of the experimental ∆Σ modulator.
Chapter 10 – Section 10 (5/2/04) Page 10.10-31
CMOS Analog Circuit Design © P.E. Allen - 2004
1.5V, 1mW, 98dB ∆∆∆∆ΣΣΣΣ Analog-Digital Converter - ContinuedMeasured SNR and SNDR versus input level of the modulator.
Chapter 10 – Section 10 (5/2/04) Page 10.10-32
CMOS Analog Circuit Design © P.E. Allen - 2004
1.5V, 1mW, 98dB ∆∆∆∆ΣΣΣΣ Analog-Digital Converter - ContinuedMeasured baseband spectrum for a -7.5dBr 1kHz input.
Chapter 10 – Section 10 (5/2/04) Page 10.10-33
CMOS Analog Circuit Design © P.E. Allen - 2004
1.5V, 1mW, 98dB ∆∆∆∆ΣΣΣΣ Analog-Digital Converter - ContinuedMeasured baseband spectrum for a -80dBr 1kHz input.
-80 dBr, 1 kHz signalVREF = 1.5 V (diff.)2048-point FFT
frequency, (kHz)
Chapter 10 – Section 10 (5/2/04) Page 10.10-34
CMOS Analog Circuit Design © P.E. Allen - 2004
1.5V, 1mW, 98dB ∆∆∆∆ΣΣΣΣ Analog-Digital Converter - ContinuedMeasured 4th-Order ∆Σ Modulator Characteristics:
Table 5.4
Measured fourth-order delta-sigma modulator characteristics
Technology : 0.5 µm triple-metal single-poly n-well CMOS process
Supply voltage 1.5 VDie area 1.02 mm x 0.52 mmSupply current 660 µA analog part 630 µA
digital part 30 µAReference voltage 0.75VClock frequency 2.8224MHzOversampling ratio 64Signal bandwidth 20kHzPeak SNR 89 dBPeak SNDR 87 dBPeak S/D 101dBHD @ -5dBv 2kHz input -105dBvDR 98 dB
3
Chapter 10 – Section 10 (5/2/04) Page 10.10-35
CMOS Analog Circuit Design © P.E. Allen - 2004
Decimation and FilteringThe decimator and filterare implemented digitallyand occupy most of thearea and consume most ofthe power.Function of the decimatorand filter are;1.) To attenuate the quantization noise above the baseband2.) Bandlimit the input signal3.) Suppress out-of-band spurious signals and circuit noiseMost of the ∆Σ ADC applications demand decimation filters with linear phasecharacteristics which leads to the use of finite impulse response (FIR) filters.FIR filters:
For a specified ripple and attenuation,
Number of filter coefficients ∝ fsft
where fs is the input rate to the filter (clock frequency of the quantizer) and ft is thetransition bandwidth.To reduce the number of stages, the decimation filters are implemented in several stages.
Fig.10.9-07
∆Σ Modulator(Analog)
Decimator(Digital)
Lowpass Filter(Digital)
fS fD<fS
AnalogInputx(t)
fB 2fB DigitalPCM
Chapter 10 – Section 10 (5/2/04) Page 10.10-36
CMOS Analog Circuit Design © P.E. Allen - 2004
A Multi-Stage Decimation FilterTypical multi-stage decimation filter:
Fig.10.9-26
L+1-th order
fs fs/D 2fN fN
First-halfband filter
Second-halfband filter
fN
Droopcorrection
1.) For ∆Σ modulators with (1-z-1)L noise shaping comb filters are very efficient.• Comb filters are suitable for reducing the sampling rate to four times the Nyquist
rate.• Designed to supress the quantization noise that would otherwise alias into the
signal band upon sampling at an intermediate rate of fs1.
2.) The remaining filtering is performed by in stages by FIR or IIR filters.• Supresses out-of-band components of the signal
3.) Droop correction - may be required depending upon the ADC specifications
Chapter 10 – Section 10 (5/2/04) Page 10.10-37
CMOS Analog Circuit Design © P.E. Allen - 2004
Comb FiltersA comb filter that computes a running average of the last D input samples is given as
y[n] = 1D ∑
i = 0
D - 1
x[n-i]
where D is the decimation factor given as
D = fsfs1
The corresponding z-domain expression is,
HD(z) = ∑i = 1
D
z-i = 1D
1 - z-D
1 - z-1
The frequency response is obtained by evaluating HD(z) for z = ej2πfTs,
HD(f) = 1D
sinπfDTssinπfTs
e-j2πfTs/D
where Ts is the input sampling period (=1/fs). Note that the phase response is linear.
For an L-th order modulator with a noise shaping function of (1-z-1)L, the requirednumber of comb filter stages is L+1. The magnitude of such a filter is,
|HD(f)| =
1
D sinπfDTssinπfTs
K
Chapter 10 – Section 10 (5/2/04) Page 10.10-38
CMOS Analog Circuit Design © P.E. Allen - 2004
Magnitude Response of a Cascaded Comb FilterK = 1,2 and 3
Fig.10.9-27
-100
-80
-60
-40
-20
0
Frequency
K = 1
K= 2
0 fb4 fsD
3 fsD
2 fsD
fsD
K = 3
|HD
(f)|
dB
Chapter 10 – Section 10 (5/2/04) Page 10.10-39
CMOS Analog Circuit Design © P.E. Allen - 2004
Implementation of a Cascaded Comb FilterImplementation:
Fig.10.9-28
-
+z-1
-
+z-1
-
+z-1
fs/D
K = L +1 Integrators
Numerator Section
z-1
+
-z-1
+
-z-1
+
-
X
Y
K = L +1 Differentiators
Denominator Section
Comments:1.) The L+1 integrators operating at the sampling frequency, fs, realize the denominator
of HD(z).
2.) The L+1 differentiators operating at the output rate of fs1 (= fs/D) realize thenumerator of HD(z).
3.) Placing the integrator delays in the feedforward path reduces the critical path fromL+1 adder delays to a single adder delay.
Chapter 10 – Section 10 (5/2/04) Page 10.10-40
CMOS Analog Circuit Design © P.E. Allen - 2004
Implementation of Digital Filters†
Digital filter structures:
Fig.10.9-29
x(n) h(0) y(n)
Input Output
z-1h(1)
z-1h(2)
z-1h(3)
z-1h(N-1)
x(n)h(0)y(n)
InputOutput
z-1h(1)
z-1h(2)
z-1h(3)
z-1h(N-1)
Direct-form structure for an FIR digital filter.
Transposed direct-form FIR filter structure.
† S.R. Norsworthy, R. Schreier, and G.C. Temes, Delta-Sigma Data Converters-Theory, Design, and Simulation, IEEE Press, NY, Chapter 13, 1997.
Chapter 10 – Section 10 (5/2/04) Page 10.10-41
CMOS Analog Circuit Design © P.E. Allen - 2004
Digital Lowpass FilterExample of a typical digital filter used in removal of the quantization noise at higherfrequencies
-110
-80
-50
-20
10
4000 Frequency (Hz)
Mag
nitu
de (
dB)
Chapter 10 – Section 10 (5/2/04) Page 10.10-42
CMOS Analog Circuit Design © P.E. Allen - 2004
Illustration of the Delta-Sigma ADC in Time and Frequency Domain
∑∆ MODULATOR
DECIMATORLOW-PASS
FILTERanalog input
fDfS
2fB
digital PCM
fB
TimeTime
Frequency FrequencyFrequency
Chapter 10 – Section 10 (5/2/04) Page 10.10-43
CMOS Analog Circuit Design © P.E. Allen - 2004
Bandpass ∆∆∆∆ΣΣΣΣ ModulatorsBlock diagram of a bandpass modulator:
Components:• Resonator - a bandpass filter of order
2N, N= 1, 2,....• Coarse quantizer (1 bit or multi-bit)The noise-shaping of the bandpass oversampled ADC has the following interestingcharacteristics:
Center frequency = fs ·(2N-1)/4
Bandwidth = BW = fs /M
Illustration of the Frequency Spectrum(N=1):
Application of the bandpass ∆Σ ADC is for systems with narrowband signals (IFfrequencies)
Fig.10.9-27A
-
+Resonator A/D
D/A
x
u
v y
Quantizer
fS
Frequency3fs4
fs4
fs
BW BW
dB
Attenuation
0Fig. 11-32
Chapter 10 – Section 10 (5/2/04) Page 10.10-44
CMOS Analog Circuit Design © P.E. Allen - 2004
A First-Order ∆∆∆∆ΣΣΣΣ Bandpass ModulatorBandpass Resonator:
V(z) = z-1 [X(z) - z-1V(z)] = z-1X(z) - z-2V(z)
V(z) (1+z-2) = z-1X(z) →V(z)X(z) =
z-1
1+z-2
Modulator:
Y(z) = Q(z) + [X(z) - Y(z)]
z-1
1+z-2 → Y(z) =
1+z-2
1+ z-1-z-2 Q(z) +
z-1
1+ z-1-z-2 X(z)
NTFQ (z) =
1+z-2
1+ z-1-z-2
The NTFQ (z) has two zeros on the jω axis.
z-1
z-1
ΣX(z) V(z)+
-
Fig. 10.9-27C
Fig.10.9-27B
-
+ z-1 +X(z)
Q(z)
Y(z)
1+z-2
Chapter 10 – Section 10 (5/2/04) Page 10.10-45
CMOS Analog Circuit Design © P.E. Allen - 2004
Resonator DesignResonators can be designed by applying a lowpass to bandpass transform as follows:
z-1ΣX(z) V(z)+
+
Fig. 10.9-27D
z-2ΣX(z) V(z)+
+
Replace z-1 by -z-2
1 - z-1z-1
1 + z-2-z-2
Result:• Simple way to design the resonator• Inherits the stability of a lowpass modulator• Center frequency located at fs/4
Chapter 10 – Section 10 (5/2/04) Page 10.10-46
CMOS Analog Circuit Design © P.E. Allen - 2004
Fourth-Order Bandpass ∆∆∆∆ΣΣΣΣ ModulatorBlock diagram:
ΣX(z) Y(z)+
-
Fig. 10.9-27E
1 + z-2z-2
0.5 Σ+
+ 1 + z-2z-2
0.5
Comments:• Designed by applying a lowpass to bandpass transform to a second-order lowpass ∆Σ
modulator• The stabilty and SNR characteristics are the same as those of a second-order lowpass
modulator• The z-domain output is given as,
Y(z) = z-4X(z) + (1+z-2)2Q(z)• The zeros are located at z = ±j which corresponds to notches at fs/4.
Chapter 10 – Section 10 (5/2/04) Page 10.10-47
CMOS Analog Circuit Design © P.E. Allen - 2004
Resonator Circuit Implementation
Block diagram of z-2/(1+z-2):
z-1 z-1ΣX(z) V(z)+
+
Fig. 10.9-27F
Fully differential switch-capacitor implementation:
Chapter 10 – Section 10 (5/2/04) Page 10.10-48
CMOS Analog Circuit Design © P.E. Allen - 2004
Power Spectral Density of the Previous Fourth-Order Bandpass ∆∆∆∆ΣΣΣΣ ModulatorSimulated result:
Chapter 10 – Section 10 (5/2/04) Page 10.10-49
CMOS Analog Circuit Design © P.E. Allen - 2004
Application of the Bandpass ∆∆∆∆ΣΣΣΣ ADC in Wireless ApplicationsComparison of the classicalversus the bandpass ∆Σ ADCapproaches in wirelessbaseband:
Assume an IF center frequencyof 10MHz and BW of 200kHz:Sampling frequency would be40MHz and the OSR would be40/0.2 = 200 which is easilywithin capability.
Typical results (0.5µm CMOS):fs = 20MHz, fIF = 15MHz,BW = 200kHz, DR = 80dB,Supply current = 5mA,Supply voltage = 2.7V
cosωLO2t
sinωLO2t
ωRF
LP Filter
LP Filter
BP Filter
ωIF
ωLO1I
Q
Fig10.9-27G
Nyquist ADC
Nyquist ADC
sinωLO2t
cosωLO2t
BP∆ΣMod.
Mixer LPF I
Q
DigitalVCO
ωRFωIF
ωLO1
Mixer LPF
DigitalAnalog
DigitalAnalogConventional Approach
BP ∆Σ Approach
Chapter 10 – Section 10 (5/2/04) Page 10.10-50
CMOS Analog Circuit Design © P.E. Allen - 2004
DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTERSPrinciplesThe principles of oversampling and noise shaping are also widely used in theimplementation of ∆Σ DACs.Simplified block diagram of a delta-sigma DAC:
Digitaldelta-sigmamodulator
Interpolat-ion filter
Analoglowpass
filterDAC
N-bit
MfN
N-bit
fN
1-bit
MfN MfN
Input
Digital Section Analog Section
Output
Fig10.9-29
Operation:1.) A digital signal with N-bits with a data rate of fN is sampled at a higher rate of MfN by
means of an interpolator.2.) Interpolation is achieved by inserting “0”s between each input word with a rate of
MfN and then filtering with a lowpass filter.
3.) The MSB of the digital filter is applied to a DAC which is applied to an analoglowpass filter to achieve the analog output.
Chapter 10 – Section 10 (5/2/04) Page 10.10-51
CMOS Analog Circuit Design © P.E. Allen - 2004
Block Diagram of a ∆∆∆∆ΣΣΣΣ DAC
AnalogOutput-
+Interpol-ation
DigitalFilter
Digital Code Conversion
0→100000000000000 =-11→011111111111111 = 1
VRef
-VRef
DigitalInput
fN
fS=MfNfS
fS
fS
AnalogLowpass
Filter
MSB
DAC
fS fS
Fig10.9-31
y(k)
Operation:1.) Interpolate a digital word at the conversion rate of the converter (f
N) up to the sample
frequency, fs.2.) The word length is then reduced to one bit with a digital sigma-delta modulator.3.) The one bit PDM signal is converted to an analog signal by switching between two
reference voltages.4.) The high-frequency quantization noise is removed with an analog lowpass filter
yielding the required analog output signal.Sources of error: • Device mismatch (causes harmonic distortion rather than DNL or INL) • Component noise • Device nonlinearities • Clock jitter sensitivity • Inband quantization error from the ∆-Σ modulator
Chapter 10 – Section 10 (5/2/04) Page 10.10-52
CMOS Analog Circuit Design © P.E. Allen - 2004
1-BitDAC for the ∆∆∆∆ΣΣΣΣ Digital-to-Analog Converter - The Analog PartThe MSB output from the digital filter is used to drive a 1-bit DAC.Possible architectures:
-VRef
φ1y(k) φ2
y(k)
VRef
φ1y(k)
C R
Analog lowpass
filter with -3dB frequency of 0.5fN
AnalogOutputR
C
φ2
φ2y(k)
Analog lowpass
filter with -3dB
frequency of 0.5fN
AnalogOutput
IRef
-IRef
Voltage-driven DAC with apassive lowpass filter stage.
Current-driven DAC with apassive lowpass filter stage.
Fig10.9-32
Chapter 10 – Section 10 (5/2/04) Page 10.10-53
CMOS Analog Circuit Design © P.E. Allen - 2004
Errors in the 1-Bit DACOffset Error:
Vref ≠ |-Vref| or Iref ≠ |-Iref| ⇒ Offset error
Influence of offsets in the voltage reference:y(k)
y(k)
v(t)Vref +∆Vref1
Vref +∆Vref2
The resulting transfer function is:
v(t) = Vref + ∆Vref1, y(k) = 1or
v(t) = -Vref + ∆Vref2, y(k) = -1
∴ v(t) =
Vref + ∆Vref1 - ∆vref2
2 ·y(k) + ∆Vref1 + ∆Vref2
2
This results in a gain or an offset error, but the output is still linear.
Chapter 10 – Section 10 (5/2/04) Page 10.10-54
CMOS Analog Circuit Design © P.E. Allen - 2004
Errors in the 1-Bit DAC - ContinuedSwitching Time Error:
Let, v(k) = VREF, y(k) = 1
and y(k-1) = 1v(k) = (1-α)VREF, y(k) = 1 and y(k-1) = -1
v(k) = -VREF, y(k) = -1 and y(k-1) = -1
v(k) = -(1-ß)VREF, y(k) = -1 and y(k-1) = 1
Therefore, the transfer function becomes,v(k) = [(ß-α) + (α+ß)y(k-1) + (4-α-ß)y(k) + (α-ß)y(k)·y(k-1)] (VREF/4)
(Note: The φ2 switch in the voltage DAC removes this error by resetting the voltage atevery clock.)
Time
-VREF
Typical Waveform, v(t)
VREF
Time
-VREF
VREF
Average of the v(k) waveform over one clock cycle
(10.11-1)
(1-α)VREF
-(1-β)VREF
Chapter 10 – Section 10 (5/2/04) Page 10.10-55
CMOS Analog Circuit Design © P.E. Allen - 2004
Switched-Capacitor DAC and FilterTypically, the DAC and the first stage of the lowpass filter are implemented usingswitched-capacitor techniques.
-VRef
φ1y(k)
VRef
φ1y(k)
φ2+-
φ2
φ1
C1
C2
R
To analoglowpass
filter
Fig10.9-34
It is necessary to follow the switched-capacitor filter by a continuous time lowpass filterto provide the necessary attenuation of the quantization noise.
Chapter 10 – Section 10 (5/2/04) Page 10.10-56
CMOS Analog Circuit Design © P.E. Allen - 2004
Frequency Viewpoint of the ∆∆∆∆ΣΣΣΣ DACFrequency spectra at different points of the delta-sigma ADC:
Frequency0Interpolationfilter output
Delta-sigmamodulator
output
Lowpassfilter
output
Input
Magnitude
Quantization noise after filtering
-0.5fN 0.5fN fN (M-1)fN MfN
FrequencyMfN0-0.5fN 0.5fN
FrequencyMfN0-0.5fN 0.5fN
FrequencyMfN0-0.5fN 0.5fNFig10.9-33
Chapter 10 – Section 10 (5/2/04) Page 10.10-57
CMOS Analog Circuit Design © P.E. Allen - 2004
Comparision of the ∆∆∆∆ΣΣΣΣ ADC and ∆∆∆∆ΣΣΣΣ DACBoth the ∆Σ ADC and ∆Σ DAC have many of the same properties• Loops with identical topologies have the same stability conditions• Loops with identical topologies have the same amount of quantization noise for a given
oversampling ratio• Higher order loops give better noise shaping and more dynamic range• Multiple bit DACs are also used in ∆Σ DACs as well as ∆Σ ADCs
Chapter 10 – Section 11 (5/2/04) Page 10.11-1
CMOS Analog Circuit Design © P.E. Allen - 2004
SECTION 10.11 - SUMMARYComparison of the Various Types of ADCs
A/D Converter Type MaximumPractical Number
of Bits (±1)
Speed(Expressed in termsof T a clock period)
Area Dependenceon the number ofbits, N, or otherADC parameters
Dual Slope 12-14 bits 2(2NT) IndependentSuccessive Approximationwith self-correction 12-15 bits NT ∝ N
1-Bit Pipeline 10 bits T (After NT delay ) ∝ N
Algorithmic 12 bits NT Independent
Flash 6 bits T ∝ 2N
Two-step, flash 10-12 bits 2T ∝ 2N/2
Mulitple-bit, M-pipe 12-14 bits MT ∝ 2N/M
∆-Σ Oversampled (1-bit, Lloops and M= oversamplingratio = f clock/2fb) 15-17 bits MT ∝ L
Chapter 10 – Section 11 (5/2/04) Page 10.11-2
CMOS Analog Circuit Design © P.E. Allen - 2004
Comparison of Recent ADCsResolution versus conversion rate:
5
10
15
20
25
Out
put w
ord
leng
th
Conversion rate, (samples/sec.)1 102 104 106 108 1010
Figure 10.10-1
FlashPipelinedAlgorithmic
Dual-slopeDelta-sigma
Successive approximation
Folding/InterpolatingBandpass delta-sigma
Chapter 10 – Section 11 (5/2/04) Page 10.11-3
CMOS Analog Circuit Design © P.E. Allen - 2004
Comparison of Recent ADCs - ContinuedPower dissipation versus conversion rate:
Figure 10.10-2
0.01
0.1
1
10
100
1000
1 100 10 4 10 6 10 8 10 10
Pow
er D
issi
patio
n (m
W)
Conversion Rate (Samples/second)
FlashPipelined
Delta-sigmaSuccessive approximation
Folding/InterpolatingBandpass delta-sigma
Chapter 10 – Section 11 (5/2/04) Page 10.11-4
CMOS Analog Circuit Design © P.E. Allen - 2004
References for Previous Figures[1] A 12-b, 60-MSample/s Cascaded Folding and Interpolating ADC. Vorenkamp, P., IEEE J-SC, vol. 32, no. 12, Dec 97 1876-
1886[2] A 15-b, 5-Msample/s Low-Spurious CMOS ADC. Kwak, S. -U., IEEE J-SC, vol. 32, no. 12, Dec 97 1866-1875[3] Error Suppressing Encode Logic of FCDL in a 6-b Flash A/D Converter. Ono, K., IEEE J-SC, vol. 32, no.9, Sep 97 1460-
1464[4] A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25 MHz Signal Bandwidth and 89 dB SNR. Brooks, T. L., IEEE J-
SC, vol.32, no.12, Dec 97 1896-1906[5] A 10-b, 100 MS/s CMOS A/D Converter. Kwang Young Kim, IEEE J-SC, vol. 32, no. 3, Mar 97 302-311[6] A 1.95-V, 0.34-mW, 12-b Sigma-Delta Modulator Stabilized by Local Feedback Loops. Au, S., IEEE J-SC, vol. 32, no. 3,
Mar 97 321-328[7] A 250-mW, 8-b, 52Msamples/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers. Nagaraj, K., IEEE J-
SC, vol. 32, no. 3, Mar 97 312-320[8] A DSP-Based Hearing Instrument IC. Neuteboom, H., IEEE J-SC, vol. 32, no. 11, Nov 97 1790-1806[9] An Embedded 240-mW 10-b 50MS/s CMOS ADC in 1-mm2. Bult, K., IEEE J-SC, vol. 32, no. 12, Dec 97 1887-1895[10] Low-Voltage Double-Sampled Σ∆ Converters. Senderowicz, D., IEEE J-SC, vol. 32, no.12, Dec 97 1907-1919[11] Quadrature Bandpass ∆Σ Modulation for Digital Radio. Jantzi, S. A., IEEE J-SC, vol. 32, no. 12, Dec 97 1935-1950[12] A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20 MHz. Ong, A. K., IEEE J-SC, vol. 32, no. 12, Dec 97
1920-1934[13] A 240-Mbps, 1-W CMOS EPRML Read-Channel LSI Chip Using an Interleaved Subranging Pipeline A/D Converter.
Matsuura, T., IEEE J-SC, vol. 33, no. 11, Nov 98 1840-1850[14] A 13-Bit, 1.4 MS/s Sigma-Delta Modulator for RF Baseband Channel Applications. Feldman, A. R., IEEE J-SC, vol. 33,
no. 10, Oct 98 1462-1469[15] Design and Implementation of an Untrimmed MOSFET-Only 10-Bit A/D Converter with –79-dB THD. Hammerschmied,
C. M., IEEE J-SC, vol. 33, no. 8, Aug 98 1148-1157[16] A 15-b Resolution 2-MHz Nyquist Rate ∆Σ ADC in a 1-µm CMOS Technology. Marques, A. M., IEEE J-SC, vol. 33, no.
7, Jul 98 1065-1075[17] A 950-MHz IF Second-Order Integrated LC Bandpass Delta-Sigma Modulator. Gao, W., IEEE J-SC, vol. 33, no. 5, May
98 723-732 [18] A 200-MSPS 6-Bit Flash ADC in 0.6µm CMOS. Dalton, D., IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing, vol. 45, no. 11, Nov 98 1433-1444
Chapter 10 – Section 11 (5/2/04) Page 10.11-5
CMOS Analog Circuit Design © P.E. Allen - 2004
References - Continued [19] A 5-V Single-Chip Delta-Sigma Audio A/D Converter with 111 dB Dynamic Range. Fujimori, I., IEEE J-SC, vol. 32, no.
3, Mar 97 329-336[20] A 256 x 256 CMOS Imaging Array with Wide Dynamic Range Pixels and Column-Parallel Digital Output. Decker, S.,
IEEE J-SC, vol. 33, no.12, Dec 98 2081-2091[21] A 400 Msample/s, 6-b CMOS Folding and Interpolating ADC. Flynn, M., IEEE J-SC, vol. 33, no.12, Dec 98 1932-1938[22] An Analog Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters. Dyer, K. C., IEEE J-SC,
vol. 33, no.12, Dec 98 1912-1919[23] A CMOS 6-b, 400-Msample/s ADC with Error Correction. Tsukamoto, S., IEEE J-SC, vol. 33, no.12, Dec 98 1939-1947[24] A Continuously Calibrated 12-b, 10-MS/s, 3.3-V ADC. Ingino, J. M., IEEE J-SC, vol. 33, no.12, Dec 98 1920-1931[25] A Delta-Sigma PLL for 14b, 50 ksamples/s Frequency-to-Digital Conversion of a 10 MHz FM Signal. Galton, I., IEEE J-
SC, vol. 33, no.12, Dec 98 2042-2053[26] A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters. Fu, D., IEEE J-SC, vol. 33,
no.12, Dec 98 1904-1911[27] An IEEE 1451 Standard Transducer Interface Chip with 12-b ADC, Two 12-b DAC’s, 10-kB Flash EEPROM, and 8-b
Microcontroller. Cummins, T., IEEE J-SC, vol. 33, no.12, Dec 98 2112-2120[28] A Single-Ended 12-bit 20 Msample/s Self-Calibrating Pipeline A/D Converter. Opris, I. E., IEEE J-SC, vol. 33, no.12, Dec
98 1898-1903[29] A 900-mV Low-Power ∆Σ A/D Converter with 77-dB Dynamic Range. Peluso, V., IEEE J-SC, vol. 33, no.12, Dec 98
1887-1897[30] Third-Order ∆Σ Modulator Using Second-Order Noise-Shaping Dynamic Element Matching. Yasuda, A., IEEE J-SC, vol.
33, no.12, Dec 98 1879-1886[31] R, G, B Acquisition Interface with Line-Locked Clock Generator for Flat Panel Display. Marie, H., IEEE J-SC, vol. 33,
no.7, Jul 98 1009-1013[32] A 25 MS/s 8-b - 10 MS/s 10-b CMOS Data Acquisition IC for Digital Storage Oscilloscopes. Kusayanagi, N., IEEE J-SC,
vol. 33, no.3, Mar 98 492-496[33] A Multimode Digital Detector Readout for Solid-State Medical Imaging Detectors. Boles, C. D., IEEE J-SC, vol. 33, no.5,
May 98 733-742[34] CMOS Charge-Transfer Preamplifier for Offset-Fluctuation Cancellation in Low Power A/D Converters. Kotani, K., IEEE J-
SC, vol. 33, no.5, May 98 762-769[35] Design Techniques for a Low-Power Low-Cost CMOS A/D Converter. Chang, Dong-Young, IEEE J-SC, vol. 33, no.8,
Aug 98 1244-1248
Chapter 10 – Section 11 (5/2/04) Page 10.11-1
CMOS Analog Circuit Design © P.E. Allen - 2004
CONCLUSION• Key aspects:
1.) Square law relationship:
iD = K’W2L (vGS - VT)2
2.) Small-signal transconductance formula:
gm = 2K’WID
L
3.) Small-signal simplification:gm ≈ 10gmbs ≈ 100gds
4.) Saturation relationship:
VDS(sat) = 2ID
K’(W/L)
• Remember to think and understand the problem before using the simulator.• Any questions concerning the course can be e-mailed to [email protected]• Other analog resources can be found at www.aicdesign.org