CMOS Analog Integrated Circuits: Models, Analysis, & Design

CMOS Analog Integrated Circuits: Models, Analysis, & Design

EE448

MOS Circuit Level Models

Fall 2001

Dr. John Choma, Jr.Professor of Electrical Engineering

University of Southern CaliforniaDepartment of Electrical Engineering-Electrophysics

University Park; Mail Code: 0271Los Angeles, California 90089-0271

213-740-4692 [OFF]626-915-7503 [HOME]626-915-0944 [FAX]

johnc@almaak.usc.edu (E-MAIL)

Lecture Overview Lecture Overview

2

•Static ModelCutoff RegionOhmic (Triode) Region ModelSaturation Region ModelSubthreshold Model

•Short Channel Effects In SaturationChannel Length ModulationSubstrate/Bulk PhenomenaMobility DegradationCarrier Velocity Saturation

•Small Signal Model In SaturationForward TransconductanceBulk TransconductanceCapacitances

•Sample Circuit Analysis (Inverter)GainBandwidth

N–Channel MOSFET N–Channel MOSFET

3

I s = I d + I g + I b

I g ≈ 0

I b ≈ 0, for Vbs < 0

I s ≈ I d

Vds = Vgs – Vgd

Silicon Dioxide

B

L

Tox

S DG

N+

Sour

ce N+

Drain

LdLd

W

Xd

P–Type Substrate(Concentration = ND cm-3 )

Id

D

G

S

Vds

+

−

B

Vbs

+

−

Vgs

+

−

Vgd+

−

Ig

Is

Ib

P–Channel MOSFET P–Channel MOSFET

4

I s = I d + I g + I b

I g ≈ 0

I b ≈ 0, for Vsb < 0

I s ≈ I d

Vsd = Vsg – Vd g

D

G

S

Vsd

−

+

B

Vsb

−

+

Vdg

−

+Ig

Is

Ib

Id

Vsg

−

+

Silicon Dioxide

B

L

Tox

S DG

P+

Sour

ce P+ D

rain

LdLd

W

Xd

N–Type Substrate(Concentration = ND cm-3 )

Characteristic Curves: Cutoff And Ohmic Regimes Characteristic Curves: Cutoff And Ohmic Regimes

Cutoff Regime:

Threshold Voltage, Function Of Bulk–Source Voltage

Ohmic Regime:

(Hundreds Of µmhos/Volt)

CommentsW/L Is Gate–Channel Aspect Ratio, A Designable Parameter

Temperature Effects (Holes And Electrons):

Resistance For Small Drain–Source Voltage:

5

Vgs < Vhn

I d = 0

Vhn

I d = K n W L

Vds Vgs – Vhn – Vds

2

K n = µn Cox = µn εox

Tox

Vds = Vgs – Vgd < Vgs – Vhn Implies Vgd > Vhn

µ(T) ≈ µ(To)ToT

3 / 2

Vgs – Vhn – Vds

Vgs – Vhn –Vds

2

Vgs ≥ Vhn and Vds < Vgs – Vhn

∂ Id∂Vds

2 1R ds

= K nW L

Vgs – Vhn – Vds = Id

Vds

IdVds

≈

Characteristic Curves: Saturated Regime Characteristic Curves: Saturated Regime

Saturation Regime:

CommentsSquare Law Voltage–Controlled Current SourceDrain Current Shows Negative Temperature CoefficientBecause Of Its Proportionality To MobilityDifferential Current Of Two Matched Devices Is Linear WithDifferential Gate–Source Voltage , Provided Common Mode Gate–Source Voltage Is A Constant

6

Vgs ≥ Vhn & Vds ≥ Vgs – Vhn

I d = K n 2

W L

Vgs – Vhn 2

Vdss

2

Vgs – Vhn → Drain Saturation Voltage

I dss = K n2

W L Vdss

2 → Drain Saturation Current

I d1 – I d2 = K n 2

W L

Vgs1 – Vhn 2 – Vgs2 – Vhn

2

I d1 – I d2 = K n W L

Vgs1 + Vgs2

2 – Vhn Vgs1 – Vgs2

I d1 – I d2 = K n W L

VCM – Vhn VDM

VDMVCM

Simple Differential Pair Simple Differential Pair

6a

Vgs1 = VCM + VDM

2

Vgs2 = VCM –

VDM 2

Vgs1 + Vgs2 = 2 VCM

c

R

c

Id2Id1

M1 M2

R

+VDDc

Vo +–

+

–

VDM2

–

+

VDM2

+

–VCM

c Vgs1 – Vgs2 = VDM

I d1 – I d2 = K n W L

VCM – Vhn VDM

Vo = R I d1 – I d2 = K n R W L

VCM – Vhn VDM

Inputs

Response

Note Differential Output Current And Voltage Are Linear With RespectTo Differential Input Voltage Without Invoking Small Signal Approximation

Characteristic Curves: Subthreshold Regime Characteristic Curves: Subthreshold Regime

7

Subthreshold Regime:

CommentsBipolar Type I–V Action Indigenous To Subthreshold Regime

Subthreshold Operation Corresponds To Gate–Channel InterfacePotentials Lying Between One And Two Fermi PotentialsUseful Only For Low Speed, Low Power Applications

Vgs < Vhn + 2 n VT & Vds 3 VT

VT = k T q = 26 mV @ 27 8C

1.2 < n < 2.0

I d = 2 K nWL

n VTε

2

e ( Vgs – Vhn ) / n VT

Sample Simplified MOS Static Characteristics Sample Simplified MOS Static Characteristics

Drain-Source Voltage (volts)

0

100

200

300

400

500

600

700

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8

Gate-Source Voltage = 2 volts

3 volts

4 volts

5 volts

DrainSaturation

Current

SaturationRegime

OhmicRegime

Drain Current (microamperes)

K n W

L = 80 µmho/volt

Vhn = 1.2 volts

8

Depletion

Zero Current

Voltage AcrossOxide

InterfacePotential

Vds

P–Type Substrate

DEPLETION LAYER, V > 0ds

SiO 2 Id

S D

Gc

− +Vgs

− +

− − − − − − − − − − − −−

N+

DrainN

+ So

urce

DEPLETION LAYER, V = 0ds

B

Vbs− +

Fixed Immobile Charges

Vds ≥ 0

0 < Vgs < Vhn

Vbs ≤ 0

Vgs = Vox + Vy

Vox →

Vy →

Cutoff RegimeCutoff Regime

9

Channel Inversion: Ohmic Regime Channel Inversion: Ohmic Regime

10

Vgs > Vhn

Vds = 0

Vgs > Vhn

0 ≤ Vds ≤ Vgs – Vhn

Vgd > Vhn

N+ Drain

P–Type Substrate

N+ So

urce

N+ Drain

P–Type Substrate

N+ So

urce

L

L' DL

DVds

Metal or Polysilicon

Silicon Dioxide

Inversion Layer

Depletion

DSG

DSG

Vdss +− +−

Channel Inversion: Saturation Regime Channel Inversion: Saturation Regime

11

Vgs > Vhn

0 ≤ Vds = Vgs – Vhn

Vgd ≤ Vhn

Vgs > Vhn

0 ≤ Vds > Vgs – Vhn

Vgd < Vhn

N+ Drain

P–Type Substrate

N+ So

urce

N+ Drain

P–Type Substrate

N+ So

urce

L

L' ∆L

∆Vds

Metal or Polysilicon

Silicon Dioxide

Inversion Layer

Depletion

DSG

DSG

Vdss +− +−

Channel Length Modulation Channel Length Modulation

Modified Saturation Regime Current

12

I d | Vds > Vdss

= I dssL

L – ∆ L = K n

2WL Vgs – Vhn

21 + Vds – Vdss

V λ

Vλ = L 2 q NAεs

Vds – Vdss + Vj

Vdss = Vgs – Vhn

Vj = k T

q N D N A

N iB 2

ln (Typically Under 20 Volts And As Small As 1/3 Volt For DeepSubmicron MOSFETs)

Channel Modulation Voltage

N+ DrainN+ So

urce

L' DL

∆ Vds

DSG

Vdss +− +−

Channel Length Modulation Parameters Channel Length Modulation Parameters

13

Parameters→ Average Substrate Impurity Concentration→ Dielectric Constant Of Silicon (1.05 pF/cm)→ Electronic Charge Magnitude→ Channel Length Modulation Voltage→ Built In Substrate–Drain/Source Junction Potential

NoteLarge Channel Length Reduces Channel ModulationSmall Substrate Concentration Increases Channel Modulation

N Aesq

VlVj

Modified Saturation Regime Current

I d | Vds > Vdss

= I dssL

L – ∆ L = K n2

WL Vgs – Vhn

2 1 + Vds – VdssVλ

Vλ = L 2 q NAεs

Vds – Vdss + Vj

Vdss = Vgs – Vhn

Vj = k T

q N D

N A

N iB 2

ln

Substrate/Bulk Phenomena Substrate/Bulk Phenomena

Effect On Threshold Voltage

Parameters→ Fermi Potential; Renders Channel Surface Intrinsic→ Intrinsic Carrier Concentration In Substrate→ Dielectric Constant Of Silicon Dioxide (345 fF/cm)

NoteSmall Oxide Thickness Reduces Threshold ModulationSmall Substrate Concentration Reduces Threshold Modulation

VFN iB

14

(High Hundreds Of µVolts)

(Few Tenths Of Volts)

εox

I d = K n2

WL Vgs – Vhnc

2 1 + Vds – VdssVλ

Vθ = q NA εs

Cox2

= q N A εsToxεox

2

VF = VT ln N A

N iB

Vh = Vho + 2 Vθ VF – VT 1 – Vbs2 VF – VT

– 1

Threshold Voltage Modulation Threshold Voltage Modulation

Threshold Correction (volts)

Bulk–Source Voltage, Vbs (volts)15

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

-6 -5 -4 -3 -2 -1 0

Oxide Thickness = 1,500 A

750 A

100 A50 A

N iB = 10 10 cm –3 ; N A = (10) 14 cm –3

Mobility Degradation Due To Vertical Field Mobility Degradation Due To Vertical Field

16

Electric Field ProblemsThin Oxide Layers Conduce Large Gate -To- Channel FieldsFor Even Small -To- Moderate Gate–Source VoltagesThese Enhanced Fields Impart Increasing Energies To Carriers,Thereby Causing More Carrier Collisions And Degraded Mobilities

Mobility:

Parameters→ Effective Carrier Mobility In Channel

→ Vertical Field Degradation Voltage Parameter

Crude One Dimension Approximation To Two Dimensional Problemin MKS Units Yields In Volts

µneff

Tox VE

VE

µneff ≈µn

1 + Vgs – Vhnc

VE

VE ≈ (500)(106 )T ox (Low Hundreds Of Volts)

Impact Of Mobility Degradation Impact Of Mobility Degradation

17

Static Drain Current

Other EffectsReduced Bandwidth And Increased Carrier Transit TimeSmaller Current For Given Gate–Source BiasReduced Forward Transconductance

K n = µ n C ox → K neff = µ neff C ox

I d = K n2

WL

Vgs – Vhnc2

1 + Vds – Vdss

Vλ

1 + Vgs – Vhnc

VE

Mobility Degradation Due To Lateral Field Mobility Degradation Due To Lateral Field

18

Electric Field ProblemsShort Channels Conduce Large Drain -To- Source FieldsFor Even Small -To- Moderate Drain–Source Voltages

These Enhanced Fields Impart Increasing Energies To Carriers,Thereby Causing More Carrier Collisions And Degraded MobilitiesAt Very Large Horizontal Fields, Carrier Velocities UltimatelySaturate To A Value Of , Which Is About 0.1 µm/pSECSaturation Occurs When Horizontal Field, ,Equals Or Exceeds ACritical Value, , Which Is About 5 V/µm

Mobility And Field

vsatE h

Ec

µne ≈µn

1 + E hE c

= vsat

E c + E h

vsat = µ n E c

v = µne E h ≈µn E h

1 + E hE c

E h ≈Vgs – Vhn

L

Velocity – Mobility – Field RelationshipsVelocity – Mobility – Field Relationships

18a

Lateral Electric Field (V/µm)

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

0 5 10 15 20 25 30 35 40 45 50

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1Carrier Velocity (µm/psec) Normalized Carrier Mobility

Carrier Velocity

Normalized Mobility

Mobility And Lateral Field Mobility And Lateral Field

19

Mobility And Field

Electric Field ProblemsCrude Approximation For Horizontal Field, Free Carriers Exist Only Over Channel Where Voltage WithRespect To The Source Is At Most Channel Length, L, Should Be Effective Channel Length, L',But This Shrinkage Is Already Accounted For By Channel LengthModulation Voltage Parameter,

Is About 1.75 Volts For L = 0.35 µm

E h

Vλ

E h ≈Vgs – Vhnc

L = VdssL

µne ≈µn

1 + E hE c

≈µn

1 + Vgs – Vhnc

L E c

= µn

1 + VdssL E c

Vdss = Vgs – Vhnc

L E c

Volt–Ampere Impact Of High Lateral Field Volt–Ampere Impact Of High Lateral Field

Static Drain Current

Very High Fields

CommentsDrain Current Scales Approximately With W, As OpposedTo W/LDrain Current Almost Linear W/R To Gate–Source Voltage

20

K n = µ n C ox → K neff = µ neff C ox

I d = K n2

WL

(Vgs – V )hnc2 1 +

Vds – VdssVλ

1 + Vgs – Vhnc

L E c

Vgs – Vhnc >> L E c

I d ≈W Cox vsat

2 Vgs – Vhnc 1 + Vds – VdssVl

MOS Large Signal Model MOS Large Signal Model

→ Gate-Drain Capacitance

→ Gate-Source Capacitance

→ Drain-Bulk Capacitance

→ Source-Bulk Capacitance

→ Drain Overlap Capacitance

→ Source Overlap Capacitance

DBD → Bulk-Drain Diode

DBS → Bulk-Source Diode21

Cgd

Cgs

Cdb

Csb

Cold

Cols

c c

c

c

c

c

c

DBD

id

B

S

D

G

Id

rdb

DBS

c

Csb

cc cc

Cgd

Cols

Cgs

Cold

Cdb

rbbrsb

rdd

rss → Drain Ohmic Resistancerdd

→ Source Ohmic Resistancerss

→ Bulk Ohmic Resistancerbb

→ Bulk Spreading Resistancersb

→ Bulk Spreading Resistancerdb

Static Drain Current

Device Capacitances In Saturation Device Capacitances In Saturation

22

c c

c

c

c

c

c

DBD

id

B

S

D

G

Id

rdb

DBS

c

Csb

cc cc

Cgd

Cols

Cgs

Cold

Cdb

rbbrsb

rdd

rss

→ Drain-Bulk Junction Area

→ Source-Bulk Junction Area

→ Zero Bias Depletion Capacitance Density

Ad

As

Cjo

C gd + C old ≈ C old = W L d C ox

C gs = W L C ox 2

3 +

L d L

C db = Ad C jo

1 – Vbd

Vj

C sb = As + W L C jo

1 – Vbs

Vj

C ols = W L d C ox

→ Large (Hundreds Of fF)Cdb

→ Large (Hundreds Of fF)Csb

→ Moderate (High Tens Of fF)Cgs

Cgd , Cold , Cols → Small (Tens Of fF)

Approximate (Long Channel) Small Signal Model Approximate (Long Channel) Small Signal Model

23

cc

cc

c

B

D

G

gmf vga go

vba +−vga

Cold

+ −

cc

Cgdc

c

gmb vba

Cgs

Cdb

c

Csb

Colsc

S

AssumptionsAll Series Ohmic Resistances Are NegligibleTransistor Operates In Saturation Regime"Long Channel" Approximation Invoked For Static Drain CurrentModel To Be Used As A Precursor To Computer–Based Studies

g mf

2 ∂I d

∂Vgs | Q

≈ 2 K nWL

I dQ

g mb

2 ∂I d

∂Vbs | Q

= λb g mf

λb = Vθ/ 2 2 VF – VT – VbsQ

g o2 ∂I d

∂Vds | Q

≈I dQ

Vλ + Vds – Vdss

Short Channel Small Signal Model Short Channel Small Signal Model

24

Drain Current:

Intermediate Parameters:

ForwardTransconductance:

Bulk Transconductance:

Output Conductance:

I d = K n2

WL

Vgs – Vhnc2 1 +

Vds – VdssVλ

1 + Vgs – Vhnc

L E c

f λ = Vds – VdssVλ

f c = Vdss

L E c

g mf = 2 K n W

L

I dQ

g mfs = g mf1 + f λ1 + f c

1 – Vdss /2 Vλ1 + f λ

– f c /21 + f c

g mbs = λb g mfs

g o = I dQ

Vλ + Vds – Vdss

λb = Vθ/ 2 2 VF – VT – VbsQ

Hypothetical Device Hypothetical Device

25

Physical ParametersN A = 5 (10) 14 cm –3

N D = 5 (10) 20 cm –3

N iB = (10) 10 cm –3

εs= 1.05 pF/cm

εox= 345 fF/cm

µn = 400 cm 2 / volt-secE c = 4 volts / µm

Device ParametersTox = 50 Angstroms

L = 0.35 µm

Vhn = 0.65 volts

T = 300 8KW / L = 5

Circuit ParametersVds = 2 voltsVgs = 1.2 voltsVbs = –3 volts

Static Performance Static Performance

Peripheral Calculations

26

VF = 280.0 mV (Fermi Potential)Vj = 917.4 mV (Junction Potential)Vu = 176.4 µV (Body Effect Potential)Vhnc = 685.2 mV (Compensated Threshold) → ∆Vhn = 35.2 mVVdss = 514.8 mV (Drain Saturation Voltage)Vλ = 669.7 mV (Channel Length Voltage)L E c = 1.4 volts (Lateral Field Voltage)Kn = 276.0 µmho / volt (Transconductance Parameter)f λ = 2.218 (Channel Length Parameter)f c = 0.368 (Lateral Field Parameter)

I d = 182.9 µA (Long Channel Drain Current)

I d = 430.2 µA (Short Channel Drain Current)

Static Drain Current

Note Short Channel -To- Long Channel Ratio of 2.35; Ratio IsGenerally Between 1.5 And 3.0

Small Signal Parameters Small Signal Parameters

27

Forward Transconductance

Note Short Channel -To- Long Channel Ratio of 1.14; Ratio IsGenerally Between 0.5 And 2.0

Bulk Transconductance

Note Bulk Transconductance Is About 200 Times SmallerThan Forward Transconductance

Drain–Source Conductance

Corresponds To Shunt Output Resistance Of About 5 KΩMandates Conductance Enhancement Strategies When

Designing High Performance Transconductors

gmf = 1.09 mmho (Ignoring Short Channel Effects)gmf = 1.25 mmho (Incorporating Short Channel Effects)

(10) –3λb = 5.0 2 (Bulk Parameter)

gmb = 6.25 µmho (Incorporating Short Channel Effects)

go = 199.7 µmho (Incorporating Short Channel Effects)

Device Unity Gain Frequency Device Unity Gain Frequency

CommentsUnity Gain Frequency Is Good Device Figure Of Merit;Crude Circuit Performance Figure Of MeritResult Assumes ω T Cgd << gmf

AC Short Circuit

28

ioutiin

= g mf – s Cgd + Cold

s C gs + Cols + Cgd + Cold

ω T ≈g mf

Cgs + Cols + C gd + Cold≈

µn Vgs – Vhn

L 2 23

+ 3 L d

L

c

c

c

BS

D

G

gmf v1 gmb v2go

v2 +−v1+ −

c

c

Vdd

c

Ibias Cbig

c

iouti in i in

c

iout

Cgd Cold+

Cgs Cols+

Common Source Inverter Common Source Inverter

29

VDDML

MD

LC

Vo

Vs

VGG

MD

LC

Vos

RLeff

Schematic Diagram AC Schematic Diagram

RLeff

c

+

+

–

–Vs

+

–

c

c

cc

c

c

Inverter Load Resistance Calculations Inverter Load Resistance Calculations

30

ML

IxVx

rol

rbblrssl

rddl

vba

c

c

+

–

g mfl vga

vga+ –

IxVx

+

–

g mbl vba

+–

c

c c c

vga = vba = – Vx + r ssl I x

Vx = r ssl + r ddl I x + r ol I x + g mfl vga + g mbl vba

R Leff

2 VxI x

= r ssl + r ddl + r ol

1 + 1 + λbl g mfl r ol≈

11 + λbl g mfl

Inverter Gain Calculations Inverter Gain Calculations

31

gmbd vbarod

rbbd

vba +–vga

rssd

rddd

+ –gmfd vga

LC

Vos

Vs

+

–

RLeff

R outR '

Ignore For Low

Frequenciesc

cc

cc

cMD

LC

Vos

RLeff

c

Vs

+

–

c

c

Av = VosVs

= –gmfd R Leff

1 + 1 + λbd gmfd r ssd + R Leff + r ddd + r ssd

r od

≈ – gmfd R Leff ≈ –gmfd

1 + λbl gmfl

Av ≈ – 11 + λbl

W d / L W l / L

Inverter Bandwidth Calculations Inverter Bandwidth Calculations

32

IxVx

+

–

gmbd vbarod

rbbd

vba +–vga

rssd

rddd

+ –gmfd vga

R '

c cc

c

R / = VxI x

= r ddd + r ssd + 1 + 1 + λbl g mfd r ssd r od

B 3dB ≈1

R Leff CL≈

1 + λbl g mflCL

B 3dB = 1R out CL

= 1R / | R Leff C L

≈1

R Leff CL

GBP

2

Av B 3dB = g mfdC L