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Cmos Design Modelling

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VLSI, CMOS, CELL DESIGN, MODELLING
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Cours en ligne CMOS Design MOS Device n MOS Behavior n Three MOS Options n MOS as a Switch MOS Modeling n History n What is a MOS model? n MOS Model 1 n MOS Model 3 n BSIM4 n Dynamic Behavior n Temperature Effect n Conclusion Inverter n Inverter Behavior n Inverter Power Consumption n Ring Oscillator n Conclusion Basic Design Rules n Lambda Based Design n MOS Design Rules n Interconnect Design Rules n Conclusion Analog Cell Design n Introduction n MOS Diod n Voltage Reference n Current Mirror n Amplifier n Converters n Sample and Hold Circuit n Frequency Converter Field Programmable Gate Array n Introduction Page 1 of 2 CMOS Design Menu 3/19/2007 http://www.lesia.insa-toulouse.fr/~bendhia/Cours/CMOS/menu_cmos.html
Transcript
Page 1: Cmos Design Modelling

Cours en ligne

CMOS Design

MOS Device

n MOS Behavior

n Three MOS Options

n MOS as a Switch

MOS Modeling

n History

n What is a MOS model?

n MOS Model 1

n MOS Model 3

n BSIM4

n Dynamic Behavior

n Temperature Effect

n Conclusion

Inverter

n Inverter Behavior

n Inverter Power Consumption

n Ring Oscillator

n Conclusion

Basic Design Rules

n Lambda Based Design

n MOS Design Rules

n Interconnect Design Rules

n Conclusion

Analog Cell Design

n Introduction

n MOS Diod

n Voltage Reference

n Current Mirror

n Amplifier

n Converters

n Sample and Hold Circuit

n Frequency Converter

Field Programmable Gate Array

n Introduction

Page 1 of 2CMOS Design Menu

3/19/2007http://www.lesia.insa-toulouse.fr/~bendhia/Cours/CMOS/menu_cmos.html

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n Configurable Logic Circuits

n Programmable Logic Block

n Interconnection between Blocks

n Conclusion

Memories

n The World of Memories

n Static RAM Memory

n A 64 Bit Static RAM

n Dynamic RAM

n ROM Memory

n EEPROM Memory

n Flash Memories

n Classification

n Conclusion

I/O Interface Design

n I/O Interface

n Schmidt Trigger

n Pad Ring Structure

Execises

Page 2 of 2CMOS Design Menu

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MOS Behavior

N-channel MOS behavior

The expected behavior of the n-channel MOS device is summarized below. The 0 on the gateshould leave the drain floating. The 1 on the gate should link the drain to the source, via aresistive path.

P-channel MOS behavior

The expected behavior of the p-channel MOS device is summarized below. The 0 on the gateshould link the drain to the source, via a resistive path. The 1 on the gate should leave the drainfloating. In other words, the p-channel transistor simulation features the same functions as then-channel device, but with opposite voltage control of the gate.

This figure shows the reduction of the MOS Roff with the technology scale down andconsequently the static current in stand by regime increases dramatically. For a block including1 million transistors the current could reach almost 1A in 0.07µm technology that isenaffordable for most of CMOS applications. This kind of problems was the stargins points of

CMOS Design > MOS Device

l ROFF close from 1M (drain floating)

l RON close from 1K (drain linked to source)

l ROFF close from 1M (drain floating)

l RON close from 1K (drain linked to source)

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Page 4: Cmos Design Modelling

new concepts for advanced technologies as the creation of diferenct MOS transistors with betterproperties.

l ROFF decreases with technology => static leakage current increases

l For a block of 1M transistors, the stand by current may reach 200mA in 0.07µml Need for new MOS with better properties for many embedded applications (GSM…)

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Three MOS Options

A new kind of MOS device has been introduced in deep submicron technologies, starting the0.18µm CMOS process generation. the new MOS, called "low leakage" or "High-Vt" MOS deviceis available as well as the normal on, recalled "high-speed MOS".

For I/Os operating at high voltage, specific MOS devices called "High voltage MOS" are used. Wecannot use high-speed or low leakage devices as their oxide is too small. A 2.5V voltage woulddamage the gate oxide of a high-speed MOS in 0.12µm technology. The high voltage MOS isbuilt using a thick oxide, two to three times thicker than the low voltage MOS, to handle highvoltages as required by the I/O interfaces.

CMOS Design > MOS Device

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New kind of MOS introduced in deep submicron technology (0.18µm)

l High Speed: for critical path in term of speedl Low Leakage: for embedded application (less consumption)l High Voltage: for I/O which need higher voltage (oxide thicker than the others MOS)

Low leakage

The main drawback of the "Low leakage" MOS device is a 30% reduction of the Ion current,leading to a slower switching. High speed MOS devices should be used in the case of fastoperation linked to critical nodes, while low leakage MOS should be placed whenever possible,for all nodes where a maximum switching speed is not required.

l High Ionl More performantl High Ioff (leakage)

l High VTl Low Ion, Ioffl Low leakage

l Very High Ionl Used for IOl Analog cells

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High voltage

The I/V Characteristics of the high voltage MOS are plotted in the figure, for Vgs and Vds up to3.3V. The channel length is 0.3µm, channel width 1.2µm.

There are two main reasons to keep a low-voltage supply for the core of the integrated circuit.The first one is low-power consumption, which is of key importance for integrated circuits usedin cellular phones or any portable devices. Low supply strongly reduces power consumption byreducing the amplitude of signals, thus reducing the charge and discharge of each elementarynode of the circuit. The second reason for low internal supply is the oxide breakdown. Increasedswitching performances have been achieved by a continuous reduction of the gate oxidethickness. In 0.12µm technology, the MOS device has an ultra thin gate oxide, around 0.003µm,that is 3nm or 30 Å.

The main objective is to reduce significantly the Ioff current, that is the small current that flowsfrom between drain and source with a gate voltage 0 (Supposed to be no current in first orderapproximation). On the figure below, the low leakage MOS device (right side) has an Ioffcurrent reduced by a factor 50, thanks to a higher threshold voltage (0.45V rather than 0.35V).

Low leakage MOS has higher Vt, slight Ion reductionLow leakage MOS has 1/100 Ioff of high speed MOS

CMOS Design > MOS Device > Three MOS Options

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MOS as a Switch

NMOS

The channel is off, consequenctly nothing happens to the drain. When the gate is on, thechannel enables Vout to copy the value of Vdrain (Time 1.0). The voltage Vout never reached1.2V. It "saturates" to around 0.8V. The reason is the parsitic effect called threshold voltage,which is around 0.4V in the default technology 0.12µm. In summary, the n-channel MOS devicebehaves as a switch, but when on, it do not passes correctly the high voltages. A zero on oneside leads to a good zero, a logic 1 on one side leads to a poor 1. The main reason is thethreshold voltage of the MOS.

PMOS

The p-channel MOS is on when Vgate is zero, and off when Vgate is 1.2V. When the gate is on,the channel enables Vout to copy the value of Vdrain. The voltage Vout never reaches 0.0V. It"saturates" to around 0.3V, due to the threshold voltage of the device. In summary, the p-channel MOS device behaves as a switch, but when on, it do not passes correctly the lowvoltages. A zero on one side leads to a poor zero, a logic 1 on one side leads to a good 1.

The Perfect switch

Both NMOS devices and PMOS devices exhibit poor performances when transmitting oneparticular logic information. The nMOS degrades the logic level 1, the pMOS degrades the logiclevel 0. Thus, a perfect pass gate can be constructed from the combination of nMOS and pMOSdevices working in a complementary way, leading to improved switching performances. Such acircuit is called the transmission gate.

The transmission gate let a signal flow if en=1 and /en=0. In that case both the n-channel andp-channel devices are on. The n-channel MOS transmits low voltage signals, while the p-channeldevice preferably transmits high voltage signals. The main drawback of the transmission gate isthe need for two contraol signals Enable and /Enable, thus an inverter is usually required.

Simulation of the MOS as a Switch

CMOS Design > MOS Device

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The Transmission Gate: A Perfect Switch

Important features

l NMOS: degrades the logic level 1l PMOS: degrades the logic level 0

l Transmission gate: combination of PMOS and NMOS working in complementary wayl NMOS transmits low voltage and PMOS transmits high voltage

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Larger width W =>

l RON lower

l IDS higher

l faster switching

Longer length L =>

l RON higher

l IDS lower

l slower switching

CMOS Design > MOS Device > MOS as a Switch

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History

Firstly, the original MOS model 1 is presented, as it was proposed in the early versions of SPICEsimulator developed by the University of Berkeley, California. This model only applies for longchannel devices. Secondly, we introduce the semi-empirical model 3, which is still in use todayfor MOS device simulation with a channel length greater than 1µm. Thirdly, we present asimplified version of the BSIM4 models, developed by the University of Berkeley for MOSdevices with channel length down to 0.1µm.

CMOS Design > MOS Modeling

1925: J. Lilienfeld invents the field effect MOS

1935: O. Heil proposes a structure similar to actual MOS

1960: NMOS and PMOS are made on the same substrate

1968: Set up of MOS MODEL 1 (Shichman-Hodges)(validity domain: technologies 10µm)

1980: Set up of MOS MODEL 2 and 3 in SPICE : univ. of Berkeley(validity domain: 10µm > technologies 0.8µm)

1997: Set up of models for submicron MOS (techno < 0.8µm)MM9(european standard of Phililps)

2000: Set up of models for deep submicron MOS (techno < 0.25µm)BSIM4 (american standard of univ. of Berkeley)

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What is a MOS model?

Modeling the MOS device consists in writing a set of equations that link voltages and currents, inorder to simulate and predict the behavior of the single device, and consequently the behaviorof a complete circuit. For MOS devices, one of the key objective of the model is to evaluate thecurrent Ids which flows between the drain and the source, depending on the supply voltages Vd,Vg, Vs and Vb.

The equations represent the variation of the current Ids versus voltages in two different ways,as illustrated in the figure. The graphs are usually called "Ids/Vds", "Ids/Vgs". For simplicity, weconsider that the voltage Vs is grounded. This assumption has no consequence on the results.

CMOS Design > MOS Modeling

A model is made of :

l some equations describing IDS (VDS) and IDS (VGS)

l some parameters linked with the technology and given by the fonder

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CMOS Design > MOS Modeling > What is a MOS model?

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MOS Model 1

Historically, the MOS model 1 was the first to be proposed by Shockley, in 1952. The equationsof the MOS level 1 give the evaluation of the current IDS between the drain and the source as a

function of VD, VG and VS. The device operation is divided into three regions: cut-off, linear and

saturated.

The fonders give a set of parameters for each technology

The basic SPICE parameters for model 1 are listed in this table : the threshold voltage VTO, thetransconductance KP, the channel width and length, as well as two parameters linked to theVTO modulation : GAMMA and PHI.

A SPICE netlist consists of a text, as shown below. The letter "M" means MOS device. The star"*" adds a comment. The ".MODEL" keyword is used for listing the parameters.

SPICE File :

CMOS Design > MOS Modeling

SPICEparameter

UnitValue in0.8µm

Value in0.25µm

Description

VTO V 0.8 0.5 Threshold voltage

KP A/V2 500 250 Transconductance

W µm 1.6 0.5 Channel width

L µm 0.7 0.25 Channel length

GAMMA V1/2 0.4 0.4Threshold dependancy withVsbstrat

PHI V 0.7 0.7 Surface potential

MN1 0 6 3 0 TN W= 3.60U L= 1.20UMP1 1 6 3 2 TP W= 9.60U L= 1.20U

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Influence of each parameters on the curve

In the Id/Vg curve, we extract the threshold voltage. In the previous chapter we observed theparasitic effects due to this threshold. Analog design is much concerned by an accurateprediction of the threshold voltage.

The role of VTO, GAMMA and PHI can be observed in the figure. Act on VTO cursors in order toshift the curves right or left, and GAMMA and PHI to fit the spacing between curves. KP acts onthe slope.

In the Ids/Vds curve, the current Ids is plotted for varying gate voltage Vgs, from 0 to VDD. Theparameter Ion gives the maximum available current, corresponding to maximum voltage Vdsand Vgs. Ion is a very important parameter for signal switching, for example in logic gates.

Mismatch between simulation and measurements

*n-MOS Model 1 :.MODEL TN NMOS LEVEL=1 VTO=0.70 KP=80.000E-6 GAMMA=0.400 PHI=0.700

*p-MOS Model 1:.MODEL TP PMOS LEVEL=1 VTO=-0.76 KP=25.000E-6 GAMMA=0.400 PHI=0.700

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These old equations (1968, in [Shichman]) are not acceptable in 0.12µm. If we consider MOSdevices with very long length (L>10µm), the mismatch between the simulation and themeasurement is the order of a factor of five. Let us compare the simulation and themeasurement, for a device with a width W=10µm, and a long channel length L=10µm,fabricated in 0.12µm CMOS technology, as presented in figure. The measurement"Ne10x10.MES" was downloaded using the button "Load Measurement". This measurementcorresponds to a n-channel MOS device with a channel width 10µm and length 10µm, fabricatedin CMOS 0.12µm from ST-microelectronics.

Initially, the simulation and measurement do not correspond at all. The mobility U0 needs to bedecreased from its initial value 0.06 down to 0.01. The curves are fitted at the price of anunrealistic change in the mobility parameter.

The model 1 predict a current 5 times higher than the measurement in the case ofa large channel MOS device (L=10µm).

Comparing measured Id/Vd and level 1 simulations for a 10x10µm device result in asurprising similarity (Ne10x10.MES).

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When dealing with sub-micron technology, the current predicted by model "Level 1" is severaltimes higher than the real-case measurements. This means that several parasitic effectsappeared with the technology scale down, most of them tending to reduce the effective currentcompared to the early modeling equations of the model 1.

CMOS Design > MOS Modeling > MOS Model 1

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MOS Model 3

The MOS model 3 is slightly more complicated than model 1. We show here some of the mostimportant equations. We introduce several limiting parameters that affect the transconductanceKeff, the efficient LEFF, and the saturation Vsat. The Vdsat equation is a typical fitting curve

between Vc and Vsat.

Lateral Drain Diffusion

The lateral drain diffusion (LDD) vis a small low-doped diffusion on both sides of the gate, thatprevents from hot carrier parasitic currents. Without, electrons are so accelerated during theirtransport beneath the gate that they create by impact a pair or elections and holes. Electronsare added to the Ids current while holes are evacuated to the substrate. The LDD limits thiseffect, which becomes negligeble at normal voltage supply. The hot carrier effect reappears at1.5 to 2 VDD.

CMOS Design > MOS Modeling

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The MOS model 3 requires a large number of parameters. We give here the most importantones. The physical parameters of Level 1 reappear, as well as new paarameters such as LD,PHIN, NSS, VMAX. Not all these parameters have a physical origin. Some of them are justempirical parameters.

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Several screens may be proposed:

l Id vs. Vd, for varying Vg. This is the default screen. Its main interest is thecharacterization of the Ion current, the maximum current available in the device, for Vdand Vg set to VDD.

l Id vs. Vg, for varying Vb. In this screen, the threshold voltage VTO is characterized, aswell as its dependence with the bulk polarization.

l Id vs. Vg, in logarithmic scale. This screen is mandatory to characterize the MOS device insub-threshold mode, that is for Vgs<Vt. Two of the important parameters are the slope ofthe current vs. Vgs, and the Ioff current. The Ioff current is the standby current appearingbetween drain and source for Vgs=0.

Current versus drain-source voltage

Using the display mode "Id vs. Vd", you may see the effect of parameters U0, TOX, KAPPA andVMAX. Basically, the carrier mobility U0 moves the whole curve, as it impacts in an almostlinear way the current Ids. As U0 is nearly a physical constant, a significant change of mobilityhas no physical meaning. The oxide thickness TOX does the same but in an opposite way.

A TOX increase leads to a less efficient device, with less current. KAPPA changes the slope ofthe current when Vds is high, corresponding to the saturation region. Finally, VMAX truncatesthe curves for low values of Vds, to fit the transition point between the linear and the saturatedregion.

Current versus gate voltage

The role of VTO and GAMMA can be observed in the figure below, using the display mode "Idvs. Vg". If we use a long channel device, that is a length much greater than the minimumlength, the second order effects are minimized. Act on VTO cursors in order to shift the curvesright or left, and GAMMA to fit the spacing between curves. U0 and TOX have also a directimpact on the slope for high Vgs.

Demonstration of the role of U0, KAPPA and VMAX in Id./Vd(W=10µm, L=0.12µm)

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Now we focus on a short channel MOS device, for example W=2µm, L=0.12µm. Using the samedisplay mode Id vs. Vg, we obtain similar curves as for long-channel device. We observe thatthe shape of the current is bent. This modification is due to short channel parasitic effects. Theparameter THETA is used to bend the current curves at high VGS. The MOS model 3 do notprovide parameters to account for the VTO dependence with length.

Current vs Vg in logarithmic scale

We finally illustrate the role of NSS in the display mode "Id(log)/Vg". The parameter NSS hasa direct impact on the slope in sub-threshold mode, that is for Vgs<VTO.

.The effects of VTO and GAMMA are illustrated in Id/Vg mode voltage(W=10µm, L=0.12µm)

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In sub-threshold region, the Id dependence on Vgs is exponential. Theslope is tuned by parameter NSS. The whole curve is shifted using VTO

voltage (W=10µm, L=0.12µm)

CMOS Design > MOS Modeling > MOS Model 3

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BSIM4

A family of models has been developed at the University of Berkeley for the accurate simulationof sub-micron technology. The Berkeley Short-channel IGFET Model (BSIM) exist in severalversion (BSIM1, BSIM2, BSIM3). The BSIM3v3 version promoted by the Electronic IndustriesAlliance (EIA) is an industry standard for deep-submicron device simulation.

A new MOS model, called BSIM4, has been introduced in 2000. A simplified version of thismodel is supported by Microwind2, and recommended for ultra-deep submicron technologysimulation. BSIM4 still considers the operating regions described in MOS level 3 (linear for lowVds, saturated for high Vds, sub-threshold for Vgs<Vt), but provides a perfect continuitybetween these regions. BSIM4 introduces a new region where the impact ionization effect isdominant. In that region, Vds is very high, over the nominal supply voltage VDD. One of the keyfeatures of BSIM4 is the use of one singly equation to build the current, valid for all operatingmodes. Smoothing functions ensure a nice continuity between operating domains.

The number of parameters specified in the official release of BSIM4 is as high as 300. Asignificant portion of theses parameters is unused in our implementation. We concentrate on themost significant parameters, for educational purpose. The set of parameters is reduced toaround 20.

Threshold voltage

VTHO is the long channel threshold voltage at Vbs=0 (Around 0.5V), K1 is the first order bodybias coefficient (0.5 V1/2), s is the surface potential, Vbs is the bulk-source voltage, K2 s thgesecond order body bias coefficient, &DeltaVtSCE is the short channel effect on Vt, VtNULD is the

non-uniform lateral doping effect explained in the equation, VtDIBL is the drain-induced barrier

lowering effect of short channel on Vt.

Short channel effect

DVT0 is the first coefficient of short-channel effect on the threshold voltage (2.2 by default),DVT1 is the second coefficient of short-channel effect on the threshold voltage (0.53 bydefault), Leff is the effective channel length, and lt is the characteristic length, approximated in

CMOS Design > MOS Modeling

BSIM4 was created for analog submicron simulation100 principal parameters

BSIM4 gives:

l current equationsl charge equationsl noise equations

Many kinds of parameters

l reference parametersl dependency parameters (with L, W, T°)

A limitation procedure force parameters in their validity domain

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our implementation to 1/4 of the minimum channel length (0.03 µm for a 0.12µm ), Vbi isdefined in the equation, and s is the surface potential.

The main impact of the Vt decrease is the Ioff parasitic current, detailed in the next paragraphs,that exhibits an exponential dependence with 1/Vt. Consequently, short channel MOS devicesconsume a very high standby current, which impacts the power consumption of the wholecircuit.

Non-uniform lateral doping

The lateral drain diffusion (LDD) is a technique introduced in recent technologies to reduce thepeak channel fields in the MOS channel.

For decreasing length, the threshold voltage tends to increase first (due to VtNULD), before

decreasing rapidly due to the short channel effect VtSCE described.

Drain induced barrier lowering

When we apply a positive voltage on the drain of a long-channel n-MOS device, we observe nosignificant change in the value of Vt. When we do the same for a short-channel n-MOS device,we observe a decrease of the threshold voltage. The physical origin of DIBL is the increase ofthe depletion layer due to a high value of Vdrain, that reduces the equivalent channel length,and consequently decreases the threshold voltage.

CMOS Design > MOS Modeling > BSIM4

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Dynamic Behavior

The five main capacitance considered in our implementation of MOS model 3 are:

l the gate to bulk capacitance Cgbl the gate to source capacitance Cgsl the gate-to-drain capacitance Cgdl the junction capacitance between source and bulk Csbl the junction capacitance between drain and bulk Cdb

The variation of the capacitance must be computed at each iteration of the analog simulation,for accurate prediction of the switching delay. The junction capacitance for drain and sourcehave a significant contribution to the MOS capacitance.

CMOS Design > MOS Modeling

Parasitic capacitances play an important role:

CGD/CGS : grid/drain and grid/source -- depend on VGS and VDS -- fixed in model 1 -- well predicted by MM9, BSIM4

CDB/CSB: drain/substrate and source/substrate -- composed by CJ and CJSW CJ: surfacic junction capacitance CJSW: peripheric junction capacitance périphérique de jonction

CGB or Cox : grid/substrate (gate oxyde capacitance)

30 parameters in BSIM4 for capacitance model !

CMOS Design > MOS Modeling > Dynamic Behavior

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Temperature Effect

Three main parameters are concerned by the sensitivity to temperature: the threshold voltageVTO, the mobility U0 and the slope in sub-threshold mode dependent on kT/q. Both VTO and U0decrease when the temperature increases.

A higher temperature leads to a reduced mobility, as UTE is negative. Consequently, at a highertemperature, the current Ids is lowered.

Meanwhile, in an opposite trend, the threshold voltage is decreased. Therefore, there exists aremarkable operating point where the daring current is almost constant and independent oftemperature variation. In 0.12µm CMOS, the Vds voltage with zero temperature coefficient(ZTC) is around 0.9V.

CMOS Design > MOS Modeling

2 sensible parameters:

KP(T) = KP(T0) (T- T0) e-1.5

VTO(T) = VTO(T0)-0.002 (T- T0)

Physical aspect:carrier mobility degradation

CMOS Design > MOS Modeling > Temperature Effect

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Conclusion

Many choice of models for MOS simulation

The number of parameters required for various MOS models is increased in order to take inaccount various effects linked to the device scale down.

BSIM4 has been created for the analog simulation of submiron devices.

Having accurate models is necessary for high precision logic circuit evaluation, for analog device(AOP, Sample and Hold, converters,..) and signal integrity analysis.

CMOS Design > MOS Modeling

CMOS Design > MOS Modeling > Conclusion

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Inverter Behavior

The CMOS inverter design is detailed. Here one p-channel MOS and one n-channel MOStransistors are used as switches.

When the input signal is logic 0, the nMOS is switched off while PMOS passes VDD through theoutput, which turns to 1. When the input signal is logic 1, the pMOS is switched off while thenMOS passes VSS to the output, which goes back to 0. The n-channel MOS symbol is a devicethat allows the current to flow between the source and the drain when the gate voltage is "1".

The analog simulation of the circuit is performed.

The truth-table is verified. A logic zero corresponds to a zero voltage and a logic 1 to a 1.20V.

CMOS Design

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The inverter delay is significantly increased.

It can be seen that the gate delay variation with the loading capacitance is quite linear.

l In 0.25µm typical commutation delay 50psl Depends on computing conditions (10%-90% or 50%)l Depends on charge (output parasitic or real capacitance)

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CMOS Design > Inverter > Inverter Behavior

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Inverter Behavior

The CMOS inverter design is detailed. Here one p-channel MOS and one n-channel MOStransistors are used as switches.

When the input signal is logic 0, the nMOS is switched off while PMOS passes VDD through theoutput, which turns to 1. When the input signal is logic 1, the pMOS is switched off while thenMOS passes VSS to the output, which goes back to 0. The n-channel MOS symbol is a devicethat allows the current to flow between the source and the drain when the gate voltage is "1".

The analog simulation of the circuit is performed.

The truth-table is verified. A logic zero corresponds to a zero voltage and a logic 1 to a 1.20V.

CMOS Design

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The inverter delay is significantly increased.

It can be seen that the gate delay variation with the loading capacitance is quite linear.

l In 0.25µm typical commutation delay 50psl Depends on computing conditions (10%-90% or 50%)l Depends on charge (output parasitic or real capacitance)

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CMOS Design > Inverter > Inverter Behavior

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Inverter Power Consumption

The inverter consumes power during transitions, due to two separate effects. The first is shortcircuit power arising from momentary short-circuit current that flow from VDD to VSS when thetransistor functions in the incomplete-on/off state. The second is the charging/dischargingpower, which depends on the output wire capacitance. With small loading, the short circuitpower loss is dominant. With a huge loading, i.e a large output node capacitance, the loadingpower is dominant. The power consumption occurs briefly during transitions of the output,either from 0 to 1 or from 1 to 0.

The transient current peaks appear at each modification of the output voltage, as shown in thefigure. The simulation contains the supply currents in the upper window, and all voltagewaveforms in the lower window. The current consumption is important only during a very shortperiod corresponding to the charge or discharge of the output node. Without any switchingactivity, the current is very small.

Inverters consume power during transitions (momentary short circuit and C charge)For one inverter 0.2mA => May reach 100A peak on VDD in ultra complex circuit

Consequence of current peaks: noise propagation

CMOS Design

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CMOS Design > Inverter > Inverter Power Consumption

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Ring Oscillator

An illustration of the frequency increase with the technology scale down is proposed using a ringoscillator made from 5 inverters. This very simple circuit has the property to oscillate naturally.We observe the oscillating output and measure its corresponding frequency.

Although the supply voltage (VDD) has been reduced (VDD is 5V in 0.8µm, 2.5 in 0.25µm, 1.2Vin 0.12µm), the gain in frequency improvement is significant.

Simulation of the 3 MOS options

CMOS Design

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Let us consider the ring oscillator with an enable circuit, where one inverter has been replacedby a NAND gate to enable or disable oscillation. The schematic diagram is shown below, as wellas its layout implementation. We analyze the switching performances in high speed and lowleakage mode, by changing the properties of the option layer which surrounds all devices.

CMOS Design > Inverter > Ring Oscillator

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Conclusion

l Illustration of technology scale downl Continuous gain in frequencyl Power supply reductionl The MOS keeps the same, but many versionsl Increased interconnects improve densityl In 2000, ST produces the 0.18µm technology

CMOS Design

CMOS Design > Inverter > Conclusion

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Lambda Based Design

The layout window features a grid, scaled in lambda () units. The size of the grid constantlyadapts to the layout. In the figure, the grid is 5 lambda. The lambda unit is fixed to half of theminimum available lithography of the technology Lmin. For example, the default technology is a

CMOS 6-metal layers 0.12µm technology, consequently lambda is 0.06µm.

= Lmin / 2

The objective is to draw the devices according to the design rules and usual design practices.The tool MICROWIND is used to draw devices layout and simulate thier behavior.

Good points

l Enables technology changesl Enable design reusel Reduce design costl Used at Infineon, Motorola

Bad points

l Not optimal designl Partially used in ST

CMOS Design > Basic Design Rules

CMOS Design > Basic Design Rules > Lambda Based Design

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MOS Design Rules

N-channel MOS

The narrow box in polysilicon layer should not have a width inferior to 2 . The N+ diffusionshould have a minimum of 7 lambda on both sides of the polysilicon gate. The intersectionbetween diffusion and polysilicon creates the channel of the nMOS device.

P-channel MOS

The narrow polysilicon box to create the p-channel MOS gate should have a width 2

The P+ diffusion should have a minimum of 7 on borh sides of the polysilicon gate. Add an n-well region that completely includes the P+ diffusion, with a border of 6 , as illustrated below.

CMOS Design > Basic Design Rules

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Inverter with same nMOS and pMOS sizes

Using the same default channel width (0.6µm in CMOS 0.12µm) for nMOS and pMOS is not thebest idea, as the p-channel MOS switches half the current of the n-channel MOS.

If Wnmos=Wpmos and Lnmos=Lpmos, Ids(Nmos) is proportional to µn while Ids(Pmos) isproportional to µp. Typical mobility values are given below.

for electrons (µn) : 1350 cm2/V·s

for holes (µp) : 480 cm2/V·s

Consequently, the current delivered by the n-channel MOS device is twice the one of the p-channel MOS. Usually, the inverter is designed with balanced currents to avoid significantswitching discrepancies. In other words, switching from 0 to 1 should take approximately thesame time as switching from 1 to 0. Therefore, balanced current performances are required.

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The reason for this addition of contacts is due to the intrinsic current limitation of eachelementary contact plug. One single contact can suffer less than 1mA current without anyreliability problem. When the current is stronger 1mA, the contact can be damaged. A verystrong current (around 10mA) destroys immediately the contact.

The contact is 2x2 , and the separation is 3 .

A good design consists in creating a p-channel MOS with twice the width of the n-channel MOS.The pMOS current is doubled, and becomes comparable to the nMOS current. The behavior willbe balanced in terms of switching speed.

l Minimize drain/source areal Use L minimum

l 1 contact = 1mAl Multiply contacts

l Same N and P alters symmetry l L min

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l Wpmos=2 Wnmos

CMOS Design > Basic Design Rules > MOS Design Rules

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Interconnect Design Rules

Although we designed the CMOS inverter using two layers of metal, up to 6 metal layers areavailable for signal connection and supply purpose. A significant gap exists between the 0.7µm2-metal layer technology and the 0.12µm technology in terms of interconnect efficiency.

The stacking of contacts is not allowed in micro technologies. This means that a contact frompoly to metal2 requires a significant silicon area as contacts must be drawn in a separatelocation. In deep-submicron technology (Starting 0.35µm and below), stacked contacts areallowed.

Metal layers are labeled according to the order in which they are fabricated, from the lower level1 (metal 1) to the upper level (metal 6 in 0.12µm). Each layer is embedded into a silicon oxide(SiO2) which isolates layers from each others. A cross-section of a 0.18µm CMOS technology isshown in the figure.

CMOS Design > Basic Design Rules

l Routing strategy metal 2vertical, metal 3 horizontal

l Metal 1: high resistancel Supply in metal 3l Use stacked vias

l Up to 6 metal layersl Metal 1 has high resistance

(Tungstene)l Metal 2,3,4 identicall Metal 5,6 thicker, larger to be used

for supply and long routing

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The connection material between diffusion and metal is called "contact". The same layer is alsoused to connect poly to metal, or poly2 to metal. The connection material between metal andmetal2 is called "via". By extension, the material that connects metal2 to metal3 is "via2",metal3 to metal4 "via3", etc..

The role of interconnects in integrated circuit performances has considerably increased with thetechnology scale down.

In 0.18µm, 6 metal layers are available. This cross section of a 0.18µm CMOS technology showstechnological evolution: introduction of lateral drain diffusion, shallow tretch isolation and thepossibility to use different MOS options. The capacitance effects have severely increased due tomuch nearer routing, and the interconnect resistance has significantly increased due to acontinuous reduction of the wire section.

In 0.12µm technology, the metal layers 1, 2 , 3 and 4 have almost identical characteristics.Concerning the design rules, the minimum size w of the interconnect is 3 lambda. The minimum

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spacing is 4 lambda. In Microwind, each interconnect layer is drawn with a different color andpattern. Examples of minimum width and distance interconnects are reported in the figure.

These minimum width and spacing are critical dimensions. They define the limit below which theprobability of manufacturing error rises to an unacceptable value. If we draw metal 1 lines with2 lambda width and 2 lambda spacing, interconnect interruptions or short-cuts may appear.Consequently, the design rules must always be checked to ensure that the whole circuitcomplies with the width and spacing rules, to avoid unwanted interruptions or bridges in thefinal integrated circuit. Still, there exist a small probability of manufacturing error even if thecircuit complies to all design rules.

The basic width for metal interconnects is usually a little higher than the minimum value. Thepitch is the usual distance that separates two different interconnects. In 0.7µm, due to severconstraints in the contact size, the pitch has been fixed to 10 lambda. In deep-submicrontechnology, improvements in contact sizing may reduce that pitch to 8 lambda. In 0.12µmtechnology, this routing pitch is equivalent to 0.48µm.

Antenna Ratio

During interconnect fabrication, the plasma etching charges the metal lines. The accumulationof those charges may damage the gate oxide of the MOS connected to this interconnect. As aconsequence, the threshold voltage VT may be affected.

A specific design rule give the antenna ratio to avoid this kind of problem.

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Antenna ratio = Area (metal) / Area (gate) < 50 in 0.18µm for example.

To be sure to avoid any charges accumulation, we can eliminate them thanks to diodes asshown in the next figure.

Those 2 diodes eliminate the charges accumulation on the interconnect, in the Nwell for thepositive charges and in the substrate for the negative ones.

CMOS Design > Basic Design Rules > Interconnect Design Rules

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Conclusion

l Confidentiality protects advances and weaknessesl Lambda-based design features easy reusel Basic rules investigatedl Interconnect design rules describedl Power supply design rules introducedl Illustration made for hcmos7

CMOS Design > Basic Design Rules

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Introduction

CMOS Design > Analog Cell Design

CMOS Design > Analog Cell Design > Introduction

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MOS Diod

The resistance obtained using such a circuit can reach easily 100K in a very small silicon area.The same resistance can be drawn in poly but would require a much larger area. In the figure, apolysilicon resistance of 20K is drawn close to the MOS device with a 30K on resistance. Theadvantage of using MOS resistance rather than polysilion resistance are obvious.

CMOS Design > Analog Cell Design

Using MOS diod:

Advantages: big R, small area, reduces noise

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CMOS Design > Analog Cell Design > MOS Diod

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Voltage Reference

The voltage reference is usually derived from a voltage divider made from resistance. The mainproblem is that the value of the resistance must be high to keep the short cut current low, toavoid wasted power consumption. A key idea is to use MOS devices rather than polysilicon ordiffusion resistance to keep silicon area very small.

CMOS Design > Analog Cell Design

CMOS Design > Analog Cell Design > Voltage Reference

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Current Mirror

The current mirror is one of the most useful basic blocs in analog design. In its most simpleconfiguration, it consists in two MOS devices, as represented below. A current I1 flowingthrough the nMOS device Master is copied to the MOS device Slave. If the size of Master andSlave are identical, in most operating conditions, the currents are the same. The remarkablepoint is that the current is almost independent of the drain voltage of the slave V2. If the rationW/L of the Slave is 10 times the ratio of the Master, the current on the right branch is 10 timesthe current on the left branch.

A set of design techniques can improve the current mirror behavior.

l All MOS devices should have the same orientation. During fabrication, the chemicalprocess has proven to be slightly different depending on the orientation, resulting invariations of effective channel length. This mismatch alters the current duplication.

l Long channel MOS devices are preferred. In such devices, the channel length modulationis small, and consequently Ids is almost independent of Vds.

l Dummy gates should be added at both sides of the current mirror. Although some siliconarea is lost, due to the addition of inactive components, the patterning of active gatesleads to very regular structures, ensuring a high quality matching.

CMOS Design > Analog Cell Design

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l MOS devices should be in parallel. If possible, portions of the two MOS devices should beinterleaved, to reduce the impact of an always-possible gradient of resistance, orcapacitance with the location within the substrate.

1. Design MOS with large L:

2. Have same orientation for all the MOS devices :

Process variationwith differentorientation

3. Have parallel structures

4. Add dummy gates at each side:

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CMOS Design > Analog Cell Design > Current Mirror

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Amplifier

l How to use an inverter to amplify a signal?l Single stagel Add stages to increase the gainl Simple differential amplifierl Wide range amplifier

How to use an inverter to amplify a signal?

Could the logic CMOS inverter act as an amplifier? In principles, yes, as the static characteristicsof the CMOS amplifier is very much like the static response of the basic amplifier describedearlier. The main problem is the very high gain of the amplifier. When trying to compute theslope, we find 180. To operate in the amplifier zone, we should inject a signal around 1.20V,otherwise there is no chance to take advantage of the very high amplification.

Furthermore, as the process parameters are not well controlled, the commutation point of theinverter may fluctuate in a significant range, depending on the location of the die on the wafer,or even on the die itself. As a consequence, very high gain structures are not adequate. Usually,amplifiers with gain around 10 (that is 20dB) are used, for example in the low noise inputamplifier of the GSM.

CMOS Design > Analog Cell Design

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Single stage

The single-stage amplifier described here consists of a MOS device (we choose here a n-channelMOS) and a load resistance. The resistance can be made from polysilicon or diffusion. As thegain of this amplifier is proportional to the load resistance, a MOS device with gate and drainconnected could replace the resistance. This is called an active resistance. Using a small siliconarea, high resistance can be obtained, meaning high amplifier gains.

The range of voltage input that exhibits a constant gain appears clearly. For VDS higher than0.6V and lower than 0.8V, the output gain is around 5. Therefore, an optimum offset value is0.11V.

Problems

l We can not charge the gainl With a high gain, it is less accuratel Amplification zone very small

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We define the transconductance gm as the derivative of iDS versus vDS. Thus gm is the invertof the channel resistance. Using the very simple approximation of the MOS current in saturation,a formulation of gm in saturation is obtained. Thus, the gain of the amplifier can be expressedby (5).

Add stages to increase the gain

To further increase the gain, the ratio between the active load resistance and the n-channelMOS resistance should be increased.

l To increase the gain we can plan on WN/WP:

If we decrease Wp (RP ): we increase the noise

If we increase Wn (RN ): we increase the consumption

l With a high gain there is a problem of accuracy (slope tooimportant)Solution : add an other stage

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Simple differential amplifier

The goal of the differential amplifier is to compare two analog signals, and to amplify theirdifference.

The differential pair is built from n-channel MOS devices. Their size must be identical, anddrawn with the same orientation, to minimize the offset generated by transistor mismatch.

The differential amplifier formulation is reported below. Usually, the gain K is high, ranging from10 to 1000. The consequence is that the differential amplifier output saturates very rapidly,because of the supply voltage limits.

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Vout=K(Vp-Vm)

In the simulation, it can be seen that a small voltage difference between V+ and V- induces thesaturation of the output either near VSS and VDD.

Push Pull amplifier

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The push-pull amplifier is built using a voltage comparator and a power output stage. Itsschematic diagram is reported in the figure. The difference between V+ and V- is amplified andit produces a result, codified : Vout.

The gain near 2.5V is more than 1,000. Use the Voltage vs. Voltage simulator mode to get thetransfer characteristics Vout/V+. The input range is around 0.5V to 4.0V.

You can easily build a follower by designing an extra connection from Vout to V-. The outputstage is not strong enough to be able to drive large loads such as output pads.

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CMOS Design > Analog Cell Design > Amplifier

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Converters

l Analog to Digital Converterl Digital to Analog Converter

Analog to Digital Converter

The analog-digital converter converts an analog value Vin into a two-bit digital value calledA0,A1. The flash converter uses three converters and a coding logic to produce A0 and A1. Avery complex logic circuit and 255 comparators would be used for an ADC eight-bit flash.

The polysilicon has a high resistance (50 per square) and can be used as a resistor network,which generates intermediate voltage references used by the voltage comparators located in themiddle.

CMOS Design > Analog Cell Design

l The ADC converts an analog Vin in 2 bits A0, A1l Resistor scale in polysiliconl To produce A0, A1 the ADC needs 2 comparators and 3 logic gatesl For a 8 bits CAN, 255 comparators are necessary

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Digital to Analog Converter

This digital-analog converter converts a digital three-bit input (A0,A1,A2) into an analog valueVout.

The polysilicon resistive net gives intermediate voltage references which flow to the output via atransmission gate net. The resistance symbol is inserted in the layout to indicate to thesimulator that an equivalent resistance must be taken into account for the analog simulation.

AnalogInput Vin

C0 C1 C2 A1 A0

Vin<1.25V 0 0 0 0 0

1.25<Vin<2.5 1 0 0 0 1

2.5<Vin<3.5 1 1 0 1 0

Vin>3.75V 1 1 1 1 1

l This DAC converts 3 bits A0, A1, A2 into an analog voltage Vinl Resistor scale in polysiliconl Structure : 14 transmission gates

A2 A1 A0Analog output

Vout (V)

0 0 0 0.0 V

0 0 1 0.625

0 1 0 1.25

0 1 1 1.875

1 0 0 2.5

1 0 1 3.125

1 1 0 3.75

1 1 1 4.375

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CMOS Design > Analog Cell Design > Converters

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Sample and Hold Circuit

Sample and Hold (S/H) circuits are critical in converting analog signals to digital signals. Itsmain function is to capture the signal value at a given instant and hold it until the ADC canprocess the information.

The transmission gate can be used as a sample and hold circuit.

When the gate is off, the value of the sampled data remains constant. This is mainly due to theparasitic capacitance CLoad of the node, which has a value of 0.8 fF, as extracted in a CMOS

0.12µm process.

Ron and Cload adjust the bandwidth of the system.

Advises to design the sample and hold circuit:

l PMOS and NMOS have same size to compensate parasitic capacitances: CGS/CGDl PMOS must switch before the NMOS to compensate the higher mobility of elections in

NMOS

The layout of the transmission gate is reported figure.

CMOS Design > Analog Cell Design

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When sampling, the transmission gate is turned on so that the sampled data DataOut reachesthe value of the sinusoidal wave DataIn.

The operation is repeated in time with a regular sampling period.

We can notice that during the sampling period, the S/H circuit operates in dynamic mode(sample) and the in static (hold) mode.

The critical element in accurately capturing the analog input voltage is the number of sampleddata in the considered time window. We can also talk about the sampling frequency comparedto the input voltage frequency. The Shannon's Sampling Theorem gives the minimum frequencyrequired to accurately represent the analog input voltage:

Shannon's Sampling Theorem:

The minimum sampling frequency must be equal to or greater than twice the highest frequencycomponent of the original signal. To be strictly accurate we should use the term "Bandwidth"rather than highest frequency component.

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CMOS Design > Analog Cell Design > Sample and Hold Circuit

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Frequency Converter

Goal : To shift a high frequency in lower frequency

In many situations for radio frequency receivers, there is a need for shifting a high frequencyinput waveform into a low frequency waveform. The operation is called down conversion. Infrequency domain, it consists in shifting a high frequency information contained in frequency finto a lower frequency fout, as illustrated in the figure.

One very simple solution consists in using a transmission gate with a very accurate tuning of thegate clock. As an illustration, we use a 1.900 GHz sinusoidal wave, and a 1.818 Ghz samplingsignal (550 ps period). The expected output frequency is therefore 1.900-1.818=0.082 GHz,that is 82MHz. The layout of the sample circuit is a simple transmission gate with an RC filter.

CMOS Design > Analog Cell Design

Simple solution :Transmission gate followed by a RC filter

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CMOS Design > Analog Cell Design > Frequency Converter

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Introduction

Field programmable gate arrays (FPGA) are specific integrated circuits that can be user-programmed easily. The FPGA contains versatile functions, configurable interconnects andinput/output interface to adapt to the user specification. FPGA allow rapid prototyping usingcustom logic structures, and are very popular for limited production products. Modern FPGA areextremely dense, with complexity of several millions of gates which enable the emulation ofvery complex hardware such as parallel microprocessors, mixture of processor and signalprocessing, etc c One key advantage of FPGA is their ability to be reprogrammed, in order tocreate a completely different hardware by modifying the logic gate array. The usual structure ofa FPGA is given in figure 9-1.

One example of a very simple function (3-input XOR) implemented in a FPGA is given in figure9-2. Three pads on the left are configured as inputs, one logic block is used to create the 3-input XOR and one pad on the right is used as output. The propagation of signals is handled byinterconnect lines, connected together at specific programmable interconnect points.

CMOS Design > Field Programmable Gate Array

Figure 9-1: Basic structure of a field programmable gate array

Figure 9-2: Using a field programmable gate array to build a 3-input XOR

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Three pads are configured as inputs and represent the logical information A,B and C (Figure 9-3). An internal routing path is created to establish an electrical link between the I/O region andthe logic bloc. Internally, the logic bloc may be configured in any combination of sequentialbasic function. Each logic bloc usually supports 3 to 8 logic inputs. In our example, the bloc isconfigured as a 3-input XOR. Then, other internal routing wires are configured in order to carryout the signal to an I/O pad configured as an output. The global propagation delay of sucharchitecture is evidently very high, if compared to a 3-input XOR gate that may be found in thecell library. This is usually the price to pay for configurable logic circuits.

Notice that FPGA not only exist as simple components, but also as macro-blocs in system-on-chip designs (Figure 9-4). In the case of communication systems, the configurable logic may bedynamically changed to adapt to improved communication protocol. In the case of very lowpower systems, the configurable logic may handle several different tasks in series, rather thanembedding all corresponding hardware that never works in parallel.

gate

Figure 9-3: Equivalent circuit for the FPGA configured in XOR3 gate

Figure 9-4: FPGA exist as stand-alone Ics or blocks within asystem-on-chip

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CMOS Design > Field Programmable Gate Array > Introduction

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Configurable Logic Circuits

The programmable logic block must be able to implement all basic logic functions, that is INV,AND, NAND, OR, NOR, XOR, XNOR, etc... Several approaches are used in FPGA industry toachieve this goal. The first approach consists in the use of multiplexor, the second one of look-up tables.

l Multiplexorsl Look Up Tablel Memory Pointsl Implementation in DSCH

Multiplexors

Surprisingly, a two-input multiplexor can be used as a programmable function generator, asillustrated in table 9-1. Recall that the multiplexor output is equal to i0 if en=0, and i1 ifen=1. For example, the inverter is created if the multiplexor input i0 is equal to 1, i1 is equal to0, and enable is connected to A. In that case, the output is the ~A. The figure 9-5 describesthe use of multiplexor to produce the OR, AND, NOT and BUF functions.

Although NOT, AND and OR are directly available, other functions such as NAND, NOR and XORcannot be built directly using a single 2-input multiplexor, but need at least two multiplexorcircuits.

CMOS Design > Field Programmable Gate Array

Function Boolean expression for output f i0 i1 en

BUF(A) f=A 0 A 1

NOT(A) f=~(A) 1 0 A

AND(A, B) f=A&B 0 B A

OR(A, B) f=A | B B 1 A

Table 9-1: Use of multiplexor to build logic functions

Figure 9-5: Use of multiplexor to build logic functions

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The XOR function is shown in figure 9-6. The 4-input XOR gate would require 6 multiplexorcells. Remember that each multiplexor cell consists of a minimum of 6 transistors for a bufferedoutput, and has 3 delay stages (The two inverters and the pass transistor). The XOR4implementation would comprise a total of 18 delay stages, which is far too important.Therefore, the multiplexor approach is not very efficient for many logical functions.

Look Up Table

The look-up table (LUT) is by far the most versatile circuit to create a configurable logicfunction. The look-up table shown in table 9-2 has 3 main inputs F0,F1 and F2. The main outputis Fout, which is a logical function of F0, F1 and F2. The output Fout is defined by the valuesgiven to Value[0]..Value[7]. The three values F0,F1, F2 create a 3-bit address i between 0 and7, so that Fout gets the value of Value[i]. In the example of table 9-2, the input creates thenumber 5, so Value[5] is routed to Fout. The table below gives Value[i] for the most commonlogical functions of F0,F1 and F2.

Figure 9-6: The XOR gate build from 2 multiplexor circuits

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In the case of the 3-input XOR, the set of values of Fout given in the truth-table of table 9-3,must be assigned to Value[0]..Value[7]. In the schematic diagram shown in figure 9-7, we mustassign manually the Fout truth-table to each of the 8 buttons. Then Fout produces the XORfunction of inputs F0, F1 and F2.

Function Value [0] Value [1] Value [2] Value [3] Value [4] Value [5] Value [6] Value [7]

~F0 0 1 0 1 0 1 0 1

~F1 0 0 1 1 0 0 1 1

~F2 0 0 0 0 1 1 1 1

F0&F1 0 0 0 1 0 0 0 1

F0 | F1 | F2 0 1 1 1 1 1 1 1

F0^F1^F2 0 1 1 0 1 0 0 1

Table 9-2: Link between basic logic functions and

F2 F1 F0 Fout=F0^F1^F2 Assigned to

0 0 0 0 Value [0]

0 0 1 1 Value [1]

0 1 0 1 Value [2]

0 1 1 0 Value [3]

1 0 0 1 Value [4]

1 0 1 0 Value [5]

1 1 0 0 Value [6]

1 1 1 1 Value [7]

Table 9-3: Truth-table of the 3-input XOR gate for itsimplementation in a look-up-table

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Memory Points

Memory points are essential components of the configurable logic blocks. The memory point isused to store one logical value, corresponding to the logic truth table. For a 3-input function(F0,F1,F2 in the previous LUT), we need an array of 8 memory points to store the informationValue[0]..Value[7]. There exist here also several approaches to store one single bit ofinformation. The one that is illustrated in figure 9-8 consists of D-reg cells. Each register storesone logical information Value[i]. The Dreg cells are chained in order to limit the control signalsto one clock ClockProg and one data signal DataProg. The 8 logical information Value[i] are fullyprogrammed by a word of 8 bits sent in series to the signal DataProg.

The configuration of the 3-input LUT into a 3-input XOR gate obeys to a strict protocol describedin figure 9-9. A series of 8 active edges is generated by the ClockProg signal (Dreg is active onfall edges). This is done by configuring a pulse generator with series of 0-1 as shown below.

Figure 9-7: The output f produces a loical function Fout according to a look-up-tablestored in memory points Value[i]

Figure 9-8: The look-up information is given by a shift register based onD-reg cells

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At each active edge, the shift register is fed by a new value presented sequentially at inputDataProg. As the D-reg is active on fall edge, data may be changed on each rise edge. Noticethat the last Dreg corresponds to Value[7]. Therefore, Value[7] must be inserted first, andValue[0] last. This means that the DataProg pulse must describe the truth table in reverseorder, as shown below.

Implementation in DSCH

In DSCH, a look-up-table symbol is proposed in the symbol menu (Figure 9-14). It is equivalentto the schematic diagram of figure 9-8. An important property of the LUT symbol is its ability toretain the internal programming as a non-volatile memory would do. The user's interface of theLUT symbol is given in figure 9-14. There are three ways to fill the look-up-table: one consistsin defining each array element with a 0 or a 1. The number corresponds to the logiccombination of inputs F2,F1,F0. For example the n°4 is coded 100 in binary, corresponding toF2=1,F1=0 and F0=0. A second solution consists in choosing the function description in the list.

Figure 9-9: Programming the ClockProg pulse togenerate 8 active edges

Figure 9-10: At the end of the 8-th clock periodm the LUT is configured as a 3-input XOR

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The logic information Fout assigned to each combination of the inputs updates the look-up-table. A third solution is also proposed: the user enters a description based on inputs F0,F1 andF2, and the logic operators "~" (Not), "&' (And), "|" (Or) and "^" (Xor). Then, click the button"Fill LUT" to transfer the result of the expression to the table.

Figure 9-14: The look-up-tablesymbol

CMOS Design > Field Programmable Gate Array > Configurable Logic Circuits

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Programmable Logic Block

The programmable logic block consists of a look-up table, a D-register and some multiplexor.There exist numerous possible structures for logic blocks. We present in figure 9-15 a simplestructure, which has some similarities with the Xilinx XC5200 series (See [Smith] for detailedinformation on its internal structure). The configurable block contains two active structures, theLut and the D-reg, that may work independently or be mixed together.

The output of the look-up-table is directly connected to the block output Fout. The output canalso serve as the input data for the D-register, thanks to the multiplexor controlled byDataIn_Fout. The DataOut net can simply pass the signal DataIn, in that case the cell istransparent. The DataOut signal can also pass the signal nQ, depending on the multiplexorstatus controlled by DataIn_nQ.

The block now consists of the LUT and the D-register. We chain the information DataIn_Foutand DataIn_nQ on the path of the shift register by adding 2 supplementary Dreg cells. EachDreg still uses the same clock ClockProg and chained input data DataProg. The complete circuitis shown in figure 9-16.

CMOS Design > Field Programmable Gate Array

Figure 9-15: Simple configurable logic block including the Look Up Table and a D-register

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The configuring of the block is realized thanks to 10 active clock edges on ClockProg, and 10serial data on DataProg. The chain of Dreg starts at Dreg0 (Upper Dreg in figure 9-16, whichproduced Value[0]) and stops at Dreg9 (Right side of figure 9-16, which produced DataIn/nQ).The information that flows at the far end of the register chain is defined at the first cycle, whilethe closest register is configured by the data present at the last active clock edge.

Figure 9-16: The Look Up Tablem the D-register and the shift register including the 2multiplexor cells

Clock cycle 1 2 3 4 5 6 7 8 9 10

DataProg DataIn/Nq Datain/Fout Val[7] Val[6] Val[5] Val[4] Val[3] Val[2] Val[1] Val[0]

Table 9-3: Serial data information used to program the LUT memory points

CMOS Design > Field Programmable Gate Array > Programmable Logic Block

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Interconnection between Blocks

The interconnection strategy between logic blocks is detailed in this paragraph. We focus on theprogrammable interconnect point and the programmable switching matrix. Then, we discuss theglobal implementation of the structure.

l Programmable Interconnect Pointl Switching Matrixl Array of Blocksl Full-Adder Example

Programmable Interconnect Point

The elementary programmable interconnect point (PIP) may be found in "Advanced" set of"Switches" symbols (Figure 9-17). It consists of a configurable bridge between twointerconnects.

The PIP may have two states: "On" and "Off". You may switch from "On" to "Off" by a doubleclick on the symbol (Screen shown in figure 9-18) and a click in the button "On/off".

CMOS Design > Field Programmable Gate Array

Figure 9-17: The programmable interconnectpoint (PIP) in the palette of symbols

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The bridge can be built from a transmission gate, controlled once again by a D-reg cell (Figure9-19). When the register information contains a 0, the transmission gate is off and no link existsbetween Interco1 and Interco2. When the information hold by the register is 1, the transmissiongate establishes a resistive link between Interco1 and Interco2. The resistance value is around100 .

Figure 9-18: Changing the state of the PIP

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The regrouping of programmable interconnect points into matrix is of key importance to ensurethe largest routing flexibility. Examples of 3x3 and 3x2 PIP matrix are shown in figure 9-20. Thelink between In1 and Out1, In2 and Out2, In3 and Out3 is achieved by turning some PIP on. Aspecific routing tool usually handles this task, but the manual re-arrangement is not rare insome complex situations. In DSCH, just press the key "O" to switch On and off the PIP.

Figure 9-19: Internal structure of the PIP and illustration of itsbehavior when Off (a) and On (b)

Figure 9-20: Matrix of programmable interconnects points

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Switching Matrix

The switching matrix is a sophisticated programmable interconnect point, which enables a widerange of routing combinations within a single interconnect crossing. The aspect of the switchingmatrix is given in figure 9-21. The matrix includes 6 configurable bridges between the two maininterconnects. The switching matrix symbol may be found in "Advanced" set of "Switches"symbols. By a double click on the matrix symbol, you get access to the 6 "On/Off" switches.

To ease the programming of the matrix, short cuts exist in DSCH. You can change the state ofthe matrix by placing the cursor on the desired symbol and pressing the following keys:

l To switch off the matrix, press the key "o".l To switch on the matrix, press the key "O".l To enable an horizontal link, press the key "-".l To enable a vertical link, press the key "|".

Figure 9-21: Changing the state of the matrix

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Examples of 3x2 and 3x3 switching matrix are given in figure 9-22. The routing possibilities arenumerous, which improves the configurability of the logic blocs.

Array of Blocks

The configurable blocs are associated with programmable interconnect points and switchingmatrix to create a complete configurable core. An example of double configurable block and itsassociated configurable routing is proposed in figure 9-24.

Figure 9-22: 3x2 switching matrix and example of routing strategy between 6 inputsand outputs

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Full-Adder Example

The truth table and logical expression for the full-adder are recalled in Table 9-3. Theimplementation of the CARRY and SUM function is realized by programming two look-up tablesaccording to the truth-tables reported in table 9-3.

Figure 9-24: Configurable blocks, switching matrix, configurable I/Os and arrays of PIP

FULL ADDER

A B C SUM CARRY RESULT

0 0 0 0 0 0

0 0 1 1 0 1

0 1 0 1 0 1

0 1 1 0 1 2

1 0 0 1 0 1

1 0 1 0 1 2

1 1 0 0 1 2

1 1 1 1 1 3

Table 9-3: The full-adder truth-table

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The general diagram of the Full adder implementation is given in figure 9-25. Oneprogrammable logic block Block1 supports the generation of the sum, for given logic values ofthe inputs A,B and C. The information needed to configure Block1 as a Sum function (3-inputXOR) is given in table 9-4. Notice that we only use the LUT in this programmable logic block.The Dreg is not active, and we only exploit the output of the LUT Fout, which is configured asthe Sum.

The signal Sum propagates outside the block to the output interface region, by exploiting theinterconnect resources and switching matrix. The other programmable logic block Block2supports the generation of the signal Carry, from the same inputs A,B and C. The programmingof Block2 is also given in table 9-4. The result Carry is exported to the output interface regionas for the Sum signal. Again, in this block, only the LUT is active.

Figure 9-25: The SUM and CARRYfunctions to realize the full-adder in

FPGA

Block 1 (Sum of F0, F1 and F2)

Cycle 1 2 3 4 5 6 7 8 9 10

DataIn Nq Datain Fout Val[7] Val[6] Val[5] Val[4] Val[3] Val[2] Val[1] Val[0]

0 0 1 0 0 1 0 1 1 0

Block 2 (Carry of F0, F1 and F2)

Cycle 1 2 3 4 5 6 7 8 9 10

DataIn Nq Datain Fout Val[7] Val[6] Val[5] Val[4] Val[3] Val[2] Val[1] Val[0]

0 0 1 1 1 0 1 1 0 0

Table 9-4: Serial data used to configure the logic blocks 1&2 as SUM and CARRY

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The programming sequence is contained in the piece-wise-linear symbols ProgBlock1 andProgBlcok2. As seen in the chronograms of figure 9-27, the program clock ClockPgm is onlyactive at the initialization phase, to shift the logic information to the memory points inside theblocks, which configure each multiplexor. The routing of the signals A,B and C as well as Sumand Carry has been done manually in the circuit shown in figure 9-26. In reality, specificplacement/routing tools are provided to generate the electrical structure automatically from theinitial schematic diagram, which avoids manual errors and limits conflicts or omissions.

Figure 9-26: Simulation of the full-adder implemented in 2 configurable blocks

Figure 9-27: Chronograms of the full-adder FPGA

CMOS Design > Field Programmable Gate Array > Interconnection between Blocks

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Conclusion

In this chapter, we gave a brief introduction to field programmable gate arrays, from of point ofview of cell design. Firstly, the use of multiplexor and look-up-tables for building configurablelogic circuits has been illustrated. Secondly, the programming of memory points using chainedD-registers and fuse has been described. Thirdly, we described the programmable interconnectpoints and switching matrix, with their implementation in DSCH. Finally, the implementation ofa full adder and a clock divider have been realized using two configurable logic blocks,proprammable interconnect points and switching matrix.

CMOS Design > Field Programmable Gate Array

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The World of Memories

Semiconductor memories are vital components in modern integrated circuits. Stand-alonememories represent roughly 30% of the global integrated circuit market. Within system-on-chip, memory circuits usually represent more than 75% of the total number of transistors.

Two main families of devices exist: volatile and non-volatile memories. In volatile circuits(Figure 10-1 left), the data is stored as long as the power is applied. The dynamic randomaccess memory (DRAM) is the most common memory. When the power supply is turned off, theinformation is lost. Non-volatile memories are capable of storing the information even if thepower is turned off (Figure 10-1 right). The read-only memory (ROM) is the simplest type ofnon-volatile memory. One-time programmable memories (PROM) are a second importantfamily, but the most popular non volatile memories are erasable and rogrammable devices: theold electrically programmable ROM (EPROM), the more recent Electrically Erasable PROM(EEPROM, FLASH), and the new magneto resistive RAM (MRAM) and ferroelectric RAM (FRAM)memories

Millions of elementary memories are used by microprocessors for executing of software. Micro-code, operating systems and low level software are usually stored in non-volatile memory. Thesoftware execution requires fast-access random access memory such as static or dynamic RAM.Memory exist as stand-alone components (Figure 10-2-a), but also as embedded blocks insystem-on-chip, such as shown in figure 10-2-b.

CMOS Design > Memories

Figure 10-1: Major classes of CMOS compatible memories

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Memory organization

Figure 10-3 shows a typical memory organization schematic. It consists of a memory array, arow decoder, a column decoder and a read/write circuit. The row decoder selects one row from2N, thanks to a N-bit row selection address. The column decoder selects one row from 2M,thanks to a M-bit column selection address. The memory array is based on 2N rows and 2M

columns of a repeated pattern, the basic memory cell. A typical value for N and M is 10, leading

Figure 10-2: The memory exists as a stand-alone component andan embedded block

Figure 10-3: Typical memory organization

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to 1024 rows and 1024 columns, that corresponds to 1048576 elementary memory cells(1Mega-bit). Several organization exist: 1024x1024 bit, 128Kx8bit, 64Kx16bit, 32Kx32 bits,etc.. For example, the organization 128Kx8bit consists in selecting 8 columns in parallel. In thatcase, the size of DataOut and DataIn bus is 8 bit.

Access Time

The typical timing diagram of a memory block is shown in figure 10-4. A fast system clock,around 1GHz period, synchronizes the whole sequence. On an active level of the Read command(Usually a low level), the read cycle begins. It may take several clock cycles before the data isavailable. In the case of figure 10-4, two clock cycles are necessary before the valid data isproposed at the DataOut bus. The typical access time for Mega-bit memories ranges between1ns and 10ns.

Figure 10-4: Read Access Time

CMOS Design > Memories > The World of Memories

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Static RAM Memory

l Introductionl The 6 transistor Memory Celll The 6T Cell Layoutl The 6T Memory Simulation

Introduction

The static RAM is a very important class of memory. It consists of two cross-coupled inverters,which form a positive feedback with two possible states illustrated in figure 10-5. This cell isalso the base of many sequential circuits, as detailed in chapter 8.

The 6 transistor Memory Cell

The basic cell for static memory design is based on 6 transistors, with two pass gates instead ofone. The corresponding schematic diagram is given in Figure 10-16. The circuit consists again ofthe 2 cross-coupled inverters, but uses two pass transistors instead of one. The cell has beendesigned to be duplicated in X and Y in order to create a large array of cells. Usual sizes forMegabit SRAM memories are 256 column x 256 rows or higher. A modest arrangement of 4x4RAM cells is proposed in figure 10-16. The selection lines WL concerns all the cells of one row.The bit lines BL and ~BL concern all the cells of one column.

CMOS Design > Memories

Figure 10-5: Elementary memory cell based on an inverter loop

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The 6T Cell Layout

The RAM layout is given in Figure 10-18. The BL and ~BL signals are made with metal2 andcross the cell from top to bottom. The supply lines are horizontal, made with metal3. This allowseasy matrix-style duplication of the RAM cell.

Figure 10-16: The layout of the 6 transistor staticmemory cell

Figure 10-17: An array of 6T memory cells, with 4 rows and 4 columns

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Figure 10-18: The layout of the static RAM cell

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The cross-section shows the nMOS devices and the connection to VSS using metal3, situated onthe middle of the cell. The BL and ~BL lines, in metal2 are on both sides. The word line controlsthe access between the bit lines and the internal memory information.

The size of the static RAM is given in the menu Layout size, accessible through the commandFile > Properties. As shown in figure 10-20, the layout dimensions are 41x46 lambda.

The 6T Memory Simulation

WRITE CYCLE. Values 1 or 0 must be placed on Bit Line, and the data inverted value on ~Bit

Figure 10-19: Cross-section of the static RAM cell in the n-channel MOS region

Figure 10-20: Size of the static RAM cellcan be found in the Properties menu

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Line. Then the selection Word Line goes to 1. The two-inverter latch takes the Bit Line value.When the selection Word Line returns to 0, the RAM is in a memory state.

READ CYCLE. The selection signal Word Line must be asserted, but no information should beimposed on the bit lines. In that case, the stored data value propagates to Bit Line, and itsinverted value ~Data propagates to ~Bit Line.

SIMULATION. The simulation parameters correspond to the read and write cycle in the RAM.The simulation steps proposed in figure 10-21 consist in writing a 0, a 1, and then reading the1. In a second phase, we write a 1, a 0, and read the 0. The Bit Line and ~Bit Line signals arecontrolled by pulses. The floating state is obtained by inserting the letter "x" instead of 1 or 0 inthe description of the signal.

Figure 10-21: Proposed stimulation patterns for the simulation of the 6T static Rammemory

Figure 10-22: The bit Line pulse used the "x" floating state to enablereading the memory cell

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The simulation of the RAM cell is proposed in figure 10-23. At time 0.0, Data reaches anunpredictable value of 1, after an unstable period. Meanwhile, ~Data reaches 0. At time 0.5ns,the memory cell is selected by a 1 on Word Line. As the Bit Line information is 0, the memorycell information Data goes down to 0. At time 1.5ns, the memory cell is selected again. As theBit Line information is now 1, the memory cell information Data goes to 1. During the readcycle, where Bit Line and ~Bit Line signals are floating, the memory sets these wiresrespectively to 1 and 0, corresponding to the stored values.

Figure 10-23: Write cycle for the static RAM cell

CMOS Design > Memories > Static RAM Memory

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A 64 Bit Static RAM

l Row Selection Circuitl Column Selection Circuitl A Complete 64 bit SRAMl Precharge Circuitl Analog Amplifier

Row Selection Circuit

The row selection circuit decodes the row address and activates one single row. This row isshared by all word line signals of the row. The row selection circuit is based on a multiplexorcircuit. One line is asserted while all the other lines are at zero.

In the row selection circuit for the 16x4 array, we simply need to decode a two-bit address.Using AND gates is one simple solution. In figure 10-34, we present the schematic diagram of2-to-4 and 3-to-8 decoders. In the case of very large number of address lines, the decoder issplit into sub-decoders, which handle a reduced number of address lines.

CMOS Design > Memories

Figure 10-33: The row selection circuit

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Figure 10-34: The row selection circuit in 2 bit and 3 bit configuration

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The 6-bit decoder of figure 10-35 is built from two stages of 3-bit decoders. A total of 64 wordlines are generated using this circuit. All word lines have not been shown for clarity. The rowselection circuit loads a very significant capacitance, which is the sum of Word Bit of eachelementary memory cell. Consequently, the AND gate is designed using a NAND gate followedby a strong buffer (Figure 10-36).

Figure 10-35: The 6-bit row selection circuit using groups of 3 bits

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The Row Selection circuit height should be adjusted to that of the RAM cell height. When makingthe final assembly between blocks, the command Edit > Move Step by Step is very useful.This command helps to move a selected block with a lambda step (Figure 10-37).

The row selection layout has the particularity to be very regular. It encrypts a binary patternthrough the addition of contacts, as illustrated in figure 10-38. The binary encoding can berealized in a semi-automatic way in Microwind. The idea is to create a pattern consisting of avertical metal box (Address lines), crossing an horizontal metal2 box, and a via to create tobuild an electrical link between these two nodes. The basic pattern is duplicated 6 times in Xand 3 times in Y for each word line circuit. The via layer is copied only if a physical layer isneeded at the intersection between vertical address lines and horizontal interconnects. Thecopying of the via is controlled by a Boolean table sown in figure 10-39.

Figure 10-36: Buffering the word line command

Figure 10-37: Moving a portion of layout step by step

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The data matrix is filled by zeros and ones. A zero indicates that no via will be generated, a oneindicates that the via will be copied. The tick Assign data must be asserted, and the via boxmust be chosen in this case. In the Boolean matrix, the "0" ma be changed into a "1" by adouble click at the desired location.

Figure 10-38: The address uses contacts on selected address lines to program the wordline according to each address

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The aspect of the row decoder circuit is shown in figure 10-40. At the left side, we recognize theregular interconnect matrix and its associated via. In the middle, the 3-input NAND gate and abuffer are designed, with the appropriate whirring and supply connections to fit exactly with therigid layout of the static RAM cell.

Column Selection Circuit

Figure 10-39: Generating the matrix of contacts using the Duplicate XY command

Figure 10-40: The decoder circuit and its link to the memory array

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The column decoder selects a particular column in the memory array for reading the contents ofthe selected memory cell (Figure 10-41) or to modify its contents. The column selector is basedon the same principles as those of the row decoder. The major modification is that the dataflows both ways, that is either from the memory cell to the DataOut signal (Read cycle), or fromthe DataIn signal to the cell (Write cycle).

Figure 10-42 proposes an architecture based on n-channel MOS pass transistors. We considerhere 4 columns of memory cells, which requires 2 address signals Address_Col[0] andAddress_Col[1]. The n-channel MOS device is used as a switch controlled by the columnselection. When the nMOS is on and Write is asserted, (Figure 10-42) the DataIn is amplified bythe buffer, flows from the bottom to the top and reaches the memory through BL and ~BL. IfWrite is off, the 3-state inverter is in high impedance, which allows one to read the informationon DataOut.

Figure 10-41: The column selection circuit principles

Figure 10-42: Row selection and Read/Write circuit

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In many cases, the DataIn and DataOut signals have a wide format, usually 8 or 16 bits. In theschematic diagram of figure 10-43, the DataIn and DataOut bus is 2-bit wide. Only one addressline Address_Col[0] is required to select the appropriate columns. From a layout point of view,the nMOS transistors should fit the narrow width of the memory cell. This is usually done bystacking BL and ~BL pass MOS devices on the top of each other. Furthermore, the passtransistors should be designed with a large width to avoid any bad surprise at the write cycle.

A Complete 64 bit SRAM

The 64 bit SRAM memory interface is shown in figure 10-44. The 64 bits of memory areorganized in words of 4 bits, meaning that DataIn and DataOut have a 4 bit width. Each dataD0..D15 occupies 4 contiguous memory cells in the array. Four address lines are necessary todecode the one address among 16. The memory structure shown in figure 10-44 requires twoaddress lines A0 and A1 for the word lines WL[0]..WL[3] and two address lines A2 and A3 forthe bit line selection. The final layout of the 64 bit static RAM is proposed in Figure 10-45.

Figure 10-43: Row selection and Read/Write circuit with a 2-bit DataIn and DataOutinformation

Figure 10-44: The architecture of the 64 bit RAM

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Precharge Circuit

Safe read and write operations require a modification of the memory array and timingsequence, based on a precharge circuit. The usual voltage of precharge is VDD/2. Beforereading or writing to the memory, the bit lines are tied to VDD/2 using appropriate pass gates.When reading, the BL and ~BL diverge from VDD/2 (Figure 10-48) and reach the "1" and "0"levels after a short time. As the static RAM cells are based on active devices (Two ringinverters), the SRAM memories usually provide the fastest read and write access times.

Figure 10-45: The complete RAM layout

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A simple precharge circuit consists of a n-channel MOS or p-channel MOS (Both switch thevoltage VDD/2 without degradation). The drain is connected to VDD/2, the source to the bit line(Figure 10-49).

Analog Amplifier

To further speed up the read process, analog amplifiers are used. The tiny difference is rapidlyconverted into a logic level, without waiting until BL and ~BL reach their final voltage (Figure

Figure 10-48: Read cycle using a precharge circuit

Figure 10-49: Connecting a precharge circuit to all bit lines

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10-50).

The two commonly used operational amplifier designs are shown in figure 10-51. The firstamplifier is a current mirror amplifier (See chapter 11 for more details on this circuit). WhenEnable is on, the DataOut signal saturates either to a low or high level, depending on thevoltage difference VBL-V~BL. An alternative design for the operational amplifier is also proposed.

The positive feedback in the amplifier, that is the cross-coupled link between DataOut and thepMOS device permits faster sense operation than the basic circuit.

The complete logic circuit including the Write/Read control, precharge and sense amplifier isshown in figure 10-52. When the precharge is active, all bit lines are charged to VDD/2, whileall word lines are low. When the precharge is turned off, one of the world lines (WL) is active. Awrite operation (Write/Read=1) forces BL and ~BL to the desired value given by DataIn. A readoperation (Write/Read=0) turns the write buffers off, turns the sense amplifier on, whichcompares the value of BL and ~BL and gives the logic result.

Figure 10-50: Shorter read acess time thanks to a precharge circuit

Figure 10-51: Very short read access time thanks to an operational amplifier

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Figure 10-52: The sense amplifier used for read operation

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An implementation of the feedback sense amplifier is proposed in figure 10-54. The layoutincludes a portion of the 64 bit RAM, and the control logic. Parasitic loads corresponding to a1Mb implementation are added to the vertical bit lines using virtual capacitor of 0.3pF.

Figure 10-53: Layout of a portion of RAM with the controllogic and the sense amplifier

Figure 10-54: Simulation of the sense amplifier

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The simulation shown in figure 10-54 includes two Write and two Read cycles. The first writecycle (0-3ns) writes a 1 in the desired memory cell (Mem00). The reading operation (3-5ns)confirms that the memory value is "1" (ReadData[0]). The second write cycle (5-8ns) writes a 0in the desired memory cell (Mem00). The reading operation (8-10ns) confirms that the memoryvalue is "0" (ReadData[0]). Notice that the write operation (Write/Read=1) forces BL and ~BLto the desired value given by DataIn. The precharge effect is clearly seen during the readoperation.

CMOS Design > Memories > A 64 Bit Static RAM

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Dynamic RAM

The dynamic RAM memory has only one transistor, in order to improve by almost one order ofmagnitude the memory matrix density. The storage element is no more the stable inverter loopas for the static RAM, but only a capacitor Cs, also called the storage capacitor. The DRAM cellarchitecture is shown in figure 10-56.

The write and hold operation for a "1" is shown in figure 10-57. The data is set on the bit line,the word line is then activated and Cs is charged. As the pass transistor is n-type, the analogvalue reaches VDD-Vt. When WL is inactive, the storage capacitor Cs holds the "1".

CMOS Design > Memories

Figure 10-56: The 1 transistordynamic RAM cell

Figure 10-57: Simulation of the Write cycle for the 1 transistor dynamic RAM cell

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The reading cycle is destructive for the stored information. Suppose (Figure 10-58) that Csholds a 1. The bit line is precharged to a voltage Vp (Usually around VDD/2). When the wordline is active, a communication is established between the bit line, loaded by capacitor CBL, andthe memory, loaded by capacitor CS. The charges are shared between these nodes, and theresult is a small increase of the voltage Vp by V, thanks to the injection of some charges fromthe memory. Now, if the Cs was holding a zero, the activation of the word line result in a smalldecrease of the precharge voltage, to Vp - V.

In summary, the bit line voltage Vp+ V means that the memory state was 1, the voltage Vp- Vmeans that the memory state was 0. We say "was" because the memory information isdestroyed by the reading cycle. What the DRAM memory must do is to convert the +/- V into1/0, and rewrite the memory for a future read cycle.

DRAM Memory Cell

The DRAM memory cell should be as small as possible, but with the highest possible value forthe storage capacitor Cs. The first idea, shown in figure 10-59, consists in using the parasiticjunction capacitance as the storage capacitor Cs. The polysilicon gate is shared by all word linesin the same row, and the metal interconnect is shared by all bit lines in the same column. Thecapacitor Cs is around 0.1fF in 0.12µm technology. Notice that the bit line contact may beshared by two memory cells to improve the density.

Figure 10-58: Simulation of the Read cycle for the 1 transistor dynamicRAM cell

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There are two main problems with this design: first, the capacitance is very small, because thejunction capacitance do not have a very high value, second, a leakage exists between thecapacitor Cs and the bit line, through the access transistor, even when a zero voltage is appliedon the bit line. Consequently, the charges stored in the capacitor tend to disappear, whichmeans that the memory information is retained only for less than one µsecond (Figure 10-60).

The leakage current may be reduced by using low leakage MOS devices, non-minimal channellength, but the best technique is to increase by 2 or 3 orders of magnitude the storagecapacitor. Commercial Dynamic RAM memories use storage capacitors with a value between10fF and 50fF. This is done by creating a stacked capacitor for the storage node (Figure 10-61),

Figure 10-59: A DRAM memory design using parasitic junction capacitance

Figure 10-60: Leakage current in the dynamic RAMbased on a junction capacitance

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thanks to the following technological advances: use of specific buried layer to create a highquality capacitor, enlarged plate area thanks to a thicker distance between the substrate surfaceand metal1, and a 3D construction of the capacitor, and use of high permittivity dielectric oxide.The silicon dioxide SiO2 has a relative permittivity r of 3.9. Other oxides are also compatible

with the CMOS process: the Si3N4 ( r =7), and Ta2O5 ( r =23).

The drawback of these methods is the addition of specific process steps to build the 3Dcapacitor, including delicate fabrication of high dielectric materials. The additional processingsteps for the embedded DRAM represent approximately a 25% cost over the basic process. InMicrowind, the high capacitance memory can be generated using the option layer, as shown infigure 10-62. The option layer is placed at the intersection of the n-diffusion area and the VSSmetal line.

Figure 10-61: Increasing the storage capacitance (Left: junction capacitor, right, embeddedcapacitor)

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Figure 10-62: The option layer configured for the embeddedcapacitor

Figure 10-63: Cross-section of the DRAM cell with anembedded capacitor

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The cross-section of the DRAM capacitor is given in figure 10-63. The bit line is routed inmetal2, and is connected to the cell through a metal1 and diffusion contact. The word line is thepolysilicon gate. On the right side, the storage capacitor is a sandwich of conductor materialconnected to the diffusion, a thin oxide (SiO2 in this case) and a second conductor that fills thecapacitor and is connected to ground by a contact to the first level of metal. The capacitance isaround 20fF is this design. Higher capacitance values may be obtained using larger option layerareas, at the price of a lower cell density. A DRAM array is shown in figure 10-64, together witha vertical cross-section at the capacitor location.

Figure 10-64: The stacked capacitor cell compared to the diffusion capacitor cell

CMOS Design > Memories > Dynamic RAM

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ROM Memory

The most simple non-volatile memory consists of a layout in which the data is permanentlywritten through a specific layout arrangement and cannot be change by the user oncefabricated. The two logic states are shown in figure 10-67. The basic patterns for a "1"' canconsist of the existence of a n-channel MOS, the "0" by an open circuit. The logic programmingis part of the fabrication process. ROM memories are used for storing microprocessor programs,mathematical values such as a sampled sinusoidal data for waveform generators, etc.. The sizeof ROM memories is usually small as compared to other embedded memories, because thecontents cannot be changed.

We may create an array of ROM memory that stores the string "Hello!", which corresponds tothe following binary data stream (Table 10-2).

CMOS Design > Memories

Figure 10-67: Changing the status of the memory point by a diffusionlayer

Address Character ASCII code in hexadecimal Equivalent in binary

00 " " 0x20 0b00100000

00 "h" 0x68 0b01101000

01 "e" 0x65 0b01100101

02 "l" 0x6C 0b01101100

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The ROM architecture proposed in figure 10-68 is a NOR-like circuit [Haraszti]. The upper PMOStransistor precharges the vertical bit lines to VDD. Depending on the address, a high voltage isapplied on one word line (WL[1] in the example), while all other word lines are kept a lowpotential. The selected word line turns all programmed transistors on, which result in adischarge towards VSS, while bit lines with unprogrammed transistors remain on high voltage.The inverters situated on the lower part of the ROM array refresh and invert the bit lineinformation, which is sent to the display. Notice that the precharge effect is not simulated atlogic level. When the precharge is off, all bit line nodes are considered in 3-state, without anyconsideration of a "low 3-state" level or "high 3-state" level, which is supported in professionallogic simulators.

In DSCH, the hexadecimal display has been configured to display the character corresponding tothe ASCII input information (Figure 10-69).

03 "l" 0x6c 0b01101100

04 "o" 0x6f 0b01101111

05 "!" 0x21 0b00100001

Table 10-2: Encoding the string "Hello" in a ROM memory

Figure 10-68: Delivering the contents of the ROM memory

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Layout considerations

The basic cells shown in figure 10-70. The transistor situated on the left ("1") creates a lowresistance path between the bit line and the ground when the word line is high. The layoutcorresponding to "0" is not a transistor, as the diffusion has been removed. The polysiliconensures the continuity of the word line information, while the metal 2 ensures the continuity ofthe bit line information. The cell used for duplication in X and Y is also shown.

Figure 10-69: The hexadecimal displayconfigured in ASCII mode

Figure 10-70: The basic patterns of the ROM memory

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The duplication in X and Y can be programmed according to a binary information, through themenu shown in figure 10-71 (Edit > Duplicate X,Y in Microwind). The first step consists ingiving the desired X and Y size, 8 in this example. Secondly, we choose the layout box that willbe affected by the logic information. In our case, we select the n-diffusion box used for thechannel. The selected layout box in marked by the cross in the layout window. Finally, we enterthe desired information in hexadecimal format, and we click Fill Array to transform the stringof data into elementary binary information. After a click on Generate, the regular ROM layoutappears as shown in figure 10-72, which contains the binary version of the string " Hello! ".

Figure 10-71: Programming the ROM memory during the duplication phase

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Figure 10-72: The ROM memory stores the string"Hello!" in binary format

Figure 10-73: The ROM memory cross-section

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The cross-section (Figure 10-73) reveals the diffusion programming which creates or not thepath to ground. If no channel is fabricated, the memory cell is equal to a zero. When thechannel exists, the memory cell is equal to a one.

CMOS Design > Memories > ROM Memory

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EEPROM Memory

l Double-Gate MOSl Double-Gate MOS Layoutl Double-Gate MOS Chargel Double-Gate MOS Discharge

Double-Gate MOS

The basic element of an EEPROM (Electrically Erasable PROM) memory is the floating-gatetransistor. The concept was introduced several years ago for the EPROM (Erasable PROM). It isbased on the possibility of trapping electrons in an isolated polysilicon layer placed between thechannel and the controlled gate. The charges have a direct impact on the threshold voltage of adouble-gate device. When there is no charge in the floating gate (Figure 10-74, upper part), thethreshold voltage is low, meaning that a significant current may flow between the source andthe drain, if a high voltage is applied on the gate. However, the channel is small as compared toa regular MOS, and the Ion current is 3 to 5 times lower, for the same channel size.

When charges are trapped in the floating polysilicon layer (Figure 10-74, lower part), thethreshold voltage is high, almost no current flows through the device, independently of the gatevalue. Data retention is a key feature of EEPROM, as it must be guaranteed for a wide range oftemperatures and operating conditions. Optimum electrical properties of the ultra thin gateoxide and inter-gate oxide are critical for data retention. The typical data retention of anEEPROM is 10 years.

CMOS Design > Memories

Figure 10-74: The two states of the double gate MOS

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Double-Gate MOS Layout

Figure 10-75: The double gate MOS generated by Microwind

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The double gate MOS layout is shown in figure 10-75. The structure is very similar to the n-channel MOS device, except for the supplementary poly2 layer on the top of the polysilicon. Thelower polysilicon is unconnected, resulting in a floating node. Only the poly2 upper gate isconnected to a metal layer through a poly2/metal contact, situated on the top. The cross-section of figure 10-77 reveals the stacked poly/poly2 structure, with a thin oxide in between.

Double-Gate MOS Charge

The programming of a double-poly transistor involves the transfer of electrons from the sourceto the floating gate through the thin oxide (Figure 10-78). Notice the high drain voltage (3V)which is necessary to transfer to some electrons enough temperature to become "hot"electrons, and the very high gate control to attract some of these hot electrons to the floatingpoly through the ultra thin gate oxide. The very high voltage varies from 7V to 12V, dependingon the technology. Notice the "++" symbols attached to the upper gate and drain regions,which indicate that a voltage higher than the nominal supply are used.

Figure 10-76: Cross-section of the double gate MOS

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Double-Gate MOS Discharge

The floating gate may be discharged by ultra violet light exposure or by electrical erasure. TheU.V. technique is an heritage of the EPROM, which requires a specific package with a window toexpose the memory bank to the specific light. The process is very slow (Around 20mn). Afterthe U.V exposure, the threshold voltage of the double gate MOS returns to its low value whichenables again the current to flow (Figure 10-80).

Figure 10-78: The floating gate is charged with hotelectrons thanks to a tunneling effect through the

ultra-thin gate oxide

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In Microwind, the command Simulate > U.V exposure to discharge floating gatessimulates the exposure of all double gate MOS to an ultra violet light source. At the end of thesimulation (Which takes 10 seconds instead of 20 minutes in reality!), all floating gates of thelayout are discharged. Alternatively, the charge contained in the floating gate can be accessedindividually using the command Simulate > Mos characteristics. On the right lower corner ofthe device characteristics, a cursor named Charge appears, representing the amount ofelectrons stored in the floating gate. Changing the cursor position (Which corresponds in figure10-81 to the minimum charge of electrons) modifies dynamically the MOS characteristics.

Figure 10-80: The floating gate may be discharged by U.V lightexposure

Figure 10-81: Access tothe double gate electron

charge

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For the electrical erase operation, the poly2 gate is grounded and a high voltage (Around 8V) isapplied to the source. Electrons are pulled off the floating gate thanks to the high electrical fieldbetween the source and the floating gate. This charge transfer is called Fowler-Nordheimelectron tunneling (Figure 10-82).

Figure 10-82: Discharging the double gate MOSdevice

CMOS Design > Memories > EEPROM Memory

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Flash Memories

Flash memories are a variation of EEPROM memories. Flash arrays can be programmedelectrically bit-by-bit but can only be erased by blocks. Flash memories are based on a singledouble poly MOS device, without any selection transistor (Figure 10-85). The immediateconsequence is a more simple design, which leads to a more compact memory array and moredense structures. Flash memories are commonly used in micro-controllers for the storage ofapplication code, which gives the advantage of non volatile memories and the possibility ofreconfiguring and updating the code many times.

The main characteristics of the Flash memory are given in figure 10-85. Assuming that thefloating gate may be charged or discharged, the reading operation consists applying a VDDvoltage on the control gate, and a ground on the source (WL). The bit line drops to 0 if the gateis discharged, or remains in high impedance if the gate is charged. The charge is selective as itdepends on the applied information on the vertical bit line: a VDD value provokes chargeinjection, while a VSS value disables hot electron effect. The charge effect requires a highvoltage HVDD on the control gates. Finally, the discharge is common to all double-gate MOSdevices as soon as a high voltage HVDD is applied to the source. This is the main difference ascompared to EEPROM cells, where the high voltage was applied or not to the double-gatedevice, depending on the pass transistor.

Flash Memory Layout

CMOS Design > Memories

Figure 10-85: The flash memory point and the principles forcharge/discharge

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The Flash memory point has usually a "T-shape", due to an increased size of the source foroptimum tunneling effect [Sharma]. The horizontal polysilicon2 is the bit line, the verticalmetal2 is the word line which links all drain regions together. The horizontal metal line links allsources together. It is a common practice to violate usual design rules, in order to achieve morecompact layout. In the case of figure 10-86, the poly extension is reduced from 3 lambda to 2lambda. An example of 8x8 bit Flash memory array is shown in figure 10-87.

Figure 10-86: The flash memory point and the associated cross-section

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Figure 10-87: The flash memory bank consisting of 8x8 memory cells

CMOS Design > Memories > Flash Memories

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Classification

A summary of CMOS embedded memory performances is given in table 10-2. The typicalmemory bank capacity gives an advantage to the ROM, EPROM, EEPROM and Flash memories,which is directly correlated with the cell area. The reading and writing performances vary verysignificantly, as well as the retention of data. Dynamic RAM (DRAM) are slow but compact.Static RAM (SRAM) are fast but large. Reading the information from a passive capacitor, such asin DRAM, is much slower that reading the information from the active inverter-based memorysuch as in SRAM. In contrast, a single trench of stacked capacitor requires much less siliconsurface than a 2-inverter memory structure, at the cost of 8 supplementary process steps. TheFLASH memories combine a small area, an acceptable reading cycle and interesting non-volatilecapabilities, at the price of a slow writing process (1µs). Promising performances are achievedby ferroelectric RAM (FRAM) which are the most advanced of non-volatile challengers. FRAMhave endurance writing/erasing cycles comparable to the best memories, with fast reading andwriting cycles, and require only two additional process masks.

CMOS Design > Memories

Memorytype

TypicalCapacity

Cellarea

Reading Writing Cycles RetentionProcess

complexityHigh

voltage

ROM 32MbVerysmall

Medium Impossible 0 No limit 0 no

EPROM 16MbVerysmall

SlowExtremely

slow1-10 >30 YEARS 3 yes

E2PROM 1Mb Large Slow Very slow1E5-1E7

>10 YEARS 4 no

FLASH 16MbVerysmall

Medium Very slow1E4-1E5

>10 YEARS 4 yes

FRAM 4Mb Small Fast Fast1E12-1E15

>10 YEARS 2 no

eDRAM 32Mb Small Slow Fast >1E15Volatile,needs torefresh

8 no

SRAM 4Mb Large Very fast Very fast >1E15 Volatile 0 no

Table 10-2: A classification of embedded memories according to their performances

CMOS Design > Memories > Classification

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Conclusion

This chapter has focused on memories, which are a very important part of modern integratedcircuits. The static memory has been described first, with an illustration of design challengesand dangers in the case of five-transistor architecture. The 6-transistor cell has been presentedtogether with some layout optimization techniques to achieve the most compact memorydesign. The column and row selection circuits have been rapidly described, as well as the senseamplifiers used to speed up the read cycle. The principles and technological challenges relatedto the dynamic RAM have been introduced, with focus on the embedded stacked capacitor. TheROM memory has also been introduced. Extensive details on the EEPROM memory and itsFLASH derivative have been provided in this chapter. Finally, we introduced the principles andlayout implementation of the ferro-electric RAM memory (FRAM), and concluded by adescription of the asynchronous and synchronous memory interfaces.

CMOS Design > Memories

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I/O Interface

l Digital Outputl Digital output with programmable currentl Digital output with pull-upl Analog Outputl Output for CAN bus (automative)l Input

We give here some details about input-output pad structure. The basic bonding pad size is100x100µm. The pad consists of a sandwich of metal layers. For advanced technologies, allmetal layers are stacked on the top of each other. The passivation oxide has been removedfrom over the pad, so that a gold connection can be fixed upon it. The input-output pad containsone input stage with a polysilicon resistor and two protection diodes. The output stage containsa chain of inverters. The last stage is a 3-state inverter so that the buffer can be turned off.

CMOS Design > I/O Interface Design

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The resistor made in diffusion has a value between 10 and 500 . Its role is to limit thecurrent.

The diodes are used to limit the input voltage between Vdd + Vt and Vss - Vt and to protectfrom electro static discharge (ESD) which may be as high as 5000V!

Digital Output

An example of output pad is shown in this figure. It only consists of a n-channel MOS and a p-channel MOS device with large width to drive large currents. The 3-state function is provided bytwo extrat MOS devices, one p-MOS on the VDD path, one n-MOS on the ground path. Whenboth pass transistors are on (Enable=1), the pad works as a normal output pad. Whenenable=0, the pad is isolated from both VDD and VSS.

Goal : To ensure that the signal is propagate out of the chip safely

l Simple: inverter + level shifter: to be compatible with external worldl 3 states: Allow to let the output in high impedance state

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Digital output with programmable current

The current drive of the output pad is an important parameters for low-power application. Usinga 2mA current limits the power dissipation but provokes low speed switching. When 2mA and4mA drivers work simultaneously, a 6mA current is available to charge and discharge the outputsignal faster, at the cost of a higher power dissipation.

Digital output with pull-up

It is usual to add a pullup device, to ensure a weak link to VDD, mainly in the case of 3-state

configuration. The pull-up ties the output to VDD through a 10K equivalent resistance at least1a times larger than the normal output MOS Ron resistance.

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Analog Output

There exist also specific pads for analog output. A susal analog pad includes a wide rangeamplifier connected as a voltage follower. Diodes are added to limit the under and over voltagestress.

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Output for CAN bus (automative)

An application-oriented i/o structure is presented here. The Control Area Network (CAN) I/O iswidely used in automative. Several specific features are included: a two-state differentialoutput, one which ties CAN-L to 1.5V, and CAN-H to 3.5V, the other state which disables thepower MOS and links the bus to a weakly tied 2.5V, almost equivalent to a high impedancestate.

Input

The input circuit of an IC always use thiht voltage logic gates, which use thick oxide to enhancethe handling of over voltage. To limit the electrostatic discharge stress, Zener Diodes and shuntresistors are commonly used.

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The effect of the Zener Diode is to limit both the overvoltage (Zener in reverse mode) and theundervoltage as shown in the simulation.

CMOS Design > I/O Interface Design > I/O Interface

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Schmidt Trigger

The Schmidt trigger is an inverter with two commutation points:

l VC1 when the input rises from 0 to VDDl VC2 when the input falls from VDD to 0

The commutation point is modified by feedback transistors N1 and P1. When the input is low,the internal node is high, so N1 ties the NMOS input structure to VDD, which shifts the

commutation point to a high value. Oppositely, when the input is high, the internal node is low,so P1 ties the PMOS network to VSS, which shifts the commutation point to a lower value VC2.

A noise added to the clock shows the trigger benefits compared to a simple inverter. While thetrigger transforms the slowly varying noisy input into a clean signal "Trigger out", the inverterswitches erroneously during the input transition, which may produce an internal glitch.

CMOS Design > I/O Interface Design

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CMOS Design > I/O Interface Design > Schmidt Trigger

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Pad Ring Structure

Core/Pad Limitation

When the active area of the chip is the main limiting factor, the pad structure may be designedin such a way that the width is large but the height is as small as possible. In that case, theoversize due to the pads is minimized. Protections are placed on both sides of the pad area. Thissituation is often called "Core Limited", and corresponds to the design shown in the figurebelow. In most pad libraries, the core limited structures have a minimum height, which oftenimplies to place the protection circuits on both sides of the pad.

When the number of pads of the chip is the main limiting factor, the situation is called "PadLimited", and corresponds to the design shown in the figure below. The pad structure may bedesigned in such a way that the width is small but the height is large. In that case, the oversizedue to the pads is minimized. Protections are placed under the pad area.

The spared silicon area may be avoided by using a double pair of I/O pads, as illustrated in

CMOS Design > I/O Interface Design

Chip size fixed by the core

Chip size fixed by the number of pads

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figure 14-64. This attractive feature has been made available starting 0.25µm technology. Anexample of a test-chip using a double pad ring is reported that figure, which corresponds to aCMOS 0.18µm test-chip fabricated by ST-Microelectronics for research purpose. The pad pitch issignificantly reduced thanks to the double row of bonding pads. The pad pitch for a single row isthe sum of the minimum pad width Rp01 and the pad distance Rp02. In the double ringstructure, the pad pitch is divided by a factor of 2.

When the chip is pad limited, an interesting feature introduced in 0.18µm technology is thedouble ring of i/o pads. The pad pitch is twice smaller than a single pad ring, at the price of alittle increase in the pad height.

CMOS Design > I/O Interface Design > Pad Ring Structure

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Execises

CMOS Design > Execises

CMOS Design > Execises

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