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Joseph A. Elias, PhD 1

Class 10: CMOS Gate Design

Topics:1. Exclusive OR Implementation2. Exclusive OR Carry Circuit3. PMOS Carry Circuit Equivalent

4. CMOS Full-Adder 5. NAND, NOR Gate Considerations6. Logic Example7. Logic Negation8. Mapping Logic 09. Equivalent Circuits10. Fan-In and Fan-Out11. Rise Delay Time12. Rise Delay Time13. Rise Delay Time14. Fall Delay Time

15. Equal Delays

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Joseph A. Elias, PhD 2

Class 10: CMOS Gate DesignExclusive OR Design (Martin c4.5)

Similar to how one derives a2-input XOR (Martin, p.183)using (a+b)=(ab) (ab)=(a+b)

a XOR b= ab + ab= aa + ab + ab + bb= a(a+b) + b(a+b)= (a+b)(a+b)

= (ab)(a+b)= (ab + (ab) )= (ab + (a + b) )

3-input XOR Truth Table

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Joseph A. Elias, PhD 3

Class 10: CMOS Gate DesignExclusive OR Carry Circuit (Martin c4.5)

Vout =

NMOS realizationA in parallel with BA||B in series with CAB in parallel with (A||B)C

PMOS equivalentA in series with BAB in parallel with CA||B in series with (AB)||C

7/27/2019 CMOS Gate Design

4/16Joseph A. Elias, PhD 4

Class 10: CMOS Gate DesignPMOS Carry Circuit Equivalent (Martin c4.5)

Martin indicates equivalency between these circuitsIs this true?

(AB+C)(A+B) = (A+B)C + (AB)ABA + ABB + AC + BC = AC +BC +ABAB + AB + AC + BC = AC + BC + AB

AB + AC + BC = AB + AC + BC equivalent

7/27/2019 CMOS Gate Design

5/16Joseph A. Elias, PhD 5

Class 10: CMOS Gate DesignCMOS Full-Adder (Martin c4.5)

Carry: (A+B)C + AB

Sum: (A+B+C) Carry + ABC

7/27/2019 CMOS Gate Design

6/16Joseph A. Elias, PhD 6

Class 10: CMOS Gate Design NAND, NOR Gate Considerations (Martin c4.5)

NAND is preferable to NOR - why?

What makes p-ch undesirable?How does one compensate for it?

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Joseph A. Elias, PhD 7

Class 10: CMOS Gate DesignLogic Example (Martin c4.5)

Desired Truth Table Corresponding Karnaugh Map

Grouping of 1 (meaning what gates?):

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Joseph A. Elias, PhD 8

Class 10: CMOS Gate DesignLogic Negation (Martin c4.5)

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Joseph A. Elias, PhD 9

Class 10: CMOS Gate DesignMapping Logic 0 (Martin c4.5)

Using (ab)=(a+b)

Choice of which map to use depends on whether inputs are negated

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Joseph A. Elias, PhD 10

Class 10: CMOS Gate DesignEquivalent Circuits (Martin c4.5)

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Joseph A. Elias, PhD 11

Class 10: CMOS Gate DesignFan-In and Fan-Out (Weste p264-267)

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Joseph A. Elias, PhD 12

Class 10: CMOS Gate DesignRise Delay Time (Weste p264-267)

Rise time delay

where

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Joseph A. Elias, PhD 13

Class 10: CMOS Gate DesignRise Delay Time (Weste p264-267)

Re-writing

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Joseph A. Elias, PhD 14

Class 10: CMOS Gate DesignRise Delay Time (Weste p264-267)

Has the form:

where

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Joseph A. Elias, PhD 15

Class 10: CMOS Gate DesignFall Delay Time (Weste p264-267)

Similar to rise time delay, the fall time delay as afunction of fan-in and fan-out:

Assuming equal-sized gates (n/p size fixed) is the case(as in standard cells and gate arrays)

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Joseph A. Elias, PhD 16

Class 10: CMOS Gate DesignEqual Delays (Weste p264-267)

Assuming equal delays gives

Where the beta ratios are

So p-ch would be made ( n / m p) times wider for equal rise and fall delay