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CMOS Inverters

João Canas Ferreira

University of do PortoFaculty of Engineering

March 2016

Topics

1 Static behavior

2 Dynamic behavior

3 Inverter chains

João Canas Ferreira (FEUP) CMOS Inverters March 2016 2 / 31

The CMOS inverter

Contacts

Polysilicon


First order analysis

VOL = 0VOH = VDD

VM = f (Rn, Rp)


Constructing the voltage transfer characteristic (1/2)

Source: [Rabaey03]


Constructing the voltage transfer characteristic (1/2) (2/2)

Source: [Rabaey03]


VTC of the CMOS transistor

Source: [Rabaey03]


Operating regions of the CMOS inverter

à Summary of operating regions:

Condition pMos nMos

A 0 6 Vin < VTn linear cut-offB VTn 6 Vin < VDD/2 linear saturationC Vin = VDD/2 saturation saturationD VDD/2 < Vin 6 VDD − |VTp| saturation linearE Vin > VDD − |VTp| cut-off linear

à IDD = |IDSp| = IDSn

Source: [Weste11]


Finding the commutation point VMà Condition determining VM (ignoring channel modulation):

knVDSATn

(VM − VTn −

VDSATn

2

)+ kpVDSATp

(VM − VDD − VTp −

VDSATp

2

)= 0

à Solving for VM:

VM =

(VTn +

VDSATn2

)+ r(

VDD + VTp +VDSATp

2

)1 + r

em que

r =kpVDSATp

knVDSATn

For “high” values of VDD we have:

VM ≈r VDD

1 + rSource: [Rabaey03]


Inverter gain g

à Must take channel modulation into account.

g = −1

IDS(VM)

knVDSATn + kpVDSATp

λn − λp

g ≈ 1 + r(VM − VTn − VDSATn/2)(λn − λp)

Source: [Rabaey03]


Finding VIH and VIL

à Using the simplified (linear) model of the VTC:

VIH − VIL = −VOH − VOL

g=

−VDD

g

VIH = VM−VM

gVIL = VM+

VDD − VM

g

NMH = VDD − VIH NML = VIL

Source: [Rabaey03]


Topics

1 Static behavior

2 Dynamic behavior

3 Inverter chains


Propagation delay: current source modelà Average current calculated as average value of (for VGS= VDD):

1 IDS(VDS= VDD) [saturation]2 IDS(VDS=VDD/2) [linear]

Source: [Rabaey03]

tpHL ≈12

CLVswing

Imed≈ CL

knVDD

with

Imed =kn

2(VDD − VTn)

2

(long channel approximation)


Propagation delay: equivalent resistance model

Source: [Rabaey03]

tpHL = f(Reqn, CL)

tpHL = 0.69 ReqnCL

tpLH = f(Reqp, CL)

tpLH = 0.69 ReqpCL


Calculating tpHL

à Average resistance for a variation of VDS(=Vout) between VDDand VDD/2

Req =1

−VDD/2

∫ VDD

VDD/2

VIDSAT(1 + λV

dV

à Simplifying

Req ≈34

VDD

IDSAT

(1 −

79λVDD

)with

com IDSAT = k ′WL

((VDD − VT)VDSAT −

V2DSAT

2

)à For tpHL:

tpHL = ln(2)ReqnCL = 0.69ReqnCL


Transient response (simulation)

Source: [Rabaey03]

tp = 0.69 CLReqn + Reqp

2


Propagation delay as a function of VDDà Using λ = 0:

tpHL = 0.6934

CLVDD

IDSATn= 0.52

CLVDD

(W/L)nk ′nVDSATn(VDD − VTn − VDSATn/2)

(red dots on the graph)

Source: [Rabaey03]

à Simplifying further:

delay is independent of VDD

tpHL ≈ 0.52CL

(W/L)n k ′n VDSATn


Size of the fastest transistor (asymmetric)à A larger pMOS benefits tpLH but degrades tpHL. (Why?)

à Scenario: inverter 1 drives inverter 2 of the same size.Optimal size (width)?

Source: [Rabaey03]

β =(W/L)p(W/L)n

=Wp

Wn

Ln

Lp=

Wp

Wn

βopt =

√r(

1 +Cw

Cdn1 + Cgn2

)à r: ratio of equivalent resistances for

transistors of the same size

r = Reqp/Reqn

à Ignoring the wire capacitance:

βopt ≈√

r


Finding the best βà Load capacitance of inverter 1 (which drives inverter 2, of the same size):drain capacitance of the transistors of inverter 1 + gate capacitance of thetransistors of inverter 2 + wire capacitance

CL = (Cdp1 + Cdn1) + (Cgp2 + Cgn2) + Cw

à Assuming: Cdp1 ≈ βCdn1 e Cgp2 ≈ βCgn2

tp =0.69

2

((1 + β)(Cdn1 + Cgn2) + Cw

)(Reqn +

Reqp

β

)

tp = 0.345((1 + β)(Cdn1 + Cgn2) + Cw

)Reqn

(1 +

rβ

)à To get the optimal β:

δtpδβ

= 0


Impact of input rise time on propagation delay

Source: [Rabaey03]

à tr: rise time of the input (10 %→ 90 %)à Empirical formula:

tpHL =√

t2pHL(step) + (tr/2)2


Topics

1 Static behavior

2 Dynamic behavior

3 Inverter chains


Inverter chain

à Calculating the propagation delay in a circuit

Source: [Rabaey03]

à Given CL, the problem is:I What is the optimal number of stages to minimize thr propagation delay

along the chain?

I Best inverter sizes?→ Find all values of W for L = Lmin


Inverter loadà Assume balanced inverter: pull-up and pull-down have the samecharacteristics:

I similar resistances: Reqn = Reqp

I similar output rise/fall times (propagation delays): tpHL = tpLH

tp = 0.69Req(Cint + Cext)

à Rearranging:

tp = 0.69ReqCint

(1 +

Cext

Cint

)= tp0

(1 +

Cext

Cint

)Cint intrinsic capacitance

Cext extrinsic capacitance: wires and gates of other transistors(fan-out)

tp0 intrinsic delay (no load)


Relationship between propagation delay and relative size

à Scenrio: inverter is larger by S: (width W → S × Wref)à minimum symmetric inverter is the reference

Cint = S × Cintref and Req =Reqref

Sà Therefore:

tp = 0.69Reqref

S(S × Cintref)

(1 +

Cext

S × Cintref

)à For an inverter that is S times bigger:

tp = 0.69 Reqref Cintref

(1 +

Cext

S × Cintref

)= tp0

(1 +

Cext

S × Cintref

)à tp0 is independent of transistor size


Effective fan-out

à Technological parameter γ:

Cint = γ Cgin

à Nowadays: γ ≈ 1

à Effective fan-out

f =CL

Cgin

à The propagation delay is a linear function of the effective fan-out

tp = tp0

(1 +

Cext

γ Cgin

)= tp0

(1 +

fγ

)


Sizing for a fixed number of stagesà For a chain of N inverters:

I Delay equation (sum of the delays) has N − 1 unknowns: Cgin,2 to Cgin,N

à To find the minimum delay:1 find N − 1 partial derivatives in order to each of the unknowns;2 impose that all partial derivatives are equal to zero.

à For the optimal situation, we have:

Cgin,j+1

Cgin,j=

Cgin,j

Cgin,j-1

Cgin,j =√

Cgin,j-1 Cgin,j+1

I Size of each inverter (input capacitance) is the geometric mean of thesize of the neighbors.

I Each stage has the same effective fan-out efetivo.I Each stage has the same delay.


Minimum delay and number of stages

à In the optimal situation:I Each stage has the same effective fan-out fI f = S, the scale factor between neighboring inverters

à For a chain with N inverters:

f = N

√CL

Cgin,1=

N√

F

F is the global effective fan-out.

à The minimum delay can be found without (!) sizing the inverters:

tp = N× tp0

(1 +

N√

Fγ

)


Optimal number of stages

à Problem: Given CL and Cin = Cgin,1, find the best f .

CL = F × Cin = f N × Cin with N =ln(F)ln(f )

à Take the derivative of tpin order to N and equal to zero.à Result:

γ+N√

F −N√

F × ln(F)N

= 0

Equivalently:f = e(1+γ/f)

à For γ = 0, the solution is easy:

f = e, so N = ln(F)

à For γ 6= 0, solve the equation numerically (by iteration) or graphically.


Optimal effective fan-out (graph)

2.5

3

3.5

4

4.5

5

0 0.5 1 1.5 2 2.5 3

fopt

γ

à For γ = 1, we have fopt = 3.6. With this value, you can now find N.à Commonly: f = 4.


Comparing propagation times for different chain lengths

à If optimal sizes are used of for N stages:

tptp0

= N×

(1 +

N√

Fγ

)

à Table of tp/tp0 as a function of the global effective fan-out F(optimal relative delay for each N):

F N = 1 N = 2 Optimal N

10 11 8.3 8.3100 191 22 16.51000 1001 65 24.810000 10001 202 33.1


References

à The figures come from the following books:

Rabaey03 J. M. Rabaey et al, Digital Integrated Circuits, 2ndedition,Prentice Hall, 2003.http://bwrc.eecs.berkeley.edu/icbook/

Weste11 N. Weste, D. Harris, CMOS VLSI Design, 4th edition, PearsonEducation, 2011.http://www3.hmc.edu/~harris/cmosvlsi/4e/index.html


http://bwrc.eecs.berkeley.edu/icbook/

http://www3.hmc.edu/~harris/cmosvlsi/4e/index.html

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