Cmos invetret

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On the Design of CMOS Current Conveyors

Ivars G. Finvers1, Brent J. Maundy1, Ibiyemi A. Omole1 and Peter Aronhime2

1Department of Electrical and Computer Engineering

University of Calgary T2N 1N4

2Electrical Engineering Dept.,

University of Louisville, Louisville, KY 40292, USA

Email: [email protected]

Abstract

A general method for converting an operational amplifier into a second-generation current

conveyor is described in this paper. This method applies to a wide variety of types of op-amps.

It is illustrated by an in-depth analysis of a current conveyor constructed from a simple two-stage

op-amp with compensation. The method circumvents the use of more transistors between the

power rails than those inherent in the op-amp used, and the resulting current conveyors have a

low impedance X-input, high impedance Y-input, and a unity current transfer between the X and

Z nodes over the entire range from DC to approximately the unity gain frequency of the op-amp.

It is shown that several other designs of CCIIs that have been presented in the literature can also

be considered as applications of this design approach, thereby demonstrating the generality of

this method. Theoretical results are confirmed using HSPICE.


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1. Introduction

The second-generation current conveyor (CCII) in recent years has proven to be a useful

building block for active filter design and signal processing applications [1-5]. A block diagram

of a current conveyor is shown in Fig. 1. In it the low-impedance X input node follows the

voltage on the high impedance Yinput node. Assume for now that the resistance rin,x is small.

The current flowing into (CCII+) or out of (CCII-) the Z node is proportional to the current

flowing into theXnode. Ideally, therefore the following relationship holds for a CCII,

v

i

i

i

v

v

x

y

z

x

y

z

=

0 1 0

0 0 0

1 0 0

.

To date a variety of methods have been used to build CMOS CCIIs. These include

CMOS implementations of bipolar CCIIs [2-4], source follower implementations [6-9],

operational amplifier based approaches [10-14], as well as the current sensing approach [4, 15-

18]. The CMOS implementations of bipolar CCIIs utilize the translinear principle [4] to

implement the voltage following action between the Xnode and the Y node. The open loop

buffer formed in this manner typically suffers from high X node input impedance, and the

voltage following action is not accurate enough for some applications. The current sensing

approach uses current mirrors in the operational amplifier's power supply leads in order to

determine ix. The additional voltage drops associated with these mirrors are restrictive in today's

climate of diminishing power supply voltages. Source follower based buffers used in some CCII

implementations [6] have higher bandwidth than other implementations, but at the cost of poorer


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dc performance. Note generally speaking, the source follower implementation still employs an

operational amplifier coupled to a class A or AB source follower stage with current sensing. In

[19, 20] bilateral, low voltage single ended VI converters are employed to make an elegant CCII-

or CCII+. The high impedance at the Yport in [20] is lost however due to that circuits topology.

In the operational amplifier based approach, presented in simplified form in Fig. 2 a

standard operational amplifier is used to implement the unity gain buffer between the YandX

inputs. TheXinput current ix, is sensed by simply duplicating the buffer's output transistors MN

andMP using transistors M1 andM2, and extracting the X current from them as iz. Since

transistorsM1 andM2 have the same size and gate-source voltage as the output stage transistors

MN andMP, the current iz should be a copy of the current flowing through MN andMP - which is

ix. Since no additional transistors need to be inserted between the operational amplifier and the

supply rails, the approach will not increase the minimum operating voltage over that of the

operational amplifier core. In addition, the voltage follower is based on an operational amplifier

and so will maintain all the benefits (and disadvantages) of such a circuit (a good voltage

follower at the cost of lower bandwidth).

Interestingly enough this approach first proposed by [14] and variants by [10-13] has not

been exploited very often in the literature to make high quality current conveyors. This despite

the fact that it is probably the simplest and most general of the current conveyor designs.

Although the technique described above will be illustrated using a simple two stage Miller

compensated operational amplifier, we will demonstrate that a variety of CMOS operational

amplifier can be converted into a CCII- using this general method. Furthermore, a non-inverting

current conveyor (CCII+) can also be readily implemented with the addition of a pair of current

mirrors at the Z terminal.


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In [12, 14] similar approaches have been used to design the CCIIs, but in both these

instances the operational amplifier (although the use of an operational amplifier is not explicitly

noted in [12]) used to implement the unity gain buffer appears to be uncompensated. Since the

unity gain buffer is implemented as a two stage amplifier, for almost all practical

implementations, a compensation capacitor will be required to ensure stability. The lack of

proper compensation in a current conveyor is responsible for the significant peaking responses as

pointed out by [4].

The addition of the compensation capacitor potentially disrupts the current transfer from

ix to iz. At high frequencies and beyond the unity gain bandwidth of the buffer, some of the ix

current will be lost to compensation capacitorCc as well as to parasitic node capacitances. As a

result some of the ix current will be diverted from the output transistors and hence not be copied

to iz . It will, however, be shown that for lower frequencies iz tracks ix with good accuracy until

approximately the unity gain bandwidth of the buffer is reached. To maintain good tracking ofiz

with ix at the lower frequencies it is necessary that the magnitude of the open loop output

impedance of the operational amplifier be significantly higher than the magnitude of the

feedback impedance connected to the Xinput. This is necessary to minimize the portion ofix

which is lost in the output stage transistors' output impedance and therefore is not sensed.

Our contribution is two fold: First, the frequency characteristics of an operational

amplifier derived CCII- will be presented in depth. Second, a theoretical foundation for the

circuit operation is laid out, including the effects of the compensation capacitor. It will be shown

that the current conveyor formed in this way inherits the characteristics of the core operational

amplifier. Thus the results can be used to predict the frequencies at which the magnitude of the


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input impedance at port Xbegins to increase and the magnitude that the current transfer ratio

begins to deviate significantly from unity.

II. Small Signal Analysis

To demonstrate the method, a simple two stage Miller compensated amplifier was chosen

for the operational amplifier. The overall schematic of the CCII- is shown in Fig. 3. It should be

noted that the technique is quite general and can be applied to almost any CMOS operational

amplifier. The CCII- will retain the characteristics of the underlying operational amplifier.

However, in order for the operational amplifier to be easily converted to a CCII, the operational

amplifier output stage should be based on a common source design. This ensures that the gate

and source voltages setting the output current can be easily copied to the replica output stage.

For example, a source follower output stage would not be suitable for this technique, but it is

rarely used in low voltage designs.

A simplified small signal model of the operational amplifier based CCII- is shown in Fig.

4. Here g1 andg2 represent the transconductances of the first and second operational amplifier

stages respectively, while g3 = (gm1 + gm2) is the transconductance of the current copier formed

by M1 andM2, the output stage that is copied. The output conductance of the various stages is

represented by the go terms. The total parasitic capacitance on nodesx,y, andz are modeled by

C1 - C3 , while Cc is the operational amplifier's compensation capacitor. The small signal model

excludes the nulling resistor Rz of Fig. 2 to simplify the presentation of the idea and the analytic

expressions. Nevertheless, the governing expressions that will be presented are also valid for a

small value of Rz since the extra pole/zero caused by the nulling resistor will not disrupt the


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performance of the current conveyor until the frequency is in the proximity of the unity gain

bandwidth.

The operation of the CCII- is premised on iz being a copy of the ix input current. Straight

forward analysis shows that the copied current iz can be approximated by

i

g

g

sC

gi

sC

gg v

sCg

g

g

sCC

C

C

C

g g

z

cx

c

o

o y

c

c

+

+

+

++ +

3

2 1 2

2

1

2

1

12

1

2

2 1

1 1

1

1

1

1

(1)

Ignoring the error term go2y for now, if the circuit is designed such that g3 = g2, the copied

current iz ix at low frequencies as required. It will be shown that this equality is valid for

frequencies up to approximately the unity gain bandwidth of the buffer amplifier. The open loop

gainA(s) of the operational amplifier can also be approximated by

A s

g gg g

sCg

sC g

g g

s CC C

C C

gC

C C

o o

c

c

o o

c

c

c

c

( )

+

++

+

+

1 2

1 2 2

2

1 2

21

1

2

1

1

1 1

(2)

if the dominant and non-dominant poles are widely separated. The closed-loop voltage gain of

the input buffer is therefore,

A sv

v A sBUF

x

y

( ) =+ ( )

1

1 1/(3)


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+

++ +

1

1

1

1

1

2

1

2

1

12

1

2

2 1

sC

g

sCg

g

g

sCC

C

C

C

g g

c

c

c

which shares the same poles as Eq. (1). Combining Eq. (1) with Eq. (3) allows the current

transfer ratio iz / ix to be written in terms of the buffer's closed loop response, that is

i

i

g

g

A ssC

g

sCg

z

x

BUFc

c

= ( ) +

3

2

1

2

1

1

(4)

For unity gain stability, the buffer requires that g2 > g1 , andCc C1, 2 . ThereforeABUF(s) 1

below the unity gain bandwidth (UGBW) of approximately g1/Cc . Since the remaining

poles/zeros in Eq. (4) are at or above the UGBW, it is clear that for frequencies below the

buffer's UGBW, the input current ix is copied to output with a current gain of approximately

i

i

g

g

z

x

32

(5)

If therefore the current copier stage transistors are sized such that:

WL

WLN( ) = ( )1 and

WL

WLP( ) = ( )2

then iz / ix - 1 below the buffer's unity gain frequency. Therefore a copy of the input current ix

has been generated as required for a CCII-.


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The above result has one shortcoming; it ignores the error term in Eq. (1) due to y.

When a signal is applied to the non-inverting Yterminal, the voltage on theXterminal will track

that of the Yterminal. Due to the finite output resistance of the buffer's output stage, some of the

ix current flowing into the X terminal in this mode will be lost in the output resistance and not

copied to iz . The error term go2 y in Eq. (1) represents the current lost in the buffer's output

conductance go2, which is usually small compared to ix. Redoing the previous work with the y

term included, a more accurate expression for the CCII- transfer function (it now has both a

transconductance and a current gain component) can be obtained; that is

i i g vz x o y= ( )2 (6)

Usually, the simplified form iz = - ix is sufficient for most calculations since the error term tends

to be of negligible consequence on the performance of the device for the desired frequency

range.

TheXterminal's input resistance rin,x is frequency dependent even though it is generally

of a low value. Appropriate analysis reveals that rin,x is approximated by

r

g

g g

s C C

g

sCg

g

g

sCC

C

C

C

g g

in x

o

o

c

c

, +

+( )

+

++ +

1

1 2

1 2

1

1

2

1

12

1

2

2 1

1

1

1

1

1

(7)

=+

+( )

g

g g

A ss C C

g

sC

g

o

BUF

c

o

c

1

1 2

1

1

2

1

1

( )


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Thus for low frequencies, theXterminal's input resistance is approximately equal to

r

g g gin x

o

, 1 1

2 1 1

.

For most operational amplifiers, good performance implies a large second stage

transconductance g2, and a high first stage (DC) gain g go1 1 . Therefore a low rin,x will naturally

follow. Note that the poles of rin,x are the same as those of the input buffer which is to be

expected since the operational amplifier functions as a buffer.

III. Mis-Match Effects

It is worth mentioning the effects due to mismatch in the transistors M1-2 and MN-P. The

accuracy of the current transfer ratio as derived in Eq. (5) relies heavily on g2 = g3. In practice

the ratio of the transconductances will not be equal and errors will occur due to first and second

order effects in processing any VLSI layout, as well as electrical error effects. While a full

treatment of process parameter variation is beyond this paper, suffice to say parameters such as

gate oxide thickness and, lateral diffusion and oxide charge density will affect the performance

of copying transistors. In that case layout methods such as the common centroid approach,

interdigitization, and dummy elements can be used to reduce significantly the error in current

copying [21]. Finally, in so far as electrical effects are concerned, for sub-micron processes

increasing the channel length of the transistors will also serve to reduce channel length

modulation effects and threshold variation effects. Increasing the overdrive voltage on

transistors M1-2 and MN-P will also reduce the current copying error and harmonic distortion, but

at the expense of mobility degradation, and reduced transconductance [21].


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IV. Simulation Results

To verify the results from the previous section, a Miller two stage compensated

operational amplifier along with a selection of designs of operational amplifiers from the

literature were used to make the buffer required in the transformation process to the CCII-. The

other designs used included a push-pull operational amplifier design [22], a cascode output

operational amplifier [22], and a class AB input stage operational amplifier design [7] as

examples of various operational amplifier structures. All the operational amplifiers were

designed to work with a 3V supply. The designs were simulated in a 0.35m CMOS process

with all the operational amplifiers having a unity gain bandwidth of approximately 10MHz.

Simulations were carried out with HSPICE using a level 28 model. The aspect ratios of all the

transistors used in the designs are shown on the corresponding figures. Transistor parameters

used for analytical calculations were extracted from the simulations. The key parameters were

Kn = 156 A/V2, Kp = 59 A/V

2, VTp = 0.71 V, and VTn = 0.57 V. Bulk effects were found to

have little effect in all the simulations. Further comparisons were made between the simulated

responses from HSPICE with Rz included and the theoretical responses from Matlab for the

Miller compensated operational amplifier in order to verify the validity of the technique, the

approximations made and the expressions presented.

Fig. 5 shows both the simulated and theoretical responses of the Miller compensated two

stage operational amplifier based current conveyor in terms of the open-loop gain A(s), current

transfer ratio iz/ix and the input resistance of the X terminal rin,x. The theoretical responses are

based on equations (2), (4) and (7) presented earlier in section II, and the extracted values of

transconductances and capacitances from HSPICE. As shown in Fig. 5, the simulated response


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of the open-loop gain, A(s) tracks the theoretically expected response closely until after the unity

gain bandwidth. The current transfer ratio stays at 0dB indicating the value of |iz/ix| to be unity

until approximately the unity gain bandwidth is reached. This reveals that the circuit exhibits a

good degree of accuracy in its current following capability as is expected of a current conveyor.

Also the simulated input resistance rin,x tracks the theoretically expected response until the unity

gain bandwidth is reached. At low frequencies up to about 100kHz, rin,x stays at 3.2, and then

gradually increases with frequency to about 205 at the unity gain bandwidth frequency.

The deviation observed in the responses beyond the unity gain bandwidth result from the

effect of the nulling resistor Rz on the theoretically predicted pole/zero location in equations (4)

and (7). In the case of rin,x, an additional zero is introduced by the nulling resistor, which is in

the region of the unity gain bandwidth and can be approximated by,

sC g R C

C C Rz

r o z c

c z

in x, + +( )1 1

1

1(8)

while the poles are at and beyond the unity gain bandwidth. For the current transfer ratio, the

zero is shifted and can be approximated by

sg

C g Rz

i i

c z

z x +( )

1

11. (9)

However, the results indicate within reasonable error (< 0.2%), good tracking of the

theoretical response by the simulated response for all frequencies well below the unity gain

bandwidth, thus authenticating the validity of the technique, the approximations made and the

governing expressions presented.


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In establishing the generality of the technique, several other types of operational

amplifiers were used to implement the required buffer for the CCII-. Their designs were by no

means optimized for their best performance, but they were used to verify the general validity of

the conclusions of section II. The push-pull operational amplifier and the cascode output

operational amplifier as reported in [7], were designed to drive a 10pF load and have a unity gain

bandwidth product of 10MHz; same as that for the previously used Miller compensated two

stage operational amplifier. Moreover, to demonstrate how diversely the technique can be

applied to a variety of operational amplifiers, the Class AB operational amplifier reported in [7]

was also designed to the same specification as the other aforementioned operational amplifiers.

The class AB operational amplifier does not use a differential pair at the input and has a

relatively low open-loop gain, which results in rin,x being higher than the Miller compensated

operational amplifier of Fig. 5. The cascode example used has relatively low first stage gain

with the majority of the gain obtained from the output stage. The net result was a comparatively

low open-loop gain in the order of 66 dB, and a significant rin,x comparable to the class AB

operational amplifier design. Note because the dominant pole in the cascode design occurs at the

output, compensation can be achieved by a shunt capacitor at the output. The circuit schematics

are shown in Figs. 6, 7 and 8 and the simulated results for the current transfer ratio and the X

terminal's input resistance obtained from the current conveyor made from these three types of

operational amplifier are shown in Fig. 9(a) and Fig. 10, respectively.

As shown in Fig. 9(b), the method works well with the other types of operational

amplifiers since the current transfer ratio obtained is of unity value until around the unity gain

bandwidth. The different responses observed around and beyond the unity gain bandwidth are

due to the different poles/zero locations for the individual current conveyors that evolve from the


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different operational amplifiers. TheXterminal's input resistance rin,x of each current conveyor

is as shown in Fig. 10 with the Class AB and cascode output type having a relatively higher rin,x

but nevertheless still low in comparison with the impedance of the Y terminal.

V. Conclusion

In this paper we have demonstrated the conversion of an operational amplifier to a

second-generation current conveyor and presented the necessary theoretical foundation for the

operation of such. The observed results provided by the approximate expressions for the

theoretical location of the poles and zeroes provide useful insight into the CCII- high frequency

behavior. The conversion technique also reveals a simple way of developing a current conveyor

from any almost existing operational amplifier.

Moreover it suggests an elegant approach to making a current conveyor of good

performance that will be pertinent for use in low voltage circuits which are compatible with

today's diminishing power supply for VLSI circuits. Finally, the generality of the technique

cannot be over-emphasized as the achievable bandwidth of the resulting device is that of the

operational amplifier used in the design.


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VI. References

[1] A. Sedra and K. C. Smith, "A second generation current conveyor and its applications,"

IEEE Transactions on Circuit Theory, vol. 17, pp. 132-134, February 1970.

[2] A. S. Sedra, G. W. Roberts, and F. Gohh, "Current conveyor. History, progress and new

results," IEE Proceedings Part G: Electronic circuits and Systems, vol. 137, pp. 78-87

1990.

[3] D. C. Wadsworth, "Accurate Current Conveyor Integrated Circuit,"Electronics Letters,

vol. 25, pp. 873-874, June 1989.

[4] C. Toumazou, F. Lidgey, and D. Haigh, Analogue IC Design: The Current-Mode

Approach: IEE Press, 1990.

[5] B. Wilson, "Trends in current conveyor and current-mode amplifier design,"

International Journal of Electronics, vol. 73, pp. 573-583, September 1992.

[6] M. C. H. Cheng and C. Toumazou, "3V MOS current conveyor cell for VLSI

technology,"Electronics Letters, vol. 29, pp. 317-318, February 1993.

[7] D. D. Shulman and J. Yang, "An Analytical Model for the Transient Response of CMOS

Class AB Operational Amplifiers," IEEE Transactions on Circuits and Systems

I:Fundamental Theory and Applications, vol. 41, pp. 49-52, January 1994.

[8] W. Surakampontorn and K. Kumwachara, "CMOS-based electronically tunable current

conveyor,"Electronics Letters, vol. 28, pp. 1316-1317, July 2nd 1992.

[9] W. Surakampontorn, V. Riewruja, K. Kumwachara, and K. Dejhan, "Accurate CMOS-

based current conveyors,"IEEE Transactions on Instrumentation and Measurement, vol.

40, pp. 699-702, August 1991.


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[10] I. A. Awad and A. M. Soliman, "New CMOS realization of the CCII-," IEEE

Transactions on Circuit and Systems II: Analog and Digital Signal Processing, vol. 46,

pp. 460-463, April 1999.

[11] W. Chiu, S.-I. Liu, H.-W. Tsao, and J.-J. Chen, "CMOS differential difference current

conveyors and their applications,"IEE Proceedings: Circuits, Devices and Systems, vol.

143, pp. 91-96, April 1996.

[12] H. O. Elwan and A. M. Soliman, "Low voltage low power CMOS current conveyors,"

IEEE Transactions on Circuits and Systems I, vol. 44, pp. 828-835, September 1997.

[13] T. Laopoulos, S. Siskos, M. Bafleur, and P. Givelin, "CMOS Current Conveyor,"

Electronics Letters, vol. 28, pp. 2261-2262, November 19th 1992.

[14] S.-I. Liu, H.-W. Tsao, and J. Wu, "CCII-based continuous-time filters with reduced gain-

bandwidth sensitivity," IEE Proceedings, Part G: Electronic Circuits and Systems, vol.

138, pp. 210-216, April 1991.

[15] E. Bruun, "Differential-input, differential-output current mode operational amplifier,"

International Journal of Electronics Letters, vol. 71, pp. 1047-1056, December 1991.

[16] E. Bruun, "CMOS High Speed, high precision current conveyor and current feedback

amplifier structures,"International Journal of Electronics, vol. 74, pp. 93-100, January

1993.

[17] E. Bruun, "On dynamic range limitations of CMOS current conveyors," presented at

IEEE International Symposium on Circuits and Systems, May 30-Jun 2 1999.

[18] I. Mucha, "Fully differential, current conveyor based CMOS operational amplifier,"

International Journal of Electronics Letters, vol. 74, pp. 697-703, May 1993.


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[19] H. O. Elwan and A. M. Soliman, "Novel CMOS current conveyor realisation with an

electronically tunable current mode filter suitable for VLSI," IEEE Transactions on

Circuit and Systems II, vol. 43, pp. 663-670, September 1996.

[20] W. Surakampontorn, V. Riewruja, and F. Cheevasuvit, "Integrable CMOS-base

realization of current conveyors,"International Journal of Electronics, vol. 71, pp. 793-

798, November 1991.

[21] R. Baker, H. W. Li., and D. Boyce, CMOS: Circuit Design, Layout, and Simulation:

IEEE Press, 1998.

[22] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design: Holt, Rinehart and

Winston Inc., 1987.


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VII. Acknowledgment

The authors would like to acknowledge the support of the Natural Sciences and EngineeringResearch Council (NSERC) of Canada and the Canadian Network of Centers of Excellence in

Microelectronics (MICRONET).


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FIGURES

1

r

ZY

X

V

V

i

in,x

x

+ iz

_

+ i_x

Y

X

Figure 1 Simplified model of a CCII.

V V

V V

M

M M

+

-

ii

Z

X

Y

dd

ss

p

n

2

1

x z

dd

ss

Operational Amplifier

M

R C

zc

Figure 2 CCII- based on an operational amplifier.


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Y X Z

V

1 0 p F

C

8 0

1

8 0

1

1 4

1

1 4

1

3 5 0

1

3 5 0

1

1 2 5

1

1 2 5

1

5 0

1

5 0 A

c

b i a s

R

z

V

d d

3 5 5

MN

MP

M2

M1

V1

Figure 3 Complete schematic of a CCII- based on the two stage Miller compensated

operational amplifier.


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g

g C

Cgg

V

i

i

V

y

V

1

C

c

C

1

g

2

x

x

3

1

z

U n i t y G a i n B u f f e r

o 1

o 2

o 3

1

3

V

2

g V

1

V V

y

x

-

( )

Figure 4 Small Signal model of the operational amplifier based CCII-. The nulling resistor

Rz has been omitted to simplify the analysis.


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21

-40

-20

0

20

40

60

80

100

1 10 100 1000 104

105

106

107

108

Magnitude(dB)

Frequency (Hz)

A(s)

iz/ ix

ri n ,x

Figure 5 Simulation results for CCII based on Miller compensated two-stage operational

amplifier. Solid lines and dashed lines represent simulated and theoretical

responses, respectively. Note rin,x in dB is normalized to 1 .


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3 2

0 . 3 5

3 2

0 . 3 5

3 0

0 . 3 5

5 5 . 8

0 . 3 5

1 7 1 . 4

1

1 7 1 . 4

1

1 5 0

1

1 5 0

1

2 0

0 . 3 5

1 5

0 . 3 5

1 5

0 . 3 5

5 p F

V

b i a s

Y

X Z

V

s s

V

d d

Figure 6 The push pull operational amplifier based current conveyor.


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4 0

0 . 3 5

4 0

0 . 3 5

3 5

0 . 3 5

3 5

0 . 3 5

4 0

0 . 3 5

3 6

0 . 3 5

2 0

0 . 3 5

1 1 4

1

1 0 2 . 9

1

1 1 4

1

1 0 2 . 9

1

5 7 . 1

1

5 7 . 1

1

1 1 4

1

1 1 4

1

6 . 7

0 . 3 5

V

V

Y

X

Z

b i a s 1

b i a s 2

V

d d

V

s s

Figure 7 The cascode output operational amplifier based current conveyor.


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V

V

Y

X

Z

5 . 1

0 . 3 5

1 0 2 . 9

1 . 2

1 0 2 . 9

1 . 2

1 0 2 . 9

1 . 2

5 6 . 1

0 . 3 5

5 6 . 1

0 . 3 5

6 8 . 5

1

3 4 . 3

1 . 2

3 4 . 3

1 . 2

5 . 1

0 . 3 5

3 4 . 3

1 . 2

6 8 . 5

1

1 6 0 . 2

1

1 8 6 . 6

1

1 8 6 . 6

1

1 6 0 . 2

1

6 6 . 7

1

b i a s 1

b i a s 2

V

s s

V

d d

6 6 . 7

1

Figure 8 The Class AB operational amplifier based current conveyor.


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-10

0

10

20

30

40

1 10 100 1000 104

105

106

107

108

CurrentTransferRatio

(dB)

Frequency (Hz)

ClassAB

Push-pull

Cascode

Figure 9(a) Current transfer ratio (in dB) for Class AB operational amplifier, push pull

operational amplifier and the cascode output operational amplifier.


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0.98

0.985

0.99

0.995

1

1.005

1.01

1.015

1.02

1 10 100 1000 104

Current

TransferRatio

Frequency (Hz)

Push-pull

Cascode

ClassAB

Figure 9(b) An expanded view of the current transfer ratio of Fig. 9(a) for Class AB, push pull

and the cascode output operational amplifiers showing the low frequency errors.


27/28

27

0

20

40

60

80

1 10 100 1000 10

4

10

5

10

6

10

7

10

8

rin,x

(d

B)

Frequency (Hz)

Cascode

Class ABPush-pull

Miller Two-Stage

Figure 10 The X terminal input resistance for the Miller Compensated two-stage, Class AB,

push pull and cascode output operational amplifiers. Note rin ,x in dB is

normalized to 1 .


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Figure Captions

Figure 1 Simplified model of a CCII.

Figure 2 CCII- based on an operational amplifier.

Figure 3 Complete schematic of a CCII- based on the two stage Miller compensated

operational amplifier.

Figure 4 Small Signal model of the operational amplifier based CCII-. The nulling resistor

Rz has been omitted to simplify the analysis.

Figure 5 Simulation results for CCII based on Miller compensated two-stage operational

amplifier. Solid lines and dashed lines represent simulated and theoretical

responses, respectively. Note rin,x in dB is normalized to 1 .

Figure 6 The push pull operational amplifier based current conveyor.

Figure 7 The cascode output operational amplifier based current conveyor.

Figure 8 The Class AB operational amplifier based current conveyor.

Figure 9(a) Current transfer ratio (in dB) for Class AB operational amplifier, push pull

operational amplifier and the cascode output operational amplifier.

Figure 9(b) An expanded view of the current transfer ratio of Fig. 9(a) for Class AB, push pull

and the cascode output operational amplifiers showing the low frequency errors.

Figure 10 The X terminal input resistance for the Miller Compensated two-stage, Class AB,

push pull and cascode output operational amplifiers. Note rin,x in dB is

normalized to 1 .

Date post:	14-Apr-2018
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