CMOS LNA co design

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Co-design Approach for Wide-Band Asymmetric Cross

Shaped Slotted Patch Antenna with LNA

Sandeep Kumar1,2 • Binod Kumar Kanaujia2 •

Santanu Dwari1

• Ganga Prasad Pandey3

•

Dinesh Kumar Singh1

Springer Science+Business Media New York 2015

Abstract The proposed work presents a co-design approach for a new asymmetric

rectangular cross shaped slotted patch antenna with low noise amplifier that occupies

17.2–25.8 GHz wide-band for SDR applications. This co-design approach minimizes the

chip area and noise and also improves integration system over the bandwidth of 8.6 GHz.

Three different architectures have been designed in this work. Firstly, a two stage CMOS

CG–CS LNA is designed using a technique of series–parallel resonant network as an input

matching network and as inter-stage matching network between CG and CS LNA. Insecond architecture stage, a rectangular shaped microstrip antenna is designed and a slot of

asymmetric cross shape is cut on the patch antenna. In third architecture the slotted antenna

is integrated with low noise amplifier in order to form a co-design approach in which

series–parallel resonant network is used as a band pass filter between slotted patch antenna

and LNA. A two-stage CMOS LNA design is simulated and layout is made using foundry

design kit for the TSMC 65 nm CMOS process in ADS.v.12. A simulation result of LNA

achieves S11 of -21.4 dB with gain ranging from 7.4 to 21.3 dB over the wide-band of

19.1–28.8 GHz. The slotted antenna achieves S11 of -19 dB at 26 GHz and covers

& Binod Kumar Kanaujia

[email protected]; [email protected]

Sandeep Kumar

[email protected]

Santanu Dwari

[email protected]

Ganga Prasad Pandey

[email protected]

Dinesh Kumar [email protected]

1 Department of Electronics Engineering, Indian School of Mines, Dhanbad 826004, India

2 Department of Electronics and Communication Engineering, Ambedkar Institute of Advanced

Communication Technologies and Research, Delhi 110031, India

3 Department of Electronics and Communication Engineering, MAIT, Delhi 110085, India

1 3

Wireless Pers Commun

DOI 10.1007/s11277-015-2814-3

http://crossmark.crossref.org/dialog/?doi=10.1007/s11277-015-2814-3&domain=pdfhttp://crossmark.crossref.org/dialog/?doi=10.1007/s11277-015-2814-3&domain=pdf


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frequency range of 20.1–27.8 GHz with good radiation and receiving patterns. This co-

design approach is analysed considering the 50 X impedance matching throughout the

design and simulated on the platform of ADS.v.12. The best achievement of proposed co-

design approach is reduced noise figure which is most suitable for SDR applications.

Keywords Software defined radio (SDR) Low noise amplifier (LNA) Complementarymetal oxide semiconductor (CMOS) Microstrip antenna

1 Introduction

In Last few years, a fastest growth for the wide range of wireless networks is continuously

finding a new solution, which often comes either with new frequency bands or with newmodulation schemes. Recently, the hardware and software system design have been done

individually for every standard which overcomes the drawback of redesigning of hardware

modules for every new standard. This suggests the integration of many communication

devices into a single chip [1]. Moreover, there have been researchers for the already

available spectrum for their efficient use e.g., cognitive radio. It is desirable to have a

universal programmable hardware which gives the flexibility in designing the system by

using software-defined radio (SDR) technique [2]. The first proposed idea of an SDR,

developed by Mitola [3], is to perform all RF and baseband signal processing designs in

both analog and digital domains. It brings the flexibility, cost efficiency and enhanced

power in order to carry forward communication, resulting in benefits to the service pro-viders [4]. The extensive progress of CMOS technology has enabled its application in SDR

wireless networks. At present, the CMOS technology is one of the most attractive choices

in implementing receiver due to its low cost and high level of integration [ 5]. In spite of

having several advantages, the design of CMOS receiver in SDR applications exhibit

various challenges and difficulties to which the designers should take care off. Although by

using the integrated patch antenna with LNA, most of the performances parameters have

been improved but SDR applications are not yet considered.

The most difficult task for the wide band co-design of low noise amplifier (LNA) with

microstrip antenna are: (1) To take care of the performance parameters like impedance

matching and noise over a wider range (2) To take care of size an effect of miniaturization

and (3) Low power consumption for long lasting battery. Several authors have devoted

their research about the many LNA’s and different shaped slotted antennas which offered

wider bandwidth [6, 7]. But the wide band co-design approach of slotted antenna with

LNA concept is still needs exploration.

In [8], the return loss of filter degrades the noise figure (NF) when LC ladder filter has

been placed at the input of a common source (CS) amplifier. Another inter-stage LC

network is added to CG–CS stage that increase the power gain, but the NF is 6 dB at

around 10 GHz [9]. In [10], coupled resonators have been used to design a wideband inter-

stage matching network for a V-band cascaded CS amplifier. A wideband LNA operatingin 23–32 GHz has been proposed in which coupled resonators are used as a load for the

common-emitter stage [11]. In [12], design of wideband LNA’s using parallel-series res-

onant matching network between CG and CS stages at 3–10 and 14–29 GHz achieved

9.6–12.7 and 8.25–1.65 dB gain but sacrificed NF. In [13], analysis of LNA-antenna co-

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design for UWB system achieved 13 dB gains on the 3.25–5 GHz bandwidth but noise

performances has not been discussed.

In this paper, a new approach of co-design of wide band asymmetric cross shaped

microstrip antenna with LNA is proposed. Three architectures operating in the frequency

ranges of 20.13–27.8, 19.1–28.8 and 17.2–25.8 GHz respectively are executed to verifythis co-design approach. The designing of asymmetric cross shaped antenna is discussed in

section II. Section III, presents the analysis of Wide band CMOS CG–CS topology using

series–parallel resonant network. A co-design approach over wide band range is addressed

in **Sect. 4. Finally, simulated results are discussed in Sect. 5 and are followed by

conclusion in Sect. 6.

2 Design and Implementation of Asymmetric Cross Shaped MicrostripAntenna

The microstrip antenna is a small electrically thin patch having numerous advantages i.e.

light weight, inexpensive, and easily integrable with active devices for improving system

reliability. The schematic of the proposed antenna is shown in Fig. 1. The feedline of

dimension W 1 9 L 1 is attached with a slot loaded rectangular patch of dimension L 9 W in

the same plane. An asymmetric cross slot is cut in the rectangular patch. All the detailed

dimensions are listed in Table 1. The proposed structure is designed on RT Duriod-5870

substrate. The height, dielectric constant and loss tangent of the substrate are 0.762 mm,

Fig. 1 Geometry of proposed antenna with asymmetric cross shaped slot

Co-design Approach for Wide-Band Asymmetric Cross Shaped…

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2.33, and 0.0012 respectively. The width of the smaller rectangular patch section (W1) is

adjusted to provide a 50 X microstrip line. By cutting a cross slot on the patch, additional

resonances are created and much wider impedance bandwidth is produced. The 3D

Table 1 Dimensions of patch

antenna with cross shaped cut-

slot

Dimensions Values (mm)

w 9.2

W 4.6

W1 2.2W2 0.9

W3 0.7

W4 0.7

W5 0.7

Ws 0.7

l 9.4

L 3.1

L1 1.6

L2 0.4 L3 1.2

L4 0.5

L5 1.1

Ls 1.1

d1 1.9

d2 1.9

d3 0.4

d4 2.2

d5 1.8

Fig. 2 3D view of asymmetric cross shaped slotted patch antenna

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isometric view of asymmetric shape slotted antenna is shown in Fig. 2. The simulated

return loss and radiation at 26 GHz of the antenna is shown in Figs. 3 and 4 respectively.

The return loss plot clearly shows two resonances eparated appropriately to create a

wideband response. The bandwidth of the antenna ranges from 20.1 to 27.8 GHz providing

a fractional bandwidth of 32.15 %. Figure 4 illustrates the simulated radiation pattern atresonant frequency of 26 GHz when phi rotates 90. This plot shows electric field com-

ponents of co and cross polarization.

3 Wide-Band CMOS LNA Analysis

In order to achieve the best impedance matching, gain and NF over a wide band range,

many topologies are available [14]. Out of these topologies, CS and common gate (CG) are

the most popular choices for LNA design. The CS with the source inductor degeneration

technique achieves a good input impedance matching with ideal noiseless components

providing a minimal NF and a higher gain whereas CG offers wideband operating per-

formance with good linearity and input–output isolation property [15]. But at higher fre-

quencies, cascaded CG–CS topology suffers with noise. Therefore, a series–parallel

resonant network is used for CG–CS amplifier as an input and inter-stage matching net-

work which improves the noise performance and other parameters. The details of the

proposed structure of two stage CG–CS LNA using series to parallel resonant network are

addressed below.

3.1 Series–Parallel Resonant Network

In [12], a parallel to series resonant network is used as a band pass filter is shown in Fig. 5.

This resonant network achieved a band pass response and dual band response by selecting

proper values of inductors and capacitors. For the parallel and series resonance networks,

the impedances Zp and Zs are shown in Eq. (1) and (2) respectively [12].

Fig. 3 Variation of return loss with operating frequency


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Z p ¼ 1 R1

þ jwC 1 þ 1 jwL 1

1ð1Þ

Z s ¼ R2 þ jwL 2 j 1

wC 2ð2Þ

Here, the concept implies that different values of source and load impedances

R1 = 250 X and R2 = 40 X in parallel to series resonant network offered dual band

response with a dip in the middle. A wide band response is achieved when parallel-series

network is used as inter-stage matching network between CG and CS LNA. The same

concept is used in this work. However parallel-series resonant network is inverted asseries–parallel resonance network which is used as matching network between CG and CS

LNA for improving performance parameters like impedance matching, NF and gain over

wider range of operating frequencies. A proposed two stage CMOS CG–CS LNA using

inverted parallel-series resonant network is discussed in subsection B.

Fig. 4 Simulated radiation pattern of the proposed antenna at 26 GHz

Fig. 5 Schematic of parallel-series resonant network

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3.2 CG–CS LNA Using Series–Parallel Resonant Network

The proposed schematic of two stages CG–CS LNA using series–parallel resonant network

is shown in Fig. 6. This is implemented using commercial TSMC design kit of 65 nm RF

CMOS technology in Agilent Advanced Design System (ADS). The input matching andinter-stage matching networks of CG–CS LNA are composed of inductors and capacitors

as L1, L2, L3, L4, C1, C2, C4, C5 having values of 0.48, 0.27, 0.83, 0.6 nH, 14.75, 30, 0.06

and 0.0835 pF respectively.

Selection of on-chip inductors is the key for the designing of a matching network, as it

determines the performance quality of matching network. The input and inter-stage

matching network is accomplished with the combination of a series–parallel LC impedance

transformation network. In order to maintain the 50 X impedance matching, firstly a single

stage of CG LNA using series to parallel resonant network as an input is designed that

provides good reverse isolation parameter over a wide band range of operation. It is well

known that the NF and high gain are the essential requirements of the LNA design. For

improving these parameters further, the next stage i.e. CS with source degeneration via

series–parallel resonant network is combined. For the two-stage of CG–CS LNA, the width

of M1 (WM 1) is calculated to be 492 lm using Eq. (3) as given in [14]. The second stage of

CS device is designed to meet the desired performance criterion while width of M 2 (WM 2)

is calculated as 532 lm using Eq. (4) as given in [14].

WM 1 ¼ 3

2

cgs

L mincoxð3Þ

WM 2 ¼ g2m L min

2K n I Dð4Þ

where, L is channel length, K n is transconductance parameters, Cox is gate oxide capaci-

tance, ID is the drain current, gm is transconductance of device and C gs is the gate to source

capacitance. In this design, a more difficult task is to maintain an output impedance of

Fig. 6 Proposed schematic of CMOS CG–CS LNA using series to parallel network


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250 X of CG stage and input impedance of 40 X of CS stage for obtaining wide band

operation. The designed circuit of CG–CS LNA is simulated and reflection coefficient of

-21.4 and -21 dB at operating frequency of 20.5 and 26.2 GHz is obtained respectively.

This return loss shows a frequency band from 19.1 to 28.8 GHz with a fractional band-

width of 40.5 % as shown in Fig. 7. It also shows transmission gain S21 of the circuit. TheCMOS LNA provides a gain in the range of 7.4–21.3 dB for the entire band of operation

with relatively constant NF of around 2.8 dB as shown in Figs. 7 and 8 respectively. The

forward gain (S21) shows a high gain over the bandwidth of 9.7 GHz ranging from 19.1 to

28.8 GHz as shown in Fig. 7. Using series–parallel networks a wideband impedance

matching is obtained as shown in Fig. 9. It clearly indicates that the imaginary part of input

impedance remains near zero value while real part is matched around 50 X within the band

of operation. The total power consumption for two stage CG–CS LNA is 11.2 mW from

1.6-V power supply. Figure 10 shows layout of CG–CS LNA with final area of 0.74 mm2.

Table 2. Show the comparison of previous works with present one on various parameters.

4 Strategy of Combined Structure

In this section, the technique of proposed combined structure of slotted patch antenna with

LNA is addressed. The schematic of this co-design is shown in Fig. 11. From the sche-

matic, it can be observed that slotted patch antenna is integrated with the CMOS LNA

which forms a co-design structure. In this structure, the input of CG–CS LNA i.e. series–

parallel resonant network has been used as an inter-stage matching network between the

asymmetric slotted patch antenna and the CG–CS LNA. As discussed above, the series–parallel resonant network which acts as a band pass filter is connected between slotted

patch antenna and LNA to form a complete receiver system. The RF signal is applied to

patch antenna with the help of two ports and the output from the antenna is connected to

the microstrip line with help of another port while applying the approach of co-design, four

major goals need to be fulfilled: (1) To sustain 50 X impedance matching throughout the

design for achieving performance parameters (2) To achieve higher gain and lower NF that

Fig. 7 Variation of return loss and forward gain of CG–CS LNA

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is essential for amplification (3) To minimize the chip area and (4) To achieve less power

dissipation [16–18]. To predict the received signal, one port of RF signal with 50 X is

attached on the slotted patch and the received signal is passed via series to parallel resonant

network to the LNA for the amplification. Keeping above goals in mind, a strategy is

adopted to combine the structure of slotted patch antenna and LNA that provides goodresults as per design specifications and that would be discussed in next section.

Fig. 8 Variation of NF with frequency

Fig. 9 Variation of Input impedance of CG–CS LNA with frequency


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5 Results Discussion of Co-design

From previously discussed results of slotted antenna and LNA in section II and III, it can

be seen that the proposed asymmetric cross shaped antenna works on the wide band range

of 20.1–27.8 GHz with fractional bandwidth of 32.15 % whereas LNA achieves a wide

Fig. 10 Layout snapshot of CMOS CG–CS LNA

Table 2 Comparisons of LNA’s with other reported papers

Design parameters [19] [20] [12] [12] Present work

Technology 0.18 lm 0.18 lm 0.18 lm 0.18 lm .065 lm

Peak Gain (dB) 12.4 12.9 12.7 8.95 21.3

NF (dB) 4.4–6.5 3.7–4.7 2.5–3.9 4.3–5.8 2.9–2.7

B.W (GHz) 0.4–10 1.5–11.7 3.1–10.3 14–29 GHz 19.2–28.8

Power (mW) 12 10.34 13.4 13.9 11.2

Area (mm2) 0.42 0.536 0.68 0.54 0.74

Fig. 11 Schematic of co-design of slotted patch antenna with LNA

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range of 19.1–28.8 GHz with fractional bandwidth of 40.15 %. The obtained bandwidths

of both the devices are approximately same and give the wide band when co-design

approach is applied. Using above discussed strategy the two structures are combined,

analyzed and simulated on ADS platform. The simulated result of co-design structure

obtains the S11 of -18 dB at three different frequencies 19.8, 21 and 23.4 GHz with a wide

band ranging from 17.2 to 25.8 GHz with fractional bandwidth of 40 % as shown in

Fig. 12. The band of operation of the complete design shifts downward while the impe-

dance matching of antenna and LNA remains within the acceptable limit. The best

achievement of this co-design is to improve the performance parameters like gain and NF

that is required for receiver system. The new band of operation is 17.2–25.8 GHz with gain

ranging from 3.4–13 dB. The NF varies between 2.9–1.9 dB which is shown in Fig. 13.

Fig. 12 Return loss and forward gain behavior for co-design strategy

Fig. 13 NF variation with frequency for co-design system


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Moreover, an impedance matching (real and imaginary) of co-design structure is also

obtained and shown in Fig. 14. The calculated area of the slotted patch antenna is

9.2 9 9.4 mm2

whereas the area of two stage CG–CS LNA is 0.92 9 0.81 mm2

. The total

area of co-design layout is 9.2 9 10.2 mm2.

6 Conclusions

The proposed method of co-design of asymmetric cross shaped patch antenna with LNA is

discussed in the paper with achieving a wider bandwidth of 17.2–25.8 GHz. It is also found

that the proposed antenna design exhibits an extremely wideband impedance by new type

of slot cut in the cross shaped and also LNA design revealed an wideband by using series to

parallel resonant network as a input and inter-stage matching network. The state of the art

of this co-design work achieves S11 of -18 dB by proper impedance matching with wider

gain variation from 3.1 to 13 dB and NF from 2.9 to 1.9 dB. Moreover, the proposedmethod of co-design system for SDR applications, increase the level of system integration,

reducing chip area size thus, escalating the overall system performance.

References

1. Brandolini, M., Rossi, P., Manstretta, D., & Svelto, F. (2005). Towards multistandard mobile termi-

nals—Fully integrated receiver requirements and architectures. IEEE Transactions on Microwave

Theory and Techniques, 53(3), 1026–1038.

2. Abidi, A. A. (2007). The path to the software-defined radio receiver. IEEE Journal of Solid-StateCircuits, 42(5), 954–967.

3. Mitola, J. (1995). The software radio architecture. IEEE Communications Magazine, 33(5), 26–38.

4. Osmany, S. A., Herzel F., & Scheytt, J. C. (2009). An integrated 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz,

and 20–28 GHz frequency synthesizer for software-defined radio applications. In Proceedings of the

IEEE bipolar/BiCMOS circuits and technology meeting (BCTM 2009), Capri, Italy (pp. 39–42).

Fig. 14 Impedance variation with frequency for co-design system

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5. Zolfaghari, A., & Razavi, B. (2003). A low-power 2.4-GHz transmitter/receiver CMOS IC. IEEE

Journal of Solid-State Circuits, 38, 177–181.

6. Pandey, G. P., Kanauajia, B. K., Guatam, A. K., & Gupta, S. K. (2013). Ultra wideband L-strip

proximity coupled slot loaded circular microstrip antenna for modern communication systems. Wireless

Personal communication, 70, 139–151.

7. Kumar, S., Kanaujia, B. K., Dwari, S., Pandey, G. P., & Singh, D. K. (2015). A miniurazation approachtowards 40 GHz single chip receiver system for MMW Communication networks. Wireless Personal

Communication. doi:10.1007/s11277-015-2688-4.

8. Bevilacqua, A., & Niknejad, A. M. (2004). An ultrawideband CMOS low noise amplifier for 3.1–10.6-

GHz wireless receivers. IEEE Journal of Solid-State Circuits, 39(12), 2259–2268.

9. Lin, Y. J., Hsu, S. S. H., Jin, J. D., & Chan, C. Y. (2007). A 3.1–10.6 GHz ultrawideband CMOS low

noise amplifier with current-reused technique. IEEE Microwave Wireless Compon. Lett., 17 (3),

232–234.

10. Vecchi, F. (2010). A wideband mm-wave CMOS receiver for Gb/s communications employing inter-

stage coupled resonator. In Proceedings of the IEEE international solid-state conference (pp. 220–221).

11. El-Nozahi, M., Sanchez-Sinencio, E., & Entesari, K. (2010). A millimeterwave (23–32 GHz) wideband

BiCMOS low-noise amplifier. IEEE Journal of Solid-State Circuits, 45(2), 289–299.

12. Lo, Y. T., & Kiang, J. F. (2011). Design of wideband LNAs using parallel to series resonant matchingnetwork between commom-Gate and common-source stage. IEEE Transactions on Microwave Theory

and Techniques, 59(9), 2285–2293.

13. Bories, S., Pelissier, M., Delaveaud, C., & Bourtoutian, R. (2007). Performances Analysis of LNA-

antenna co-design for UWB system. Antennas and Propagation EuCAP, 34, 1–5.

14. Shaeffer, D. K., & Lee, T. H. (1997). A 1.5-V, 1.5-GHz CMOS low noise amplifier. IEEE Journal of

Solid-State Circuits, 32, 745–759.

15. Allstot, D. J., Li X., & Shekhar, S. (2004). Design considerations for CMOS low-noise ampliifers. In

Proceedings of the IEEE radio frequency integrated circuits (RFIC) symposium (pp. 97–100).

16. Wang, Hongrui, Zhang, Lei, Zhang, Li, Wang, Yan, & Zhiping, Yu. (2011). Design of 24-GHz high-

gain receiver front-end utilizing ESD-split input matching network. IEEE Transactions on Circuits and

Systems, 58(8), 482–486.

17. Liu, L. C., Liu, C. S., Kessler, J. R., Kuo Wang, S., & Chang, C. D. (1986). A 30-GHz monolithicreceiver. IEEE Transactions on Microwave Theory and Techniques, 33(12), 2079–2083.

18. Queudet, F., Pele, I., Froppier, B., Mahe, Y., & Toutain, S. (2002).Integration of pass-band filters in

patch antennas. 32nd European microwave conference, Milan, vol.35, pp. 685–688.

19. Chen, K. H., Lu, J. H., Chen, B. J., & Liu, S. I. (2007). An ultra-wideband 0.4–10 GHz LNA in 0.18 lm

CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs, 54 , 217–221.

20. Lin, Y. S., Chen, C. Z., Yang, H. Y., Chen, C. C., Lee, J. H., Huang, G. W., et al. (2010). Analysis and

design of a CMOS UWB LNA with dual—RLC-branch wideband input matching network. IEEE

Transactions on Microwave Theory and Techniques, 58(2), 287–296.

Sandeep Kumar received his B.E. degree in Electronics and Com-

munication Engineering in 2008 and M.Tech. degree in VLSI Designin 2012 from Gautam budh University, Uttar Pradesh, India. Currently,

he is doing Ph.D. Degree in Electronics Engineering from Indian

School of Mines, Dhanbad, India. His current research interests are

focus on transceiver systems, Millimeter wave applications and

microstrip antennas.


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Binod Kumar Kanaujia (M’ 04) joined Ambedkar Institute of

Technology (AIT), Govt. of N.C.T. Delhi, Geeta colony Delhi -31 as

Assistant Professor in Jan. 2008 in the Department of Electronics and

Communication Engineering after getting selected by Union Public

Service Commission, New Delhi. Before joining AIT, Dr. Kanaujia

has served in the M.J.P Rohilkhand University in the capacity of Reader in Electronics and Communication Engineering Department

from 26/02/2005 to 30/01/2008 and lecturer in ECE Department from

25/06/1996 to 25/02/2005. While working with MJP Rohilkhand

University Dr. Kanaujia has been a active Member of Academic

council and Executive council of the university and played a vital role

in the academic reforms. He has also served as Head of Department of

E&C Department of the university for the period from 25th July 2006

to 30th Jan 2008. Prior to his career in the academics, Dr. Kanaujia has

been working as Executive Engineer in the R&D division of M/s

UPTRON India Ltd. Dr. Kanaujia, presently working as Associate

Professor in ECE Department of AIT has served various key portfolios i.e. he has been Head of Department

of E&C Department of the Ambedkar Institute of Technology from 21 February 2008 to 05 Aug 2010, and17 Aug. 2012 to till now, As Library In-charge of Central Library of AIT from March 2008 to 05 Aug 2010

and responsible for upgrading the Library with the introduction of Fully Automatic Book issue and

receiving, on-line journal, on-line retrieval of catalogue of the Library, Establishment of E-Library. Apart

from it, he has been holding the Charge of Head of office of Ambedkar Institute of Technology since 09

Aug. 2008–3rd May 2013 and responsible for day to day administration of the institute. Dr. Kanaujia has

done his B.Sc. from Agra University Agra U.P. in 1989 and B.Tech. in Electronics Engineering from KNIT

Sultanpur U.P. in 1994. He did his M.Tech. and Ph.D. from Electronics Engineering Department of IIT

Banaras Hindu University,Varanasi in 1998 and 2004 respectively. He has been awarded Junior Research

fellow by UGC Delhi in 2001–2002 for his outstanding work in his field. His keen research interest in design

and Modeling of Microstrip Antenna, Dielectric Resonator Antenna, Left handed Metamaterial Microstrip

Antenna, Shorted Microstrip Antenna Wireless Communication, Wireless Communication and Microwave

Engineering etc. Till date he has been credited to publish more than 80 research papers in peer-reviewed journals and International/national conferences. Dr. Kanaujia is a Member of IEEE and Life members of the

Institution of Engineers (India), Indian Society for Technical Education and The Institute of Electronics and

Telecommunication Engineers of India.

Santanu Dwari was born in Howrah, West Bengal, India. He received

his B.Tech. and M.Tech. degree in Radio Physics and Electronics from

University of Calcutta, Kolkata, West Bengal, India in the year of 2000

and 2002 respectively and PhD degree from Indian Institute of Tech-

nology, Kharagpur, West Bengal, India in the year of 2009. He joined

Indian School of Mines, Dhanbad, Jharkhand, India in 2008 where he

is currently an Assistant Professor in the Department of Electronics

Engineering. He has published seven research papers in referredInternational Journals. He is carrying out two sponsored research

project as Principal Investigator. His research interest includes

Antennas, RF planar circuits, Computational Electromagnetic.

S. Kumar et al.

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Ganga Prasad Pandey received B. Tech. in Electronics Engineering

from K.N.I.T. Sultanpur, India in 2000. He completed M.E. in Com-

puter Technology and Application from Delhi College of Engineering

Delhi (India) in 2004. Presently, he is Assistant Professor in Elec-

tronics and Communication Engineering department of Maharaja

Agrasen Institute of Technology, Delhi, India. He is currently workingtowards his Ph.D. degree from Uttrakhand Technical University. His

research interests include active, Reconfigurable, frequency agile

microstrip antennas and microwave/millimeter wave integrated circuits

and devices.

Dinesh Kumar Singh received B.E. in Electronics and Communica-

tion Engineering from Kumaon University, Nainital, in 2003. He is

done M. Tech. in Digital Communication from RGPV University,

Bhopal, India. Currently, he is pursuing PhD from ISM, Dhanbad. His

area of interest is microwave Engineering.


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