Sheet 1 of 11 CMOS Logic In many aspects of RF design it is useful to have some knowledge of logic design, in particular PLL systems always employ some form of phase detector and sometimes a prescalar/divider. First lets re-cap on the operation of a N-type CMOS switch. Figure 1 shows the switch OFF condition ie no current flow between the drain and source. The bulk or substrate is made of lightly doped p-type silicon, which consists of positive ‘holes’ (and a few negative electrons). An area of highly doped (many electrons) is deposited on the substrate in two positions to form the source and drain connections. Bridging these source and drain terminals is an area of insulating SiO2 (Silicon Dioxide) coated in metal which now forms the gate t erminal. With no potential on the gate, there is no depletion region for current to flow between the drain and source terminals and so the switch is off. + +++ + + + + + + - - - Lightly doped p-type substrate ------ - - - - Drain Source Heavily doped N-type SiliconHeavily doped N-type SiliconSiO2 Insulating Layer Metal layer PolySilicateGate 0V Figure 1 Showing the CMOS switch in the ‘OFF’ condition, as there is 0V on the gate junction and there is no conducting layer under the gate to allow current to flow between the drain and source junctions. In Figure 2 the ‘ON’ state is shown ie +5V is applied to the gate terminal. In this case the postive gate potential attracts electrons from the substrate causing a region of electrons formed under the gate insulation region. Current can now flow through this induced n-channel ‘inversion region’ between the drain and source terminals.
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CMOS Logic
In many aspects of RF design it is useful to have some knowledge of logic design, in
particular PLL systems always employ some form of phase detector and sometimes aprescalar/divider.
First lets re-cap on the operation of a N-type CMOS switch.
Figure 1 shows the switch OFF condition ie no current flow between the drain and source.The bulk or substrate is made of lightly doped p-type silicon, which consists of positive ‘holes’(and a few negative electrons). An area of highly doped (many electrons) is deposited on thesubstrate in two positions to form the source and drain connections. Bridging these sourceand drain terminals is an area of insulating SiO2 (Silicon Dioxide) coated in metal which nowforms the gate terminal.
With no potential on the gate, there is no depletion region for current to flow between the
drain and source terminals and so the switch is off.
+
+
+
+ + +
++++
-
-
-Lightly doped p-type substrate
-
-
-
-
- -
-
-
-
-
DrainSource
Heavily doped
N-type
Silicon
Heavily doped
N-type
Silicon
SiO2 Insulating
Layer
Metal layer
PolySilicate
Gate
0V
Figure 1 Showing the CMOS switch in the ‘OFF’ condition, as there is 0V on the gatejunction and there is no conducting layer under the gate to allow current to flowbetween the drain and source junctions.
In Figure 2 the ‘ON’ state is shown ie +5V is applied to the gate terminal. In this case thepostive gate potential attracts electrons from the substrate causing a region of electronsformed under the gate insulation region. Current can now flow through this induced n-channel‘inversion region’ between the drain and source terminals.
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+
+
+
+ + +
++++
-
-
-
Lightly doped p-type substrate
-
-
-
-
- -
--
-
-
DrainSource
Current flow
through the
Inversion
Electrons attracted
to area under thegate
SiO2 InsulatingLayer
Metal layer
PolySilicate
Gate
+5V
- - - -
Figure 2 Showing the CMOS switch in the ‘ON’ condition, as there is +5V on the gatejunction. Electrons from the substrate are attracted to the area under the gate causinga conducting path between the drain and source junctions.
CMOS INVERTER (NOT Gate)
To form a simple inverter circuit we need to add a load resistor as shown in Figure 3.
Vcc
Vin
Vout
N-Type CMOS
R
Figure 3 N-type CMOS FET switch with resistive load resistor.
With Vin set to 0V the voltage across the gate to source junction will also be 0V. For a N-TypeCMOS FET to switch the Vgs voltage needs to be > VT+VSAT, so with Vgs set to 0V the switchwill be off and vout will be at Vcc (Vout will be directly connected to Vcc via the resistor R). In
this case vin = lo; Vout = hi.
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When Vin is set to +5V (which is much greater than VT+VSAT) the CMOS Fet will be switchedon and Vout will be shorted to ground making it 0V. In this case vin = hi; Vout = lo.
Note that current will flow through the resistor R when the switch is ON and this is a waste ofpower. However, we can use a push-pull configuration using a P-type and N-type CMOSswitch as shown in Figure 4.
Vcc (+5V)
VinVout
N-Type CMOS
TR2
P-Type CMOS
TR1
Figure 4 Push-Pull CMOS Inverter circuit.
With Vin Set to 5V (and Vcc set to 5V).
Vgs across the N-type CMOS FET (TR2) will be 5V, well above VT+VSAT and therefore TR2will be switched ON.
The Vgs across the P-type CMOS FET (TR1) will be 0V (Vcc (5V) – Vin (5V)). This devicerequires VT+VSAT below Vcc before it switches on and so this device is OFF.
With TR1 OFF and TR2 ON - Vout will be connected to 0V via TR2.
With Vin Set to 0V (and Vcc set to 5V).
Vgs across the N-type CMOS FET (TR2) will be 0V, below VT+VSAT and therefore TR2 will beswitched OFF.
The Vgs across the P-type CMOS FET (TR1) will now be ~ -5V (Vin (0V – Vcc (5V)). Thisdevice requires at least VT+VSAT (~1V) below Vcc before it switches on – in this case it will benearly 5V and so this device will be switched ON.
With TR1 ON and TR2 OFF - Vout will be connected to 5V (Vcc) via TR1.
Note the Bulk/substrate connections (shown by the RED arrow), N-type bulk is connected to the lowest voltage in this case 0V and the P-type connected to the highest voltage in this caseVcc (+5V).
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The circuit was simulated to verify operation using a 0.8um silicon-gate bulk CMOS n-wellprocess using ADS.
Figure 5 shows the ADS simulation setup using a Transient (Time domain) simulation with theinverter circuit connected to a square wave pulse generator operating at 50KHz.
Vin
Vout
VDD
VAR
VAR1
W=1
L=1
LAMBDA=0.1/L
EqnVar
VtPulseDTSRC2
Rout=1 Ohm Period=20 usec Width=10 usec Delay=0 nsec Vhigh=5 V
Vlow=0 VDT
Tran Tran1
MaxTimeStep=250
StopTime=50 usec
TRANSIENT
LEVEL1_Mode
MOSFETM2
Uo=210
Ld=0.015 umTox=150e-10
Mjsw=0.35
Cjsw=5e-10
Mj=0.5
Cj=560e-6
Cgbo=700e-12
Cgdo=220e-12
Cgso=220e-12
Pb=0.95
Lambda=LAMBDA
Phi=0.8
Gamma=0.6
Kp=50e-6Vto=0.7
LEVEL1_Mode
MOSFETM1
Uo=660
Ld=0.016 umTox=140e-10
Mjsw=0.38
Cjsw=5e-10
Mj=0.5
Cj=770e-6
Cgbo=700e-12
Cgdo=220e-12
Cgso=220e-12
Pb=0.95
Lambda=LAMBDA
Phi=0.8
Gamma=0.6
Kp=50e-6Vto=0.7
MOSFET_NMOS
MOSFET1
Width=W um
Length=L um
Model=MOSFETM
MOSFET_PMOS
MOSFET2
Width=W um
Length=L um
Model=MOSFETM V_DC SRC1 Vdc=5.0 V
Figure 5 ADS simulation setup to analyse the CMOS inverter based on 0.8um gateprocess. The pulse source provides a 50KHz square wave to the inverter. Note that theP-MOS device source is connected to Vcc and the N-MOS device source is connectedto ground (the two drains are connected together to form the output).
Figure 6 Resulting waveforms generated from the ADS simulation shown in figure 5,showing the inverting action. Note the overshoot appears to be a ‘quirk’ of thetransient simulation.
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CMOS NOR Gate
A NOR gate can be designed by adding CMOS inverters in parallel. Figure 7 shows the circuit
diagrams of a 2 NOR gate if more inputs are required more devices are added in parallel withTR3/TR4 and is series with TR1/TR2.
Looking at the truth table we can see that a logic high output only occurs when A & B arelow. With A & B at 0V CMOS P-type switches TR1 & TR2 will be ON – connecting Vout toVcc. Also the N-type CMOS switches TR3 & TR4 will be switched off (as Vgs =0 which is <VT+VSAT). In all other cases (where A or B are 1) one of the P –type switches will be OFFand Vout will not be connected to VCC always resulting in a logic low on the output.
Vcc (+5V)
Vin – ‘A’
Vout A+B
N-Type CMOS
TR3 & TR4
P-Type CMOS
TR1 & TR2
Vin – ‘B’
A B Vout
0 0 1
0 1 0
1 0 0
1 1 0
Figure 7 Two-Input NOR gate. To add more inputs another N-type device is added inparallel with TR3 & TR4 and another P-type device added in series with TR1 & TR2 –the gates of the new devices connected together to form the new input.
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CMOS NAND Gate
The structure of a 2-input NAND gate is the inversion of the 2-input NOR gate, ie parallel
devices connected to +5V Vcc and series devices connected to ground as shown in Figure 8. The main problem with this circuit are the cumulative Vsats of the series devices.
The ADS transient simulation of the NAND is shown in Figure 9 and is used as a basicbuilding block for other more complex logic circuits eg flip-flops.
The practical limit is for four devices ie 4-input NAND gate, to generate more inputs thenthese circuits can be cascaded as shown by a 4 input NAND using 2 off 2-input NANDS inFigure 11.
Vcc (+5V)
Vin – ‘A’
Vout = A*B
P-Type CMOS
TR1 & TR2
N-Type CMOS
TR3 & TR4
Vin – ‘B’
A B Vout
0 0 1
0 1 1
1 0 1
1 1 0
Figure 8 Two-Input NAND gate. To add more inputs another P-type device is added inparallel with TR1 & TR2 and another N-type device added in series with TR3 & TR4 –the gates of the new devices connected together to form the new input.
One other disadvantage of this circuit is that the output impedance varies depending on thenumber of parallel P-type CMOS FETS are on or off. To eliminate this effect an inverter isadded to the NAND output and will now form a AND gate. To restore the NAND function twoinverters in series need to be added to the output of the NAND gates as shown in Figure 10.
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Figure 9 ADS Transient simulation setup for a 2 input NAND gate. NOTE this version isunbuffered and normally would have two inverters in series on the output.
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MOSFET_PMOS
MOSFET4
Width=W um
Length=L um
Model=MOSFETM2
MOSFET_PMOS
MOSFET2
Width=W um
Length=L um
Model=MOSFETM2
VAR
VAR1
W=1
L=1
LAMBDA=0.1/L
EqnVar
Port
B
Num=4
Port
A
Num=1
MOSFET_NMOS
MOSFET3
Width=W um
Length=L um
Model=MOSFETM1
MOSFET_NMOS
MOSFET1
Width=W um
Length=L um
Model=MOSFETM1
LEVEL1_Model
MOSFETM2
Uo=210
d=0.015 um
ox=150e-10
sw=0.35
jsw=5e-10
=0.5 j=560e-6
gbo=700e-12
gdo=220e-12
gso=220e-12
Pb=0.95
Lambda=LAMBDA
Phi=0.8
Gamma=0.6
Kp=50e-6
Vto=0.7
L
T
Mj
C
MjC
C
C
C
LEVEL1_Model
MOSFETM1
Uo=660
Pb=0.95
Lambda=LAMBDA
Phi=0.8
Gamma=0.6
Kp=50e-6
Vto=0.7
Ld=0.016 um
Tox=140e-10
Mjsw=0.38
Cjsw=5e-10
Mj=0.5Cj=770e-6
Cgbo=700e-12
Cgdo=220e-12
Cgso=220e-12
Port
OUT
Num=2
Port
VccNum=3
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Vin – ‘A’
Vout = A*B
P-Type CMOS
TR1 & TR2
N-Type CMOS
TR3 & TR4
Vin – ‘B’
Vcc (+5V) Vcc (+5V)Vcc (+5V)
A*B
Figure 10 Buffered output 2-input NAND gate using CMOS inverters on the output. One inverter will realise a 2-is added to restore the NAND function.
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4-Input NAND gate using 2-Input logic gates
A
B
C
D
E
F
G
H
NAND
NAND
NOR NOT
Figure 11 Realisation of a 4-input NAND gate using 2-input logic circuits
Table 1 Truth table for the 4-input NAND gate using 2 input logic circuits
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XOR Exclusive OR gate
The exclusive OR gate differs from a normal OR gate in that the output is 1 if ‘ONE’ of the
inputs are one but not both of them. The truth table for the exclusive OR gate is shown belowand the gate circuit diagram is shown in Figure 12:-
A B C0 0 00 1 11 0 11 1 0
This type of gate can be used as a digital phase detector in PLL (phase locked loop) systems.
A
B
C
D
ENAND
OR
AND
A B C D E0 0 0 1 00 1 1 1 11 0 1 1 11 1 1 0 0
Figure 12 Showing XOR circuit and it’s corresponding truth table.
In a PLL circuit the phase detector XOR gate is fed by two digital signals. One signal comesfrom the reference and the other from the VCO (voltage controlled oscillator). The operationof the XOR gate is analogous to that of an analogue multiplier and will produce a trianglewave output representing the phase error of the two input signals.
