+ All Categories
Home > Documents > CMOS RFIC Design Principles - GBV

CMOS RFIC Design Principles - GBV

Date post: 15-Oct-2021
Category:
Upload: others
View: 6 times
Download: 2 times
Share this document with a friend
7
CMOS RFIC Design Principles Robert Caverly BOSTON|LONDON artechhouse.com
Transcript
Page 1: CMOS RFIC Design Principles - GBV

CMOS RFIC Design Principles

Robert Caverly

BOSTON|LONDON ar techhouse.com

Page 2: CMOS RFIC Design Principles - GBV

Contents

Preface

Acknowledgments

CHAPTER 1 Introduction

1.1 Historical Perspective and Background 1.1.1 A (Very) Brief History 1.1.2 Basic Communication System Architectures 1.1.4 Multiple Users

1.2 Review of System Fundamentals 1.2.1 System Gain 1.2.2 System Noise Figure 1.2.3 System Nonlinearities 1.2.4 Link Budget

1.3 Introduction to the Book References Selected Bibliography

CHAPTER 2 CMOS Integrated Circuit Fundamentals

2.1 Review of CMOS Technology 2.1.1 The CMOS Physical Structure 2.1.2 Technology Scaling

2.2 The MOSFET 2.2.1 The Basic «-Channel MOSFET 2.2.2 The Basic p-Channel MOSFET 2.2.3 Design Note: de characteristics 2.2.4 Basic MOSFET RF Equivalent Circuit Model 2.2.5 Advanced MOSFET RF Equivalent Circuit Model 2.2.6 Linear Operation of the MOSFET

2.3 MOSFET Weak Inversion and Accumulation Operation 2.3.1 Accumulation Mode 2.3.2 Weak Inversion-Subthreshold Operation 2.3.3 MOSFET Variable-Voltage Capacitors

2.4 Review of S-Parameters 2.5 SPICE Modeling of CMOS RF Circuits

2.5.1 SPICE Level 3

xm xiv

1

1 1 8

16 17 17 18 30 39 43 46 47

49

49 49 51 52 52 55 58 58 61 70 74 74 76 79 81 85 85

v/7

Page 3: CMOS RFIC Design Principles - GBV

2.5.2 BSIM Parameters References Selected Bibliography

CHAPTER 3 The Passive Components

3.1 Capacitors 3.1.1 Metal-Insulator-Metal Capacitors 3.1.2 RFIC Capacitance RF Equivalent Circuit Model 3.1.3 Concept of Top/Bottom Plate 3.1.4 Modeling Example

3.2 Inductors 3.2.1 On-Chip Inductor Types 3.2.2 Planar Spiral Inductor RF Equivalent Circuit Model 3.2.3 Reduction of Inductor Parasitics 3.2.4 Modeling Example 3.2.5 Transformers 3.2.6 Transmission Lines and Equivalents

3.3 Interconnections 3.3.1 Simple RC Models 3.3.2 Transmission Line Models

3.4 RF Microelectrical Mechanical Systems 3.4.1 Basic Types and Operation 3.4.2 Actuation Voltage 3.4.3 MEMS Switches 3.4.4 MEMS Resonators 3.4.5 MEMS Reliability and Packaging

3.5 Basic Packaging 3.5.1 Anatomy of an RF Package 3.5.2 Bond Wire Inductance 3.5.3 Package and Päd Capacitance 3.5.4 Thermal Properties—Thermal Resistance

3.6 RFIC Grounding and Signal Isolation 3.6.1 The Grounding Problem 3.6.2 Ground and Isolation Improvements References Selected Bibliography

CHAPTER 4 Small-Signal MOS Amplifiers for RF

4.1 Basic Amplifying Structure 4.1.1 Single FET with Generalized Load 4.1.2 Amplifier Loading 4.1.3 Effect of Parasitics 4.1.4 Basic Behavioral Model

4.2 Improvements to the Basic Amplifying Structure 4.2.1 Cascode Circuits

Page 4: CMOS RFIC Design Principles - GBV

IX

4.2.2 Multigate Finger Layouts 158 4.2.3 Differential Amplifiers 160 4.2.4 Current Reuse 163 4.2.5 Input/Output Impedance Modeling Example 165

4.3 Amplifier and On-Chip Biasing 168 4.3.1 Current Mirror Structures 169

4.4 Amplifier Matching 179 4.4.1 Classic LC 179 4.4.2 Inductive Matching: Source Degeneration 180 4.4.3 Example of LC Matching 183 4.4.4 Frequency Agile Matching 184

4.5 Low-Noise Amplifiers 190 4.5.1 Noise Modeling for LNAs: Common Source LNA 190 4.5.2 Noise Modeling for LNAs: Common Gate LNA 194 4.5.3 Modeling Example 198 4.5.4 Stability Considerations in MOS RFIC Amplifiers 200 References 201 Selected Bibliography 202

CHAPTER 5 Ancillary CMOS Circuits and Measurements 203

5.1 Ancillary CMOS RFIC Circuits 203 5.1.1 Negative gm Circuits (Q-Enhancement) 203 5.1.2 Source Follower 206 5.1.3 Simple Automatic Gain Control Circuits 207

5.2 Ancillary Passive CMOS RFIC Circuits 213 5.2.1 Generation of de from Applied RF Power 213 5.2.2 Active Inductor Circuits 216

5.3 Tuned Amplifiers 218 5.3.1 LC Tuned Filters 219 5.3.2 SAW Filtering 227 5.3.3 Polyphase Filters 227

5.4 Measurement Concepts 230 References 232 Selected Bibliography 234

CHAPTER 6 CMOS Oscillator Circuits 235

6.1 Review of General Feedback Principles 236 6.1.1 General Feedback Systems 236 6.1.2 Gain/Phase Margins 237 6.1.3 Reactance Oscillators 238 6.1.4 Classic Reactance Oscillator Circuits 243

6.2 Fixed-Frequency Oscillators 245 6.2.1 Single-Stage Amplifier with LC Tank Load 245 6.2.2 Feedback Cascade of Two Amplifiers 247 6.2.3 Negative Gm Perspective 250

Page 5: CMOS RFIC Design Principles - GBV

Contents

6.2.4 Coarse Frequency Control 251 6.2.5 Oscillator Design Specifications: Voltage Swing and Q 252 6.2.6 Modeling/Design Example 253 6.2.7 Mechanical-Based Oscillators 257

6.3 Ring Oscillator 261 6.3.1 Basic CMOS Inverter and Ring Oscillator 261 6.3.2 Single/Differential Ring Oscillators 263

6.4 Voltage Control of Oscillators 264 6.4.1 Location in the Tank Circuit 264 6.4.2 Variable Capacitance Devices 267 6.4.3 Voltage Control of Ring Oscillators 268 6.4.4 VCO Design Example 269

6.5 Oscillator Phase Noise and Estimation 270 6.5.1 LC Tank Phase Noise 272 6.5.2 Ring Oscillator Phase Noise 275 6.5.3 VCO Control Line Phase Noise 276 6.5.4 PN Example Calculation 276 References 278 Selected Bibliography 279

CHAPTER 7 CMOS Mixer Circuits 281

7.1 General Mixer Concepts 281 7.1.1 Terminology 281 7.1.2 Ideal Passive Mixers—Weak Nonlinearity 284 7.1.3 Ideal Active Mixers—Switching or Multiplying Mixers 285 7.1.4 Single- and Double-Balanced Mixers: General Definitions 287

7.2 Single MOS Mixer Topologies 288 7.2.1 Conceptual MOSFET Mixer (VGS- Vr) 288 7.2.2 Transconductance Mixer 290 7.2.3 Resistive Mixer 293 7.2.4 Design Example: Transconductance Mixer 295

7.3 Balanced MOSFET Mixers 297 7.3.1 Single Balanced Mixer 300 7.3.2 Double Balanced Mixer 301 7.3.3 Mixer Noise 304 7.3.4 Design Example: Single Balanced Mixer 307 7.3.5 Mixer Nonlinearities 310 7.3.6 Mixer Summary 311

7.4 Image Rejection Circuit Topologies 311 7.4.1 Architectures 312

7.5 I/Q Mixer Topologies 318 7.5.1 Architectures 318 References 320 Selected Bibliography 321

Page 6: CMOS RFIC Design Principles - GBV

Contents XI

CHAPTER 8

CMOS PLLs and Frequency Synthesizers 323

8.1 Introduction to the Phase Lock Loop 323 8.1.1 Definitions and Basic Operation 323 8.1.2 Phase Detection and Phase-Frequency Detection 326 8.1.3 Loop Filters 334 8.1.4 PLL Noise Behavior 346 8.1.5 PLL Behavioral Modeling 349

8.2 Frequency Synthesis 352 8.2.1 PLL-Based Synthesizers 352 8.2.2 Direct Digital Synthesis 360 References 366 Selected Bibliography 367

CHAPTER 9 CMOS Power Amplifiers 369

9.1 Review of Amplifier Terms 369 9.1.1 Linear 370 9.1.2 Nonlinear 371

9.2 Transconductance Amplifiers 373 9.2.1 Conduction Angle 375 9.2.2 Class A and B Design Examples 383

9.3 Switching Amplifiers 388 9.3.1 Class E Amplifiers 389 9.3.2 Class F Amplifiers 397

9.4 Other Amplifiers 401 9.4.1 Distributed Amplifiers 401 9.4.2 Kahn and Doherty Structures 406

9.5 Amplifier Linearizers 409 9.5.1 Basic Amplifier Linearization 410 9.5.2 Predistortion Linearizers 411 9.5.3 Feed-Forward Linearizers 412 References 414 Selected Bibliography 415

APPENDIX A Sample SPICE-3 Parameters 417

Sample SPICE BSIM Parameters 419

V-Parameters of the MOSFET Model 421

Parameter Conversion Equations for Two-Port Networks 423

Page 7: CMOS RFIC Design Principles - GBV

XII Contents

APPENDIX E

Constants and Some Properties of Silicon and CMOS-Related Materials 425

About the Author 427

Index 429


Recommended