Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

1(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8086

- 8

0386

SX 1

6-bi

t M

emor

y In

terf

ace

Thes

e m

achi

nes

diff

er fr

om th

e 80

88/8

0188

in s

ever

al w

ays:

• T

he d

ata

bus

is16

-bits

wid

e.•

The

IO/ M

pin

isre

plac

edw

ith

M/I

O(8

086/

8018

6)an

dM

RD

Can

dM

WTC

for

8028

6 an

d 80

386S

X.

•BH

E,B

us H

igh

Enab

le, c

ontr

ol s

igna

l is

adde

d.•

Add

ress

pin

A0

(or

BLE,

Bus

Low

Ena

ble)

is u

sed

diff

eren

tly.

The

16-b

it d

ata

bus

pres

ents

a n

ew p

robl

em:

The

mic

ropr

oces

sor

mus

t be

able

to r

ead

and

wri

te d

ata

to a

ny 1

6-bi

tlo

cati

on in

add

itio

n to

any

8-b

it lo

cati

on.

The

data

bus

and

mem

ory

are

divi

ded

into

ban

ks:

FFFF

FFFF

FFFD

0000

0300

0001

8 M

B

8 bi

tsD

15-D

8

FFFF

FEFF

FFFC

0000

0200

0000

8 M

B

8 bi

tsD

7-D

0

Hig

h ba

nkLo

w b

ank

Odd

byt

esEv

en b

ytes

BHE

sele

cts

BLE

sele

cts

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

2(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8086

- 8

0386

SX 1

6-bi

t M

emor

y In

terf

ace

BHE

and

BLE

are

used

to s

elec

t one

or

both

:

Bank

sel

ecti

on c

an b

e ac

com

plis

hed

in tw

o w

ays:

Sep

arat

e w

rite

dec

oder

s fo

r ea

ch b

ank

(whi

ch d

rive

CS)

. A

sep

arat

e w

rite

sig

nal (

stro

be) t

o ea

ch b

ank

(whi

ch d

rive

WE)

.N

ote

that

8-bi

trea

dre

ques

tsin

this

sche

me

are

hand

led

byth

em

icro

pro-

cess

or (i

t sel

ects

the

bits

it w

ants

to r

ead

from

the

16-b

its

on th

e bu

s).

Ther

e do

es n

ot s

eem

to b

e a

big

diff

eren

ce b

etw

een

thes

e m

etho

ds a

ltho

ugh

the

book

cla

ims

that

ther

e is

.

Not

e in

eit

her

met

hod

that

A0

does

not

con

nect

to m

emor

y an

d bu

s w

ire

A1

conn

ects

to m

emor

y pi

n A

0, A

2 to

A1,

etc

.

BH

EB

LEFu

ncti

on0

0Bo

th b

anks

ena

bled

for

16-b

it tr

ansf

er0

1H

igh

bank

ena

bled

for

an 8

-bit

tran

sfer

10

Low

ban

k en

able

d fo

r an

8-b

it tr

ansf

er1

1N

o ba

nks

sele

cted

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

3(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

8038

6SX

16-

bit

Mem

ory

Inte

rfac

e (S

epar

ate

Dec

oder

s) A0

A15

O0

O7

...

...

CS

A20

CS CS CS CS C

S CS CS

M/I

O

CS CS CS CS C

S CS CS

A0

A15

O0

O7

...

...

CS

BH

E

A17

BLE

G2A

G2B

G1

A B C0 1 2 3 4 5 6 774LS138

G2A

G2B

G1

A B C

0 1 2 3 4 5 6 7

(64K

X 8

)62

512

374LS138

A18

A19

A21

A22

A23

Data Bus

D0

to D

7

D8

to D

15

80386SXSeparate Decoders

(64K

X 8

)62

512

WE

OE

MW

TC

OE

WE

Add

ress

Bus

A1

to A

16

G2A

G2B

G1

A B C0 1 2 3 4 5 6 774LS138

MR

DC

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

4(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

Mem

ory

Inte

rfac

esSe

e te

xt fo

rSe

para

te W

rite

Str

obe

sche

me

plus

som

e ex

ampl

es o

f the

inte

gra-

tion

of E

PRO

M a

nd S

RA

M in

a c

ompl

ete

syst

em.

It is

just

an

appl

icat

ion

of w

hat w

e’ve

bee

n co

veri

ng.

8038

6DX

and

804

86 h

ave

32-b

it da

ta b

uses

and

ther

efor

e 4

bank

s of

mem

ory.

32-b

it,16

-bit

and

8-bi

t tra

nsfe

rs a

re a

ccom

plis

hed

by d

iffer

ent c

ombi

na-

tion

s of

the

bank

sel

ecti

on s

igna

lsBE

3,BE

2,BE

1,BE

0.

The

Add

ress

bits

A0

and

A1

are

used

wit

hin

the

mic

ropr

oces

sor

toge

ner-

ate

thes

e si

gnal

s.Th

ey a

redo

n’t c

ares

in th

e de

codi

ng o

f the

32-

bit a

ddre

ss o

utsi

de th

ech

ip (u

sing

a P

LD s

uch

as th

ePA

L 16

L8).

The

hig

h cl

ock

rate

s of

thes

e pr

oces

sors

usu

ally

req

uire

wai

t sta

tes

for

mem

ory

acce

ss.

We

will

com

e ba

ck to

this

late

r.

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

5(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

Pen

tium

Mem

ory

Inte

rfac

eTh

e Pe

ntiu

m, P

enti

um P

ro, P

enti

um II

and

III c

onta

in a

64-

bit d

ata

bus.

Ther

efor

e, 8

dec

oder

s or

8 w

rite

str

obes

are

nee

ded

as w

ell a

s 8

mem

ory

bank

s.Th

e w

rite

str

obes

are

obt

aine

d by

com

bini

ng th

e ba

nk e

nabl

e si

gnal

s(B

Ex) w

ith

the

MW

TC s

igna

l.M

WTC

is g

ener

ated

by

com

bini

ng th

e M

/IO

and

W/R

sig

nals

.BE

7

BE6

BE5

BE4

MW

TCBE

3

BE2

BE1

BE0

WR

7

WR

6

WR

5

WR

4

WR

3

WR

2

WR

1

WR

0

W/R

M/I

O

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

6(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

Pen

tium

Mem

ory

Inte

rfac

e

I1 I2 I3 I4 I5 I6 I7 I8 I9 I10

16L8O1

O2

O3

O4

O5

O6

O7

O8

A29

A30

A31

I1 I2 I3 I4 I5 I6 I7 I8 I9 I10

16L8O1

O2

O3

O4

O5

O6

O7

O8

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A0

A15

O0

O7

...

...

CE

OE

27512

D0-D7

D8-D15

D15-D23

D24-D31 D56-D63

D48-D55

D40-D47

D32-D39

A3-

A18

MR

DC

A0

A15

O0

O7

...

...

CE

OE

27512

A0

A15

O0

O7

...

...C

EO

E

27512

A0

A15

O0

O7

...

...

CE

OE

27512

A0

A15

O0

O7

...

...

CE

OE

27512

A0

A15

O0

O7

...

...

CE

OE

27512

A0

A15

O0

O7

...

...

CE

OE

27512

A0

A15

O0

O7

...

...

CE

OE

27512

(64K X 8)

WE

WE

WE

WE

WE

WE

WE

WE

WR0

WR1

WR2

WR3WR7

WR6

WR5

WR4

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

7(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

Pen

tium

Mem

ory

Inte

rfac

eIn

ord

er to

map

pre

viou

s m

emor

y in

to a

ddr.

spac

eFF

F800

00H

-FFF

FFFF

FH

Use

a16

L8 to

do

the

WR

0 -W

R7

deco

ding

usi

ngM

WTC

and

BE0

-BE7

.Se

e th

e te

xt --

Fig

ure

10-3

5.

;pin

s 1

2

3

4

5

6

7

8

9

10

A29

A30

A31

NC

NC

NC

NC

NC

NC

GN

D;p

ins

11

12

1

3

14

15

16

1

7 1

8 1

9

20U

2 C

E N

C

NC

NC

NC

NC

NC

NC

VC

C

Equa

tion

s:/C

E =

/U2

* A

29 *

A30

* A

31

I1 I2 I3 I4 I5 I6 I7 I8 I9 I10

16L8O1

O2

O3

O4

O5

O6

O7

O8

A29

A30

A31

I1 I2 I3 I4 I5 I6 I7 I8 I9 I10

16L8O1

O2

O3

O4

O5

O6

O7

O8

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

;pin

s 1

2

3

4

5

6

7

8

9

10

A19

A20

A21

A22

A23

A24

A25

A26

A27

GN

D;p

ins

11

12

13

1

4

15

16

17

1

8

19

20

A28

U2

NC

NC

NC

NC

NC

NC

NC

VC

C

Equa

tion

s:/U

2 =

A19

* A

20 *

A21

* A

22 *

A23

* A

24 *

A25

*A

26 *

A27

* A

28

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

8(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

Mem

ory

Arc

hite

ctur

eIn

ord

er to

bui

ld a

nN

-wor

dm

emor

y w

here

eac

h w

ord

isM

bits

wid

e (t

ypi-

cally

1, 4

or

8 bi

ts),

a st

raig

htfo

rwar

d ap

proa

ch is

to s

tack

mem

ory:

This

app

roac

h is

not

pra

ctic

al.

Wha

t can

we

do?

S 0 S 1 S 2 S N-2

S N-1

N words

Wor

d 0

Wor

d 1

Wor

d 2

Stor

age

cell

Wor

d N

-2W

ord

N-1

Inpu

t-O

utpu

t(M

bit

s)

A w

ord

is s

elec

ted

by s

etti

ng e

xact

lyon

e of

the

sele

ct b

its,

Sx,

hig

h.

This

app

roac

h w

orks

wel

l for

sm

all

mem

orie

s bu

t has

pro

blem

s fo

r la

rge

For

exam

ple,

to b

uild

a 1

Mw

ord

mem

orie

s.

(whe

re w

ord

= 8

bits

) mem

ory,

req

uire

s1M

sel

ect l

ines

, pro

vide

d by

som

eof

f-ch

ip d

evic

e.

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

9(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

Mem

ory

Arc

hite

ctur

eA

dd a

dec

oder

to s

olve

the

pack

age

prob

lem

:

This

doe

s no

t add

ress

the

mem

ory

aspe

ct r

atio

pro

blem

:

The

mem

ory

is 1

28,0

00 ti

me

high

er th

an w

ide

(220

/23 ) !

Besi

des

the

biza

rre

shap

efa

ctor

,the

desi

gnis

extr

emel

ysl

owsi

nce

the

ver-

tica

l wir

es a

re V

ERY

long

(del

ay is

at l

east

line

ar to

leng

th).

S 0 S 1 S 2 S N-2

S N-1

Wor

d 0

Wor

d 1

Wor

d 2

Stor

age

cell

Wor

d N

-2W

ord

N-1

Inpu

t-O

utpu

t(M

bit

s)

Decoder

A0

A1

A2

AK

-1

K =

log 2

N

one-

hot

Binary encoded address

This

red

uces

the

num

ber

of e

xter

nal

addr

ess

pins

from

1M to

20.

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

10(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

Mem

ory

Arc

hite

ctur

eTh

eve

rtic

alan

dho

rizo

ntal

dim

ensi

ons

are

usua

llyve

rysi

mila

r,fo

ran

aspe

ctra

tio

ofun

ity.

Mul

tipl

e w

ords

are

sto

red

in e

ach

row

and

sel

ecte

d si

mul

tane

ousl

y:S 0 S 1 S 2 S N

-2S N

-1

Stor

age

cell

Inpu

t-O

utpu

t(M

bit

s)

AK

AK

+1

AK

+2

AL-

1

Col

umn

addr

ess

=A

0

AK

-1

Bit l

ine

Wor

d lin

e

A0

to A

K-1

Row

add

ress

=A

K to

AL-

1

A c

olum

n de

code

r is

add

ed to

sele

ct th

e de

sire

dw

ord

from

a r

ow.

Col

umn

deco

der

Row Decoder

Sens

e am

psan

d dr

iver

sno

t sho

wn

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

11(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

Mem

ory

Arc

hite

ctur

eTh

is s

trat

egy

wor

ks w

ell f

or m

emor

ies

up to

64

Kbi

ts to

256

Kbi

ts.

Larg

er m

emor

ies

star

t to

suff

er e

xces

s de

lay

alon

g bi

t and

wor

d lin

es.

Ath

ird

dim

ensi

on is

add

ed to

the

addr

ess

spac

e to

sol

ve th

is p

robl

em:

Glo

bal D

ata

bus

Row

Add

ress

Col

umn

Add

ress

Bloc

kA

ddre

ss

Bloc

k 0

Bloc

k i

Bloc

k P-

1

Glo

bal

ampl

ifier

/dri

ver

I/O

Add

ress

: [R

ow][

Blo

ck][

Col

]

Bloc

k se

lect

or

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

12(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

Dyn

amic

RA

MD

RA

M r

equi

res

refr

eshi

ng e

very

2to

4 m

s.R

efre

shin

g oc

curs

aut

omat

ical

ly d

urin

g a

read

or

wri

te.

Inte

rnal

cir

cuit

ry ta

kes

care

of r

efre

shin

g ce

lls th

at a

re n

ot a

cces

sed

over

this

inte

rval

.

This

spe

cial

ref

resh

occ

urs

tran

spar

entl

y w

hile

oth

er m

emor

y co

mpo

nent

sop

erat

e an

d is

cal

led

tran

spar

ent r

efre

sh o

rcy

cle

stea

ling.

AR

AS-

only

cyc

le s

trob

es a

row

add

ress

into

the

DR

AM

, obt

aine

d by

7- o

r 8-

bit b

inar

y co

unte

r.

The

capa

cito

rs a

re r

echa

rged

for

the

sele

cted

row

by

read

ing

the

bits

out

inte

rnal

ly a

nd th

en w

riti

ng th

em b

ack.

For

a25

6K X

1 D

RA

M w

ith

256

row

s, a

ref

resh

mus

t occ

ur e

very

15.6

us(4

ms/

256)

.Fo

r th

e 80

86, a

rea

d or

wri

te o

ccur

s ev

ery

800n

s.T

his

allo

ws

19 m

emor

y re

ads/

wri

tes

per

refr

esh

or5%

of t

he ti

me.

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

13(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

Dyn

amic

RA

M

A0

A1

A2

A3

A4

A5

A6

A7

A8

RA

S

CA

S

Decoder

Row Latches Column Latches

8

WE

DIN

DO

UT

MUX

Dir

A9(

A0

from

inpu

t pin

on

RA

S)A

8S1 S0

MU

X25

6-to

-1M

UX

256-

to-1

MU

X25

6-to

-1M

UX

256-

to-1

64K

arr

ay(2

56 X

256

)

255

254

1 0

64K

arr

ay(2

56 X

256

)64

K a

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(256

X 2

56)

64K

arr

ay(2

56 X

256

)

256K

X 1

DR

AM

A0-

A7

A10

-A17

Bloc

k 0

Bloc

k 1

Bloc

k 2

Bloc

k 3

Thes

e si

gnal

s pr

ovid

e th

e bl

ock

addr

ess.

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

14(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

ED

O a

nd S

DR

AM

Mem

ory

Exte

nded

Dat

a O

utpu

t mem

ory:

Any

mem

ory

acce

ss in

an

EDO

mem

ory

(inc

ludi

ng a

ref

resh

) sto

res

the

256

bits

in a

set

of l

atch

es.

Any

sub

sequ

ent a

cces

s to

byt

es in

this

set

are

imm

edia

tely

ava

ilabl

e(w

ithou

t the

dec

ode

time

and

ther

efor

e w

ait s

tate

s).

This

wor

ksw

ellb

ecau

seof

the

prin

cipl

eof

spat

iall

ocal

ity,

and

impr

oves

syst

em p

erfo

rman

ce b

y 15

to 2

5 %

!

Sync

hron

ous

Dyn

amic

RA

M:

Acc

ess

tim

es a

re10

ns (f

or u

se w

ith

66M

Hz

bus)

and

8ns

(for

use

wit

h10

0MH

z bu

s).

Stan

dard

DR

AM

acc

ess

tim

es a

re60

ns.

How

ever

, the

se a

cces

s ti

mes

only

app

ly to

the

2nd,

3rd

and

4th

64-b

itre

ads

-- th

e fir

st ta

kes

the

sam

e ti

me

as a

sta

ndar

d D

RA

M.

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

15(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

ED

O a

nd S

DR

AM

Mem

ory

Sync

hron

ous

Dyn

amic

RA

M:

How

ever

, thi

s im

prov

es p

erfo

rman

ce a

gain

, par

ticu

larl

y fo

r re

ads

into

cach

e bl

ock

size

s of

256

bits

.

For

exam

ple,

256

bit

tran

sfer

take

sth

ree

bus

cycl

es fo

r th

efir

st re

ad a

ndth

ree

for

the

next

thre

e 64

-bit

wor

ds, f

or a

tota

l of7

bus

cyc

les.

Thi

s co

ntra

sts

wit

h th

e 3*

4 or

12 b

us c

ycle

s fo

r D

RA

M o

r ED

O.

Mea

sure

men

ts s

how

abo

ut a

10%

incr

ease

in p

erfo

rman

ce.

DR

AM

Con

trol

lers

:A

DR

AM

con

trol

ler

is u

sual

ly r

espo

nsib

le fo

r ad

dres

s m

ulti

plex

ing

and

gene

rati

on o

f the

DR

AM

con

trol

sig

nals

.

Thes

e de

vice

s te

nd to

get

ver

y co

mpl

ex.

We

will

focu

son

asi

mpl

erde

vice

,the

Inte

l82C

08,w

hich

can

cont

rolt

wo

bank

s of

256K

X 1

6 D

RA

M m

emor

ies

for

a to

tal o

f 1 M

B.

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

16(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

DR

AM

Con

trol

lers

:In

tel 8

2C08

:M

icro

proc

esso

r bi

ts A

1 th

roug

h A

18 (1

8 bi

ts) d

rive

the

9A

ddre

ss L

ow

(AL)

and

9A

ddre

ss H

igh

(AH

) bit

s of

the

82C

08.

9of

each

ofth

ese

are

stro

bed

onto

the

addr

ess

wir

esA

0th

roug

hA

8to

the

mem

orie

s.

Eith

er R

AS0

/CA

S0 o

r R

AS1

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re s

trob

ed d

epen

ding

on

the

addr

ess.

This

driv

esa

16-b

itw

ord

onto

the

Hig

han

dLo

wda

tabu

ses

(ifW

Eis

low

) or

wri

tes

an 8

or

16 b

it w

ord

into

the

mem

ory

othe

rwis

e.

WE

(fro

m th

e 82

C08

), BH

E an

d A

0 ar

e us

ed to

det

erm

ine

if a

wri

te is

to

be p

erfo

rmed

and

whi

ch b

yte(

s) (l

ow o

r hi

gh o

r bo

th) i

s to

be

wri

tten

.

Add

ress

bitA

20th

roug

hA

23al

ong

wit

hM

/IO

enab

leth

ese

mem

orie

sto

map

ont

o 1

MBy

te r

ange

(000

000H

-0FF

FFFH

).

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ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

17(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

DR

AM

Con

trol

lers

A0

A8

O0

O7

...

...

RA

SC

AS

41256A8

WE

(256

K X

8)

Low Data Bus

A0

A8

O0

O7

...

...

RA

SC

AS

41256A8

WE

A0

A8

O0

O7

...

...

RA

SC

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41256A8

WE

High Data Bus

A0

A8

O0

O7

...

...

RA

SC

AS

41256A8W

E

I1 I2 I3 I4 I5 I6 I7 I8 I9 I10

16L8O1

O2

O3

O4

O5

O6

O7

O8

A0

A20

R1

A0

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AL 0

AL 8... AH

0

AH

8

... WR

RES

ETC

LKPC

TL

RD

PE BS

RFR

QPD

1

RA

S0C

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RA

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A1

A18

S0 S1 A21

A22

A23

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A19

R2

WA

IT

82C08

BH

E

Syst

ems

Des

ign

& P

rogr

amm

ing

Mem

ory

III

CM

PE 3

10

18(M

ar. 6

, 200

2)U

MB

CU

M B

C

UNIVERSITY OF M

AR

YL

AN

D B

ALTIM

ORE COUNTY

1 9

6 6

DR

AM

Con

trol

lers

:16

L8 P

rogr

amm

ing:

;pin

s 1

2

3

4

5

6

7

8

9

1

0W

E BH

E A

0 A

20 A

21 A

22 A

23 N

C N

C G

ND

;pin

s 1

1

12

13

14

15

16

1

7

18

1

9

20M

IO C

E N

C N

C N

C N

C L

WR

HW

R P

E V

CC

Equa

tion

s:

/HW

R =

/BH

E *

/WE

I1 I2 I3 I4 I5 I6 I7 I8 I9 I10

16L8O1

O2

O3

O4

O5

O6

O7

O8

A0

A20

A21

A22

A23

M/I

O/L

WR

= /

A0

* /W

E

/PE

= /A

20 *

/A

21 *

/A

22 *

/A

23 *

MIO

WE

PE HW

RLW

R