Sp12 CMPEN 411 L03 S.1
CMPEN 411VLSI Digital Circuits
Spring 2012
Lecture 03: MOS Transistor
Kyusun Choi
[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
Sp12 CMPEN 411 L03 S.2
Review: Design Abstraction Levels
SYSTEM
GATE
CIRCUIT
VoutVin
CIRCUIT
VoutVin
MODULE
+
DEVICE
n+
S D
n+
G
Sp12 CMPEN 411 L03 S.3
The NMOS Transistor Cross Section
n areas have been doped with donor ions
(arsenic) of concentration ND - electrons
are the majority carriers
p areas have been doped with acceptor
ions (boron) of concentration NA - holes
are the majority carriers
Gate oxide
n+
Source Drain
p substrate
Bulk (Body)
Field-Oxide
(SiO2)n+
Polysilicon
Gate
L
W
Sp12 CMPEN 411 L03 S.4
The MOS Transistor
Polysilicon Aluminum
Sp12 CMPEN 411 L03 S.5
Switch Model of NMOS Transistor
Gate
Source
(of carriers)
Drain
(of carriers)
| VGS |
| VGS | < | VT | | VGS | > | VT |
Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’)
Ron
Sp12 CMPEN 411 L03 S.6
Switch Model of PMOS Transistor
Gate
Source
(of carriers)
Drain
(of carriers)
| VGS |
| VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| |
Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’)
Ron
Sp12 CMPEN 411 L03 S.7
Threshold Voltage Concept
S D
p substrate
B
GVGS +
-
n+n+
depletion
regionn channel
The value of VGS where strong inversion occurs is called
the threshold voltage, VT
Sp12 CMPEN 411 L03 S.8
The Threshold Voltage
VT = VT0 + (|-2F + VSB| - |-2F|)where
VT0 is the threshold voltage at VSB = 0 and is mostly a function of the manufacturing process
Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc.
VSB is the source-bulk voltage
F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at 300K is the thermal voltage; NA is the acceptor ion concentration; ni 1.5x1010 cm-3 at 300K is the intrinsic carrier concentration in
pure silicon)
= (2qsiNA)/Cox is the body-effect coefficient (impact of changes in VSB) (si=1.053x10-10F/m is the permittivity of silicon; Cox = ox/tox is the gate oxide capacitance with ox=3.5x10-11F/m)
Sp12 CMPEN 411 L03 S.9
The Body Effect
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
-2.5 -2 -1.5 -1 -0.5 0
VBS (V)
VSB is the substrate
bias voltage (normally
positive for n-channel
devices with the body
tied to ground)
A negative bias Vbs
causes VT to increase
from 0.45V to 0.85V
Sp12 CMPEN 411 L03 S.10
Transistor in Linear Mode
S
D
B
G
n+n+
Assuming VGS > VT
VGS VDS
ID
x
V(x)- +
The current is a linear function of both VGS and VDS
Sp12 CMPEN 411 L03 S.11
Voltage-Current Relation: Linear Mode
For long-channel devices (L > 0.25 micron)
When VDS VGS – VT
ID = k’n W/L [(VGS – VT)VDS – VDS2/2]
where
k’n = nCox = nox/tox = is the process transconductance parameter (n is the carrier mobility (m2/Vsec))
kn = k’n W/L is the gain factor of the device
For small VDS, there is a linear dependence between VDS
and ID, hence the name resistive or linear region
Sp12 CMPEN 411 L03 S.12
Transistor in Saturation Mode
S
D
B
GVGS VDS > VGS - VT
ID
VGS - VT- +n+ n+
Pinch-off
Assuming VGS > VT
VDS
The current remains constant (transistor saturates)
Sp12 CMPEN 411 L03 S.13
Voltage-Current Relation: Saturation Mode
For long channel devices
When VDS VGS – VT
ID’ = k’n/2 W/L [(VGS – VT) 2]
since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at VGS – VT
However, the effective length of the conductive channel is modulated by the applied VDS, so
ID = ID’ (1 + VDS)
where is the channel-length modulation (varies with the inverse of the channel length)
Sp12 CMPEN 411 L03 S.14
Current Determinates
For a fixed VDS and VGS (> VT), IDS is a function of
the distance between the source and drain – L
the channel width – W
the threshold voltage – VT
the thickness of the SiO2 – tox
the dielectric of the gate insulator (e.g., SiO2) – ox
the carrier mobility
- for nfets: n = 500 cm2/V-sec
- for pfets: p = 180 cm2/V-sec
Sp12 CMPEN 411 L03 S.16
Long Channel I-V Plot (NMOS)
0
1
2
3
4
5
6
0 0.5 1 1.5 2 2.5
VDS (V)
X 10-4
VGS = 1.0V
VGS = 1.5V
VGS = 2.0V
VGS = 2.5V
Linear Saturation
VDS = VGS - VT
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.43V
cut-off
0.57V
1.07V
2.07V
1.57V
Sp12 CMPEN 411 L03 S.17
Short Channel Effects
0
10
0 1.5 3
(V/m)
For an NMOS device with L of .25m, only a couple of volts
difference between D and S are needed to reach velocity
saturation
c=
Behavior of short channel device mainly due to
Velocity saturation
– the velocity of the
carriers saturates due
to scattering (collisions
suffered by the
carriers)
5
Sp12 CMPEN 411 L03 S.18
Voltage-Current Relation: Velocity Saturation
For short channel devices
Linear: When VDS VGS – VT
ID = (VDS) k’n W/L [(VGS – VT)VDS – VDS2/2]
where
(V) = 1/(1 + (V/cL)) is a measure of the degree of velocity saturation
Saturation: When VDS = VDSAT VGS – VT
IDSat = (VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT2/2]
Sp12 CMPEN 411 L03 S.19
Velocity Saturation Effects
0
10
VDSAT < VGS – VT so
the device enters
saturation before VDS
reaches VGS – VT and
operates more often in
saturation
For short channel devices
and large enough VGS – VT
IDSAT has a linear dependence wrt VGS so a reduced
amount of current is delivered for a given control
voltage
Sp12 CMPEN 411 L03 S.20
Short Channel I-V Plot (NMOS)
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5VDS (V)
X 10-4
VGS = 1.0V
VGS = 1.5V
VGS = 2.0V
VGS = 2.5V
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.43V
Early Velocity
Saturation
Linear Saturation
Sp12 CMPEN 411 L03 S.21
Long Channel I-V Plot (NMOS)
0
1
2
3
4
5
6
0 0.5 1 1.5 2 2.5
VDS (V)
X 10-4
VGS = 1.0V
VGS = 1.5V
VGS = 2.0V
VGS = 2.5V
Linear Saturation
VDS = VGS - VT
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.43V
cut-off
0.57V
1.07V
2.07V
1.57V
Sp12 CMPEN 411 L03 S.22
MOS ID-VGS Characteristics
0
1
2
3
4
5
6
0 0.5 1 1.5 2 2.5VGS (V)
Linear (short-channel)
versus quadratic (long-
channel) dependence of
ID on VGS in saturation
Velocity-saturation
causes the short-
channel device to
saturate at substantially
smaller values of VDS
resulting in a substantial
drop in current drive
(for VDS = 2.5V, W/L = 1.5)
X 10-4
Sp12 CMPEN 411 L03 S.23
Short Channel I-V Plot (PMOS)
-1
-0.8
-0.6
-0.4
-0.2
0
0-1-2 VDS (V)
X 10-4
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
All polarities of all voltages and currents are reversed
Sp12 CMPEN 411 L03 S.24
The MOS Current-Source Model
VT0(V) (V0.5) VDSAT(V) k’(A/V2) (V-1)
NMOS 0.43 0.4 0.63 115 x 10-6 0.06
PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1
S D
G
B
ID
ID = 0 for VGS – VT 0
ID = k’ W/L [(VGS – VT)Vmin–Vmin2/2](1+VDS)
for VGS – VT 0
with Vmin = min(VGS – VT, VDS, VDSAT)
and VGT = VGS - VT
Determined by the voltages at the four terminals and
a set of five device parameters
Sp12 CMPEN 411 L03 S.25
Other (Submicon) MOS Transistor Concerns
Velocity saturation
Subthreshold conduction (aka weak inversion)
Transistor is already partially conducting for voltages below VT
Threshold variations
In long-channel devices, the threshold is a function of the length (for low VDS)
In short-channel devices, there is a drain-induced threshold barrier lowering (DIBL) at the upper end of the VDS range (for small L)
Parasitic resistances
resistances associated with the source and drain contacts
Latch-up
S
G
D
RS RD
Sp12 CMPEN 411 L03 S.26
Subthreshold Conductance
0 0.5 1 1.5 2 2.5
VGS (V)
10-12
10-2
Subthreshold
exponential
region
Quadratic region
Linear region
VT
Transition from ON to
OFF is gradual (decays
exponentially)
Current roll-off (slope
factor) is also affected by
increase in temperature
S = n (kT/q) ln (10)(typical values 60 to 100
mV/decade)
Has repercussions in
dynamic circuits and for
power consumptionID ~ IS e (qVGS
/nkT) where n 1
Sp12 CMPEN 411 L03 S.27
Subthreshold ID vs VGS
VGS from 0 to 0.5V
ID = IS e (qVGS
/nkT) (1 - e –(qVDS
/kT))(1 + VDS)
Sp12 CMPEN 411 L03 S.28
Subthreshold ID vs VDS
VDS from 0 to 0.3V
ID = IS e (qVGS
/nkT) (1 - e –(qVDS
/kT))(1 + VDS)
Sp12 CMPEN 411 L03 S.29
Threshold Variations
VT
L
Low VDS
threshold
Threshold varies as a
function of the length of the transistor (for low VDS)
For short channel devices, the
threshold varies as a function of
VDS - drain-induced barrier lowering (DIBL)
VDS
VT
Long channel threshold
Sp12 CMPEN 411 L03 S.30
DIBL
For high VDS, the drain depletion region interacts with the source near the channel surface lowering the source potential barrier. The source then injects carriers into the channel without the gate playing a role.
DIBL is enhanced at higher VDS and shorter L.
0 0.5 1 1.5 2 2.5
VGS (V)
10-12
10-2
increasing VDS
Sp12 CMPEN 411 L03 S.31
Next Time: The CMOS Inverter
VDD
Vout
CL
Vin
Next lecture
CMOS inverter – a static view
- Reading assignment – Rabaey, et al, 5.1-5.3
