CMPEN 411 VLSI Digital Circuits

Kyusun Choi

Chip Fabrication and Layout

Fig. 12 Increase in wafer sizes, showing the increased number of dice (chips) per wafer available when increasing the wafer area. (a) 100-mm (4-in.) wafer. (b) 150-mm (6-in.) wafer. (c) 300-mm (12-in.) wafer. (Intel Corp.)

Fig. 7 Person with lint-free garments in a vertical laminar-flow clean room forintegrated-circuit fabrication with 300-mm (12-in.) wafer. (Personnel do not handle wafers in this manner. This was done just for the photograph.) (Intel Corp.)

Fig. 1. Cross-section of a 64-bit

high-speed processor in a 90nm

technology. (Courtesy: IBM)