CMS GCT ESR: Concentrator Card (with post ESR modifications)

CMS GCT ESR: Concentrator Card: Greg Iles ([email protected])10 May 2006 1

CMS GCT ESR: Concentrator CardCMS GCT ESR: Concentrator Card(with post ESR modifications)(with post ESR modifications)

24th May 200624th May 2006

version 7version 7

Changes on p8/9: Removal of unfinished jetsChanges on p8/9: Removal of unfinished jets


What is the concentrator ?What is the concentrator ?

Last processing Last processing stage before stage before calorimetry data calorimetry data sent to Global sent to Global TriggerTrigger

– 9U VME64x card

– 2 DPMCs mounts for electron-leaf cards

– 2x3 Samtec cables to interface to jet-wheel cards

– 1 DPMC mount for Global Trigger interface


Incoming dataIncoming data

Jet interface Jet interface – Arrives from 2 x wheel cards via high speed Samtec cable

assemblies• 240 LVDS signals from each Wheel card (40 MHz DDR -> 80Mhz)

– 200 for trigger path– 34 for control & readout– 2 for clk– 4 for jtag

Electron interfaceElectron interface– Arrives from 2 x leaf dual PMC cards mounted on concentrator card

• Only 206 out of 360 I/O used)– 160 for trigger path– 40 for control & readout– 2 for clk– 4 for jtag


Outgoing dataOutgoing data

Global Trigger interface Global Trigger interface – Tranmit to Global Trigger on 7 cables

• 2 unidirectional SerDes channels per cable• Each channel driven by NatSemi DS92LV16• Takes 16 bit parallel data at 80MHz. Transmits at 1.44 Gb/s

– Loopback testing possible with 1 extra cable– Mounted on Dual PMC

• All 360 I/O connected• Allows relatively fast & cheap modifications if problems exist with

high speed serial links

Slink to DAQSlink to DAQ– Signals connect to VME J2

• Uses ECAL transition card to host SLINK transmitter card


ImplementationImplementation

ProcessingProcessing– Two Xilinx Virtex4 FPGAs– XC4VLX100-FF1513

• Must concentrate large amount of data– Choose package with most I/O

• Integrated differential termination makes layout simpler

• High speed I/O provide reserve capability

CommunicationCommunication– Xilinx Virtex2 FPGA– XC2V3000-BF957

• Robust in 3.3V enviroment– VME 64x interface– Slink– TTCrx– Ethernet PHY & USB for future

Elec FPGAElec FPGA– Isolated Electrons– Non-Isolated

Electrons– Energy Sums– Jet Counts

Jet FPGAJet FPGA– Forward Jets– Central Jets– Tau Jets


TriggerTrigger

Electron η+ datafrom Leaf DPMC

Jet η+ datafrom

Wheel Card

ElectronV4 FPGA

JetV4 FPGA

Global Trigger DPMC

7 x dual channelSerdes links

Electron η- datafrom Leaf DPMC

Jet η- datafrom

Wheel Card

Sorted Et and jet count2 x 50 Diff Pairs

Via Samtec J2 & J3

Electron data2 x 160 Single EndedVia J11, J12, J21, J22

All paths 40 MHz DDR -> 80MHz

Sorted & unfinished jets2 x 150 Diff Pairs

Via Samtec J1 & J3

80 Single Ended

1) Iso Elec2) Non-Iso Elec3) Energy Sum4) Jet Counts

5) Forward Jet6) Central Jet7) Tau Jet

2 x 180 Single EndedVia fully populated 1/2 DPMC

Leaf

Leaf

Leaf

Leaf

Leaf

Leaf


Jet Trigger: GuideJet Trigger: Guide

6 x Leaf (3 per Wheel)

Jet

2 x Wheel

All numbers in “bits” assuming 80 MHz data transmission on single-ended & differential pairs6 clustered jets (12) & Ht(13) = 6 clustered jets of 12 bits each and 13bits for Ht per leaf card H: ~3x160 = “Have” aprrox 160 bits from each of the 3 leaf cardsR: 3x85 = “Require” 85 bits from each of the 3 leaf cards (6x12+13)

What does this mean ?

How to understand the next slide

Spare capacity on bus

Bus at limit, although running at double capacity (160MHz data) should be possible in future

U21 x JetFinder

& Cntrl 6 clustered jets (12) & Ht(13)H: ~3x160, R: 3x85


Jet Trigger: Old DesignJet Trigger: Old Design

Electron

Jet

GT

Leave at least 2bits per bus for BC0 (equivalent to 1 signal at 80MHz)


5) Forward Jet6) Central Jet7) Tau Jet8) LoopBack cable


Energy

Jet

U21 x JetFinder

& Cntrl

U12 x JetFinder

Comm

400

12 sorted jets (14)H: 2x174, R: 2x168

3 PreClustered, Unsorted Jets (12GH or 14MH)H: 6x42, R: 6x36 (GH) or 6x42 (MH)

2 x Wheel 1 x Concentrator

Et(13), Exy(26)

JetCnt(36)H: 2x80, R: 2x75

Ctnrl (64), Et(13),Exy(26GH or 34MH)H: ~3x160, R: 3x111

6 clustered jets (12) & Ht(13)H: ~3x160, R: 3x85

12 clustered jets (12)& Ht(13)

H: ~3x320, R: 3x157

Ht(13)H: 2x20, R: 13

JetCnt(36)H: 160, R: 36

Ht(13) & JetCnt(36) from Eta0

H: 160, R: 49

SerDes pair (40)H: 180, R: 160



Jet Trigger: New DesignJet Trigger: New Design

Electron

Jet

GT

Leave at least 2bits per bus for BC0 (equivalent to 1 signal at 80MHz)

1) Iso Elec2) Non-Iso Elec3) Energy Sum4) LoopBack cable

5) Forward Jet6) Central Jet7) Tau Jet8) JetCounts


Energy

Jet

U21 x JetFinder

& Cntrl

U12 x JetFinder

12 sorted jets (14 + 2 spare) JetCnt(60)

H: 2x280, R: 2x192

2 x Wheel 1 x ConcentratorEt(13), Exy(34)Ht(13)

H: 2x80, R: 2x60

Ctnrl (64), Et(13), Exy(34), Ht(13)H: ~3x160, R: 3x124

6 clustered jets (12+2 spare)JetCount(60)

H: ~3x160, R: 3x144

12 clustered jets (12+2 spare)JetCount(60)

H: ~3x320, R: 3x228

H: 160, R: 0 H: 160, R: 0



H: 2x20, R: 2x0

Semi 3x3 requires 2x3 pre clusters (18)

H: 120, R: 108

Et(13), Exy(34), Ht(13)Semi 3x3 requires

2x3 pre clusters (18)H: 400, R: 168

Next Leaf


Control & ReadoutControl & Readout

Electron η+ datafrom Leaf DPMC

ElectronV4 FPGA

JetV4 FPGA

Electron η- datafrom Leaf DPMC

2 x 34 Diff Pairs Via Samtec J2

V2 driving LVDSEXT

2 x 40 Single EndedVia J23


5) Forward Jet6) Central Jet7) Tau Jet

2 x 32 Single EndedCommV2 FPGA

40 MHz DDR -> 80MHz

100

V4V2

100DCI LVDS requires62.5mW per pair

SlinkVME

TTCrxClock Control

FMMUSB

Ethernet

Jet η+ datafrom

Wheel Card

Jet η- datafrom

Wheel Card

Leaf

Leaf

Leaf

Leaf

Leaf

Leaf


Design issuesDesign issues

High speed serial linksHigh speed serial links– Susceptible to power supply noise

• SerDes power will be provided by local linear regulators

– Mounted on DPMC• If design revision necessary

cost and turnaround time should be substantially less.

PCB layout concerns dominatePCB layout concerns dominate– Must do a reasonable job of length

matching• Retain option for increased

speed• Must match as pairs

– More time consuming that SE bus matching

– Once again, budget extra time for layout

Virtex 4 FPGAsVirtex 4 FPGAs– New devices

• Highly desirable due to enhanced I/O

– Conservative design requirements• Likely requires .0201

decoupling cap scheme• Blind/buried vias, small drill

diameters– .008” used extensively on leaf

card

Straightforward, but physically Straightforward, but physically large designlarge design

– Layout may be longer than estimated

– Risk of error or omission higher due to design size


TestingTesting

Connectivity testConnectivity test– Can test connectivity of ~80% of board with either JTAG or

custom firmware.• Samtec connections

– Loopback with production cables

• PMC sites– DPMC test board (Matt Stettler)

• FPGA-FPGA connnections

Insitu testsInsitu tests– VME & Slink etc are probably best tested by final or test

firmware • E.g. for VME by writing/reading register many times• Alternative is a dedicated JTAG loopback system.

– Time consuming to construct


Status of layoutStatus of layout


ScheduleSchedule

HardwareHardware– Concentrator currently in

layout.• Aim to finish before

end June • Component order to

be placed this week or next

– PCB manufacture & assembly in July

• Manufacture 6 PCBs• Assemble 2

– At present 1 month ahead of schedule

• However need GT DPMC card schematics & layout

FirmwareFirmware– VME64x and TTC distribution

currently under test in LTC• Need to debug serial VME64x

– Electron• Sort by rank in leaf cards &

concentrator– Jet

• Eta-0 jets– Seed & cluster – Convert Et to rank– Distinguish between tau, central

and forward jets

• Sort all jet types by ranks– GT interface– Less than 3 months until boards

return


AppendixAppendix

Following slides list the signal counts Following slides list the signal counts and how they were obtainedand how they were obtained


Signal: From single Jet-WheelSignal: From single Jet-Wheel

Jet data sent to ‘”Jet’” FPGAJet data sent to ‘”Jet’” FPGA– Top 4 rank of central, forward and tau

jets. Hence 12 objects– 12 sorted jets (min 14 bits each)

• 5 bits phi• 3 bits eta (no need for sign)• 6 bits rank

– 9 unsorted jets (min 14 bits each)• 18 phi regions -> max 9 jets• 1 bit phi (each jet covers 2 phi)• 0 bits eta (events in the middle)• 10 bits Et• 1 bit tau veto• 2 bits spare

– Total = 147 signals @ 80MHz • 294 bits

– Available = 150 signals @ 80MHz

Jet data sent to “Elec” FPGAJet data sent to “Elec” FPGA– Et-total (13 bits)

• 12+1 bits mag + overflow– Et-missing (26 bits)

• x & y components• 12+1 bits mag + overflow

– Jet counts (36 bits)• 6 jet count regions each 5 bit• Alternative more flexible

system of 12 jet count regions of 3 bits each (not TDR)

– Ht (13 bits)• 12+1 bits mag + overflow

– Total = 38 + 7 signals @ 80MHz• 75 + 13 bits

– Available = 40 + 10 signals @ 80MHz


Signal: From single Elec-Leaf Signal: From single Elec-Leaf

Electron data sent to ‘”Elec” FPGAElectron data sent to ‘”Elec” FPGA– Top 4 rank of isolated and non-isolated electrons (min 14 bits each)– 8 electron objects (14 bits)

• 5 bits phi• 3 bits eta (no need for sign)• 6 bits rank

– To reduce the latency the FPGAs on the electron leaf card will not share data. Hence each FPGA will send 8 electron objects to the concentrator (i.e. concentrator receives 16 electron objects from each leaf card)

– Total = 112 signals @ 80MHz• 224 bits



Signal: Between Jet/Elec FPGAsSignal: Between Jet/Elec FPGAs

Data transmitted between V4 FPGAsData transmitted between V4 FPGAs– The 9 unsorted jets on the boundary between the two wheels are

turned into clusters in the “Jet” FPGA– These jets will contribute to Ht and the jet-counts being summed in

the “Elec” FPGA

– Ht (13 bits)• 12+1 bits mag + overflow

– Jet counts (60)• 12 types each 5 bits

– Total = 37 signals @ 80MHz• 73 bits



Signal: Control & ReadoutSignal: Control & Readout

ReadoutReadout– Max slink sustained rate = 200 MB/s– Assume no source generates more than 100MB/s

• 10bits @ 80MHz

ControlControl– Serial VME

• 2bits– L1A & BC0

• 2bits– Serial Fast Commands from TTC B channel (e.g. resync)

• 1bit– AsyncReset

• 1bit– Serial FastFeedback

• 1bit

Total Total – Required = 17 signals– Minimum available = 32 signals


Signal: GT interfaceSignal: GT interface

Global Trigger interface Global Trigger interface – GT receives 7 cables (2 unidirectional SerDes channels per cable)

• Each channel driven by NatSemi DS92LV16• Takes 16 bit parallel data at 80MHz. Adds 2 bits. Transmits at 1.44 Gb/s• Require 2 bits for powerdown/sync• 252 signals (7 x 2 x 18)

– Require 1 cable for loopback testing• Generates 16 bits parallel data• Require 4 bits for lock, refclk, powerdown and recovered clk• 40 signals (1 x 2 x 20)

– NatSemi chips do not have JTAG• Could use local loopback to test data lines only.• Require 2 bits for outenable and local loopback on all chips• 44 signals ((14 x 2) + 16

– Mounted on dual PMC • All 380 I/O connected, • Require at least 292 signals, perhaps 336

SlinkSlink– Signals connect to VME J2 and hence to ECAL transition card

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CMS GCT ESR: Concentrator Card (with post ESR modifications)

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