CMS PIXEL Test Chip FCP130

FermilabF.Fahim, G.Deptuch, T.Zimmerman,

A.Shenai, J. Hoff, M.Trimpl

22

Design of a test CMS pixels chip

Farah Fahim - Fermilab

• Technology platform: GF130nm

• ASIC size: 5.5 mm x 8.5 mm

• Pixel size: 30 µm x 100 µm

• Analog part: 20 µm x 100 µm

• Digital Part: 10 µm x 100 µm

• Rows x Columns: 48 x 160

• Column pattern: A D D A - A D D A -….

• 4 columns are grouped together to create a superColumn (192 pixels)

• Each ASIC has 40 super columns.

• Analog Pixel options:• 1) Preamplifier + 3 bit Flash ADC (praying mantis ) + hit comparator (independent of ADC to get hit in the

processing – to be reviewed on final realizations)

• 2) Preamplifier + 3 bit ADC based on asynchronous conversion using in-pixel oscillator triggered by signal (more power consumption but more compact + perspectives for other uses)

• Translation of major blocs to 65 nm node is planned to be done collaboratively with INFN

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Analog Front-End

Farah Fahim - Fermilab

Id

InPreamp Out

Active transistor feedback resistance

Comparator

Comparator

Comparator

ComparatordiscReset

Itail> Id+ Ileak

Comparator

Comparator

Comparator

Comparator

Vth0

Vth1

Vth2

Vth3

Vth4

Vth5

Vth6

Vhit

Digital Encoder (7 to 3)

Preamp (regulated Cascode)

Source follower

Hit

Leakage current compensation circuit

• Dynamic range 0.32fC – 2.5fC• Power Consumption : 5uA (preamp ) + 8uA (all comparators)

44 Farah Fahim - Fermilab

Design Details Front-End

Comparator (compact, single-ended architecture,

Auto-zeroed, “lurk-trigger-done” – praying mantislow-power, fast, insensitive to corners)

Low capacitance to minimize threshold transients

Out

native Vt

Clamp to maintain constant Idd

ΔVth

Gain with positive regeneration

ΔVth ΔVsig

In

VthVdd

discReset for switching same rate as bunch crossing clock

Farah Fahim - Fermilab 5

Analog simulationsTransient simulation2.5fC charge

Charge pileup simulation(2.5fC charge @ 1Mhz)

Farah Fahim - Fermilab 6

Analog simulationsTransient Noise analysis0.32fC charge

Preamplifier rms noise: 62e-Comparator rms jitter: 725psIncluding Correlated double sampling noise: 86e-

I/P detector capacitance Preamp rms noise Comparator rms jitter15fF 52e- 644p30fF 62e- 725p45fF 70e- 777p60fF 77e- 851p100fF 88e- 1.1n

Farah Fahim - Fermilab 7

9 10 11 12 13 14 15 16

Vth (mV)

A constant I/P charge of 1000e- threshold voltage(Vth) is varied from 10mV to 16mV, the comparator output pulse width is measured. Determined by comparator reset For a 500ps pulse width Vth must be set to 14.83mV

Parametric Analysis Linearity

Variable a = charge ( 5u = 2.5fC)

Farah Fahim - Fermilab 8

With an input charge of 0.125fC, the comparator threshold voltage is varied from 11mV to 16mV

Corner Analysis

0.0105

0.011

0.0115

0.012

0.0125

0.013

0.0135

0.014

0.0145

Series1

0:Vth vs. corners (charge =0.125fC)

Vth

(V)

1.10E-02 1.30E-02 1.50E-020.00E+00

1.00E-09

2.00E-09

3.00E-09

4.00E-09

CompOut <0> vs. Vth (charge =0.125fC)

ss

sf

fs

ff

tt

Vth (V)

Com

pOut

<0>

pulse

wid

th (s

)

Farah Fahim - Fermilab 9

Charge injected at 12.5ns; Comparing montecarlo sims of process only, mismatch only and both for I/P charge of 800e- at Vth = 12mV

Montecarlo AnalysisComparator Mismatch only

0.00E+00

5.00E-09

1.00E-08

1.50E-08

2.00E-08

2.50E-08

3.00E-08

(preamp + comparator)

Min

Max

Mean

Sigma

Com

pOut

All MismatchProcess

Time at which comparator responds (ns), I/P charge injected at 12.5ns

Farah Fahim - Fermilab 10

Comparator LayoutPixel layout Analog

Dimension: 7um x 11umPost Layout simulations performed and layout is optimized. Capacitor C2 is critical and parasitic metal over the layout must be avoided.

Dimension: 100um x 20um.

Layout

C2

Farah Fahim - Fermilab 11

Digital Pixel

• Thermometric encoder• Priority encoder sparsification• Hit processor• Mask/demask capability• Functionality finalized, parasitic

extracted superColumn simulated. Simulations confirm performance.

• Double pixel layout (20µm x 100µm)

Farah Fahim - Fermilab 12

Digital Simulation

• Super column simulation • Previous_Frame has no

hits (default pixel no. is 5)• Frame 1 has 2 hits: Pixel 1(16) and Pixel 48(63)• With ADC values of

Max (7) and Min (0) respectively

BXClk

Hit

alertConflux

ReadStrobe

ADC Value

Pixel no.

Column no.

Farah Fahim - Fermilab 13

• Bunch crossing clock distribution across the chip (proposed solution does not suffer from ballistic deficit but relies on clock distribution)

• Delays across the chip are chip size dependant

• For a column with 48 pixels ~5mm long post layout simulations indicate around 800ps delay

• Across columns(160) ~5mm, with the aid of digital place and route we estimate an additional delay of 200ps

Top level considerations

Supercolumn Layout (zoomed ~10 pixels)

Farah Fahim - Fermilab 14

Readout Electronics• Conflux: Asynchronous data readout scheme with

implicit multiplexing of data• Uses a 4 phase handshaking protocol• FIFO2 daisy: enables daisy chaining of data from

every pixel to the output. • Also used to communicate between the

sparsification logic and Conflux

Farah Fahim - Fermilab 15

FIFO2daisy is a set of three 5-word deep FIFOs arranged in phases such that in any given BX Clock period, one FIFO is in the Write Phase, one is in the Read Phase and one is being reset.

In the Write Phase, the FIFO accepts up to 5 words from the pixel matrix.

In the Read Phase, the FIFO outputs any stored words to Conflux.

At any time, the contents of all three FIFOs can be captured without interfering with normal operations. Then this captured word can be streamed out of one long daisy chain that includes all double columns.

FIFO 2 daisy

Farah Fahim - Fermilab 16

Conflux – an asynchronous 2-to-1 multiplexor with data latching and utilizing a four-phase handshake

Conflux

1717 Farah Fahim - Fermilab

Design of a test CMS pixels chip

• Architecture is defined and designed:Sparsified readout using priority encoder (VIPIC1)Second layer of sparsification and data transfer with Conflux (asynchronous digital pipeline system)

• Layout of the analog pixel finished

• 2 types of ADC’s are planned to be tested by dividing the matrix into 2 parts

• Bump bonding to sensors built by Perdue U.

• Submission in May depending on run availability

• Depending on resources (manpower and funding) and exchange of ideas translation to 65 nm in collaboration with INFN.