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THE COMPUTER SYSTEM
Computer function andInterconnection
o Computer functions
o Interconnection Structureso Bus Interconnection
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Structure & Function
Structure is the way in which componentsrelate to each other
Function is the operation of individualcomponents as part of the structure
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Function
All computer functions are:Data processing
Data storage
Data movement
Control
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Functional View
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Operations (a) Data movement
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Operations (b) Storage
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Operation (c) Processing from/to storage
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Operation (d)
Processing from storage to I/O
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Structure - Top Level
Computer
MainMemory
Input
Output
Systems
Interconnection
Peripherals
Communication
lines
CentralProcessing
Unit
Computer
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Structure - The CPU
Computer Arithmeticand
Login Unit
Control
Unit
Internal CPU
Interconnection
Registers
CPU
I/O
Memory
System
Bus
CPU
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Hardwired Program
For every instruction there is a small set of basic
logic components are used These component can be combined in various ways
to store binary data and to perform arithmetic andlogical operations on data
For each computation , a confirmation of logiccomponent is design.
This is as process of connecting the variouscomponents in desire configuration as form of
programming This resulting program is in form of hard ware so
known as hardwired program
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Program is actually sequence of steps andfor each step some arithmetic and logical
operation is performed on some data we need to provide the general purpose
hardware program that can accept a codeand generate control signal
So instead of rewriting hardware for eachnew program, we need to provide a newsequence of codes
Each codes nothing but instruction andpart of hardware interpret each instructionand generates control signal
This new method is called as software
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General purpose
arithmetic and
logic functions
ResultData
ResultData
Sequence of
arithmetic andlogic functions
Instruction
interpreter
Instruction
code
Control signal
Programming in Hardware
Hardware and Software Approaches
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What is a program?
A sequence of steps
For each step, an arithmetic or logicaloperation is done
For each operation, a different set of
control signals is needed
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Function of Control Unit
For each operation a unique code is
providede.g. ADD, MOVE
A hardware segment accepts the code and
issues the control signals
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CPU Components
The Control Unit and the Arithmetic and
Logic Unit constitute the CentralProcessing Unit
Data and instructions need to get into the
system and results outInput/output
Temporary storage of code and results isneededMain memory
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Computer Components:
Top Level View
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Instruction Format
Opcode
0 3 4 15
Ex.Opcodes
0001 = Load AC from Memory
0010 = Store AC to Memory
0101= Add to AC from Memory
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Instruction Cycle
Two steps:Fetch
Execute
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Fetch Cycle
Program Counter (PC) holds address of
next instruction to fetch
Processor fetches instruction frommemory location pointed to by PC
Increment PCUnless told otherwise
Instruction loaded into InstructionRegister (IR)
Processor interprets instruction andperforms required actions
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Example of Program Execution
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Instruction Cycle Diagram
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Interrupts
Mechanism by which other modules (e.g.
I/O) may interrupt normal sequence ofprocessing
Program
e.g. overflow, division by zero Timer
Generated by internal processor timer
Used in pre-emptive multi-tasking
I/Ofrom I/O controller
Hardware failure
e.g. memory parity error
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Interrupts
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Interconnection Structures
A computer consists of a set of
components (CPU,memory,I/O) that com
municate with each other.
The collection of paths connecting the
various modules is call the interconnectionstructure.
The design of this structure will depend on
the exchange that must be made betweenmodules.
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Input/Output for each module
MemoryN Word
0..
.N-1
Read
Write
Address
Data
Data
CPUInterrupt Signal
Data
DataInstructions
ControlSignal
I/O Module
Read
Write
Address
InternalData
ExternalData
InternalData
ExternalData
InterruptSignal
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Type of transfers
Memory to CPU
CPU to Memory
I/O to CPU
CPU to I/O I/O to or from Memory (DMA)
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Bus Interconnection
A bus is a communication pathway
connecting two or more device.
A key characteristic of a bus is that it is a
shared transmission medium.
A bus consists of multiple pathways or
lines.
Each line is capable of transmitting signalrepresenting binary digit (1 or 0)
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Bus Interconnection
A sequence of bits can be transmit across
a single line. Several lines can be used to transmit bits
simultaneously (in parallel).
A bus that connects major components(CPU,Memory,I/O) is called System Bus.
The most common computerinterconnection structures are based on the use of one or more system buses.
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Bus Structure
A system bus consists of 50-100 lines.
Each line is assigned a particular meaning or
function.
On any bus the lines can be classified into 3
groups
Data Bus
Address Bus
Control Bus
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Data Bus
Provide a path for moving data between system
modules. These lines, collectively, are called the data bus
The data bus typically consists of 8,16 or 32separate lines, the numbers of lines being transfe
rred to as the width of the data bus. Each line carry only 1 bit at a time, the number
of lines determines how many bits can transferred at a time - overall system performance.
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The Address Bus
Used to designate the source or
destination of the data on the data bus
The width of the address bus determines
the maximum possible memory capacity o
f the system.
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The Control Bus
Used to control the access to and the useof the data and address lines.
Typical control lines includeMemory write
Memory read
I/O write
I/O readClock
Reset
Bus request
Bus grant
Interrupt request
Interrupt ACK
Transfer ACK
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The operation of the bus
If one module wishes to send data obtain the use of the bus
transfer data via the busIf one module wishes to request data obtain the use of the bus
transfer request to the other module over the
control and address lines, then wait for thatsecond module to send the data.
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Physical Bus Architecture
System bus is a number ofparallel electrical conductors.
The conductors are metal
lines etched in a card or print
ed circuit board.
The bus extends across all of
the components tat taps into
the bus lines.
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buses look like
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Multiple-Bus Hierarchies
More devices attached to bus, propagation
delays affect performance
Bottleneck as the aggregate data
transfer demand approaches capacity of bus.
(e.g graphics & video controller)
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Traditional Bus Architecture
Local busCPU - Cache
System bus
Main memory - Cache
Expansion bus
I/O Modules - Main memory
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Traditional Bus Architecture
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High-Performance Architecture
Local busCPU - Cache/bridge
System bus
Cache/bridge - memory High-speed bus
High-speed I/O module - Cache/bridge
Expansion busLow-speed I/O modules - Expansion interface
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High-Performance Architecture
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Bus Design
TypeDedicated
Multiplexed
Bus WidthAddress
Data
TimingSynchronousAsynchronous
Method of Arbitration
Centralized
Distributed Data Transfer Type
Read Write
Read-modify-write Read-after-write
Block
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Type
Dedicated
permanent assigned bus either toone function or to a physical subset of computer components
Multiplexed
use in the same bus for multiple
purpose`
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Bus Width
Address
the wider of address bus has animpact on range of locations that canbe referenced
Datathe wider of data bus has an
impact on the number of bits transferred at one time
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Timing
Synchronous
occurrence of eventson the bus is
determined by a clock (Clock Cycle or BusCycle)
Asynchronous
occurrenceof one event followsand depends on the
previous event.
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Method of Arbitration
Centralized
buscontroller (Arbiter), hardware device,is responsible for allocating
time on the bus (daisychain)
Distributed
access controllogic in each module act together to share bus
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Data Transfer Type
Read Multiplexed
bus is used to specifying address andthen for transferring data after a waitwhile data is being fetched
Read Dedicatedaddress is put on bus andremain there while data are put on the data bus
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Data Transfer Type
Write Multiplexed
bus is used to specifying addressand then transferring data (same as readoperation)
Write Dedicateddata put on data bus as soon asthe address has stabilized
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Read-modify-write
address is broadcast once atbeginning a simply read is followed immediately by a write to the same address
Read-after-writea write followedimmediately by a read from the same address,performed for checking purposes
Data Transfer Type
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Industry Standard Architecture
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Micro Channel Architecture
Developed by IBM for its line of PS/2 desktop
computers, MCA is an interface between a computer (or multiple computers) and its expansion cards and their associated devices.
MCA was a distinct break from previous bus
architectures such as ISA. The pin connections in MCA are smaller than other
bus interfaces. For this and other reasons, MCAdoes not support other bus architectures.
Micro Channel Architecture
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(cont.)
Although MCA offers a number ofimprovements over other bus architectures, its proprietary, nonstandard aspects did
not encourage other manufacturers to adopt it.
It has influenced other bus designs and it
is still in use in PS/2s and in some minicomputer systems.
x en e n us ry an ar
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yArchitecture
EISA is a standard bus architecture that
extends the ISA standard to a 32-bit interface. It was developed in part as an open alternative to the proprietary Micro ChannelArchitecture (MCA) that IBM introduced inits PS/2 computers.
EISA data transfer can reach a peak of 33megabytes per second
VESA[Video Electronics Standards
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[
Association ]Local Bus
VESA VL bus is a standard interfacebetween your computer and its expansion slot that provides faster data flow between the devices controlled by the expansion cardsand your computer's microprocessor.
A "local bus"is a physical path on whichdata flows at almost the speed of themicroprocessor, increasing total system perf
ormance.
S ( )
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VESA Local Bus (cont.)
VESA Local Bus is particularly effectivein systems with advanced video cards and supports 32-bit data flow at 50 MHz
A VESA Local Bus is implemented byadding a supplemental slot and card that aligns with and augments an ISA expansion card. (ISA is the most common
expansion slot in today's computers.)
Peripheral Component Interconnect
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Peripheral Component Interconnect
PCI is an interconnection system betweena microprocessor and attached devices inwhich expansion slot are spaced closely for high speed operation.
Using PCI, a computer can support bothnew PCI cards while continuing to supportISA expansion cards, currently the most c
ommon kind of expansion card.
Peripheral Component Interconnect
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(cont.)
Designed by Intel, the original PCI was similar to theVESA Local Bus.
PCI2.0 is no longer a local bus and is designed to beindependent of microprocessor design.
PCI is designed to be synchronized with the clock
speed of the microprocessor, in the range of 33 to66 MHz.
Standard : Up to 64 data-lines at 66 MHz. Rawtransfer rate of 528 MBps or 4.224 Gbps.
Peripheral Component Interconnect
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(cont.)
PCI is now installed on most new desktop
computers, not only those based on Intel'sPentium processor but also those based on the PowerPC.
PCI transmits 32 bits at a time in a 124-pin connection (the extra pins are forpower supply and grounding) and 64 bits in a 188-pin connection in an expanded im
plementation.
Peripheral Component Interconnect
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(cont.)
PCI uses all active paths to transmit both
address and data signals, sending the address on one clock cycle and data on the next.
PCI deliver better system performance forhigh-speed I/O subsystemse.g. graphic display adapters, networkinterface controllers, disk controllers
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PCI Bus Structure
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U i l S i l B
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Universal Serial Bus
Standard bus which is invented by a group of
companies : Compaq, DEC, IBM, Intel, Microsoft,NEC, Northern Telecom, etc.
Not change switch, jumper on board or otherdevices
Can use the same cable Device that use USB can use power supply from
PC.
Up to 127 devices connected off single port
Support real-time system Hot Plug-in
Low cost
M lti S t B
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Multi-System Buses