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SEQUENTIAL LOGIC GATE DESIGN (LAB-6)

INTRODUCTION TO VLSI DESIGN (ECE-467)

FALL- 2013

UNIVERSITY OF ILLINOIS AT CHICAGO

TA: VAHID FAROUTAN

NAME: DEBOPAM DATTA

UIN: 653501335

STUDENT: GRADUATE

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1.Introduction:Sequential circuit designing is nothing but a combinatorial circuit working hand

in hand with a memory element. The basic memory element can be implemented

using two inverter loop. We have used that type of building Blocks. We have used the

supply voltage of 2 volts for Static CMOS design and minimum feature size (aspect

ratio) of (250nm/250nm). The technology file we have used mitll_fdsoi which is a

low power CMOS process.

2.Organisation:1. Design Theory2. Circuit Topology and structure3. Layout Samples of Positive Edge triggered D-Flip flop and other Design

Process

4. Parasitic extraction and display5. Circuit Response i) Without parasitic ii) With Parasitic.6. Discussion

3.Design Theory:As per the problem statement we have to design a positive edge triggered

master-slave D-flip flop. The Truth Table for D- Flip Flop is shown below. The

master slave configuration works in an alternative way when Master is

transparent to its Input the slave is latched and vice versa. So though the D-Flip

Flops are Level triggered implementation of this configuration makes the whole

circuit behave as an edge triggered. We have used a two inverter Loop with theTransmission gate switch topology to implement Level triggered D-flip flop. The

inverters have a PMOS/NMOS aspect ratio of 3 and the pass transistor have a

PMOS/NMOS aspect ratio of 1. We have sacrificed the standard CMOS design to

reduce the number of Transistor count. For General NAND based design the

transistor count is 28. But for our design the number of count is only 16. The

problem statement had a restriction of 10GHz operating clock but we had

designed the circuit to operate it in 5GHz ideally and 0.8GHz practically.

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4. CIRCUIT TOPOLOGY:

FIG-1: Schematic of the used circuit

FIG-2: Schematic of Pass Transistor FIG-3: Schematic of the Inverter

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Symbol Generation:

FIG-4: Symbol of the Generated D Flip Flop

Test Bench circuit:

FIG-5: Test bench circuit

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5.LAYOUT DESIGN:For layout design purpose we have made the PMOS aspect ratio 3 times the NMOS for

Inverter and Transmission gate has same aspect ratio for PMOS and NMOS.

FIG-6: Layout of the circuit with Pin displayed (0 to 1stlayer shown)

FIG-7: Layout of the circuit with Pin displayed (only 0th

Layer)

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FIG-8: Inverter Layout FIG-9: Transmission gate Layout

DESIGN RULE CHECK (DRC):

FIG-10: DRC for Whole circuit run is successful

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Fig-11: DRC for Pass Transistor run is successful

CIRCUIT EXTRACTION AND EXTRACTED VIEW:

FIG-12: Successful Extraction of the circuit

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FIG-13: Successful extraction of the Transmission Gate

EXTRACTED VIEW OF THE CIRCUIT:

FIG-14: Extracted view of the circuit

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LAYOUT VERSUS SCHEMATIC (LVS):

FIG-15: LVS successful and analog_extraction of the main circuit

FIG-16: Successful LVS for the Transmission Gate

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6. PARASITIC EXTRACTION AND VALUES:

FIG-17: Parasitic capacitance values for the layout

7.TRANSIENT RESPONSE OF THE CIRCUIT :Transient response of the circuit are characterised by two means

1. With Parasitic 2. Without Parasitic

For Proper Output we have tried to simulate the circuit with different Clock

Frequency but at 10GHz the transient response is really deteriorating and we could

not use that clock frequency. I have provided the comparison between 5GHz and10GHz clock frequency response.

With Parasitic the response of the circuit at 5GHz is also undesirable. So I have to

decrease the frequency below 5GHz.I have obtained a decent response when the

clock frequency is 0.8 GHz. So I have shown the final comparison of the Transient

response with parasitic and without parasitic keeping the clock frequency at 0.8 GHz.

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Simulation at 5 GHz clock frequency :

FIG-18: Transient Response without Parasitic

FIG-19: Transient Response with Parasitic

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Transient Response at 1GHz Clock Frequency:

FIG-20: Transient Response Without Parasitic

FIG-21: Transient Response with Parasitic

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Simulation of the circuit using 0.8 GHz Clock frequency:

FIG-22: Transient response without Parasitic

FIG-23: Transient Response with Parasitic

As the response for 0.8 GHz is pretty acceptable we have measured the delay

for 0.8 GHz by enlarging the response for 1 clock cycle. Both the response

appeared to be almost similar, hence we have simulated using this clock

frequency.

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FIG-24: Without Parasitic at 0.8 GHz

FIG-25: With Parasitic at 0.8 GHz

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8.AREA:

FIG-26: Layout for area calculation

Area = 1266 * 566 = 716556 * ^2 = 716556 * (50nm)^2 = 1791390000 (nm) ^2

= 1791.39(um) ^2

9.CONCLUSION:

The delay performance of the circuit at 0.8 GHzclock frequency is quite good after

implementing the parasitic. So the overall design is quite optimized with respect to the

transistor count. But the main problem of the circuit was that the transient response had

some spikes. We have tried to overcome the spikes by adding a two inverter buffer. The

buffer actually stops the sudden changes of voltage.

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FIG-27: The modified test bench for overcoming spikes

FIG-28: Transient Response after adding buffer at 0.8 GHz