Combinational Logic - University of Hong Kong · 2012. 12. 3. · Combinational Logic ENGG1015 1st...

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Combinational Logic

ENGG1015 1st Semester, 2012

Dr. Hayden So

Department of Electrical and

Electronic Engineering

3 Representations of Logic Functions n  Recall that any complex logic function can be

expressed in 3 ways: Truth Table, Boolean Expression, Schematics

n  Only Truth Table representation is unique

n  We can convert representation from one form to the other

1st semester, 2012 ENGG1015 - H. So 2

Truth Table

Boolean Expression

Schematics

Schematics à Boolean Expression n  Start from the inputs, deduce the Boolean

expression of each intermediate nodes until the output is obtained.

n  The fact that the AND operation (AB) is performed before the OR operation (+C) is captured implicitly by the precedence of Boolean algebra

n  A redundant, but still correct expression:


x = (AB)+C

Precedence n  Determines the order of evaluation of a

Boolean expression

n  Order:

n  A “bar” over an expression can be viewed as one with a (), therefore, () take precedence

n  E.g.

4 1st semester, 2012 ENGG1015 - H. So

Operation Precedence

( ) Highest NOT

AND

OR Lowest

a+ b = (a+ b) ⇒ (a+ b) first, then inverse

Schematics à Boolean Expression n  Similar conversion, using ()s to show

precedence of the OR operation

n  Whenever an INVERTER is present in a logic-circuit diagram, its output expression is simply equal to the input expression with a bar over it.


Quick Quiz

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n What is the output expression of the following logic-circuit diagram?

•  •  •  • 

( )x ABC A D= +

x ABCD=

( )x ABC A D= +

x ABCD=

1st semester, 2012 ENGG1015 - H. So

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2

3

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Boolean Expression à Schematics n  Start with the inputs, convert each Boolean

operation into the corresponding gate, obeying the precedence of operation

n  E.g. Implement the expression as circuit:


y = ac+ bc + abca

b

c

y

a

c

abc

bc

ac

ABCCBACBAx ++=

CBACBA

ABC

Truth Table à Boolean Exp n  List all combinations that give 1 at output n  Each row contributes to a minterm n  Sum up all terms n  Sum of products (SOP)


Canonical Form n  Boolean expression can be expressed in

many different ways

n  Two standard ways of organizing the terms: •  Sum of Product •  Product of Sum

n  A canonical form puts rules to allows unique representation of Boolean expression •  E.g. sort the minterms according to order of input

signal (write AB, not BA)

9

€

(A + D)(B + C) ≡ AB + AC + BD+ CD


Canonical SOP n  Boolean expression expressed as a sum of

product of basic inputs •  Basic input may optionally negated

n E.g. is not NOT canonical: •  No parentheses

n  Very natural for human

10

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AB C + BD + AD

Product Sum

€

A + B(C + D)


Canonical POS n  Boolean expression expressed as a product of

sum of basic inputs •  Basic input my optionally negated

n  E.g. This is not in canonical POS form:

n  Not too natural for human, but equally good for computers.

11

€

(A + B + C)(B + D )(A + D)Product Sum

€

A + B(C + D)


SOP or POS? n  SOP

n  What about?

A B C S

0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1

S ABC ABC= +

A B C S

0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1

ABC→

ABC→

ABC ABC+1

( )( )A B C B C+ + +2

( ) ( )A B C A B C+ + ⋅ + +3

( ) ( )A B C A B C+ + ⋅ + +4


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Example: This example illustrate the complete procedure for designing a logic circuit. Suppose the logic circuit having 3 inputs, A, B, C will have its output HIGH only when a majority of the inputs are HIGH.

Step 1 Set up the truth table

Step 2 Write the AND term for

each case where the output

is a 1.

Step 3 Write the SOP form the output

Step 4 Simplify the output expression

Step 5 Implement the circuit

A B C x

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

BCA→

CBA→CAB→

ABC→

( ) ( ) ( )x ABC ABC ABC ABC ABC ABCBC A A AC B B AB C CBC AC AB

= + + + + +

= + + + + +

= + +

x ABC ABC ABC ABC= + + +


Example: Conversion through the opposite direction:

Step 1 Start from the circuit

Step 2 Obtain Boolean expression

from the circuit (in SOP form)

Step 3 Write the truth table

A B C y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

BCA→

CBA→←CAB

ABC→BCACBACy ++=

←CBA

Truth Table

Boolean Expression

Schematics y

BOOLEAN ALGEBRA


Axioms of Boolean Algebra

n  The very basis of Boolean algebra n  Cannot be proven, assumed true

n  Note the Dual of the Axiom •  Replace � with +, replace 1 with 0, and the axiom

still holds true

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Axioms and theorems of Boolean algebra obey the principle of dual-ity. If the symbols 0 and 1 and the operators • (AND) and ! (OR) areinterchanged, the statement will still be correct. We use the prime (")symbol to denote the dual of a statement.

2 . 3 .1 Axioms

Table 2.1 states the axioms of Boolean algebra. These five axioms andtheir duals define Boolean variables and the meanings of NOT, AND,and OR. Axiom A1 states that a Boolean variable B is 0 if it is not 1.The axiom’s dual, A1", states that the variable is 1 if it is not 0. Together,A1 and A1" tell us that we are working in a Boolean or binary field of0’s and 1’s. Axioms A2 and A2" define the NOT operation. Axioms A3to A5 define AND; their duals, A3" to A5" define OR.

2 . 3 . 2 Theorems of One Variable

Theorems T1 to T5 in Table 2.2 describe how to simplify equationsinvolving one variable.

The identity theorem, T1, states that for any Boolean variable B, BAND 1 # B. Its dual states that B OR 0 # B. In hardware, as shown inFigure 2.14, T1 means that if one input of a two-input AND gate isalways 1, we can remove the AND gate and replace it with a wire con-nected to the variable input (B). Likewise, T1" means that if one input ofa two-input OR gate is always 0, we can replace the OR gate with a wireconnected to B. In general, gates cost money, power, and delay, soreplacing a gate with a wire is beneficial.

The null element theorem, T2, says that B AND 0 is always equalto 0. Therefore, 0 is called the null element for the AND operation,because it nullifies the effect of any other input. The dual states that BOR 1 is always equal to 1. Hence, 1 is the null element for the ORoperation. In hardware, as shown in Figure 2.15, if one input of anAND gate is 0, we can replace the AND gate with a wire that is tied

2.3 Boolean Algebra 57

Axiom Dual Name

A1 B # 0 if B $ 1 A1" B # 1 if B $ 0 Binary field

A2 A2" NOT

A3 0 • 0 # 0 A3" 1 ! 1 # 1 AND/OR

A4 1 • 1 # 1 A4" 0 ! 0 # 0 AND/OR

A5 0 • 1 # 1 • 0 # 0 A5" 1 ! 0 # 0 ! 1 # 1 AND/OR

1 # 00 # 1

Table 2.1 Axioms of Boolean algebra

The null element theoremleads to some outlandish state-ments that are actually true! Itis particularly dangerous whenleft in the hands of advertisers:YOU WILL GET A MILLIONDOLLARS or we’ll send you atoothbrush in the mail. (You’llmost likely be receiving atoothbrush in the mail.)

Figure 2.14 Identity theorem inhardware: (a) T1, (b) T1"

1 =

(a)

B B

=0B B

(b)

Chapter 02.qxd 1/31/07 9:55 PM Page 57

Table from DDCA p.57 1st semester, 2012 ENGG1015 - H. So

Theorems of one variable


LOW (to 0). Likewise, if one input of an OR gate is 1, we can replacethe OR gate with a wire that is tied HIGH (to 1).

Idempotency, T3, says that a variable AND itself is equal to justitself. Likewise, a variable OR itself is equal to itself. The theorem getsits name from the Latin roots: idem (same) and potent (power). Theoperations return the same thing you put into them. Figure 2.16 showsthat idempotency again permits replacing a gate with a wire.

Involution, T4, is a fancy way of saying that complementing a vari-able twice results in the original variable. In digital electronics, twowrongs make a right. Two inverters in series logically cancel each otherout and are logically equivalent to a wire, as shown in Figure 2.17. Thedual of T4 is itself.

The complement theorem, T5 (Figure 2.18), states that a variableAND its complement is 0 (because one of them has to be 0). And, by dua-lity, a variable OR its complement is 1 (because one of them has to be 1).

2 . 3 . 3 Theorems of Several Variables

Theorems T6 to T12 in Table 2.3 describe how to simplify equationsinvolving more than one Boolean variable.

Commutativity and associativity, T6 and T7, work the same as intraditional algebra. By commutativity, the order of inputs for an AND orOR function does not affect the value of the output. By associativity, thespecific groupings of inputs do not affect the value of the output.

The distributivity theorem, T8, is the same as in traditional algebra,but its dual, T8!, is not. By T8, AND distributes over OR, and by T8!, ORdistributes over AND. In traditional algebra, multiplication distributesover addition but addition does not distribute over multiplication, so that(B " C) # (B " D) $ B " (C # D).

The covering, combining, and consensus theorems, T9 to T11, per-mit us to eliminate redundant variables. With some thought, you shouldbe able to convince yourself that these theorems are correct.

58 CHAPTER TWO Combinational Logic Design

Theorem Dual Name

T1 B • 1 % B T1! B " 0 % B Identity

T2 B • 0 % 0 T2! B " 1 % 1 Null Element

T3 B • B % B T3! B " B % B Idempotency

T4 B=

% B Involution

T5 T5! ComplementsB " B % 1B • B % 0

Table 2.2 Boolean theorems of one variable

Figure 2.16 Idempotencytheorem in hardware: (a) T3,(b) T3!

B =

(a)

B B

=BB B

(b)

Figure 2.17 Involution theoremin hardware: T4

Figure 2.18 Complementtheorem in hardware: (a) T5,(b) T5!

= BB

B=

(a)

B0

=BB

1

(b)

Figure 2.15 Null elementtheorem in hardware: (a) T2,(b) T2!

0 =

(a)

B 0

=1B 1

(b)


Theorems of multiple variables


De Morgan’s Theorem, T12, is a particularly powerful tool in digitaldesign. The theorem explains that the complement of the product of allthe terms is equal to the sum of the complement of each term. Likewise,the complement of the sum of all the terms is equal to the product of thecomplement of each term.

According to De Morgan’s theorem, a NAND gate is equivalent toan OR gate with inverted inputs. Similarly, a NOR gate is equivalent toan AND gate with inverted inputs. Figure 2.19 shows these De Morganequivalent gates for NAND and NOR gates. The two symbols shown foreach function are called duals. They are logically equivalent and can beused interchangeably.

2.3 Boolean Algebra 59

Theorem Dual Name

T6 B • C ! C • B T6" B # C ! C # B Commutativity

T7 (B • C) • D ! B • (C • D) T7" (B # C) # D ! B # (C # D) Associativity

T8 (B • C) # (B • D) ! B • (C # D) T8" (B # C) • (B # D) ! B # (C • D) Distributivity

T9 B • (B # C) ! B T9" B # (B • C) ! B Covering

T10 T10" Combining

T11 T11" Consensus

T12 T12" De Morgan’s Theorem! (B0 • B1 • B2)! (B0 # B1 # B2 ...)

B0 # B1 # B2...B0 • B1 • B2...

! (B # C) • (B # D)! B • C # B • D(B # C) • (B # D) • (C # D)(B • C) # (B • D) # (C • D)

(B # C) • (B # C) ! B(B • C) # (B • C) ! B

Table 2.3 Boolean theorems of several variables

Augustus De Morgan, died 1871.A British mathematician, bornin India. Blind in one eye. Hisfather died when he was 10.Attended Trinity College,Cambridge, at age 16, andwas appointed Professor ofMathematics at the newlyfounded London University atage 22. Wrote widely on manymathematical subjects, includ-ing logic, algebra, and para-doxes. De Morgan’s crater onthe moon is named for him.He proposed a riddle for theyear of his birth: “I was xyears of age in the year x2.”

Figure 2.19 De Morgan equivalent gates

A B Y0 0 10 1 11 0 11 1 0

NANDAB Y

AB Y

NORAB Y

AB Y

A B Y0 0 10 1 01 0 01 1 0

Y = A + B = A BY = AB = A + B


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Example

DBADBAy +=

( ) by distributive law

1 by rule 6

by rule 4

y AB D D

AB

AB

= +

= ⋅

=

n  Simplify the following Boolean expression:


Quick Quiz n  Simplify the following Boolean expression:

z = A +B( ) A+B( )

1

2

3

4

ABAABB

by distributive law

0 by rule 8 and rule 7

by rule 1

( 1) by distributive law

z AA AB BA BB

AB BA B

AB BA B

B A AB

= + + +

= + + +

= + +

= + +

= ⋅1 by rule 6 and rule 2 by rule 4B=


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DeMorgan’s Theorems n  Theorem 1

n  Theorem 2

Remember:

“Break the bar, change the operator”

–  DeMorgan's theorem is very useful in digital circuit design –  It allows ANDs to be exchanged with ORs by using invertors –  DeMorgan's Theorem can be extended to any number of

variables. E.g, for three variables x, y and z

x y x y+ = ⋅

x y x y⋅ = +

x y z x y z

x y z x y z

+ + = ⋅ ⋅

⋅ ⋅ = + +


Quick Quiz (1) n  Simplify •  •  •  • 

n  Simplify •  •  •  • 

( )AB C+

AC BC+

AC BC+

AC BC+

AC BC+

( ) ( )A C B D+ ⋅ +

AC BD+

AC BD+

AC BD+

AC BD+


1

2

3

4

1

2

3

4

Quick Quiz (2) n  Simplify •  •  •  • 

n  Determine the output expression for the below circuit and simplify it using DeMorgan’s Theorem •  •  •  •  A B C+ +

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AB CD EF⋅ ⋅

AB CD EF+ +

AB CD EF+ +

AB CD EF+ +

ABCDEF

A B C+ +

ABC

ABC


1

2

3

4

1

2

3

4

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) ( ) ( )a AB C AB C A B C AC BC+ = ⋅ = + ⋅ = +

) ( ) ( ) ( ) ( )b A C B D A C B D A C B D AC BD+ ⋅ + = + + + = ⋅ + ⋅ = +

) ( ) ( ) ( )c A B C A B C A B C A B C+ ⋅ = ⋅ ⋅ = ⋅ + = +

) ( ) ( ) ( ) ( )

( ) ( )( ) ( )

d A BC D EF A BC D EF

A BC D EFA B C D E FAB AC DE DF

+ ⋅ + = + + +

= ⋅ + ⋅

= ⋅ + + ⋅ +

= + + +

Examples (Summary):

) e AB CD EF AB CD EF AB CD EF⋅ ⋅ = + + = + +

f ) Determine the output expression for the below circuit and simplify it using DeMorgan’s Theorem

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Bubble Pushing in Schematics x y x y+ = ⋅

Usually redrawn in this way

x y x y⋅ = +

Usually redrawn in this way


DeMorgan’s Theorem allows us to push bubbles across gates to eliminate unnecessary inversions in signals

SIMPLIFYING LOGIC CIRCUITS


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Simplifying Logic Circuits n  Once the expression for a logic circuit is obtained, we may try to simplify it, so

that the implementation requires fewer gates n  Example: below two circuits are the same, but the second one is much more

simpler

n  Two methods for simplifying •  Algebraic method (use Boolean algebra theorems) •  Karnaugh mapping method (systematic, step-by-step approach)


Minimization by Algebra n  Make use of relationships and theorems of

Boolean algebra to simplify the expressions •  this method relies on your algebraic skill

n  E.g. To simplify


( ) [by DeMorgan thm]( ) [cancel double inverions]

[multiply out] [ ]

( )

z ABC AB A CABC AB A CABC ABA ABCABC AB ABC A A AAC B B ABAC AB

= + ⋅ +

= + ⋅ +

= + +

= + + ⋅ =

= + +

= + [ 1]( )

B BA C B

+ =

= +

( )z ABC AB AC= + ⋅

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Minimization by Karnaugh Maps n  What is a Karnaugh map?

•  Karnaugh map (K map) is a graphical tool used to simplify a logic equation or to convert a truth table to its corresponding logic circuit

•  With a simple and orderly process, the resulting logic expression will be in its simplest SOP form !!!

n  K map format: •  3 Variable K map:

•  A grid of squares •  Each square represents one product term

•  eg: top-left represents , bottom-right represents •  The variables are ordered according to Gray code

•  only one variable changes between adjacent squares •  Squares on edges are considered adjacent to squares on opposite edges

A B C⋅ ⋅ A B C⋅ ⋅

A\BC 00 01 11 10

0

1


•  4 Variable K map

•  The square marked ? represents •  The square marked ?? represents •  Note that they differ in only the C variable. •  Karnaugh maps become clumsier to use with more than 4 variables

AB\CD 00 01 11 10

00

01 ? ??

11

10

A B C D⋅ ⋅ ⋅A B C D⋅ ⋅ ⋅

•  General procedure for using K map: 1.  Fill out the K map for a given Boolean expression 2.  Simplify the expression by properly combining those squares in the

K map that contains 1s. This process is called looping


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Filling out a Karnaugh Map n  Given an initial (unsimplified) logic Boolean expression n  Write the expression in SOP form

n  For each product term, write a 1 in all the squares which are included in the term, 0 elsewhere •  All variables present in the product term: one square •  One variable missing: two adjacent squares •  Two terms missing: 4 adjacent squares

n  Example 1:

n  Example 2:

n  Example 3:

A\BC 00 01 11 10

0 0 0 1 0

1 0 1 1 1

X ABC ABC ABC ABC= + + +

X BC ABC AC= + +

A\BC 00 01 11 10

0 1 0 0 0

1 1 1 1 1

X B ABC A= + +

A\BC 00 01 11 10

0 1 1 0 1

1 1 1 1 1


Looping n  Minimization is done by spotting patterns of 1's and 0's n  Pairs of adjacent 1's (Looping groups of two)

•  remember that adjacent squares differ by only one variable •  hence the combination of 2 adjacent squares has the form •  this can be simplified (from before) to just P

)( AAP +

•  Example 1 (continue)

-- the adjacent squares A B C and differ only in A -- hence they can be combined into just BC, indicated by the blue loop -- looping can also be done by grouping and A B C to give AC, as indicated by the red loop -- furthermore, looping can also be done by grouping A B C and to give AB, as indicated by the yellow loop -- The simplified Boolean equation is one that sums all the terms corresponding to each of the group:

A\BC 00 01 11 10

0 0 0 1 0

1 0 1 1 1

ABC

ABC

ABC

X ABC ABC ABC ABC= + + +

ABBCACX ++=


36

More examples on looping of two


Looping group of four (quads)

•  A K map may contain a group of four 1s that are adjacent to each other. This group is called quad •  Looping a quad of adjacent 1s eliminates the two variables that appear in both complemented and uncomplemented form •  Examples:


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Looping group of eight (Octets) n  A group of eight 1s that are adjacent to one another is called an octet n  Looping an octet of adjacent 1s eliminates the three variables that

appear in both complemented and uncomplemented form

n  Examples:


Complete Simplification Process 1.  Construct the K map and place 1s and 0s in the squares according to

the truth table. 2.  Group the isolated 1s which are not adjacent to any other 1s. (single

loops) 3.  Group any pair which contains a 1 adjacent to only one other 1. (double

loops) 4.  Group any octet even if it contains one or more 1s that have already

been grouped. 5.  Group any quad that contains one or more 1s that have not already

been grouped, making sure to use the minimum number of groups. 6.  Group any pairs necessary to include any 1s that have not yet been

grouped, making sure to use the minimum number of groups. 7.  Form the OR sum of all the terms generated by each group.


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n  Examples: AB\CD 00 01 11 10

00 0 1 0 0

01 0 1 0 0

11 1 1 1 1

10 0 1 0 0

AB\CD 00 01 11 10

00 0 0 0 0

01 1 0 0 1

11 1 0 1 1

10 0 0 0 0

AB CD+ BD ABC+

Step2. Isolated 1: None Step3. Adjacent to only one 1: None Step4. Octet: None Step5. Quad: Blue and red loops Step6. All 1s have been looped => skip this step

Step2. Isolated 1: None Step3. Adjacent to only one 1: red loop Step4. Octet: None Step5. Quad: Green loops Step6. All 1s have been looped => skip this step


AB\CD 00 01 11 10

00 0 0 0 1

01 0 1 1 0

11 0 1 1 0

10 0 0 1 0

Quiz AB\CD 00 01 11 10

00 0 1 0 0

01 0 1 1 1

11 1 1 1 0

10 0 0 1 0


ABCD ABCD BD+ +

ABCD ACD BD+ +

ABCD ACD BD+ +

ABCD ACD BD+ +

1

2

3

4

ABC ACD ACD ABC+ + +

ABC ACD ACD ABC+ + +

ABC ACD ACD BD+ + +

ABC ACD ACD ABC BD+ + + +

1

2

3

4

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•  More examples

S2. Isolated 1: loop 4 S3. Adjacent to only one 1: loop 11,15 S4. Octet: None S5. Quad: loop 6,7,10,11 S6. All 1s have been looped => skip

S2. Isolated 1: None S3. Adjacent to only one 1: loop 3,7 S4. Octet: None S5. Quad: loop 5,6,9,10 and loop 5,6,7,8 S6. All 1s have been looped => skip

S2. Isolated 1: None S3. Adjacent to only one 1: loop 2,6, loop 7,8, loop 11,15 and loop 9,10 S4-S6. All 1s have been looped => skip


4-BIT ADDER

Putting It Together


Binary Numbers n  Represents numbers in base 2 n  E.g.: 2310 = 101112

n  Almost all computers today utilize binary representation of numbers internally


Decimal Binary

0 0

1 1

2 10

3 11

4 100

5 101

6 110

7 111

8 1000

9 1001

10 1010

11 1011

12 1100

From Binary to Decimal n  Note that the value of a binary number is

given by: where bi is the digital at position i, starting counting from zero from the far right.

n  Converting from binary to decimal can be done by adding the power-of-2 where there is a 1


€

2ibii= 0

∞

∑

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Example n  Convert the binary number 11001 into

decimal representation


20 21 22 23 24 25

1 0 0 1 1

€

=1× 24 +1× 23 + 0 × 22 + 0 × 21 +1× 20

= 24 + 23 + 20

=16 + 8 +1= 25

From Decimal to Binary n  Can be found using “short

division”: •  Successively divide the

dividend by 2 •  The remainders form the

resulting binary number when counted from the bottom

n  Example: Converts 1910 into binary


19 2

9

1

2 1

4 2 0

2 2 0

1

è 1910 = 100112

Positive Integers n  Non-negative binary numbers

(0, 1, 2, 3, …) can be represented naturally with bitstrings that corresponds to their binary representation

n  Represents equally spaced integers on the number line

n  Sometimes called unsigned integer


Value Binary Bitstring (8-bit)

0 0 00000000

1 1 00000001

2 10 00000010

3 11 00000011

4 100 00000100

5 101 00000101

6 110 00000110

7 111 00000111

8 1000 00001000

9 1001 00001001

10 1010 00001010

11 1011 00001011

∞ 0 1 2 3 4 5 6 7 8

0000

0000

00

0000

01

0000

0010

00

0000

11

0000

0100

00

0001

01

0000

0110

00

0001

11

Positive Integers n  With a bitstring of width n, the following

properties hold:

n  The value of a bistring can be calculated as:

n  E.g. The value of


€

min value : 0max value : 2n −1

€

bn−1bn−2b0{ }

€

2ibii= 0

n−1

∑

€

101112 = 24 + 22 + 21 + 20

=16 + 4 + 2 +1= 23

Positive Integers Addition n  Two +ve integers can be added similar to the

way decimal numbers are added in “long addition”


2 3 1 9 +

2 1

4 1 +

1 1 1 0 1 1 1 0 0 1

1 0 0 1 0 1

1 1 1

How do we implement binary addition in hardware?

Half Adder n  Basic addition of 2 1-bit values n  Generate a carry out to the next bit if the

result is 2


1 +

1 1 1 0 1 1 1 0 0 1

1 0 0 1 0 1

1 1 1

a b co s

0 0

0 1

1 0

1 1

0

1

1

0

0

0

0

1

s = a⊕ bco = a ⋅b

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Full Adder n  The subsequent bits need to be slightly

smarter than a half adder •  There may be carry input from the bit to the right

n  A 3-input function (a, b, ci)

1st semester, 2012

ENGG1015 - H. So 52

1 +

1 1 1 0 1 1 1 0 0 1

1 0 0 1 0 1

1 1 1

ci a b co s

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0

1 0 1

1 1 0

1 1 1

1

0

0

1

0

1

1

1

s = a⊕ b⊕ cico = a ⋅b+ ci a+ b( )

Multi-bit Adder n  Both HA and FA can add 1 bit only

•  A half-adder is simply a full-adder with the carry input tied to ‘0’

n  To make a multi-bit adder, we can connect the carry output from one FA to the carry input of another one

n  Start from least significant bit (usually rightmost bit) and propagate the carry to the left (the most significant bit)

n  Mimic the action of a “long addition”


1 +

1 1 1 0 1 1 1 0 0 1

1 0 0 1 0 1

1 1 1

Multi-bit Adder

n  Note: the <> notation is a shorthand to denote a bit within a multi-bit signal. •  Other common notation: a(0), a[0], a0, etc

n  Engineer sometimes call multi-bit signal a bus, or a signal bus.


FA

a b

ci co

s

a<0> b<0>

s<0>

FA

a b

ci co

s

a<1> b<1>

s<1>

FA

a b

ci co

s

a<2> b<2>

s<2>

FA

a b

ci co

s

a<3> b<3>

s<3>

‘0’ Carry out

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Combinational Logic - University of Hong Kong · 2012. 12. 3. · Combinational Logic ENGG1015 1st...

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