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7/31/2019 Commercializing Printed Electronics
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Crossing the Chasm:Commercializing Printed Electronics
Daniel GamotaDirector, Printed [email protected]
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[email protected] 847.576.5084
Technology Transfer to Manufacturing
Environment• R & D
– Development of new concepts– Develop and explore new
technology space
• High-Volume Manufacturing– Distribute technology to consumers– Generate new businesses
Tech
Tr ansf er
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Manufacturing Environment - Platforms
• High-Volume
Manufacturing– Commercially-available,
qualified equipment– Outsource, leverage
vendors and suppliers– Cost, size (footprint),
reliability, throughput– Loose tolerances
– Broad processing window
• R & D– Novel machines,
custom designs
– Do most in-house– Flexibility,
adaptability,upgradeable
– Tight tolerances
– High control
7/31/2019 Commercializing Printed Electronics
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Manufacturing Environment - Operation• R & D
– Push technology– Intervention
expected– Rely on
experience– Lab notebooks
• High-VolumeManufacturing– Use what is proven– Limited user
intervention
– Training– SOPs– ISO 9000, etc.
7/31/2019 Commercializing Printed Electronics
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Small-Mid Area Printed Electronics - TodayPrinted Flex Circuitry
Solder Interconnects
• Printed circuitry – Screen – Stencil
• Printed solder interconnects – Screen – Stencil – Micro-dispensing
– Jetting
• Microelectronics encapsulationand flux dispensing – Micro-dispensing – Jetting Encapsulation and Fluxing
Many Standard Operating Procedures
and Certificates of Compliance Exist.
7/31/2019 Commercializing Printed Electronics
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Large Area Printed Electronics - Tomorrow
75 µm pixels PLED ©CDT
Printed Displays
Konarka's flexible solar cell
Printed Energy Sources
Printed battery by Power Paper
Photo courtesy E Ink
• Printed energy sources – Screen – Flexo – Litho
• Printed displays – Screen – Inkjet – Laser induced forward transfer
• Printed lighting – Screen
• Printed RFID antenna – Screen – Flexo – Litho Printed Lighting Printed RFID Antenna
Few Standard Operating Procedures and Certificates of Compliance Exist.
7/31/2019 Commercializing Printed Electronics
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Realization MarketProcess OpportunitiesResearchSpace
Technology Transfer Process
UserRequirements
Technologies
$ $ $ U s
er E x
p er i en
c e
T e c h n ol o
g y
M ar k e t i n g
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Gated Project Plan Process
Gate 15Idea
Accepted
Market Intelligence and Analysis
Gate 14Concept
Accepted
Gate 13SolutionSelected
Gate 10ProjectInitiation
Gate 12Portfolio
Accepted
Gate 9SystemRequirements
Baselined
Gate 6DesignReadiness
Gate 0End of Life
Gate 5System TestReadiness
Gate 7
Contract BookBaselined and Approved
Gate 8SystemRequirements
Allocated
Gate 2VolumeDeployment
Gate 3Ready for ControlledIntroduction
Gate 4Ready for Field Test
Gate 1RetirementPlan
Approved
ProjectDefinitionPhase
Business CaseDevelopmentPhase
PortfolioPlanningPhase
ImplementationPhase
Launchand CloseoutPhase
Gate 11SolutionLockdown
Several standards practices and methods are enforced at each GATE .
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Large Area Electronics Market Diffusion
•Establish a Deep Infrastructure– Materials Suppliers
– Manufacturing Platforms– Control Architectures– Characterization Tools
– Quality Control Equipment
• Standards– Circuit Design– Circuit Testing– Reliability Testing
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Large Area Electronics Value Chain
MaterialsProcessing/ EquipmentPlatforms
SystemTesting
Design &Applications
Printing
Services
Agreement for standards practices and methods will assist technology diffusion .
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Large Area Electronics Standards Efforts
• IEEE P1620 TM-2004 (http://grouper.ieee.org/groups/1620)– Standard for Test Methods for the Characterization of
Organic Transistors and Materials– Standard available at http://shop.ieee.org/store
• IEEE P1620.1TM
(http://grouper.ieee.org/groups/1620/1)– Draft Standard for Test Methods for the Characterizationof Organic Transistor Based Ring Oscillators
– Approved via ballot 12/05. To be published in 06/06.
• IEEE P1620.2 (http://grouper.ieee.org/groups/1620/2)
– Draft Standard Methods for the Characterization of Printed and Organic Diode Bridges Structures for RFDevices
– Project authorization requiest (PAR) submitted to IEEE.
• ISO Printing Electronics Standards– Draft Standard for Printing Electronics– Call for volunteers for Kick-off Meeting of Study Group
in August 2006
C ifi f C li f A f
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Certificate of Compliance for Acceptance of Incoming Large Area Electronics Materials
Property and ProcessCharacterization
•Viscosity
•Thermal GravimetricAnalysis
•Transferability
•Solvent resistance
•Deposition thickness
•Surface topography
Electrical Performance
•Conductivity
•Resistivity•Capacitance
•Mobility
•On/Off ratio
•IV characteristics
TGA for DuPont Dielectric 8153
60
65
70
75
80
85
90
95
100
105
0 10 20 30 40 50 60
Time [min]
W e i g
h t %
100 C120 C150 C
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Electronic MaterialsCharacterization
Fluid Dynamics
Deposition Issues
• Fluid properties• Solution stability/shelf-life• Curing/Sintering/Annealing
temperature and schedules• Particle interactions
• Printing parameteroptimization
• Meniscus oscillation• Droplet pinch-off
• Material/substratewettability
• Droplet evaporation• “Coffee Stain”
phenomena
Large Area Materials Printing Studies
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Deposition Issues –
Optical Profile of Ink “Coffee Stain Effect”• Droplet spacing (Pitch size) is observed and optimized to improve edge uniformity and toensure continuity between droplets
• Dispersion based materials experience solute diffusion
Droplet overlap determines electrical performance
D i D i f L A El t i
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Device Design for Large Area Electronics Design criteria9
Printing resolution9 Thickness9 Registration9 Orientation for critical dimensions9
Process conditions9 Process sequence9 Material chemical and process compatibility
Printing process selection9 Printing resolution to achieve finer channellength9 Film thickness for thinner dielectric layer9 Available electronic material sets
Rheological properties: viscosity,surface tension, tack
Particle size distributionSolvent compatibility
L
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b
Gate
Dielectric
Substrate
a
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
SS
SS
Source Drain
Critical design parameters for large area electronics manufacturing have been identified.
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10-13
10-12
10-11
10-10
10-9
10-8
10-7
-100 -80 -60 -40 -20 0 20 40 60
Gen2 Set1 Sub5
22232425262829303133
D r a i n
C u r r e n
t ( A )
Gate Voltage (V)
Gen1 Performance100um Printed Features
Bias V = -40 V Bias V = -40 V
10 -13
10 -12
10 -11
10 -10
10 -9
10 -8
10 -7
-120 -100 -80 -60 -40 -20 0 20 40
1
2
3
4
6
7
8
9
10
Gate Voltage (V)
Printers will soon have THE FLEXO LAW, THE GRAVURE LAW (MOORE’S LAW II)
In-Line QA/QC Tools for High Volume
Manufacturing of Large Area ElectronicsGen2 Performance50um Printed Features
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I Li QA/QC T l f Hi h V l
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In-Line QA/QC Tools for High VolumeManufacturing of Large Area Electronics
2500 ft roll
18” Diameter
More than 30miles of timing circuits demonstrated at manufacturing
speeds of 300ft/min on a 6in web platform and 7000sheets/hr on a 24in X 36in sheet-fed platform.
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Organic and Printed Electronics Technology WG
• Kickoff of iNEMI Organic and PrintedElectronics Technology Working Group(February 2006, Anaheim, CA)
• Opportunity for PET WG to engage largeend user companies to provide an outlookfor large area electronics products
• PET WG will deliver 1 st Printed andOrganic Electronics Roadmap by
September 22nd
, 2006• Representatives from graphic arts printingand microelectronics industries are joining
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Organic and Printed Electronics Technology WG• Potential Roadmap Topics
– Manufacturing Equipment – Manufacturing Processes – Materials: Organic, Inorganic – Quality/Reliability (product specifics) – Environmental Technology (product specifics) – Test, Inspection, Measurement (TIM)
• Technology Needs – Advanced functional material/ink system
– Integrated printing press for PET – Printable circuit design tools and application development – In-line registration at high speed – In-line functional testing at high speed
• Key Performance Attributes – Semiconductor charge carrier mobility (>0.1 cm2/V-s) – Functional inks: conductors (Rsheet<100 Ω / ), dielectrics ( ε >5) – Printing resolution (<25 um): printing consumable materials and imaging
technologies
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Acknowledgements• We would like to thank Dr. Michael Schen and Dr.
Francis Barros, Advanced Technology Program,
National Institute of Standards and Technology for their technical and economic contributions and guidance.
• This effort was partially funded under an award from the Advanced Technology Program, National
Institute of Standards and Technology(# 70NANB0H3033).