Compact Modeling for Symmetric and

Asymmetric Double Gate MOSFETsMOSIS

Henok AbebeThe MOSIS Service

USC Viterbi School of EngineeringInformation Sciences Institute

CollaboratorsEllis Cumberbatch and Hedley Morris:

CGU School of Mathematical Sciences, USAVance Tyree: USC/ISI MOSIS, USA

Shigeyasu Uno: Nagoya University, Department of Electrical and

Computer Engineering, Japan

1st International MOS-AK Meeting, co-located with CMC Meeting and IEDM Conference, Dec.13 2008, San Francisco, CA

2

Outline

• 1-D symmetric undoped DG MOSFET modeling.• 2-D asymmetric and lightly doped DG MOSFET

modeling. • Mid-section electrostatic potential approximation.• Long channel mobile charge and current models for

asymmetric DG MOSFET.• Preliminary simulation results and comparison with

numerical 2-D data.

MOSIS

3

1-D symmetric undoped DG MOSFET modeling MOSIS

• Undoped and symmetric.• Relatively small silicon thickness (eg. tsi=5nm).• Two gate voltages are taken to be the same.• Thin gate oxide (eg. tox=1.5nm).

4

• Boundary conditions

oxt0x

/ where)( .3

.2

0|.1

2/2/

00

0

oxoxoxtx

sitgox

x

x

tCdx

dVC

dx

d

si

si

1-D symmetric DG (continued)

• Poisson equation

kTVqi

si

enq

dx

d /)(2

2

MOSIS

sit

5

1-D symmetric DG (continued)

• Exact solution using the first two boundary conditions:

• Surface potential:

)]2

ln[cos(2

)( 2/2

00 xe

kT

nq

q

kTVx kTq

si

i

MOSIS

2/sits

6

1-D symmetric DG (continued)

• Interface boundary condition equation for β:

ln ln(cos ) 2 tan

( ) 22ln( )22

r

q V V kTg sikT t q nsi i

MOSIS

siox

oxsikTq

si

isi

t

tre

kT

nqt

and

22 where 2/

20

7

1-D symmetric DG (continued)

• Total mobile charge per unit gate area:

• Channel current:

MOSIS

tan)/2)(/2(2)/(2 2/ sisitxsi tqkTdxdQsi

S

DrII dsds

]tan

2

1tan[ 222

0

20 )

2(

4 where

q

kT

tL

WI

si

sids

2/0 and

8

• For charge and current calculations, equation needs solving at source and drain only.

• Have efficient iteration algorithm to solve for

• Results are very accurate (see WCM proceedings Vol. 3, pp. 849,  June 1-5, (2008), Boston)

MOSISSummary of the 1-D symmetric DG MOSFET

.

9

2-D asymmetric and doped DG MOSFET modeling

akTVq

isi

Nenq

dY

d

dX

d /)(

2

2

2

2

X

Y

MOSIS

ln),(),( , ,/ln thd VvwVLyYxLX

qn

VLT/qKV

n

N

i

sithdbth

i

a and , where

ScalingGBV

GFV

OXBT

OXFT

10

2-D asymmetric (continued)

11 ln)(

2

22

2

2

vwe

y

w

x

w

ln

whereL

Ld

MOSIS

2)()()(),( xycxybyayxw

Parabolic potential approximation:

11

2-D asymmetric (continued)

)(),( .3

)( .2

)( .1

00

2

2

yawyxw

t

wv

x

w

t

wv

x

w

x

oxb

fsbgbox

tx

si

oxf

fsfgfox

tx

si

si

si

MOSIS

Boundary conditions:

)(2

)(

)(2

)(

oxb

bsbgf

oxf

fsfgf

sisi

ox

oxb

bsbgf

oxf

fsfgf

si

ox

t

wv

t

wv

tyc

t

wv

t

wvyb

12

2-D asymmetric (continued) MOSIS

Surface potentials:

42

422

0

2

0

sisisb

sisisf

tc

tbww

tc

tbww

Explicit solutions can be calculated for wsf and wsb.

13

Mid-section electrostatic potential approximation

01 ln)(

020

22 0 KeEw

dy

wd vw

),,,,( and ),,( where gbgfsioxboxfsioxboxf vvtttfKtttfE

MOSIS

Long channel approximation:

factor. correction a is where

0

0*00

2

www

14

Mid-section (continued)

01 ln)(*

0

*0 KeEw vw

MOSIS

0)ln

( where

ln

)ln

(

ln)(

ln)(

*0

vE

K

vE

K

eE

E

KeE

LambertWw

15

Long channel mobile charge and current models for asymmetric DG MOSFET

OXB

FSBGB

OXF

FSFGFox T

V

T

VVQ

)()()(

MOSIS

Total mobile charge per unit gate area:

Channel current:

dsV

ds dVVQL

WI

0

0 )(

16

Preliminary simulation results and comparison with numerical 2-D data

MOSIS

1 1.5 2 2.5 3 3.5 4-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

(VGF

-VGB

) [V]

0* [

V]

Na/n

i=105, T

s=5nm, T

OXF=1.5nm, T

OXB=3nm and V

GB=-1V

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

(SF

-SB

) [V]

0* [

V]

Na/n

i=105, T

s=5nm, T

OXF=1.5nm, T

OXB=3nm and V

GB=-1V

Mid-section potential versus relative gate voltage and relative surface potential with 5nm silicon thickness (lightly doped asymmetric DG MOSFET)

17

Preliminary simulation (continued) MOSIS

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Vgs

- [V]

0* [

V]

Na/n

i=105, T

s=5nm, T

OXF=T

OXB=1.5nm

0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 10-8

0.5

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

Ts [m]

0* [

V]

Vgs

-=1V, TOXF

=TOXB

=1.5nm

Mid-section potential versus relative gate voltage and silicon thickness with 1.5nm oxide thickness (lightly doped symmetric DG MOSFET)

18

Preliminary simulation (continued) MOSIS

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

3

4

5

6

7x 10

-3

Vds

[V]

I ds [

A]

L=W=200nm

Simulation

Numerical data

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

3

4

5

6

7

8

9x 10

-3

Vds

[V]

g ds [

A/V

]

L=W=200nm

Simulation

Numerical data

25.1

2

VVgs

Channel current and output conductance versus source-drain voltage with 5nm silicon and 1.5nm oxide thicknesses (lightly doped symmetric DG MOSFET)

19

Preliminary simulation (continued) MOSIS

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

3

4

5

6

7x 10

-3

Vgs

[V]

I ds [

A]

L=W=200nm

Simulation

Numerical data

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-11

-10

-9

-8

-7

-6

-5

-4

Vgs

[V]g m

[A

/V]

(

log

scal

e)

L=W=200nm

Simulation

Numerical data

25.1

2

VVds

Channel current and tansconductance versus gate voltage with 5nm silicon and 1.5nm oxide thicknesses (lightly doped symmetric DG MOSFET)

20

Preliminary simulation (continued) MOSIS

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

3

4

5

6

7x 10

-3 L=W=118nm

Vds [V]

I ds [

A]

Simulation

Numerical data

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

3

4

5

6

7

8

9x 10

-3

Vds

[V]

g ds [

A/V

]

L=W=118nm

Simulation

Numerical data

25.1

2

VVgs

Channel current and output conductance versus source-drain voltage with 5nm silicon and 1.5nm oxide thicknesses (lightly doped symmetric DG MOSFET)

21

Preliminary simulation (continued) MOSIS

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

3

4

5

6

7x 10

-3 L=W=118nm

Vgs

[V]

I ds [

A]

Simulation

Numerical data

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-11

-10

-9

-8

-7

-6

-5

-4

Vgs

[V]

g m [

A/V

]

(lo

g sc

ale)

L=W=118nm

Simulation

Numerical data

25.1

2

VVds

Channel current and tansconductance versus gate voltage with 5nm silicon and 1.5nm oxide thicknesses (lightly doped symmetric DG MOSFET)

22

Preliminary simulation (continued) MOSIS

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

3

4

5

6

7x 10

-3 L=W=90nm

Vds

[V]

I ds [

A]

Simulation

Numerical data

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

3

4

5

6

7

8

9x 10

-3

Vds

[V]

g ds [

A/V

]

L=W=90nm

Simulation

Numerical data

25.1

2

VVgs

Channel current and output conductance versus source-drain voltage with 5nm silicon and 1.5nm oxide thicknesses (lightly doped symmetric DG MOSFET)

23

Preliminary simulation (continued) MOSIS

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

3

4

5

6

7x 10

-3 L=W=90nm

Vgs

[V]

I ds [

A]

Simulation

Numerical data

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-11

-10

-9

-8

-7

-6

-5

-4

Vgs

[V]g m

[A

/V]

(log

scal

e)

L=W=90nm

Simulation

Numerical data

25.1

2

VVds

Channel current and tansconductance versus gate voltage with 5nm silicon and 1.5nm oxide thicknesses (lightly doped symmetric DG MOSFET)

MOSIS

University of Southern California (USC)Viterbi School of Engineering

Information Sciences Institute (ISI)The MOSIS Service

Marina del Rey, California

campusmain USC

r.south towe

Marina theoffloor 7th