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Comparison of Cache Replacement Policies using GEM5 Simulator · 0 0.2 0.4 0.6 0.8 1 1.2 Matrix...

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Comparison of Cache Replacement Policies using GEM5 Simulator Teammates – Bhagyashree Nivin Sri Divya
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Page 1: Comparison of Cache Replacement Policies using GEM5 Simulator · 0 0.2 0.4 0.6 0.8 1 1.2 Matrix Size 128 L1_D L1_I L2 L3 0 0.2 0.4 0.6 0.8 1 1.2 Matrix Size 64 L1_D L1_I L2 L3 fifo

Comparison of Cache Replacement Policies using GEM5 Simulator

Teammates – Bhagyashree Nivin Sri Divya

Page 2: Comparison of Cache Replacement Policies using GEM5 Simulator · 0 0.2 0.4 0.6 0.8 1 1.2 Matrix Size 128 L1_D L1_I L2 L3 0 0.2 0.4 0.6 0.8 1 1.2 Matrix Size 64 L1_D L1_I L2 L3 fifo

Research Ideas

1. Increase the cache levels

2. Cache Replacement Favors a specific locality

3. Mixing of Cache Replacement algorithm in different levels

4. Cache associativity

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Gem5 Simulator

Install : hg clone http://repo.gem5.org/gem5-stable Build: build gem5 with “scons” e.g scons build/X86/gem5.opt

We are using matrix multiplication program for performance Evaluation.

Page 4: Comparison of Cache Replacement Policies using GEM5 Simulator · 0 0.2 0.4 0.6 0.8 1 1.2 Matrix Size 128 L1_D L1_I L2 L3 0 0.2 0.4 0.6 0.8 1 1.2 Matrix Size 64 L1_D L1_I L2 L3 fifo

Cache Replacement Favors a specific locality

9060000

9080000

9100000

9120000

9140000

9160000

9180000

9200000

9220000

1 2 3 4 5

FIFO LRU RANDOM

for ( int i=0; i<n;i++) for(int j=0; j<n; j++) data += a[j][i];

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Level 2 Cache Hierarchy

Page 6: Comparison of Cache Replacement Policies using GEM5 Simulator · 0 0.2 0.4 0.6 0.8 1 1.2 Matrix Size 128 L1_D L1_I L2 L3 0 0.2 0.4 0.6 0.8 1 1.2 Matrix Size 64 L1_D L1_I L2 L3 fifo

Set Associativity

0

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1

1.2

L1(random)

L2(random)

L3(random)

L1 (lru) L2 (lru) L3 (lru)

2 way

4 way

8 way

248

842

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Inclusive & Exclusive Caches

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Three Level Cache - System Architecture

Page 9: Comparison of Cache Replacement Policies using GEM5 Simulator · 0 0.2 0.4 0.6 0.8 1 1.2 Matrix Size 128 L1_D L1_I L2 L3 0 0.2 0.4 0.6 0.8 1 1.2 Matrix Size 64 L1_D L1_I L2 L3 fifo

Configuration – Different Cache Policy on Different

Levels • Configuration

– 1Ghz clock machine

– Coherent crossbar

Page 10: Comparison of Cache Replacement Policies using GEM5 Simulator · 0 0.2 0.4 0.6 0.8 1 1.2 Matrix Size 128 L1_D L1_I L2 L3 0 0.2 0.4 0.6 0.8 1 1.2 Matrix Size 64 L1_D L1_I L2 L3 fifo

0

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Matrix Size 32

L1_D

L1_I

L2

L3

fifo 32 0.017048 0.001168 0.723251 0.913687

fifo_lru 32 0.017067 0.001168 0.70857 0.925618

fifo_lru 32 0.017072 0.001168 0.738064 0.886211

lru 32 0.016284 0.001087 0.743995 0.928317

lru_fifo 32 0.016296 0.001087 0.757223 0.911181

lru_rand 32 0.016278 0.001087 0.771287 0.899801

rand 32 0.017586 0.001173 0.719603 0.888849

rand_fifo 32 0.017633 0.001171 0.701898 0.912015

rand_lru 32 0.01762 0.001171 0.68781 0.932473

fifo 64 0.00639 0.000479 0.686542 0.913393

fifo_lru 64 0.006389 0.000479 0.673001 0.922829

fifo_rand 64 0.00639 0.000479 0.699861 0.884465

lru 64 0.005923 0.000446 0.853641 0.999789

lru_el 64 0.005923 0.000446 0.853641 0.999789

lru_elr 64 0.005922 0.000446 0.853461 1

lru_fifo 64 0.00595 0.000446 0.733174 0.912532

lru_rand 64 0.00594 0.000446 0.7451 0.902349

rand 64 0.006615 0.000479 0.681471 0.885869

rand_fifo 64 0.006635 0.000483 0.662083 0.911556

rand_lru 64 0.006628 0.000483 0.64979 0.930711

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0

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Matrix Size 128

L1_D

L1_I

L2

L3

0

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Matrix Size 64

L1_D

L1_I

L2

L3

fifo 128 0.01909 0.000086 0.07945 0.693392

fifo_lru 128 0.019127 0.000086 0.075329 0.755658

fifo_rand 128 0.019102 0.000086 0.081351 0.675566

lru 128 0.018813 0.00008 0.076337 0.731806

lru_el 128 0.018695 0.00008 0.085995 0.755884

lru_elr 128 0.018689 0.00008 0.065093 0.998414

lru_fifo 128 0.018768 0.00008 0.08044 0.722336

lru_rand 128 0.018784 0.00008 0.082309 0.680509

rand 128 0.017315 0.000087 0.090181 0.707026

rand_fifo 128 0.017325 0.000086 0.087353 0.69527

rand_lru 128 0.017355 0.000086 0.082081 0.737382

lru 256 0.018309 0.000011 0.99013 0.050849

lru_el 256 0.018376 0.000011 0.996695 0.520432

lru_elr 256 0.018314 0.000011 0.989714 0.524697

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Changing the memory hierarchy / Cache exclusive

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matrix_size L1_D L1_I L2 L3

Matrix Size -64

lru

lru_el

lru_elr

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140

matrix_size L1_D L1_I L2 L3

Matrix Size - 128

lru

lru_el

lru_elr

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0

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matrix_size L1_D L1_I L2 L3

Matrix Size - 256

lru

lru_el

lru_elr

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Reference

• Virtual Image -

https://drive.google.com/open?id=0B8K6cnetxNFmcXZ2R2lzMUptQWs

• http://www.ece.uah.edu/~milenka/docs/milenkovic_acmse04r. pdf

• http://www.cs.ucf.edu/~neslisah/final.pdf

• http://www.cse.scu.edu/~mwang2/projects/Cache_replacemen t_10s.pdf

• https://ece752.ece.wisc.edu/lect11-cache-replacement.pdf

• https://en.wikipedia.org/wiki/Cache_replacement_policies

• http://people.csail.mit.edu/emer/papers/2010.06.isca.rrip.pdf

• http://www.cs.utexas.edu/users/mckinley/papers/evict-me-pac t-2002.pdf

• http://snir.cs.illinois.edu/PDF/Temporal%20and%20Spatial%20L ocality.pdf

• https://math.mit.edu/~stevenj/18.335/ideal-cache.pdf

• https://pdfs.semanticscholar.org/6ebe/c8701893a6770eb0e19a 0d4a732852c86256.pdf • https://fD3hhNnfL6kwww.youtube.com/watch?v=

• http://pages.cs.wisc.edu/~david/courses/cs752/Spring2015/ge m5-tutorial/index.html

• http://blog.stuffedcow.net/2013/01/ivb-cache-replacement/

• https://github.com/dependablecomputinglab/csi3102-gem5-ne w-cache-policy


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