Comparison of strained SiGe heterostructure-on-insulator (0 0 1) and (1 1 0) PMOSFETs: C–V characteristics, mobility, and ON current Anh-Tuan Pham a,d,⇑ , Qing-Tai Zhao c , Christoph Jungemann b , Bernd Meinerzhagen a , Siegfried Mantl c , Bart Soree d,e , Geoffrey Pourtois d a BST, TU Braunschweig, 38023 Braunschweig, Germany b ITHE, RWTH Aachen University, 52056 Aachen, Germany c IBN1_IT, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany d Physics Modelling and Simulation, IMEC, 3001 Leuven, Belgium e Physics Department, Universiteit Antwerpen, 2020 Antwerpen, Belgium article info Article history: Available online 14 July 2011 Keywords: Heterostructure-on-insulator PMOSFETs Crystallographic orientation Strain Quantum confinement SiGe alloy abstract Strained SiGe heterostructure-on-insulator (0 0 1) and (1 1 0) PMOSFETs are investigated including impor- tant aspects like C–V characteristics, mobility, and ON current. The simulations are based on the self- consistent solution of 6 6 k p Schrödinger Equation, multi subband Boltzmann Transport Equation and Poisson Equation, and capture size quantization, strain, crystallographic orientation, and SiGe alloy effects on a solid physical basis. The simulation results are validated by comparison with different exper- imental data sources. The simulation results show that the strained SiGe HOI PMOSFET with (1 1 0) sur- face orientation has a higher gate capacitance and a much higher mobility and ON current compared to a similar device with the traditional (0 0 1) surface orientation. Ó 2011 Elsevier Ltd. All rights reserved. 1. Introduction Strained SiGe heterostructure-on-insulator (HOI) stacks in com- bination with non-traditional surface and channel orientations are promising concepts for improving PMOS performance. On the re- search level, transport and electrostatics of strained SiGe HOI PMOSFETs with the traditional (0 0 1) surface orientation have pre- viously been studied both experimentally [1,2] and by simulation [3–5]. Advanced HOI PMOS structures contain a heterostructure of Si/SiGe/Si in the channel as shown in Fig. 1. The inclusion of a SiGe layer in the channel improves the mobility of the hole inver- sion layer, but at the same time the gate induced drain leakage cur- rent (GIDL) increases due to the lower band gap between the conduction band and the valence subbands of the SiGe alloy (0.661 eV for Ge compared to 1.12 eV for Si). The Si layers sand- wiched between the SiGe layer and the oxide layers reduce the GIDL because the off-state current leaks through these regions with higher band gaps [2,6]. The channel layers are strained in or- der to boost channel mobility and ON current. During the fabrica- tion of HOI PMOS structures [1] the semiconductor layers are first grown pseudomorphically on a relaxed Si 1y Ge y substrate with a Ge content y and subsequently transferred to oxide, in such a way that the strain state of the original epitaxial layer stack is re- tained after the transfer. The difference z–y between the Ge con- tents in the thin Si 1z Ge z channel layer and the relaxed Si 1y Ge y substrate determines the compressive strain in the Si 1z Ge z layer. In this work simulation of strained SiGe HOI PMOSFETs is ex- tended to the (1 1 0) surface orientation in order to provide a better understanding of the differences between the (0 0 1) and (1 1 0) sur- face orientations for strained SiGe HOI PMOSFETs. The comparison is focused on many important aspects including C–V characteris- tics, mobility, and ON current. The (1 1 0) surface orientation is of special interest because it was observed both experimentally [7] and using simulations [8,9] that the (1 1 0) surface orientation en- hances the effective hole mobility for unstrained Si bulk PMOSFETs compared to the (1 0 0) surface. The simulation results are vali- dated by comparison with different experimental data sources. 2. Simulation methods The simulations are based on the self-consistent solution of the 6 6 k p Schrödinger Equation (SE), the multi subband Boltz- mann Transport Equation (BTE), and Poisson Equation (PE) [10,11]. This simulation method captures the influence of size quantization, strain, surface/channel orientations, and SiGe alloys on a solid physical basis. Each device is partitioned into many 0038-1101/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2011.06.021 ⇑ Corresponding author at: BST, TU Braunschweig, Hans-Sommer Str. 18, 38106 Braunschweig, Germany. E-mail address: [email protected](A.-T. Pham). Solid-State Electronics 65–66 (2011) 64–71 Contents lists available at ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Transcript
Solid-State Electronics 65–66 (2011) 64–71
Contents lists available at ScienceDirect
Solid-State Electronics
journal homepage: www.elsevier .com/locate /sse
Comparison of strained SiGe heterostructure-on-insulator (001) and (110)PMOSFETs: C–V characteristics, mobility, and ON current
Anh-Tuan Pham a,d,⇑, Qing-Tai Zhao c, Christoph Jungemann b, Bernd Meinerzhagen a, Siegfried Mantl c,Bart Soree d,e, Geoffrey Pourtois d
Strained SiGe heterostructure-on-insulator (001) and (110) PMOSFETs are investigated including impor-tant aspects like C–V characteristics, mobility, and ON current. The simulations are based on the self-consistent solution of 6 � 6 k � p Schrödinger Equation, multi subband Boltzmann Transport Equationand Poisson Equation, and capture size quantization, strain, crystallographic orientation, and SiGe alloyeffects on a solid physical basis. The simulation results are validated by comparison with different exper-imental data sources. The simulation results show that the strained SiGe HOI PMOSFET with (110) sur-face orientation has a higher gate capacitance and a much higher mobility and ON current compared to asimilar device with the traditional (001) surface orientation.
� 2011 Elsevier Ltd. All rights reserved.
1. Introduction
Strained SiGe heterostructure-on-insulator (HOI) stacks in com-bination with non-traditional surface and channel orientations arepromising concepts for improving PMOS performance. On the re-search level, transport and electrostatics of strained SiGe HOIPMOSFETs with the traditional (001) surface orientation have pre-viously been studied both experimentally [1,2] and by simulation[3–5]. Advanced HOI PMOS structures contain a heterostructureof Si/SiGe/Si in the channel as shown in Fig. 1. The inclusion of aSiGe layer in the channel improves the mobility of the hole inver-sion layer, but at the same time the gate induced drain leakage cur-rent (GIDL) increases due to the lower band gap between theconduction band and the valence subbands of the SiGe alloy(0.661 eV for Ge compared to 1.12 eV for Si). The Si layers sand-wiched between the SiGe layer and the oxide layers reduce theGIDL because the off-state current leaks through these regionswith higher band gaps [2,6]. The channel layers are strained in or-der to boost channel mobility and ON current. During the fabrica-tion of HOI PMOS structures [1] the semiconductor layers are firstgrown pseudomorphically on a relaxed Si1�yGey substrate with a
ll rights reserved.
Hans-Sommer Str. 18, 38106
Pham).
Ge content y and subsequently transferred to oxide, in such away that the strain state of the original epitaxial layer stack is re-tained after the transfer. The difference z–y between the Ge con-tents in the thin Si1�zGez channel layer and the relaxed Si1�yGey
substrate determines the compressive strain in the Si1�zGez layer.In this work simulation of strained SiGe HOI PMOSFETs is ex-
tended to the (110) surface orientation in order to provide a betterunderstanding of the differences between the (001) and (110) sur-face orientations for strained SiGe HOI PMOSFETs. The comparisonis focused on many important aspects including C–V characteris-tics, mobility, and ON current. The (110) surface orientation is ofspecial interest because it was observed both experimentally [7]and using simulations [8,9] that the (110) surface orientation en-hances the effective hole mobility for unstrained Si bulk PMOSFETscompared to the (100) surface. The simulation results are vali-dated by comparison with different experimental data sources.
2. Simulation methods
The simulations are based on the self-consistent solution of the6 � 6 k � p Schrödinger Equation (SE), the multi subband Boltz-mann Transport Equation (BTE), and Poisson Equation (PE)[10,11]. This simulation method captures the influence of sizequantization, strain, surface/channel orientations, and SiGe alloyson a solid physical basis. Each device is partitioned into many
Fig. 1. HOI sSi(cap)/sSi1�zGez/sSi PMOS structure. The biaxial strain in the Si andSiGe layers is assumed to be consistent with a pseudomorphic growth of each layeron a relaxed Si1�yGey virtual substrate.
vertical slices along the channel direction [12]. For each slice the1D SE is solved. The total Hamiltonian of the k � p SE is given by
bH6�6totalðz0;kÞ ¼ bH6�6
kp ðz0;kÞ þ bH6�6so ðz0Þ þ bH6�6
strainðz0Þ þ Evðz0ÞbI þ Vðz0ÞbIð1Þ
where bH6�6kp ; bH6�6
so , and bH6�6strain are the k � p Hamiltonian, spin–orbit
coupling Hamiltonian, and strain Hamiltonian, respectively. Ev isthe average valence band energy of each alloy and V the electro-static potential. z0 is the position along the quantization directionez0 . ez0 is also the growth direction of the planar PMOS structureindicating the surface orientation. k is the wave vector.
For the evaluation of the strain Hamiltonian bH6�6strain, the biaxial
strain tensor is determined based on the Ge contents z and y inthe channel layer and the virtual substrate, respectively [9]. ThePikus–Bir strain Hamiltonian is calculated using the resultantstrain tensor and is added to the 6 � 6 k � p Hamiltonian. The va-lence band offset energies Ev(z0) due to the Si/SiGe/Si heterostruc-ture are calculated based on the average valence band energy ofeach alloy layer following [13]. The diagonal Hamiltonian due tothese valence band offsets is also added to the total Hamiltonian.Spin–orbit coupling is considered by an additional spin–orbit cou-pling Hamiltonian. Size quantization effects and the electrostaticpotential are considered by solving the 1D 6 � 6 k � p envelop func-tion SE which results from the total Hamiltonian. The solution ofthe SE provides the valence subband structure and allows to calcu-late the scattering overlap factors. A rotation of the k � p and strainHamiltonian is necessary in order to handle different surface orien-tations [14,9].
Please note that the derivation of the k � p theory for a hetero-structure is much more complicated than for a single layer struc-ture due to the nature of the problem: the periodicity of thelattice is destroyed in a heterostructure. In principle, this aperio-dicity of the lattice should be included in the derivation of thek � p SE [15,16]. However, the aperiodicity of the lattice for multiplelayers in a Si–SiGe heterostructure is often neglected [17]. Thisassumption allows to use the described k � p theory for both singlelayer structures and heterostructures implying that the k � p theoryis unchanged for heterostructures. Nevertheless, due to the z0
dependence of the k � p parameters as well as of Ev, the discretiza-tion of the k � p SE at the interface between two layers of a hetero-structure is not trivial in order to obtain a hermitian eigenproblem, which ensures real values for the eigen energies. To solvethis problem, the box integration method is used in this work forthe discretization of the k � p SE on a non-equidistant z0 grid. Ashows the details of discretization and the discretized equationsof all grid points can be casted into matrix form as follows:
. . .bD�j�1bDj�1
bDþj�1bD�j bDjbDþjbD�jþ1bDjþ1
bDþjþ1
. . .
0BBBBBBB@
1CCCCCCCA
. . .
fj�1
fj
fjþ1
. . .
0BBBBBB@
1CCCCCCA ¼ ebC. . .
fj�1
fj
fjþ1
. . .
0BBBBBB@
1CCCCCCA ð2Þ
where e is the eigen energy, fj the eigen function associated withgrid point j, and bC a positive-definite and diagonal matrix. The enve-lope functions are assumed to vanish at the interfaces between thesemiconductor and the top or bottom oxide. In A it is demonstratedthat the discretization results in bDyj ¼ bDj and bD�j� �y
¼ bDþj�1. Theeigen problem (2) is, therefore, hermitian which ensures real valuedeigen energies.
The stationary multi subband BTE is solved with a deterministicmethod based on a Fourier harmonic expansion of the distributionfunction up to high order (13th). This method is well documentedin [11]. The transport simulations include scattering due to pho-non, surface roughness and alloy disorder. The calculation of thetransition rates of these scattering mechanisms is described in[4]. The hole density resulting from the subband structure andthe distribution function is considered in the 2D PE in order to ob-tain a self-consistent solution. The electron density and the holedensity in the bulk layer below the BOX layer are calculated classi-cally based on the electrostatic potential and a constant quasi-Fermi level. The three equations are solved self-consistently usingan efficient quasi Newton iteration scheme [11]. For a given gatebias the typical CPU times for obtaining the mobility and the ONcurrent are 20–30 min and 3–4 h, respectively.
3. Results
For the C–V characteristics and mobilities a homogeneous chan-nel HOI PMOS structure is simulated. The thickness of the top oxideis 1 nm or 3.5 nm and the thickness of the bottom oxide is 10 nm.The thicknesses of the channel stack layers are tsSi(cap) = 2 nm,tsSiGe = 20 nm, and tsSi = 4 nm. The thickness of the bulk layer belowthe bottom oxide is 800 nm. The Ge contents in the strained Si1�z-
Gez layer and in the relaxed Si1�yGey virtual substrate are z = 0.46and y = 0.25, respectively. A uniform donor doping concentrationof 1015 cm�3 is assumed in both the channel layers and the bulkSi region. A metal gate contact and an ohmic contact at the bottomof the bulk region are assumed. A bulk bias VB of 0 V and a constantlattice temperature of 300 K are assumed in all simulations. Thesimulations are performed for the two interface orientations(001) and (110). The channel directions for the (001) and (110)interface orientations are [110] and [�110], respectively.
The quasi static gate capacitance per unit area defined as
CGG ¼@qNinv
@VGð3Þ
is evaluated based on the variation of the inversion charge Ninv w.r.t.a small variation of the gate bias VG (here, q is the elementarycharge). Fig. 2 shows the C–V characteristics for the two differentstrained SiGe HOI PMOS structures over a wide range of VG. Pleasenote that CGG refers to a gate length L and width W of 50 lm and30 lm, respectively.
For the oxide thickness of 3.5 nm the simulated CGG of the (001)HOI PMOS reproduces quite well the experimental data of Aberget al. [1] as shown in Fig. 2 (top). Here, a work function differenceof 0.87 eV is assumed in the simulations. Moreover, the C–V curvefor the (110) HOI PMOS differs substantially from the C–V curvefor the (001) HOI PMOS. The difference is small for jVGj < 2.0 Vresulting in a very small threshold voltage difference of a fewmV only. However, for jVGj > 2.0 V the gate capacitance ofthe (110) PMOS structure is significantly larger than the gatecapacitance of the (001) alternative. Moreover the second
Fig. 2. C–V characteristics for the two strained SiGe HOI (001) and (110) PMOSstructures. tSiO2 ¼ 3:5 nm, a work function difference of 0.87 eV is assumed in thesimulations (top); tSiO2 ¼ 1 nm, a work function difference of 0.0 eV is assumed inthe simulations (bottom). L = 50 lm, W = 30 lm. The experimental results for the(001) device with tox = 3.5 nm are reported in Aberg et al. [1]. The C–V curves forthe (001) surface orientation show no hump, whereas a hump is visible for the(110) orientation.
Fig. 3. C–V characteristic for the two strained SiGe HOI (001) and (110) PMOSstructures including a stack of HfO2/SiO2 in the oxide. A work function difference of0.23 eV is assumed in the simulations. The measured data is for a strained SiGe HOI(001) PMOS structure fabricated using the Jülich processing [22].
changes its sign twice near VG = �2 V. This is not ob-served for the (001) structure. The experimental C–V characteris-tics for the strained SiGe HOI (001) PMOS structure reported in[1] show these sign changes of @2CGG
@V2G
when the strained Si cap thick-
ness is larger than 3–4 nm. In [1] this feature of the C–V character-
istic is addressed as a hump in a certain range of gate biases. For aSi cap thickness smaller than 2 nm this hump vanishes for the(001) case. This is confirmed by the experimental results shownin Fig. 2 (top). Consistent with [1] the simulated C–V curve (seeFig. 2 (top)) for the HOI (001) PMOS structure with 2 nm Si capthickness shows no hump. However, as already outlined above,this hump occurs for the simulated C–V characteristic of the HOI(110) PMOS structure even for the small Si cap thickness of2 nm (see Fig. 2 (top)).
For the thinner oxide with 1 nm thickness the C–V curves for thetwo interface orientations again differ substantially as shown inFig. 2 (bottom). Here, a work function difference of 0.0 eV is as-sumed in the simulations. Again the difference between the (001)and (110) cases is small for jVGj < 0.5 V resulting in a very smallthreshold voltage difference of a few mV only. However, forjVGj > 0.5 V the gate capacitance of the (110) PMOS structure ismuch larger than the gate capacitance of the (001) alternative.For the 1 nm oxide thickness case, again no hump occurs in the C–V curve for the (001) PMOS structure, whereas a hump is observedin the C–V curve for the (110) PMOS structure (see Fig. 2 (bottom)).
Another validation for the C–V simulations is shown in Fig. 3.Here, strained SiGe (001) and (110) HOI PMOS structures with
tsSi(cap) = 3.7 nm, tsSiGe = 25 nm, tsSi = 12 nm, and z = 0.5, y = 0.2 aresimulated. The devices contain a stack of HfO2/SiO2 withtHfO2 ¼ 5 nm; tSiO2 ¼ 1:48 nm which is more complicated than thesingle layer of SiO2 considered in Figs. 1 and 2. For the (001) casethis HOI PMOS structure was processed [22] and characterized aswell in the research center in Jülich, Germany.
In the simulations shown in Fig. 3 a work function difference of0.23 eV is assumed. As shown in Fig. 3 the simulation results pre-dict well the measured C–V curve for the (001) surface. For thissurface a hump occurs in the range 1V < jVGj < 2 V due to a ratherthick Si cap layer (tsSi(cap) = 3.7 nm). For the (110) surface a humpis also found in the C–V curve. For jVGj < 1.1 V the C–V curves forthe (001) and (110) surfaces are rather similar. The threshold volt-age difference is again very small (a few mV only). For jVGj > 1.1 VFig. 3 shows that Cð1 1 0Þ
GG > Cð0 0 1ÞGG for the same gate bias, similar to
the C–V curves shown in Fig. 2.Next, the difference between the C–V curves shown in Fig. 2 for
the two surface orientations is studied. This difference is due to thedifference in the spatial hole density distributions for the two ori-entations of the structures with tSiO2 ¼ 1 nm as shown in Fig. 4. Forlow inversion charge (Ninv = 2 � 1012 cm�2) the hole density withinthe two structures shows peaks only in the SiGe layer near the Sicap/SiGe interface (Fig. 4 (top)). Moreover, it is shown in the samefigure that the sum of the electrostatic potential energy and the va-lence band offset energy is lowest within the SiGe layer at the Sicap/SiGe interface. This is on one hand due to the large valenceband offset potential between the Si cap and the SiGe layer(�0.2 eV for the Ge content of z = 0.46 considered here) and onthe other hand due to the small variation of the electrostatic poten-tial in these two layers. Consequently, the hole density is confinedmainly in the SiGe layer near the Si cap/SiGe interface. Moreover,the distance between the SiO2/Si interface and the hole densitypeak is slightly shorter for the (110) surface orientation. This isconsistent with the observation that the gate capacitance for the(110) structure is slightly larger than the gate capacitance forthe (001) structure (Fig. 2). For higher inversion charges (hereNinv = 1.5 � 1013 cm�2) the hole densities for the two structuresare completely different as shown in Fig. 4 (bottom). For the(001) orientation the holes are still mainly confined close to theSi cap/SiGe interface, although the first quantum well near theSiO2/Si interface has now a much smaller energy than the secondquantum well in the SiGe layer near the Si cap/SiGe interface.The spatial hole density distribution for the (110) structure how-ever shows two distinct peaks indicating that the holes in this casemove more and more from the SiGe to the Si quantum well with
hole
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[cm
-3]
hole
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[cm
-3]
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-0.2 0.0 0.2 0.4
-0.2 0.0 0.2 0.4
elec
. pot
. ene
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vale
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offs
et e
nerg
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V]
HOI: sSi(cap)-sSi0.54Ge0.46-sSi
virtual substrate: rSi0.75Ge0.25
tsSi(cap)=2 nm, tsSiGe=20 nm, tsSi=4 nm
Ninv=2x1012 cm-2
(110) surface/[-110] channel(001) surface
0 5 10 15 20 25 elec
. pot
. ene
rgy+
vale
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band
offs
et e
nerg
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V]
z’ position [nm]
0 5 10 15 20 25z’ position [nm]
HOI: sSi(cap)-sSi0.54Ge0.46-sSi
virtual substrate: rSi0.75Ge0.25
tsSi(cap)=2 nm, tsSiGe=20 nm, tsSi=4 nm
Ninv=1.5x1013 cm-2
0e+00
1e+18
2e+18
3e+18
4e+18
5e+18
6e+18
0e+00
1e+19
2e+19
3e+19
4e+19
5e+19
6e+19
7e+19
8e+19
9e+19
1e+20
Fig. 4. Spatial distributions of hole density and electrostatic potential + valenceband offset energy in the strained SiGe HOI (001) and (110) PMOS structures.tSiO2 ¼ 1 nm. Top: Ninv = 2 � 1012 cm�2 (VG = 0.014 V for the (001) surface andVG = 0.015 V for the (110) surface). Bottom: Ninv = 1.5 � 1013 cm�2 (VG = �1.059 Vfor the (001) surface and VG = �0.990 V for the (110) surface).
increasing gate voltage. Moreover, the dominant peak of the holedensity distribution for the (110) structure is much closer to theSiO2/Si interface compared to peak position for the (001) structure.This is consistent with the higher gate capacitance for (110) struc-ture (Fig. 2).
Equi energy lines for multiples of 100 meV are shown in Fig. 5for the first HH subband and the two surface orientations. The equienergy lines for the two cases differ substantially. The typical 4-and 2-fold symmetries of the subband structures for the (001)and (110) surface orientations, respectively, are clearly visible. In
-0.3 -0.2 -0.1 0 0.1 0.2 0.3
(001) surface
[110]
chan
nel
kx [2π/aSi]
k y [2π/
a Si]
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Fig. 5. Equi energy lines in multiples of 100 meV of the first HH subband for the strainedHH subband is shifted to 0 meV. Ninv = 1.5 � 1013 cm�2.
the optimum channel direction ([�110]) for the (110) structurethe distance from the C point (k = 0) to the point on the first100 meV equi energy line is much shorter for the (110) surface ori-entation than for the (001) case irrespectively of the channel direc-tion chosen for the (001) case. This indicates that the curvature ismuch higher and consequently the effective mass resulting fromthe first HH energy dispersion relation near the C point for thisdirection is much smaller for the (110) structure than for (001)alternative. Please note that both the ohmic mobility tensor as wellas the average effective mass tensor for the (001) case are isotro-pic. The effective mass for the [�110] channel direction and the(110) surface as calculated directly based on the subband struc-ture is shown in Fig. 6 as a function of inversion charge in compar-ison to the isotropic (001) case. It can be clearly seen that theeffective mass for the (110) case is about a factor of two smallercompared to the (001) case. This is consistent with the differentcurvatures of the first HH energy dispersion relations near the Cpoint mentioned above for the two surface orientations.
For the (001) surface orientation the effective ohmic mobility iscalculated and shown in Fig. 7 for an unstrained Si bulk PMOSstructure and the strained SiGe HOI PMOS structure. The phononand surface roughness scattering parameters have been calibratedto reproduce the experimental mobility by Takagi et al. [18] for un-strained bulk PMOSFETs. For SiGe in addition alloy scattering is ta-ken into account and only one experimental data point of [1] hasbeen used to calibrate the alloy scattering potential. Fig. 7 showsthe excellent agreement between the simulated mobilities andthe measured low-field mobility data of Aberg et al. [1]. All simu-lations in this paper are based on the same scattering parametersextracted only based on the two key experiments shown in Fig. 7as just described. For the (110) surface orientation and the[�110] channel direction, the simulation results reproduce wellthe measured mobility data of Irie et al. [7] for an unstrained Sibulk PMOS structure (Fig. 8). Moreover, as can be seen in the samefigure the simulation results predict that the mobility in thestrained SiGe HOI (110) PMOS structure is much higher than themobility for the unstrained Si bulk (110) PMOS case. For the samestrained SiGe HOI PMOS structure and the optimum [�110] chan-nel direction for the (110) surface case the mobility for the (110)surface orientation is much higher than the mobility for the (001)surface orientation as shown in Figs. 8 and 7, respectively. This isconsistent with the reduction of the effective mass for the (110)case compared to (001) shown in Fig. 6.
Fig. 9 clearly shows that the contribution of alloy scattering tothe mobility in (001) and (110) HOI PMOS structures is important.
Fig. 10 shows the measured mobility for (001) HOI PMOSstructures fabricated using the Jülich processing including aHfO2/SiO2 or LaLuO3/SiO2 gate stack. Simulation results are alsoshown. In the simulations only a single layer of SiO2 with the
(110) surface
[-110
] cha
nnel
-0.3 -0.2 -0.1 0 0.1 0.2 0.3
kx [2π/aSi]
k y [2π/
a Si]
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
SiGe HOI (001) and (110) PMOS structures. For both devices the bottom of the first
Fig. 7. Mobility characteristics of strained SiGe HOI (001) PMOS compared tounstrained Si (001) bulk PMOS. Measured data for HOI and bulk PMOS are takenfrom [1,18], respectively.
Fig. 10. Mobility characteristics of strained SiGe HOI (001) and (110) PMOS withdifferent oxide materials. The measured mobilities are for HOI PMOS structuresfabricated using the Jülich processing [22] including a HfO2/SiO2 or LaLuO3/SiO2
stack. The simulations consider only a single SiO2 layer in the oxide.
equivalent thickness is considered instead of the high-j materials.Nevertheless, the simulation results predict quite well the mea-sured mobility for inversion charges higher than 5 � 1012 cm�2.For smaller inversion charges the simulation results overestimatethe experimental results. This is due to the fact that additional re-mote scattering mechanisms caused by high-j materials (HfO2 andLaLuO3) like remote Coulomb scattering, remote phonon scattering[19] are neglected in the simulations. As shown in Fig. 10 the sim-
Fig. 8. Mobility characteristics of strained SiGe HOI (110) PMOS compared tounstrained Si (110) bulk PMOS. Measured data for bulk PMOS are taken from [7].
ulated mobility for the (110) HOI PMOS is much larger than themobility for the (001) HOI PMOS.
The dependence of the mobility on strained Si cap thickness isshown in Fig. 11. For the (001) surface orientation the simulationresults agree well with measured data from [1]. For all cap thick-nesses the mobility of the (110) structure is much higher. More-over, in both cases the maximum mobility results for a Si capthickness of 1 nm.
Short channel strained SiGe HOI (001) and (110) PMOSFETs aresimulated next. The vertical PMOS stack is the same as for the pre-vious simulations. Here, tSiO2 ¼ 1 nm is considered. The channellength is 22 nm and the acceptor doping concentration in thesource and drain regions is 2 � 1020 cm�3.
ID(VDS) characteristics of the 22 nm strained SiGe HOI (001) and(110) PMOSFETs are shown in Fig. 12. For the same VDS and thesame VGS the simulation results show that the drain current forthe (110) PMOSFET is always higher than the drain current forthe (001) PMOSFET.
The hole sheet charge and drift velocity along the channel areshown in Fig. 13 for the two cases and the ON state bias VGS = �1 Vand VDS = �0.7 V. At about �3 nm (near the source side) the holecharge in the two devices is nearly the same, but the drift velocityfor the (110) device is much larger than the drift velocity for the(001) device. This results in a much higher ON current for the(110) orientation compared to the traditional (001) orientation.
Fig. 12. ID(VDS) characteristics of the 22 nm strained SiGe HOI (001) and (110)PMOSFETs. VGS = �1 V.
ohm
ic c
hann
el c
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ctan
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/(cm
V)]
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s]
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50
60
Fig. 14. Top: Ohmic channel conductance and homogeneous channel low-fieldmobility for the strained SiGe HOI (001) and (110) PMOSFETs. VDS = �1 mV for theshort channel PMOSFETs. Bottom: ON current and homogeneous channel low-fieldmobility for the strained SiGe HOI (001) and (110) PMOSFETs. VDS = �0.7 V for theshort channel PMOSFETs. For all cases VGS = �1 V and the channel directions for(001) and (110) surface orientation are [110] and [�110], respectively.
Fig. 11. Mobility vs. strained Si cap thickness in strained SiGe HOI (001) and (110)PMOS structures. The measured data for strained SiGe HOI (001) PMOS are takenfrom [1].
The homogeneous channel low-field mobility is by a factor ofabout 2.0 larger for the (110) surface orientation (Fig. 14 (top)and (bottom)). In a short channel device this improvement cannotbe fully realized due to quasi-ballistic transport and the nonlineardevice characteristics. Already the conductance in the lineartransport regime defined as gD = ID/jVDSj for small jVDSj, which isevaluated at VDS = �1 mV and VGS = �1.0 V, is larger only by a factor
Fig. 13. Hole sheet charge and drift velocity along the channel in the 22 nmstrained SiGe HOI (001) and (110) PMOSFETs. VGS = �1 V and VDS = �0.7 V.
of 1.7 for the (110) surface orientation (Fig. 14 (top)) (see e.g.[20,21] for an explanation of the underlying reasons of this dis-crepancy). Moreover as shown in Fig. 14 (bottom) the ON currentfor the short channel device with (110) surface orientation is en-hanced by about a factor of 1.5 compared to the (001) case. ThisON current enhancement factor is again smaller than the respec-tive enhancement factor for the conductance in the linear regime(1.7).
4. Conclusions
A comprehensive comparison between strained SiGe HOI (001)and (110) PMOSFETs including important aspects like C–V charac-teristics, mobility, and ON current has been performed by simula-tions. The simulations are based on the solution of the system of6 � 6 k � p SE, multi subband BTE, and PE and capture size quanti-zation, strain, crystallographic orientation, and SiGe alloy effectson a solid physical basis. The simulation results are validated bycomparing with different experimental data sources. The simula-tion results show that the strained SiGe HOI PMOSFET with(110) surface orientation has a higher gate capacitance and a muchhigher mobility and ON current compared to the analog devicewith the traditional (001) surface orientation.
This work has been partially supported by the EU through theNANOSIL NoE (No. IST–216171).
Appendix A
This appendix provides the details about the discretization ofthe EFA SE in z0 with the box integration method.
The EFA k � p Schrödinger Equation with the total Hamiltoniangiven by (1) takes the following form [9,11], where the subband in-dex m and the wave numbers k0x; k
0y are not shown for the sake of
brevity:
�cMð2Þkp ðz
0Þ @2
@z02� icMð1Þ
kp ðz0Þ @@z0þ bH0ð0Þðz0Þ !
fðz0Þ ¼ efðz0Þ ðA:1Þ
In (A.1) cMð2Þkp and cMð1Þ
kp are 6 � 6 hermitian matrices [9]. Thek-independent Hamiltonian bH0ð0Þ is given by
where cMð0Þkp is also a 6 � 6 hermitian matrix [9].
At grid point j on the z0-axis the second, first and zero orderderivatives in (A.1) are discretized by box integration:Z jþ1
2
j�12
� cMð2Þkp ðz
0Þ @2fðz0Þ@z02
dz0 !Z jþ1
2
j�12
� @
@z0cMð2Þ
kp ðz0Þ @fðz
0Þ@z0
� �dz0
¼ cMð2Þkp ðz
0���
j�12
@fðz0Þ@z0
����j�1
2
� cMð2Þkp ðz
0���
jþ12
@fðz0Þ@z0
����jþ1
2
¼ �cMð2Þ
kp;j�1 þ cMð2Þkp;j
2 z0j � z0j�1
� � fj�1 �cMð2Þ
kp;jþ1 þ cMð2Þkp;j
2ðz0jþ1 � z0jÞfjþ1
þcMð2Þ
kp;j�1 þ cMð2Þkp;j
2 z0j � z0j�1
� � þcMð2Þ
kp;jþ1 þ cMð2Þkp;j
2 z0jþ1 � z0j� �
24 35fj ðA:3Þ
Z jþ12
j�12
� icMð1Þkp ðz
0Þ @fðz0Þ
@z0dz0 ! � i
2cMð1Þ
kp;j
Z jþ12
j�12
@fðz0Þ@z0
dz0i2
�Z jþ1
2
j�12
@cMð1Þkp ðz0Þfðz0Þ@z0
dz0 ¼ � i2cMð1Þ
kp;jfðz0Þ���jþ1
2
j�12
� i2cMð1Þ
kp ðz0Þfðz0Þ
���jþ12
j�12
¼ i4cMð1Þ
kp;j þ cMð1Þkp;j�1
h ifj�1
� i4cMð1Þ
kp;j þ cMð1Þkp;jþ1
h ifjþ1 ðA:4Þ
andZ jþ12
j�12
bH 0ð0Þðz0Þfðz0Þdz0 !Z j
j�12
bH0ð0Þðz0Þfðz0Þdz0 þZ jþ1
2
j
bH0ð0Þðz0Þfðz0Þdz0
¼ 14ðz0j � z0j�1Þ dHj� 10ð0Þ þcHj0ð0Þ
� �hþ z0jþ1 � z0j� � dHjþ 10ð0Þ þcHj 0ð0Þ
� �ifj ðA:5Þ
respectively.The discretized equations of all grid points can be casted into
matrix form (2). Here,
bDj ¼cMð2Þ
kp;j þ cMð2Þkp;j�1
2 z0j � z0j�1
� � þcMð2Þ
kp;j þ cMð2Þkp;jþ1
2 z0jþ1 � z0j� �
þz0j � z0j�1
� � dH; j0ð0Þ þ dH; j� 10ð0Þ� �
4
þz0jþ1 � z0j� � dH; j0ð0Þ þ dH; jþ 10ð0Þ
� �4
ðA:6Þ
bD�j ¼ � cMð2Þkp;j þ cMð2Þ
kp;j�1
2 z0j � z0j�1
� � þ i4cMð1Þ
kp;j þ cMð1Þkp;j�1
� �ðA:7Þ
bDþj ¼ � cMð2Þkp;j þ cMð2Þ
kp;jþ1
2 z0jþ1 � z0j� � � i
4cMð1Þ
kp;j þ cMð1Þkp;jþ1
� �ðA:8Þ
and bC is a positive-definite and diagonal matrix with
cjj ¼z0jþ1 � z0j�1
2ðA:9Þ
Because cMð2Þkp and bH0ð0Þ are hermitian, it is obviously that bDyj ¼ bDj.
Moreover:
bD�j� �y¼ �
cMyð2Þkp;j þ cMyð2Þ
kp;j�1
2 z0j � z0j�1
� � þ i�
4cMyð1Þ
kp;j þ cMyð1Þkp;j�1
� �
¼ �cMð2Þ
kp;j þ cMð2Þkp;j�1
2 z0j � z0j�1
� � � i4cMð1Þ
kp;j�1 þ cMð1Þkp;j
� �¼ bDþj�1 ðA:10Þ
because cMð1Þkp and cMð2Þ
kp are hermitian.
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[22] A lightly p–doped (<1015 cm�3) Si0.5Ge0.5 (z = 0.5) layer with a thickness of25 nm (tsSiGe = 25 nm) was grown on (001) biaxially strained SOI (SSOI)substrates. The biaxial strain in the SSOI substrates is tensile with eSi
k � 0:8%,corresponding to y � 0.2. Thus, the pseudomorphically grown Si0.5Ge0.5 layeron top of the SSOI is biaxially (compressively) strained with eSiGe
k � �1:4%. Thedeposition of the SiGe layer was directly followed by the deposition of the5 nm Si cap layer. Devices with gate lengths (L) from 1 to 4 lm and a gatewidth (W) of 20 lm aligned along the [110] crystal direction were fabricatedusing a gate-first process. After mesa definition the initial 5 nm Si cap wasthinned to approximately 3–4 nm (tsSi(cap) � 3–4 nm) by an RCA pre-high-jwet cleaning process. A 5 nm HfO2 gate dielectric was deposited by atomiclayer deposition (ALD) followed by 20 nm TiN as gate metal by atomic vapourdeposition (AVD). After patterning the TiN gate using an oxide layer as hardmask, the source/drain (S/D) implantation was carried out through the HfO2
layer using BF2 at an energy of 14 keV to a dose of 2 � 1015 cm�2. Theindividual transistors were then passivated by a 50 nm thick SiO2 layer.Dopant activation was performed at 650 �C for 1 min to assure strainconservation of the SiGe layer and to reduce Ge inter-diffusion into theadjacent Si layers. Finally, S/D and gate contact windows were opened and anAl metalization deposited.
