Comparison of universal logic gates with NAND and NOR gates in the realisation of functions of three variables S.L. Hurst and N. P. Pflaeger Indexing terms: Combinatorial circuits, Logic design, Logic gates Abstract: This report furthers earlier work of, in particular, Hellerman, who catalogued the minimum number of NOR and NAND elements necessary to realise all 2 2 logic functions of three independent binary input variables. Here we consider the use of universal logic elements rather than NOR and NAND, and derive corresponding statistical and detailed information when the former are used for random logic purposes. 1 Introduction In the design of combinatorial logic networks, it is usual to consider the use of vertex logic elements, that is AND, OR, NAND and NOR gates, from which to synthesise the required logic network. This remains the basis whether the designer is designing a monolithic i.e. layout or a hardware assembly of, say, s.s.i. packages. The number of vertex elements required perforce depends on the complexity of the required network and on the efficiency of the designer, but a measure of the minimum number required for given situations has been investigated by previous authors. An early and still most relevant work is that of Hellerman, 1 who catalogued the number of NOR and NAND gates necessary for the realisation of all possible combinatorial functions of three binary input variables. Hellerman exhaustively determined optimum NOR and NAND realisations of all 2 23 such functions, and hence determined the minimum number of such gates necessary. As may be expected, the minimum number of NOR gates is on average the same as the minimum number of NAND gates when the same restrictions on fan-in etc. are observed, because both types of gate have similar logical discrimi- nation. More recent work in digital logic, however, has suggested alternative logic elements for combinatorial design to the vertex family of gates, the eventual justification of which will depend on viable compact circuit realisations in mono- lithic form. Among such newer elements are universal logic modules (uJ.m.s) or univeral logic gates (u.l.g.s), 2 " 5 these being elements which, by appropriate connections to their input terminals, are each capable of realising a range of logic functions, unlike NOR and NAND gates which can realise only their designated function. It is a consideration of the use of such elements that we will here consider and contrast with the previously published work of Hellerman; we will in the following Sections use the designation univeral logic gate in preference to univeral logic module. 2 Review of univeral logic gates Universal logic gates are by definition circuits which are able to realise all possible functions of a given number of Paper T280C, first received 16th August and in revised form 5th October 1978 Dr. Hurst is with the School of Electrical Engineering, University of Bath, Claverton Down, Bath BA2 7AY, England and Mr. Pflaeger is with the Civil Aviation Authority, London input variables, depending on the pattern of input con- nections made to them. They are therefore 'hardwire programmable' devices. A uJ.g. capable of realising all possible functions of two input variables (x 1 ,x 2 ) may be termed a u.l.g.2; in general a u.l.g. capable of realising all functions of n independent input variables Xi,. .. , x n may be termed a u.l.g.n. The theoretical developments leading to the specification of such modules may be found documented." 1 ' 6 ' 7 For a u.l.g.2, the optimum design is some circuit with three input connections, to which are selectively connected logic signals taken from the set (0, l,X\, x 2 }, where JCI —x t or Xi and x 2 = x 2 or x 2 . For a u.l.g.3, five input connections per module are required, with inputs taken from the set {0, l,Xi,X2,Xz}, where x3 =x 3 or 3c 3 . One proposed circuit for a u.l.g.2 is given in Fig. I; 4 ' 5 the input con- nections required to realise all possible functions of f(xi,x 2 ), including degenerate functions, are detailed in Table 1. It may be noted that with this particular u.l.g.2 design it is possible to maintain a fixed input connection of x 2 on t, x 2 not being required for any 2-variable function. Both X\ and 3c 1, however, may have to be provided. ._l -f(Xi.Xj) ,. x,) Fig. 1 Proposed u.l.g.2 configuration a Logic schematic b Block schematic c Outline bipolar realisation It has been suggested that l.s.i. arrays of u.l.g. cells may be suitable for small-quantity customised applications, the design and fabrication of the hardwiring between cells being the dedication procedure for specific customer require- ments. 8 The viability of this approach in comparison with, say, p.l.a.'s 9 ' 10 involves: COMPUTERS AND DIGITAL TECHNIQUES, FEBRUARY 1979, Vol. 2, No. 1 13 0140-1335179/010013 + 08 $01-50/0
Transcript
Comparison of universal logic gates with NANDand NOR gates in the realisation of functions of
Abstract: This report furthers earlier work of, in particular, Hellerman, who catalogued the minimum numberof NOR and NAND elements necessary to realise all 22 logic functions of three independent binary inputvariables. Here we consider the use of universal logic elements rather than NOR and NAND, and derivecorresponding statistical and detailed information when the former are used for random logic purposes.
1 Introduction
In the design of combinatorial logic networks, it is usual toconsider the use of vertex logic elements, that is AND, OR,NAND and NOR gates, from which to synthesise therequired logic network. This remains the basis whether thedesigner is designing a monolithic i.e. layout or a hardwareassembly of, say, s.s.i. packages. The number of vertexelements required perforce depends on the complexity ofthe required network and on the efficiency of the designer,but a measure of the minimum number required for givensituations has been investigated by previous authors.
An early and still most relevant work is that ofHellerman,1 who catalogued the number of NOR andNAND gates necessary for the realisation of all possiblecombinatorial functions of three binary input variables.Hellerman exhaustively determined optimum NOR andNAND realisations of all 223 such functions, and hencedetermined the minimum number of such gates necessary.As may be expected, the minimum number of NOR gatesis on average the same as the minimum number of NANDgates when the same restrictions on fan-in etc. are observed,because both types of gate have similar logical discrimi-nation.
More recent work in digital logic, however, has suggestedalternative logic elements for combinatorial design to thevertex family of gates, the eventual justification of whichwill depend on viable compact circuit realisations in mono-lithic form. Among such newer elements are universal logicmodules (uJ.m.s) or univeral logic gates (u.l.g.s),2"5 thesebeing elements which, by appropriate connections to theirinput terminals, are each capable of realising a range oflogic functions, unlike NOR and NAND gates which canrealise only their designated function. It is a considerationof the use of such elements that we will here consider andcontrast with the previously published work of Hellerman;we will in the following Sections use the designationuniveral logic gate in preference to univeral logic module.
2 Review of univeral logic gates
Universal logic gates are by definition circuits which areable to realise all possible functions of a given number of
Paper T280C, first received 16th August and in revised form 5thOctober 1978Dr. Hurst is with the School of Electrical Engineering, Universityof Bath, Claverton Down, Bath BA2 7AY, England and Mr. Pflaegeris with the Civil Aviation Authority, London
input variables, depending on the pattern of input con-nections made to them. They are therefore 'hardwireprogrammable' devices. A uJ.g. capable of realising allpossible functions of two input variables (x1,x2) may betermed a u.l.g.2; in general a u.l.g. capable of realising allfunctions of n independent input variables Xi,. . . , xn maybe termed a u.l.g.n.
The theoretical developments leading to the specificationof such modules may be found documented."1'6'7 For au.l.g.2, the optimum design is some circuit with three inputconnections, to which are selectively connected logicsignals taken from the set (0, l,X\, x2 }, where JCI —xt orXi and x2 = x2 or x2. For a u.l.g.3, five input connectionsper module are required, with inputs taken from theset {0, l,Xi,X2,Xz}, where x3 = x 3 or 3c3. One proposedcircuit for a u.l.g.2 is given in Fig. I;4'5 the input con-nections required to realise all possible functions off(xi,x2), including degenerate functions, are detailed inTable 1. It may be noted that with this particular u.l.g.2design it is possible to maintain a fixed input connection ofx2 on t, x2 not being required for any 2-variable function.Both X\ and 3c 1, however, may have to be provided.
._l- f ( X i . X j )
,. x,)
Fig. 1 Proposed u.l.g.2 configuration
a Logic schematicb Block schematicc Outline bipolar realisation
It has been suggested that l.s.i. arrays of u.l.g. cells maybe suitable for small-quantity customised applications, thedesign and fabrication of the hardwiring between cells beingthe dedication procedure for specific customer require-ments.8 The viability of this approach in comparison with,say, p.l.a.'s9'10 involves:
COMPUTERS AND DIGITAL TECHNIQUES, FEBRUARY 1979, Vol. 2, No. 1 13
0140-1335179/010013 + 08 $01-50/0
Table 1 : Possible input programming of the u.l.g.2 of Fig. 1 to realise all functions of 2-input variables
Inputs All possible output functions f (x)l *2 f0 fl f2 fS U U U fl h U f10 fU fl2 '13 fU f!S
0011
0101
0000
1
0
dc
0001
1
X ,
x 2
0010
x t
X ,
x 2
0011
* i
0
dc
0100
1
X ,
x 2
0101
1
1
x 2
0110
X ,
1
x 2
0111
* i
X ,
x 2
1000
* i
X ,
*2
1001
* » .
1
*2
1010
0
1
x 2
1011
0
X ,
x 2
1100
X ,
0
dc
1101
* .
X ,
x 2
1110
0
X ,
x 2
1111
0
0
dc
r
s
t
Requiredu.l.m.2inputprogramming
dc = don't-care inputNote, alternative programmings possible
(a) the efficiency of the u.l.g. cell design in terms ofrequired silicon area and the overall cell packing density
(b) the number of u.l.g. cells necessary for typical appli-cations in comparison with alternative logic gates.The first clause (a) is the province of the integrated-circuitdesigner, and precise details will perforce vary whetherbipolar or m.o.s. realisations are being considered. Thesecond clause (b), however, is one which is relevant tothe following investigation, where we consider the numberof u.l.g.s necessary for a given range of functions incomparison with previously published NOR and NANDstatistics. The increased logical power of the u.l.g. incomparison with simple vertex gates should mean areduction in the average number of u.l.g.s necessary forgiven applications in comparison with vertex realisations.
3 Preliminary considerations of u.l.g. size
There are basic problems in deciding which size of u.l.g.cell shall be adopted for standardisation purposes to ensureoverall optimisation of silicon area and propagation speeds.This remains to be quantified, but the following con-siderations arise:
(i) The circuit complexity, and hence silicon area,of a uJ.g.3 is considerably greater than a uJ.g.2;further increase to u.l.g.4 will require a corresponding(exponential?) increase in silicon area.
(ii)The larger the standard u.l.g. adopted, the morewasteful it will be when under-utilised; the extreme case iswhere the uJ.g. has to be used as a simple inverter gate,which is clearly more wasteful if u.l.g.3s or u.l.g.4s etc.rather than u.l.g.2s are present.
(iii) Counter to (ii), however, a combinatorial functionof three inputs may require, say, three u.l.g.2s for itsrealisation compared with one u.l.g.3.Preliminary considerations of typical requirements indicatethat u.l.g.4 cells would be too large as a standard module.The optimum choice must be between the u.l.g.2 and theu.l.g.3. Further work may suggest that some form ofadditional or programmable input or output inversionfacility on the uJ.g. cell may be advantageous to eliminatethe necessity for ever having to generate separately acomplement signal with a separate u.l.g. cell.
However, for the purpose of this exercise we adopt theu.l.g.2 cell of Fig. 1 as the standard. We will quantify thenumbers of such cells necessary for the realisation of allpossible combinatorial functions of three variables andcontrast our results with those of Hellerman, the latterusing 3-input NAND and NOR cells for the same area ofconsideration. Like Hellerman, we shall assume comple-
ments of the input variables are not available and have tobe generated when necessary.
4 Function classification and u.l.g.2 configurationclassification
The 256 different functions of three independent binaryinput variables may be classified within 80 equivalent classfunctions, the full 256 functions being merely inputconnection permutations on this class.1' u Hence, it is onlynecessary to consider the realisation of the representativefunctions.
To identify these 80 representative functions and thefull 256 possible functions, we will retain the function-number classification system of Hellerman, which brieflyis as follows.
Take the truthtable for any given function f(x1,x2,X3),see example in Table 2(a). Now express the minterm valuesof the function in 3-digit octal form, as shown in Table2(b). The number classification for the function is nowthe decimal equivalent of this 3-digit octal number, whichfor the example tabulated is 346. Clearly, such a numberclassification for functions of three variables has a rangefrom 0 (00,000,000) to 377 (11, 111, 111), with numberssuch as 188 never occurring. The full listing of the 256functions of n = 3 and their relationships to the 80 repre-sentative functions will be found fully documented inHellerman and elsewhere,1 and therefore we need notconsider this aspect here.
The connection permutations to the u.l.g.2 cell and theresulting input/output function also require an identifi-cation format. This will consist of a simple crossreferencetabulation, as fully detailed in Table 3. The circuit schematicTable 2: Decimal number classification system, function 346
illustrated
MintermPi
PoPi
PaPsPA
PsPePi
Pi Pt
1 1
* i
00001111
Ps
1
Inputs*2
00110011
a
PA P3
0 0
* 3
01010101
p 2
1
Outputfix)
01100111
P. Po
1 0
a Conventional truthtableb Minterm function values in octal order
14 COMPUTERS AND DIGITAL TECHNIQUES, FEBRUARY 1979, Vol. 2, No. 1
of Fig. 1(7?) with a number '14' included in the schematicrectangle will therefore indicate that the u.l.g.2 should behardwired as shown in Table 3 to realise the functionf(x) = X( + Xj.
Table 3: Function number identification for the u.l.g.2 of Fig. 1
U.L.G. functionnumber
12345678
9
1011
12
13
14
15
16
17
U.L.G.r
10xixi10xixi
1
0*ixi1
0xi
*ixi
inputss
00001111
xixixixi
xixixixixi
t
dcdcdcdcxj
Xjxj
Xj
Xj
Xj
Xj
Xj
Xj
Xj
xj
*k
Resulting outputfunction f(x)
01*ixiXJxixi ffi xjxi ® xjXiXj, =
XiXj, =X^j, =
XiXj, =
X^j, =
XiXj, =x!x7- =XiXj, =
(x, ffi xji
(Xf + Xj)
Xf + Xj( V * -4- Y '\
Xi + Xj
(X,- + Xj)
X- + X-x, -r Xjxi + xj(X,- + Xj)
**>
5 Synthesis of f(x i , x 2 , x 3 ) using u.l.g.2 cells
Of the 80 representative functions of three variables, twelveare functions of two or fewer variables.1 Each of theseclearly may be realised by u.l.g.2 cells as already tabulatedin Table 1. With the remaining 68 functions of preciselythree variables, fully exhaustive synthesis of all possibleways of synthesising each representative function usingu.l.g.2 cells, to determine the minimum realisation, has notbeen made.* However, the designs compiled below arebased on both Reed-Muller expansions,6 see Appendix 10,and also on symmetry and spectral-translation consider-ations4' 6> 12 and it is therefore considered that the resultsare near if not minimum.
The main results are given in Table 4, together with thepreviously published NOR and NAND results of Hellerman.The numbers given in parentheses are the appropriateresults on each line multiplied by the number of functionsin each classification. When finally totalled, these numbersgive the total number of cells etc. required to realise allpossible 256 different functions of three variables, andhence the average values per function. Appendix 10illustrates the u.l.g.2 circuit realisations which form thebasis of this enumeration.
The principal results which are given by Table 4 are asfollows:
(a) The average number of cells or gates required for therealisation of a given function of three or fewer variables is
Hence, on average, it requires only 61% of the number ofuj.g.2 cells compared with the required number of 3-inputNOR or NAND cells.
(b) The average number of levels in cascade for functionsof < three input variables is
[ul.g. realisation = 537/256 = 2-09 cells in cascade
*It may be appreciated that many logically equivalent realisationsexist for any given function. Hellerman exhaustively investigated theNOR and NAND realisations, but the flexibility of the u.l.g. cellincreases the possibility of several 'good' solutions being available
NOR and NAND realisations = 770/256 = 3-01 gates incascade
Note that if some alternative u.l.g.2 cell to that of Fig. 1had been chosen for this analysis, the u.l.g. realisations forspecific functions would differ from those shown, but theaverage results would be the same.
If the number of uJ.g. cells used soley as inverters istotalled, it will be found to be 93 out of the total of680 cells; that is, some 14% of u.l.g. cells are under-utilisedto provide this complementation duty. The prior availabilityof both true and complemented xt inputs for networksynthesis, therefore, is clearly advantageous.
Finally, it may be observed from the detailed networkrealisations given in Appendix 10 that no crossovers of anyintercell connections are necessary. This is a useful bonusshould arrays of such cells be considered, a feature whichdoes not hold completely in minimum NOR and NANDrealisations,1 in spite of the unrestricted interchangeabilityof the input connections to NOR and NAND gates.
6 Implications of these results
It has previously been suggested that arrays of u.l.g. cellsmay provide a means of providing small-production-quantityi.c.s to meet specific customer requirements, the cell arraybeing a standard production item with the final-stage metal-isation on the chip being the customer dedication. Suchdedication by metalisation ('hardwire programming') maybe considered as possibly preferable to the electricalprogramming of p.r.o.m.- and p.l.a-type structures,4'9> l0> 13
as the full reliability of standard i.e. fabrication is main-tained in the former approach. Further, sequential networksmay readily be incorporated.
Existing examples where l.s.i. wafers completely fabri-cated up to the metalisation stage are used for customrequirements may be found in published literature.14"17 Aslightly modified approach is for the i.e. manufacturerto have a small library of standard cells which are thenlaid down and interconnected for a particular customerdedication,18 but this does not give a standard productionwafer up to the metalisation stage. These examples mayinvolve some internal cell-metalisation requirements,14
whereas others are true intercell metalisation only. Internalcell metalisation is clearly demanding on silicon area, andtherefore to be avoided if possible, which means that astandard cell should be as logically powerful and versatileas possible.
The 3-input u.l.g.2 cell has been shown by the aboveresults to be readily capable of realising random logicrequirements with a lower cell count than that with 3-inputNOR or NAND gates. It has also been previously shownthat the cell may be used in a bistable mode for sequentialapplications by means of a simple feedback connection,8
and hence the viability of this cell as a standard cell forgeneral-purpose digital use is strongly indicated. In passing,it may be noted that the 'JK gate' of Oberman19 is merelyanother possible variant of the uj.g.2 cell, as may beconfirmed by comparing Oberman's 'latch circuits' with thefull rangeLof uJ.g.2 circuits catalogued elsewhere.s
Thus, for simple storage purposes, it is possible to useone u.l.g.2 cell. If NOR and NAND gates are used instead,then at least two gates are necessary to provide bistableaction, i.e. a 2:1 ratio between the numbers necessary. Forcombinatorial purposes, Section 5 has shown that the NORand NAND against u.l.g.2 count, is slightly closer, i.e. a
COMPUTERS AND DIGITAL TECHNIQUES, FEBRUARY 1979, Vol. 2, No. 1 15
Table 4: Statistics of the number of u.l.g.2 cells and the number of 3-input NOR and NAND gates required in realisation of all combinatorialfunctions of up to three input variables
16 COMPUTERS AND DIGITAL TECHNIQUES, FEBRUARY 1979, Vol. 2, No. I
Table 4: continued
Octal functionclassificationnumber
352353356*357376377*
Totals
Number offunctions in eachclassification
333311
256
Number of cells/gates required
u.l.g.2
2(6)3(9)2(6)3(9)4(4)0(0)
(683)
NOR
3(9)4(12)2(6)3(9)2(2)0(0)
(1124)
NAND
3(9)6(18)3(9)3(9)2(2)0(0)
(1118)
Number of levels in realisation (cells/gates in cascade)
u.l.g.2
2(6)2(6)2(6)2(6)3(3)0(0)
(537)
NOR
2(6)3(9)2(6)3(9)2(2)0(0)
(770)
NAND
2(6)3(9)2(6)2(6)2(2)0(0)
(770)
• = functions of fewer than three input variables.
100:61 ratio. Hence, if the monolithic design of a u.l.g.2cell can be achieved with:
(a) a silicon area not appreciably exceeding that of a3-input NOR or NAND gate, including the necessary3-input/l-output pads and
(b) a propagation speed not appreciably exceeding thatof a 3-input NOR or NAND gatethen the adoption of the u.l.g. cell as a standard buildingblock in some monolithic array structure would yieldimmediate advantages for the custom-design market, inboth silicon area and operating speed. Clearly, detailedmonothic circuit design is necessary to fully quantifythese factors, but the figures given in Section 5 set a break-even target for u.l.g.2 cell designs. It should also be appre-ciated that a reduction in the number of necessary u.l.g.2cells compared with 3-input NOR and NAND gates alsocorrespondingly reduces the amount of intercell metal-isation necessary, which will have a further profound effecton overall chip area.
7 Conclusions
Although the investigation reported herewith confirms thegeneral viability of the u.l.g.2 cell as a standard buildingblock, there remains the possibility of a u.l.g.3 cell beingequally viable, or indeed preferably. One possible u.l.g.3cell has been disclosed as shown in Fig. 2, which from theabove results may show a silicon area advantage if itslayout did not exceed, say, twice the area of a u.l.g.2 cell,including input and output pads. The 4-variable cell of
f(x i .x , .x k )
—*t —•f(xi,Xj,xk)
»f(Xi.Xj,Xk)
Fig. 2 Proposed u.l.g.3 circuit of Edwards
a Logic schematicb Block schematicc Outline bipolar realisation
Gaskill et al.,16 which was exhaustively investigated andwell documented, appears to be excessively large to adoptas a standard cell in an array structure; also, its 'universal1
specification was not based upon the same theoreticalbases4"7 as the.u.l.g.2 and u.l.g.3 cells considered herewith.
Hence, although the u.l.g.2 cell already appears as aworthy candidate for standardisation purposes and adop-tion by i.e. manufacturers, further research is desirable toadd to the data reported herewith, to fully determine theoptimum size and specification of u.l.g. standard cells forcustom-design purposes.
8 Acknowledgments
The analysis of the 80 classified functions of 3-inputvariables and their realisation with u.l.g.2 cells formed partof a final-year Honours Degree project of the School ofElectrical Engineering, University of Bath, Project Report67/78 refers.
9 References
1 HELLERMAN, L.: 'A catalogue of three-variable Or-lnvert andAnd-Invert logic circuits', IEEE Trans., 1963, EC-12, pp. 198 -223
2 HSIEH, E.P., TAN, C.J.. and NEWBORN, M.N.: 'Uniformmodular realisation of sequential machines'. Proceedings 1968A.C.M. Conference, 1968, pp. 613-621
3 MUZIO, J.C.: 'Particular universal function generator', Electron.Lett., 1975, 11, p. 429
4 MURUGESAN, S.: 'Universal logic gate and its applications',Int. J. Electron., 1977, 42, pp. 55-63
5 HURST, S.L.: 'Logical processing of digital signals' (Crane-Russak, N.Y. and Edward Arnold, London, 1978)
6 EDWARDS, C.R., and HURST, S.L.: 'An analysis of universallogic modules',Int. J. Electron., 1976, 41, pp. 625-628
7 EDWARDS, C.R.: 'A special class of universal logic ga (ULG)and their evaluation under the Walsh transform', ibid., 1978, 44,pp. 49-59
8 HURST, S.L.: 'Universal logic element, or 'superfunction'arrays', Microelectronics, 1977, 8, pp. 13-19
9 HEMEL, A.: 'The PLA: a different kind of ROM', Electron.Des., 1976,24, pp. 78-87
10 National Semiconductor Corporation: 'How to design withprogrammable logic arrays' (Application Note A.N. 89, 1973)
11 HARRISON, M.A.: 'The number of equivalence classes ofBoolean functions, under groups containing negation', Universityof Michigan Technical Note 04879-4-7, June 1962
12 EDWARDS, C.R.: 'The design of easily tested circuits usingmapping and spectral techniques', Radio & Electron. Eng., 1977,47, pp. 321-342
13 HAMPEL, D., BARRON, R.L., and CLEVELAND, D.: 'Designand application of electronically programmable LSI arrays',AFIPS Conference Proceedings, May 1975, California, pp. 867-876
14 FERRANTI Ltd.: 'The uncommitted logic array - a CDIstandard product' (Publication ESB620274, Ferranti Ltd, UK,1974)
COMPUTERS AND DIGITAL TECHNIQUES, FEBRUARY 1979, Vol. 2, No. I 17
15 MARVIN, C.E., and WALKER, R.M.: 'Customising by inter-connection', Electron., February 20, 1967, pp. 157-167
19 OBERMAN, R.M.M.: 'The JK gate', IEEE Trans., 1976, C-25,pp. 1156-1159
10 Appendix
The following shows minimal circuit realisations for all 68classified functions of three input variables using the u.l.g.2cell of Fig. 1. These results may be compared with Heller-man's published minimum NOR and NAND realisations forthe same class of funtions. The u.l.g.2 realisations for the12 classified functions of fewer than three input variablesare trivial. Notice the following points:
(a) The function identification number is the octalnumbering system defined in the text, e.g. function 251is the function with the output truthtable Pi,Pe,Ps,P^,Pz, Pi, P\ =1011011001 ; the uj.g. inputs are alwaysdrawn r, s, t downwards, as in Fig. 1(6).
(b) No complement of any input variable is assumed tobe available.
(c) Alternative realisations for many functions areavailable; when considering realisations in a specific i.e.technology or cell layout format then some criteria foroptimisation may be present; for example, minimisation ormaximisation of the number of 0 or 1 logic signals fed tou.l.g. inputs.
(d) Because the uJ.g. 2 cell we are employing is derivedfrom the Reed-Muller expansion for any given function,6
the expansion for three variables being:
where rl,sl,r2,s2e{0,l,x~i,x1}, there follows a standardnetwork topology for 3-variable functions as shown inFig. 3. Thus, allowing a further u.l.g.2 cell to generate xx
when necessary, for any 3-variable function / ( x i , x 2 , x 3 )the maximum necessary number of u.l.g.2 cells is four andthe maximum number of cells in cascade is three. Note,however, that although this topology is always possible forall functions of three variables, some functions may bemore minimally realised; for example, see the resultsfollowing.
(e) Finally, each of the circuits below could be realisedwith one u.l.g.3 cell, with at more three inverters.
u.l.g.2
•f(x1,x2.x3)
u.t.g.2
Fig. 3 Network topology for 3-variable function
r
s
t11 •i >
r
t
X 3 — '
rs
t
u.l.g.2
Function No. ULG Realisation Function No. ULG Realisation Function No. ULG Realisation
10.
\<o.
2.6.
2?.
30.
31.
32.
33.
36.
18 COMPUTERS AND DIGITAL TECHNIQUES, FEBRUARY 1979, Vol. 2, No. 1
76
I SO.
COMPUTERS AND DIGITAL TECHNIQUES, FEBR UAR Y 19 79, lfol 2, No. '1
251.
255
274.
275
15 276
350
x2_|-j i i r nXI—1 1 X* 1 I
351.
352 15 U*-
353
357.
S. L. Hurst began his professionaltraining in electrical engineering at theBritish-Thomson-Houston Co. (nowGEC) Ltd., Rugby, England, 1945-1950. Then he was for 11 years withWestinghouse Brake & Signal Co.,Chippenham, England. Since 1961, hehas been employed in higher education,with teaching committments inelectronics and research interests,particularly in digital logic. M.Sc.(Eng.)
of London University on ternary logic synthesis research,Ph.D. of London University on threshold logic synthesisresearch.
N. P. Pflaeger was born in Dumfries,Scotland on the 27th December 1954.He received his higher education atWollerton College of Further Educationand at the University of Bath, gradu-ating in 1977 with a first-class honoursB.Sc. degree in electrical and electronicengineering. His industrial training wasundertaken with the Civil AviationAuthority, London, for whom he isnow working on traffic-controlproblems.
Philip Willis received a B.Sc. degreefrom Sussex University in 1971 andthe M.Sc. degree in Computer Sciencefrom Essex University in 1972. Hethen joined International ComputersLimited at Stevenage. He returnedto the University of Sussex in 1973to research into real-time computergraphics, completing a D.Phil. in 1975.
Prof. Richard Grimsdale, after gradu-ating at Manchester University, joinedthe staff and was engaged on a varietyof research topics including the pro-duction of one of the first transistorcomputers and the read-only memoryfor Atlas. After a period in industry,he was appointed to his present post atthe University of Sussex where hiscurrent research interests are multi-microprocessor systems and computerimage generation.
Aris Hadjiaslanis was born in Athens,Greece in September 1953.He receiveda B.Sc. degree in electronics from theUniversity of Sussex in 1974 andwent on to get a DJPhil. in computerengineering at the same university inJune 1978. Since June 1978, Dr.Hadjiaslanis has been employed bythe University of Sussex as a researchfellow.
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