Compiler-Directed instruction cache Compiler-Directed instruction cache leakage optimizations leakage optimizations
Discussed byDiscussed by Raid AyoubRaid Ayoub
CSE DCSE DEPARTMENTEPARTMENT
Outline
• Power consumption in CMOS• Motivation• Handling the problem at the compiler level
Breaking the at the loop level Examining various strategies for turnoff Loop level optimizations Experimental results
• Summary
Leakage power in CMOS• Leakage Power: power consumed due to subthreshold leakage current • Leakage power: 30% of L1 power and 70% of L2 power for 0.13u• Reducing leakage power improves battery life times and reliability• Leakage power will be increasingly significant
(on)
(on) (off)
(off)
SRAM cell
Handling leakage power at the circuit level: Putting cell(s) in low leakage mode• State destroying mode (Vdd close to 0)
Reduces static power dramatically Destroys state Incurs time and power overhead during the switch to active mode
• State preserving mode (lowering Vdd) Reduces static power Preserves stored data Incurs time and power overhead during the switch to active mode
Vdd
Handling Leakage power of caches
• Challenges in managing leakage-control modes of cache:• Distill at run time the inactive instructions and place them in
leakage mode• Potential for performance degradation: Putting active instructions
in leakage mode• Hardware overhead: power and latency
• Previous approaches: Utilize architectural-level techniques• Utilize hardware monitoring to manage the leakage modes of the
cache• Limitations:
Hardware complexity Power savings could be moderate
Proposed approach Utilize compiler based technique• Identify the last use of instructions and place them in leakage mode• Special instructions are used to place cache lines into leakage modes
Goals:• Simplifies hardware support• Improve power savings
Two compiler-based strategies are studied:• Conservative• Optimistic
Two leakage savings mechanisms are utilized• State destroying and state preserving mode
LoopBody-I
LoopBody-II
LoopBody-III
Compiler strategies
• Turn off instructions are applied at the loop level granularity
Conservative: • the lines for loop body-I can only be turned off when
exiting loop III Less effective when loop III encloses the majority of
instructions in the code
Optimistic: • the lines for loop body-I can be turned off every time
exiting loop I (Assume loop II take long time)
When to turn off a cache line?When to turn off a cache line?
Conservative Conservative strategystrategy
when sure its content is deadwhen sure its content is dead
Optimistic Optimistic strategystrategy
when incur a large gap in when incur a large gap in cyclescycles
Examining various strategies
ConservativeConservative OptimisticOptimistic
State-destroyingState-destroying Strategy 1Strategy 1 Strategy 2Strategy 2
State-preservingState-preserving Strategy 4Strategy 4 Strategy 3Strategy 3
Experimental results show that• Strategy 3 is the most successful one• Strategy 3 is competitive to other proposed schemes• Strategies 1 and 2 are less successful due to the overhead of
caches misses imposed by state destroying
Hybrid strategyPolicy: When exiting the loop:
(1) if the loop will be visited again, put the cache lines in leakage mode (state preserving)
(2) If the loop is dead, turn off cache lines (state-destroying) Hybrid strategy performed somewhat similar to strategy 3
Compiler optimizationsLoop Distribution Fewer cache lines need to be
activated at any given time Potential in reducing conflicts in
L2 cache and improve performance
Possible destroy in data cache locality
LoopBody-I
LoopBody-II
LoopBody-I
LoopBody-II
Header
Body-I
Body-II
Header
Body-I
Body-II
Header
Loop distributionLoop fusion
Loop Fusion Potential in enhancing data
locality Increase number of active lines at
a given time Potential in reducing the time
duration for the active lines
Compiler optimizations
Impact of various optimizations on leakage energy on adi
• Experimental results show that Loop distribution is the most successful optimization in reducing leakage energy
Summary
Proposed approach delivers competitive energy Proposed approach delivers competitive energy savings and energy-delay to other schemessavings and energy-delay to other schemes
Applying loop optimizations improves energy savingsApplying loop optimizations improves energy savings
Hardware support is simpleHardware support is simple
Adding explicit turn-off instructions impose Adding explicit turn-off instructions impose modifications into ISAmodifications into ISA
