Component Modeling and Three-Phase Power-Flow Analysis for ... · Component Modeling and...

Component Modeling and Three-Phase Power-Flow

Analysis for Active Distribution Systems

by

Mohamed Zakaria Kamh

A thesis submitted in conformity with the requirementsfor the degree of Doctor of Philosophy

Graduate Department of Electrical and Computer EngineeringUniversity of Toronto

Copyright © 2011 by Mohamed Zakaria Kamh

Abstract

Component Modeling and Three-Phase Power-Flow Analysis for Active Distribution

Systems

Mohamed Zakaria Kamh

Doctor of Philosophy

Graduate Department of Electrical and Computer Engineering

University of Toronto

2011

This thesis presents a novel, fast, and accurate 3ϕ steady-state power-flow analysis (PFA)

tool for the real-time operation of the active distribution systems, also known as the active

distribution networks (ADN), in the grid-tied and islanded operating modes. Three-

phase power-flow models of loads, transformers, and multi-phase power lines and laterals

are provided. This thesis also presents novel steady-state, fundamental-frequency, power-

flow models of voltage-sourced converter (VSC)-based distributed energy resource (DER)

units. The proposed models address a wide array of DER units, i.e., (i) variable-speed

wind-driven doubly-fed asynchronous generator-based and (ii) single/three-phase VSC-

coupled DER units. In addition, a computationally-efficient technique is proposed and

implemented to impose the operating constraints of the VSC and the host DER unit

within the context of the developed PFA tool. Novel closed forms for updating the

corresponding VSC power and voltage reference set-points are proposed to guarantee that

the power-flow solution fully complies with the VSC constraints. All the proposed DER

models represent (i) the salient VSC control strategies and objectives under balanced

and unbalanced power-flow scenarios and (ii) all the operating limits and constraints of

the VSC and its host DER unit.

Also, the slack bus concept is revisited, associated with the PFA, where a 3ϕ dis-

tributed slack bus (DSB) model is proposed for the PFA and operation of islanded ADNs.

Distributing the real and reactive slack power among several DER units is essential to

provide a realistic power-flow approach for ADNs in the absence of the utility bus. The

proposed DSB model is integrated with the developed 3ϕ PFA tool to form a complete

ADN PFA package.

The new PFA tool, including the proposed DER and DSB models, is tested using sev-

eral benchmark networks of different sizes, topologies, and parameters. Many case stud-

ies, encompassing a wide spectrum of DER control specifications and operating modes,

ii

are conducted to demonstrate (i) the numerical accuracy of the proposed models of the

DER units and their operating constraints, (ii) the effectiveness of the proposed DSB

model for the islanded ADN PFA, and (iii) the computational efficiency of the integrated

PFA software tool irrespective of the network topology and parameters.

iii

Dedication

To my parents, my wife, and my motherland Egypt..

iv

Acknowledgements

First, I would like to thank my Creator, for giving me the wisdom and foundation to

accomplish this thesis.

I am deeply indebted to my supervisor, Prof. Reza Iravani, for his continuous aca-

demic advice, constant encouragement, endless patience, and priceless guidance and sup-

port throughout this work. I am really grateful to him, not only for contributing many

valuable suggestions and improvements to this thesis, but most importantly for training

me to be an independent researcher, with the ability to identify interesting and important

research problems and to generate frameworks to solve them. Moreover, I am grateful to

him for exposing me to collaboration with different industrial and organizational institu-

tions. I feel honored to have been given the opportunity to work under his supervision.

I would also like to acknowledge my Ph.D. external examiner, Prof. Liuchen Chang,

and the esteemed internal committee members: Prof. Peter Lehn, Prof. Aleksandar

Prodic, and Prof. Zeb Tate, for the valuable input they have given into my thesis. My

appreciation also goes to my colleagues, particularly Ali Mehrizi-Sani and Amir Etemadi,

and the Faculty members in the Energy Systems group, for the friendly academic atmo-

sphere, the useful discussions, and their encouragement. I am particularly indebted to

Dr. Milan Graovac and Mr. Xiaoling Wang, from the Center for Applied Power Electron-

ics (CAPE) at the University of Toronto, for their priceless help and valuable feedback

and comments throughout my Ph.D. project.

Next, I would like to pay my humble respect and the deepest thanks from my heart

to my mother, Prof. Sanaa Kamh, my father, General Zakaria Kamh, and my lovely

sisters, Mai and Yasmin, for their endless support, love, patience, and encouragement. I

am extremely grateful to my parents for giving me the best education, the warmest care,

the righteous upbringing and the best in everything.

My final warmest thanks from my heart go to my precious wife, Angie Eldamak, who

really changed my life to the best in everything, and supported me throughout this long

Ph.D. path. She always lightened my bad days and perfected my good ones. No words

can express my gratitude and appreciation to her, and my in-laws, for the kind support

and tremendous care. Angie will always be my source of inspiration, the twin of my soul,

and the love of my life.

Mohamed Z. Kamh

July 2011

v

Contents

1 Introduction 1

1.1 Active Distribution Networks . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.2 Enabling Technologies . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1.3 ADN Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1.4 Smart Energy Management System . . . . . . . . . . . . . . . . . 4

1.2 Statement of the Problem and Thesis Motivations . . . . . . . . . . . . . 4

1.2.1 Lack of Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2.2 Lack of DER Models . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 Thesis Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4.1 Modeling Methodology . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4.2 Validation Methodology . . . . . . . . . . . . . . . . . . . . . . . 8

1.5 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.5.1 Chapter 2: A Three-Phase Sequence-Frame Power-Flow Solver

(SFPS) Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.5.2 Chapter 3: Steady-State Models of Three-Phase VSC-Coupled DER

Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.5.3 Chapters 4 and 5: Steady-State Models of Type-3 WTG-Based

DER Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5.4 Chapter 6: Steady-State Models of Single-Phase VSC-Coupled

DER Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5.5 Chapter 7: Three-Phase Distributed Real- and Reactive-Slack Bus

Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.5.6 Chapter 8: Conclusions . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Sequence-Frame Power-Flow Solver (SFPS) 12

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

vi

2.2 Three-Phase Power-Flow Analysis: Critical Review . . . . . . . . . . . . 12

2.2.1 Three-Phase Power-Flow Algorithms for Radial Network Topology 13

2.2.1.1 Backward-Forward Sweep Algorithm (BFSA) . . . . . . 13

2.2.1.2 Compensation-Based Algorithms . . . . . . . . . . . . . 13

2.2.2 Three-Phase Power-Flow Algorithms for General Network Topologies 14

2.2.2.1 Newton-Rapshon Method . . . . . . . . . . . . . . . . . 14

2.2.2.2 Gauss-Seidel Methods . . . . . . . . . . . . . . . . . . . 15

2.3 Sequence-Frame Versus Phase-Frame in Three-Phase Power-Flow Analysis 16

2.4 Sequence-Frame Models of Basic ADN Components . . . . . . . . . . . . 17

2.4.1 Distributed Generation . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.2 Unbalanced Three-phase Distribution Line . . . . . . . . . . . . . 19

2.4.3 Three-phase Power Transformers . . . . . . . . . . . . . . . . . . 22

2.4.4 Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4.4.1 Constant Power and Current Loads . . . . . . . . . . . . 22

2.4.4.2 Constant Impedance Loads . . . . . . . . . . . . . . . . 23

2.5 The SFPS Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.6 Summary and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3 Power-Flow Model of 3-ϕ VSC-Coupled DER Units 32

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2 Model Scope and Assumptions . . . . . . . . . . . . . . . . . . . . . . . . 33

3.3 Proposed Sequence-Frame Model of 3ϕ VSC-Coupled DER Units . . . . 34

3.3.1 Interface VSC Positive-Sequence Model . . . . . . . . . . . . . . . 35

3.3.2 Interface VSC Negative- and Zero-Sequence Models . . . . . . . . 36

3.3.2.1 Three-Wire VSC Configuration . . . . . . . . . . . . . . 36

3.3.2.2 Four-Wire VSC Configuration . . . . . . . . . . . . . . . 38

3.4 Implementation of the VSC Unified Model in the SFPS . . . . . . . . . . 38

3.4.1 Accommodating the VSC-Coupled DER Model in the SFPS . . . 38

3.4.2 Calculating the Internal Parameters of the Interface VSC . . . . . 39

3.4.3 Mitigating the VSC Operating Limits Violation . . . . . . . . . . 41

3.4.3.1 Mitigating the Phase Current Limit Violation . . . . . . 41

3.4.3.2 Mitigating the Reactive Power Limit Violation . . . . . 41

3.4.3.3 Mitigating the Phase Modulation Index Limit Violation 42

3.4.3.4 Updating the Interface VSC Reference Set-Points . . . . 42

3.5 Sequential-SFPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.6 3ϕ VSC Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . . 44

vii

3.6.0.5 Case-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.6.0.6 Case-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.6.0.7 Case-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.6.1 Case-4: Sequential-SFPS Validation . . . . . . . . . . . . . . . . . 49

3.7 Computation Efficiency of the Proposed Sequential-SFPS . . . . . . . . . 49


4 Power-Flow Model of Type-3 WTG DER Units 53

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.2 Classification of Wind Turbine Generators . . . . . . . . . . . . . . . . . 54

4.2.1 Type-1 WTGU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.2.2 Type-2 WTGU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.2.3 Type-3 WTGU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.2.4 Type-4 WTGU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.3 Power-Flow Models of Type-3 DER Units: Review . . . . . . . . . . . . . 56

4.4 The Scope of the Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.5 Proposed Sequence-Frame Model of A Type-3 DER Unit . . . . . . . . . 58

4.5.1 Model Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.5.2 Positive-Sequence Model of Type-3 DER Unit . . . . . . . . . . . 58

4.5.2.1 PV mode of operation . . . . . . . . . . . . . . . . . . . 59

4.5.2.2 PQ mode of operation . . . . . . . . . . . . . . . . . . . 61

4.5.3 Negative-Sequence Model of Type-3 DER Unit . . . . . . . . . . . 61

4.5.4 Equivalent Negative-Sequence Model of Type-3 DER Unit . . . . 61

4.6 Evaluating Type-3 Negative-Sequence Model Parameters . . . . . . . . . 62

4.6.1 Case A: Idle Secondary Control of Type-3 Unit . . . . . . . . . . 63

4.6.2 Case B: Balancing Rotor Currents . . . . . . . . . . . . . . . . . . 63

4.6.3 Case C: Balancing Stator Currents . . . . . . . . . . . . . . . . . 63

4.6.3.1 Case C-1: Balancing Stator Currents Via RSC . . . . . . 63

4.6.3.2 Case C-2: Balancing Stator Currents Via GSC . . . . . 64

4.6.4 Case D: Mitigating Stator Real Power Double-Frequency Component 65

4.6.5 Case E: Mitigating Double-Frequency Electromagnetic Torque (Power)

Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.6.6 Case F: Coordinated Control of GSC and RSC . . . . . . . . . . . 66

4.7 Type-3 DER Internal Parameters Calculation . . . . . . . . . . . . . . . 67

4.7.1 Calculating Positive-Sequence Internal Parameters . . . . . . . . . 68

4.7.1.1 GSC Positive-Sequence Modulation Index . . . . . . . . 68

viii

4.7.1.2 GSC Positive-Sequence Current . . . . . . . . . . . . . . 69

4.7.1.3 RSC Positive-Sequence Modulation Index . . . . . . . . 69

4.7.1.4 Stator Positive-Sequence Current Calculation . . . . . . 70

4.7.2 Evaluating Negative-Sequence Internal Parameters . . . . . . . . 70

4.7.2.1 GSC Negative-Sequence Modulation Index . . . . . . . . 70

4.7.2.2 GSC Negative-Sequence Current . . . . . . . . . . . . . 70

4.7.2.3 RSC Negative-Sequence Modulation Index . . . . . . . . 71

4.7.2.4 Stator Negative-Sequence Current . . . . . . . . . . . . . 71

4.8 Implementing Type-3 Power-Flow Model . . . . . . . . . . . . . . . . . . 71

4.8.1 Accommodating the Type-3 DER Model in the SFPS . . . . . . . 71

4.8.2 Estimating Type-3 Maximum Operating Limits . . . . . . . . . . 71

4.8.2.1 Estimating the Maximum RSC Modulation Index . . . . 72

4.8.2.2 Estimating Maximum Stator Currents . . . . . . . . . . 72

4.8.2.3 Estimating Maximum GSC Currents . . . . . . . . . . . 72

4.8.3 DER Operational Limits . . . . . . . . . . . . . . . . . . . . . . . 73

4.8.3.1 Fulfilling GSC Positive-Sequence Modulation Index Limit 73

4.8.3.2 Fulfilling GSC Positive-Sequence Current Limit . . . . . 74

4.8.3.3 Fulfilling RSC Positive-Sequence Modulation Index Limit 74

4.8.3.4 Fulfilling Stator Positive-Sequence Current Limit . . . . 74

4.8.3.5 Updating Positive-Sequence Reference Set-Points . . . . 74

4.8.3.6 Fulfilling Negative-Sequence Operating Limits . . . . . . 75

4.8.4 Sequential SPFS . . . . . . . . . . . . . . . . . . . . . . . . . . . 75


5 Applications and Validation of Type-3 WTG DER Model 78

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.2 Type-3 DER Model Validation . . . . . . . . . . . . . . . . . . . . . . . . 78

5.2.1 Case-1: Inactive Negative-Sequence Controllers . . . . . . . . . . 80

5.2.2 Case-2: Balancing Rotor Current Via RSC . . . . . . . . . . . . . 80

5.2.3 Case-3: Balancing Stator Current Via GSC . . . . . . . . . . . . . 82

5.2.4 Case-4: Mitigating Double-Frequency Stator Power Oscillations . 82

5.2.5 Case-5: Mitigating Double-Frequency Torque Oscillations and Bal-

ancing GSC Currents . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.3 Case 6: Validating the Sequential-SFPS Feasibility . . . . . . . . . . . . 84

5.4 Application of the Sequential-SFPS to Benchmark Distribution Systems . 85

5.4.1 Case 7: CIGRE MV Distribution Network . . . . . . . . . . . . . 86

ix

5.4.2 Case 8: IEEE 34-Bus Test System . . . . . . . . . . . . . . . . . . 87

5.5 Convergence Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88


6 Power-Flow Model of 1ϕ VSC-Coupled DER Units 90

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.3 Topologies and Control Objectives of Single-Phase Interface VSC . . . . 91

6.4 Steady-State Model of Dual-Stage Single-Phase Interface VSC . . . . . . 92

6.4.1 Model Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6.4.2 Incorporating Single-Phase VSC-Coupled DER Units in Power Flow

Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.4.2.1 VSC Model Tailored for the Single-Phase BFSA . . . . . 93

6.4.2.2 VSC Model Tailored for the SFPS . . . . . . . . . . . . 94

6.5 Evaluating the Interface VSC Internal Parameters . . . . . . . . . . . . . 95

6.5.1 Calculating the VSC Phase Current . . . . . . . . . . . . . . . . . 95

6.5.2 Calculating the VSC Modulation Index . . . . . . . . . . . . . . . 96

6.6 Imposing the VSC Operational Limits . . . . . . . . . . . . . . . . . . . 97

6.6.1 Phase Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.6.2 Modulation Index Limit . . . . . . . . . . . . . . . . . . . . . . . 98

6.6.3 PC Bus Voltage Limit . . . . . . . . . . . . . . . . . . . . . . . . 99

6.6.4 Updating the VSC Reference Power Set-Points . . . . . . . . . . . 100

6.6.5 Sequential Power-Flow Algorithm . . . . . . . . . . . . . . . . . . 100

6.7 1ϕ VSC Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.7.1 Validating the Single-Phase Sequential BFSA . . . . . . . . . . . 100

6.7.1.1 Case-1: Maximum Phase Current Limit Violation . . . . 102

6.7.1.2 Case-2: Maximum Modulation Index Limit Violation . . 103

6.7.2 Validating the Three-Phase Sequential-SFPS . . . . . . . . . . . . 104

6.7.2.1 Case-3: Violating the Maximum PCC Voltage Limit . . 105

6.7.2.2 Case-4: No DER Units Connected to the Violating Bus . 108

6.7.3 Computational Efficiency of the Sequential Algorithms accommo-

dating the 1ϕ VSC-Coupled DER Model . . . . . . . . . . . . . . 109


7 Power Flow Analysis of Islanded ADNs 111

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

x

7.3 The Scope of the Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7.4 Proposed Distributed Slack Bus (DSB) Model . . . . . . . . . . . . . . . 113

7.4.1 Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7.4.2 Participation Factors . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.4.3 Distributed Slack Bus Model . . . . . . . . . . . . . . . . . . . . . 115

7.4.3.1 Real Power Balance Equation . . . . . . . . . . . . . . . 115

7.4.3.2 Reactive Power Balance Equation . . . . . . . . . . . . . 115

7.4.3.3 Super-PQ-Bus Equation . . . . . . . . . . . . . . . . . . 115

7.4.4 The Updating Equation . . . . . . . . . . . . . . . . . . . . . . . 116

7.4.5 DER Generation Limits . . . . . . . . . . . . . . . . . . . . . . . 117

7.5 Validations and Case Studies . . . . . . . . . . . . . . . . . . . . . . . . . 117

7.5.1 Assumption Validation . . . . . . . . . . . . . . . . . . . . . . . . 117

7.5.2 Impacts of Deploying the Proposed DSB Model . . . . . . . . . . 121

7.5.2.1 Reference Bus Power Output . . . . . . . . . . . . . . . 122

7.5.2.2 Real Power Losses . . . . . . . . . . . . . . . . . . . . . 123

7.5.2.3 Voltage Profile . . . . . . . . . . . . . . . . . . . . . . . 124

7.5.3 Imposing the DER Power Capacity Constraint . . . . . . . . . . . 124


8 Conclusions 127

8.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8.2 General Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8.3 Quantifiable Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

8.4 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

8.4.1 Major Contributions . . . . . . . . . . . . . . . . . . . . . . . . . 129

8.4.2 Other Contributions . . . . . . . . . . . . . . . . . . . . . . . . . 129

8.5 Directions for Future Research . . . . . . . . . . . . . . . . . . . . . . . . 129

Appendices 127

A Data for Test Systems 131

A.1 Six-Bus Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

A.2 Three-Phase CIGRE MV Test System . . . . . . . . . . . . . . . . . . . 131

A.3 CIGRE MV Single-Phase Radial Feeder . . . . . . . . . . . . . . . . . . 133

A.4 IEEE 34-Bus Test System . . . . . . . . . . . . . . . . . . . . . . . . . . 133

A.5 Modified IEEE 34-Bus Test System . . . . . . . . . . . . . . . . . . . . . 137

xi

B Steady-State Power-Flow Models of Distribution Power Lines 140

B.1 Three-Phase Power Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

B.2 Two-phase Power Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

C Steady-State Power-Flow Models of Electrical Loads 144

C.1 Constant Power Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

C.1.1 Four-Wire/Three-Wire Wye-Connected Loads . . . . . . . . . . . 144

C.1.2 Three-Wire Delta-Connected Loads . . . . . . . . . . . . . . . . . 145

C.2 Constant Current Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . 146



C.3 Constant Impendence Loads . . . . . . . . . . . . . . . . . . . . . . . . . 148



D Schematic Diagrams of the PSCAD/EMTDC Models 150

Bibliography 153

xii

List of Tables

2.1 Sequence-Frame, Fundamental-Frequency, Steady-State Model of A Three-

Phase Power Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1 VSC Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.2 Parameters of G1 and G2 of Fig. 3.6 (Sbase= 1000 kVA) . . . . . . . . . 45

3.3 Power-Flow Results of Case-1 . . . . . . . . . . . . . . . . . . . . . . . . 47




3.7 Comparison Between the Sequential and the Non-Sequential Power-Flow

Algorithms in Terms of the Total Number of Jacobean Matrix Evalua-

tions/Inversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.1 Parameters of the Type-3 Negative-Sequence Model For the Six Cases of

Section 4.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.1 Parameters of G2 of Fig. 5.1 (Sbase= 1000 kVA) . . . . . . . . . . . . . . 79






5.7 Load profile used in Section 5.3 (Vbase=13.8 kV, Sbase= 1 MVA) . . . . . 84

5.8 Power-Flow Results of Case-6: Operational Limits of G2 are Discarded . 85

5.9 Power-Flow Results of Case-6: Operational Limits of G2 are Imposed . . 86

6.1 Parameters of G1, G2, and G3 of Fig. 6.5 (Vbase = 7.2 kV and Sbase = 100

kVA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.2 Power-Flow Results of Case-1: Maximum Phase Current Limit is Discarded102

xiii

6.3 Case-1: Updated Real and Reactive Power Set Points of the three DER

units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.4 Power-Flow Results of Case-1: Maximum Phase Current Limit is Imposed 103

6.5 Power-Flow Results of Case-2: Maximum Modulation Index Limit is Dis-

carded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.6 Case-2: Updated Real and Reactive Power Set Points of the three DER

units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.7 Power-Flow Results of Case-2: Maximum Modulation Index Limit is Im-

posed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

6.8 Case-3: DER Phase Distribution* . . . . . . . . . . . . . . . . . . . . . . 106

6.9 Case-3: Three-Phase Voltage Profile Without Considering the Maximum

Bus Voltage Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6.10 Case-3: Updated Real and Reactive Power Set Points of the DER Units.

Sbase = 1 MVA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6.11 Case-3: Three-Phase Voltage Profile After Adjusting the DER Power Set

Points Using (6.22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6.12 Case-4: Three-Phase Voltage Profile Without Considering the Maximum

Bus Voltage Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6.13 Case-4: Three-Phase Voltage Profile After Adjusting the DER Power Set

Points Using (6.22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

6.14 Case-4: Updated Real and Reactive Power Set Points of the DER Units

at the Violating Busses. Sbase = 1 MVA. . . . . . . . . . . . . . . . . . . 109

A.1 Power Lines Phase-Frame Parameters (in pu) of the Study System of Fig.

A.1 (Vbase=13.8 kV, Sbase= 1000 kVA) . . . . . . . . . . . . . . . . . . . 132

A.2 Loads of the Study System of Fig. A.1 (Vbase=13.8 kV, Sbase= 1000 kVA) 132

A.3 Power Lines Phase-Frame Parameters (in ohms) of the Study System of

Fig. A.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

A.4 Loads (in kVA) of the Study System of Fig. A.2 . . . . . . . . . . . . . 134


A.6 Power Lines Phase-Frame Parameters of the Study System of Fig. A.4 . 136


xiv

List of Figures

1.1 Schematic diagram of an Active Distribution Network . . . . . . . . . . . 2

1.2 Schematic diagram of an ADN operating as a virtual power plant . . . . 4

1.3 DER Model Validation Methodology . . . . . . . . . . . . . . . . . . . . 8

1.4 Schematic diagram of the thesis layout . . . . . . . . . . . . . . . . . . . 9

2.1 Classification of three-phase PFA methods . . . . . . . . . . . . . . . . . 13

2.2 Sequence-frame, fundamental-frequency, steady-state model of a three-

phase directly connected synchronous generator for the SFPS: (a) the

positive-sequence model, (b) the negative-sequence model, (c) the zero-

sequence model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3 Equivalent π-model of a three-phase distribution line . . . . . . . . . . . 19

2.4 Decoupled sequence-frame, fundamental-frequency, steady-state model of

a three-phase distribution line: (a) the positive-sequence model, (b) the

negative-sequence model, (c) the zero-sequence model . . . . . . . . . . . 21

2.5 Schematic diagram of a constant power/current load connected to Bus-k 23

2.6 Decoupled sequence-frame, fundamental-frequency, steady-state model of

a constant power/current load . . . . . . . . . . . . . . . . . . . . . . . . 23

2.7 Model of a constant impedance load connected to Bus-k: (a) phase-frame

model, (b) sequence-frame model . . . . . . . . . . . . . . . . . . . . . . 24

2.8 Decoupled sequence-frame model of a constant power/current load . . . . 25

2.9 Flow chart of the SFPS algorithm . . . . . . . . . . . . . . . . . . . . . . 26

2.10 Zero-sequence blocking scenario: (a) phase-frame network, (b) zero-sequence

impedance diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.1 Schematic diagram of three-phase VSC-coupled DER unit . . . . . . . . 33

3.2 Proposed sequence-frame, fundamental-frequency, steady-state model of

a 3ϕ interface VSC, (a) positive-sequence model, (b) negative-sequence

model, (c) zero-sequence model . . . . . . . . . . . . . . . . . . . . . . . 34

3.3 Alternative VSC output filter configurations . . . . . . . . . . . . . . . . 37

xv

3.4 Equivalent sequence-frame circuits of a VSC-coupled DER unit . . . . . . 39

3.5 Flow chart of the proposed Sequential-SFPS . . . . . . . . . . . . . . . . 43

3.6 Single line diagram of the six-bus test system . . . . . . . . . . . . . . . 45

3.7 Comparison between the sequential and the non-sequential power-flow al-

gorithms in terms of the convergence speed . . . . . . . . . . . . . . . . . 51

4.1 Schematic diagrams of the four types of wind-turbine generating systems:

(a) Type-1, (b) Type-2, (c) Type-3, and (d) Type-4 . . . . . . . . . . . . 55

4.2 Detailed schematic diagram of a Type-3 wind-driven generation system . 59

4.3 Proposed sequence-frame, fundamental-frequency, steady-state model of

Type-3 DER unit, (a) positive-sequence model, (b) negative-sequence model,

(d) equivalent negative-sequence model. . . . . . . . . . . . . . . . . . . . 60

4.4 Type-3 sequence-frame circuit used to calculate the converters’ internal

parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.5 Flow chart of the proposed Sequential-SFPS algorithm including the Type-

3 DER constraints evaluation and the proposed reference-set point updat-

ing strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1 Single line diagram of the six-bus test system . . . . . . . . . . . . . . . 79

5.2 Voltage profile of the CIGRE distribution network with 2 Type-3 based

DER units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5.3 Voltage profile of the IEEE 34-bus distribution feeder with 3 Type-3 based

DER units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

5.4 Convergence pattern of the Sequential-SFPS algorithm accommodating

the Type-3 DER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.1 Schematic diagram of dual-stage single-phase VSC-coupled DER unit . . 92

6.2 Steady-state, fundamental frequency BFSA model of a single-phase VSC-

coupled DER unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.3 Steady-state, fundamental frequency SFPS model of a single-phase VSC-

coupled DER unit, (a) positive-sequence model, (b) zero- and negative-

sequence models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6.4 Equivalent circuit of the single-phase VSC-coupled DER unit used to cal-

culate the VSC internal parameters . . . . . . . . . . . . . . . . . . . . . 96

6.5 Single line diagram of the radial test feeder . . . . . . . . . . . . . . . . . 101

6.6 Single line diagram of modified three-phase IEEE-34 bus radial feeder . . 105

7.1 Single line diagram of the CIGRE distribution benchmark network . . . . 119

xvi

7.2 Single line diagram of the modified IEEE 34-bus feeder . . . . . . . . . . 119

7.3 Validating the assumption stated in Section 7.4.1 . . . . . . . . . . . . . 120

7.4 Effect of the proposed DSB model on the apparent power output of the

reference bus DER unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7.5 Effect of the proposed DSB model on the real-power losses of the IEEE-34

bus test feeder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.6 Effect of the proposed DSB model on the voltage profile of the IEEE-34

bus test feeder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.7 Effect of imposing the DER power capacity constraint on the PQ-controlled

DER output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

A.1 Single line diagram of the six-bus test system used in Chapters 3 and 5 . 132

A.2 Single line diagram of the three-phase CIGRE MV distribution network

used in Chapters 3, 5, and 7 . . . . . . . . . . . . . . . . . . . . . . . . . 133

A.3 Single line diagram of the CIGRE MV single-phase radial feeder used in

Chapter 6. All power lines are identical. The series impedance of any

power line = 0.219+j0.14 Ω . . . . . . . . . . . . . . . . . . . . . . . . . 135

A.4 Single line diagram of the IEEE 34-bus distribution system used in Chap-

ters 3 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

A.5 Single line diagram of the Modified IEEE 34-bus distribution system used

in Chapters 6 and 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

B.1 Phase-frame model of three-phase power line . . . . . . . . . . . . . . . 140

C.1 Phase-frame model of three-phase four-wire, constant power load . . . . 144

C.2 Phase-frame model of three-phase delta-connected constant power load . 145

C.3 Phase-frame model of three-phase four-wire, constant current load . . . . 147

C.4 Phase-frame model of three-phase delta-connected constant current load 148

C.5 Phase-frame model of three-phase four-wire, constant impedance load . . 148

C.6 Phase-frame model of three-phase delta-connected constant impedance load149

D.1 PSCAD model of the test system in Fig. A.1 . . . . . . . . . . . . . . . . 150

D.2 PSCAD model of a three-phase VSC-coupled DER unit . . . . . . . . . . 151

D.3 PSCAD model of a three-phase Type-3 based DER unit . . . . . . . . . . 152

xvii

Nomenclature

Acronyms

ADN Active Distribution Network

ADS Active Distribution System

AVR Automatic Voltage Regulator

BESS Battery Energy Storage System

BFSA Backward-Forward Sweep Algorithm

DER Distributed Energy Resource

DFAG Doubly Fed Asynchronous Generator

DG Distributed Generator

DNO Distribution Network Operator

DS Distributed Storage

DSB Distributed Slack Bus

FC Fuel Cells

FIT Feed-in-Tarrif

G-S Gauss-Seidel Method

ICT Information and Communication Technology

MPPT Maximum Power Point Tracking

MT Microturbine

N-R Newton-Raphson Method

PC Point of Connection

PEV Plugged Electric Vehicle

PFA Power-Flow Analysis

xviii

PHEV Plugged Hybrid Electric Vehicle

PLL Phase-locked loop

PQ Power-controlled

PV Real-power and voltage-controlled

SEMS Smart Energy Management System

SFPS Sequence-Frame Power-flow Solver

SM Smart Meter

SPV Solar Photovoltaic

SPWM Sinusoidal Pulse-Width Modulation

SSB Single Slack Bus

SVM Space Vector Modulation

TDSG Three-phase Directly-connected Synchronous Generator

V2G Vehicle-to-Grid

VPP Virtual Power Plant

VSC Voltage-sourced converter

WTG Wind turbine generator

WTGU Wind turbine generating unit

Symbols

In this thesis, italic symbols indicated phasor quantities, e.g., I, while multi-dimensional

matrices are shown in bold uppercase, e.g., I.

xix

Chapter 1

Introduction

1.1 Active Distribution Networks

1.1.1 Definitions

Driven by technical advancement, political readiness, social awareness, and economical

incentives, the anticipated proliferation of distributed energy resources (DER) units, in-

cluding distributed generation (DG), distributed storage (DS), and controllable loads,

into the current distribution grids close to the load sites, is emerging as a complementary

infrastructure to the traditional central power plants [1,2]. Unless optimally coordinated

and efficiently integrated, the high-depth of DER penetration will bring many technical

challenges in terms of planning and operation of the distribution networks including,

among others, protection mal-coordination, voltage level violations, power quality con-

cerns, and increasing line losses. The need for efficient and safe DER integration schemes

brings about the concept of the “active distribution systems”.

The active distribution system (ADS), also known as active distribution network

(ADN), is the new generation of today’s distribution networks where the DER units are

optimally operated and efficiently integrated. The CIGRE C6.11 working group defines

the ADN as a distribution network whose operator can remotely and automatically con-

trol the DER units and network topology to efficiently manage and optimally utilize the

network assets [3]. In the ADN, the power flow between busses is bidirectional, and

variables are measured (or estimated) and controlled based on a centralized and intelli-

gent system. The central control system is capable of making decisions and operating

the ADN based on monitoring the network conditions. In general, the ultimate goal of

the ADN is to (i) enhance the DER observability and controllability, (ii) deliver cost

efficient integration of the DER units into the distribution network, and (iii) maximize

1

Chapter 1. Introduction 2

Figure 1.1: Schematic diagram of an Active Distribution Network

the technical and economical benefits achieved by both the DER owners and the host

grid [4–6].

1.1.2 Enabling Technologies

A schematic diagram of an ADN is depicted in Fig. 1.1. As represented in Fig. 1.1, the

enabling technologies to realize the ADN include:

• Information and communication technology (ICT) infrastructure to establish fast

and reliable two-way communication between the DER units, circuit breakers, in-

terconnection switches, smart meters, and the local energy management system.

In the ADN, the bi-directional communication is essential for monitoring, control,


and protection. The most deployed communication standards are the IEC61850 [7]

and the IEEE802.15 (ZigBEE) [8] standards.

• Smart meters (SM) installed at the load premises to monitor and send real-time

data of the load consumption, voltage profile, and total harmonic distortion to the

distribution network operator (DNO). In addition, proliferation of the SM allows

the DNO to control the load profile by utilizing the demand response functions [9].

• Storage devices, e.g., batteries, to maximize the utilization of the renewable energy

resources, e.g., photovoltaic and wind energy. Integrating the storage devices with

renewable-based DER units overcome the intermittent nature of these resources

and enhance their dispatchability [10,11].

• Power electronic converters to interface the DER units to the grid. In particu-

lar, AC-DC and DC-AC voltage-sourced converters (VSC) are the most widely-

adopted interface medium for DER units, e.g., battery energy storage systems,

flywheel energy storage systems, fuel cells, solar photovoltaic units, variable-speed

wind turbine generators with full-scale and partial power-electronic converters, and

micro-turbine systems [12].

• Real-time centralized and decentralized control techniques to optimally control the

large fleet of DER units [13,14].

1.1.3 ADN Operating Modes

The ADN can operate in two distinct modes, i.e.,

• Utility-Connected Mode: In the grid-tied scenarios, the SEMS optimally controls

the ADN components to maximize the technical and economical benefits of the

existing DER fleet. One way of achieving this is to coordinate the ADN apparatus

to provide a pre-specified performance profile at the point of common coupling

(PCC), i.e., the ADN operates as a virtual power plant (VPP) that is comparable

to a conventional plant [15–17]. A conceptual representation of the VPP is given

in Fig. 1.2.

• Islanded Mode: When the interconnection switch of Fig. 1.1 opens, either inten-

tionally or in response to an accidental disturbance, the entire ADN, or pre-specified

parts of it, should be able to operate safely and reliably in the autonomous mode,

i.e., form an islanded microgrid (μgrid) [18, 19].


Figure 1.2: Schematic diagram of an ADN operating as a virtual power plant

1.1.4 Smart Energy Management System

The brain of the ADN is the Smart Energy Management System (SEMS), Fig. 1.1.

SEMS is a local energy and power control and management center that collects real-time

data about (i) the status of the ADN components, e.g., DER power output, on-load

tap changers, circuit breakers, the interconnection switch, (ii) load and voltage profiles,

and (iii) line flows. Several intelligent distribution automation functions are integrated

with the SEMS, e.g., fault detection and isolation, network reconfiguration, congestion

management, blackout and brownout management, optimal asset utilization, and optimal

dispatch and control [20–23].

1.2 Statement of the Problem and Thesis Motiva-

tions

For the SEMS to conduct all the aforementioned distribution automation functions, ac-

curate power-flow analysis (PFA) results must be available. The PFA is the kernel of

the SEMS to guarantee a satisfactory and reliable operation of the ADN by calculat-

ing the appropriate voltage and power reference set points for all the DER units [24].

In addition, during the planning phase, PFA is required to (i) determine the effects

of adding/removing different apparatus, i.e., loads, interconnections, generation, volt-

age regulators, and VAr devices on the ADN performance and (ii) evaluate the optimal

sizing of different power system components. Moreover, the PFA is used to provide a


precise and efficient initialization approach for eigen analysis, transient stability, and

electro-magnetic transients programs [25,26].

1.2.1 Lack of Tools

The PFA of large power systems is a mature subject and a wide array of production

grade power-flow software tools that represent various power-system components, e.g.,

HVDC converters and FACTS controllers, are widely available [27–29]. However, such

tools are neither tailored for nor adequately address the PFA requirements of the ADN.

The main reasons are:

• the inherent large degree of imbalance of distribution networks due to (i) single-

phase and two-phase loads, (ii) single-phase DER units, (iii) untransposed lines,

and (iv) single-phase laterals [30]. As such, the distribution level PFA should

simultaneously address the three phases,

• the presence of three-phase VSC-based DER units which can include (i) three-wire

configurations, (ii) four-wire configurations, and (iii) various control strategies that

can respond to selected sequence-frame voltage and current components [31–37].

Some production grade software tools provide three-phase power-flow analysis for

distribution networks accommodating DER units [38–40]. However, these tools have the

following shortcomings:

• The commercially-available power-flow tools are developed for radial distribution

networks. However, the ADN may be mesh-connected to maximize the DER ben-

efits. Thus, the available tools cannot handle multi-directional power-flow and

general network topologies [34, 41].

• The available three-phase PFA algorithms adopt the phase-frame rather than the

sequence-frame. As will be detailed in Chapter 2, sequence-frame based PFA algo-

rithms are easier to implement, computationally more efficient, and provide flexi-

bility to model VSC-coupled DER units than their phase-frame counterparts.

• The available three-phase power-flow engines are not suitable for the islanded μgrid

operating mode. The reason is that these tools lack an appropriate three-phase

distributed real- and reactive-slack bus model to conduct the PFA. As will be

discussed in Chapter 7 of this thesis, distributed slack bus (DSB)-based PFA is

vital to conduct the power-flow analysis of the islanded μgrid operating mode since


it guarantees that the DER unit connected to the reference bus need not to be an

infinite power source [42].

1.2.2 Lack of DER Models

To obtain unerring three-phase PFA results, detailed and accurate three-phase, steady-

state, fundamental-frequency DER models are required. These models should adequately

address (i) different DER types, i.e., rotating machine-based DER units, single-phase

VSC-coupled, three-phase three-wire VSC-coupled, and three-phase four-wire VSC-coupled

DER units, (ii) different control objectives under balanced and unbalanced grid condi-

tions, i.e., voltage/frequency and real/reactive-power control, specific control actions to

mitigate the voltage and/or current unbalance at the point of connection, and (iii) the op-

erating limits of the interface VSC and the host DER unit, e.g., the converter modulation

index limit, phase current limit, power capacity limit, and terminal voltage limit.

Modeling of electronic converters for interfacing DER units is one of the most chal-

lenging problems, and is becoming an area of active research relevant to power flow

studies [43]. Developing detailed single- and three-phase VSC-coupled DER models for

the ADN power-flow analysis applications has not been systematically addressed in the

technical literature. The reasons are (i) the current relatively limited proliferation of

the electronically-coupled DER units in the distribution grids and (ii) most of the cur-

rently available DER units are based on constant speed directly-coupled three-phase

synchronous generators. The available electronically-coupled DER models, both in the

technical literature and the production-grade software tools, (i) assume only positive-

sequence DER representation, (ii) do not represent the single-phase VSC-coupled DER

units, (iii) do not address most of the aforementioned control objectives, and (iv) neglect

the interface converter operating limits [31,32,34,44–54].

1.3 Thesis Objectives

Based on the discussion of Section 1.2, the thesis objectives are:

1. Develop detailed and accurate steady-state, fundamental-frequency models of VSC-

based DER units for three-phase PFA. The DER units under study include:

• DER units interfaced via a three-phase front-end three-wire or four-wire VSC,

• Variable-speed wind-turbine-generator (WTG)-based DER units deploying a


three-phase doubly-fed asynchronous generator (DFAG), also known as Type-

3 WTG,

• Single-phase VSC-coupled DER units,

The developed DER models should address (i) balanced and unbalanced power-flow

scenarios, (ii) various VSC control strategies under balanced and unbalanced grid

conditions, and (iii) the operating limits and constraints of the VSC and its host

DER unit.

2. Develop a three-phase PFA tool for PFA of analysis and real-time operation of

ADNs. The developed program must:

• be fast and accurate for the real-time management and control of the ADN,

• incorporate the developed single-phase and three-phase DER models, includ-

ing the interface VSC operating constraints in a computationally-efficient man-

ner,

• be capable of analyzing different network topologies (radial, weakly meshed

and meshed networks), including high degrees of unbalance,

• accommodate models of multi-phase power lines and single-phase laterals,

• contain models of single, two, and three-phase loads with different connections,

including constant impedance, current, and power (ZIP) load models,

• accommodate models of three-phase distribution transformers with various

connections, including the phase shift introduced by different transformer con-

nections.

3. Develop a three-phase distributed slack bus (DSB) model. The developed DSB

model will be integrated with the aforementioned tool to conduct three-phase PFA

of islanded ADNs.

1.4 Methodology

1.4.1 Modeling Methodology

The developed DER models and the three-phase PFA tool are developed in the sequence-

components frame. The merits of the sequence-frame compared to the phase-frame for

the three-phase PFA are detailed in Chapter 2 of this thesis.


Figure 1.3: DER Model Validation Methodology

1.4.2 Validation Methodology

The developed three-phase PFA tool, including different DER and ADN components

models, is implemented in the MATLAB® platform. To verify the numerical accuracy

of the developed three-phase VSC-coupled and Type-3 WTG-based DER models, a rela-

tively small three-phase unbalanced test system, with unbalanced loads and untransposed

lines, is used where a DER unit is connected to one of the system busses. The reason for

selecting this relatively small system is to be able to simulate the system, including all

the required details, in time-domain in the PSCAD/EMTDC platform, and consequently,

validate the numerical accuracy of the DER models and the proposed three-phase PFA

tool. The detailed time-domain model of the study system, including the DER converters

and controllers, is developed in the PSCAD/EMTDC time-domain software to serve as

the benchmark for validating the proposed DER models. The PSCAD/EMTDC sim-

ulation environment is selected since it contains detailed and widely used time-domain

models of power system components and allows representation of various controls for the

VSC-interfaced DER units. The single-line diagram and parameters of the test system

are given in Appendix A.1. A conceptual representation of the DER model validation

method is depicted in Fig. 1.3.

1.5 Thesis Structure

A schematic diagram of the thesis layout is shown in Fig. 1.4. This thesis is structured

as follows.


Figure 1.4: Schematic diagram of the thesis layout

1.5.1 Chapter 2: A Three-Phase Sequence-Frame Power-Flow

Solver (SFPS) Tool

In this chapter, a fast, accurate, and robust three-phase power-flow analysis software

tool is developed for ADN applications, i.e., the SFPS tool. Three-phase, sequence

frame-based, fundamental-frequency, steady-state mathematical models of transformers,

loads, and power-lines are described and accommodated in the SFPS. The SFPS is the

hub into which different types of DER units, including their interfacing media, control

capabilities, and operating limits, are accommodated and tested. This contribution is

detailed in Chapter 2, and published in an IEEE Power Delivery Transactions paper [55]

and a reviewed conference paper [56].

1.5.2 Chapter 3: Steady-State Models of Three-Phase VSC-

Coupled DER Units

In this chapter, a unified sequence frame-based, fundamental-frequency, steady-state

mathematical model of a DER unit interfaced to the grid via a three-phase front-end

VSC is proposed and developed. As detailed in Section 1.1.2, the developed model rep-

resents a wide spectrum of DER types, e.g., battery energy storage systems, fuel cells,

solar photovoltaic units, variable-speed wind turbine generators with full-scale power-


electronic converters (Type-4 WTG), and micro-turbine systems. The proposed model is

generic since it accurately addresses (i) three-wire and four-wire VSC configurations, (ii)

balanced and unbalanced power-flow scenarios, (iii) various VSC control strategies, and

(iv) the operating limits and constraints of the interface VSC and the host DER unit.

The developed model is incorporated with the SFPS tool of Chapter 2.

In addition, an enhancement to the basic SFPS algorithm, presented in Chapter 2,

is proposed to model and impose the VSC operating constraints in a computationally-

efficient way. The enhanced algorithm is called the Sequential-SFPS. The computational

efficiency of the Sequential-SFPS is verified by comparing the convergence pattern of

the proposed algorithm against other reported methods. This contribution is detailed in

Chapter 3 and is published in an IEEE Power Delivery Transactions paper [57].

1.5.3 Chapters 4 and 5: Steady-State Models of Type-3 WTG-

Based DER Units

In Chapter 4, I applied the VSC model of Chapter 3 to develop a detailed sequence frame-

based, fundamental-frequency, steady-state mathematical model of a Type-3 WTG-based

DER unit subjected to unbalanced voltage and current conditions. The proposed model

is incorporated with the SFPS, and the Sequential-SFPS of Chapter 3 is extended to

accommodate all the operating limits of the WTG unit and its associated VSCs. A wide

array of case studies are conducted in Chapter 5 to verify the numerical accuracy and

the computational efficiency of the Sequential-SFPS accommodating the proposed Type-

3 WTG-based DER model. A two-part IEEE Sustainable Energy Transactions paper,

describing the details of the proposed DER model and its applications, has been accepted

for publication [58,59].

1.5.4 Chapter 6: Steady-State Models of Single-Phase VSC-

Coupled DER Units

In this chapter, I developed fundamental-frequency, steady-state models of a single-phase

VSC-coupled DER unit for the PFA of single-phase laterals and three-phase distribution

feeders. The proposed models represent different VSC operating modes and constraints.

The sequential approach of Chapter 3 is deployed to impose the VSC constraints into

the power-flow algorithm. The proposed models are integrated with (i) the SFPS for

the PFA of three-phase networks and (ii) a single-phase PFA algorithm to study the

radial single-phase laterals. Several case studies are conducted to evaluate and verify


the accuracy of the proposed model. This contribution is detailed in Chapter 6, and an

IEEE Power Delivery Transactions paper, describing the details and applications of the

proposed models, has been submitted and is in review [60].

1.5.5 Chapter 7: Three-Phase Distributed Real- and Reactive-

Slack Bus Model

In this chapter, a novel three-phase sequence frame-based DSB model is described and

augmented with the SFPS of Chapter 2 to conduct three-phase PFA for islanded ADNs.

Unlike the existing DSB models, the proposed formulation (i) simultaneously distributes

the real and reactive power slack and (ii) involves DER units with different control

strategies in slack compensation. A wide array of case studies is conducted to investigate

the impacts of distributing the real and reactive power slack using the three-phase DSB-

SFPS tool. This contribution is detailed in Chapter 7. In addition, an IEEE Smart Grids

Transactions paper [61] is submitted to report this contribution, and is in review.

1.5.6 Chapter 8: Conclusions

The main conclusions of the thesis and the suggestions for future research topics are

listed in Chapter 8.

Chapter 2

Sequence-Frame Power-Flow Solver

(SFPS)1

2.1 Introduction

This chapter lays the foundation of a three-phase power-flow algorithm, in the sequence-

components frame, for ADN applications. The algorithm is called Sequence-Frame

Power-flow Solver (SFPS). Basic ADN components (power-lines, transformers, and loads)

are modeled in the sequence-frame and accommodated in the SFPS to obtain an accu-

rate three-phase steady-state solution. The SFPS is the hub to which models of different

types of electronically-coupled DER units, including their interfacing media, control ca-

pabilities, and operating limits under balanced and unbalanced power-flow scenarios, are

accommodated to construct the integrated 3ϕ power-flow analysis (PFA) tool, as will be

detailed in the next four chapters.

2.2 Three-Phase Power-Flow Analysis: Critical Re-

view

The concept of three-phase PFA has been extensively addressed in the literature. As

shown in Fig. 2.1, the related algorithms are classified according to (i) the network

1The work presented in this chapter has been published and appears in M.Z. Kamh and R. Iravani,“Unbalanced Model and Power-Flow Analysis of Microgrids and Active Distribution Systems,” IEEETrans. Power Delivery, vol.25, no.4, pp.2851-2858, Oct. 2010. An earlier version of this work has beenpresented and appears in M.Z. Kamh and R. Iravani, “Three-Phase Model and Power-Flow Analysisof Microgrids and Virtual Power Plants,” Proc. of the Fourth Canadian CIGRE Conference on PowerSystems, Toronto, Ontario, Canada, October 2009.

12

Chapter 2. Sequence-Frame Power-Flow Solver (SFPS) 13

structure, i.e., radial [48, 62–68] and general network topologies [25, 30, 69–75] and (ii)

the adopted reference frame to model the power system apparatus, i.e., the phase-frame

[25,48,62–71,75], the sequence-frame [72,73], and a hybrid of both frames [74].

Figure 2.1: Classification of three-phase PFA methods

2.2.1 Three-Phase Power-Flow Algorithms for Radial Network

Topology

2.2.1.1 Backward-Forward Sweep Algorithm (BFSA)

BFSA, also known as the modified ladder network algorithm [62], exploits the radial

topology and unidirectional power flow of distribution feeders to evaluate the power-flow

solution by successively applying Kirchoff’s circuit laws. Both unbalanced three-phase

and balanced single-phase power-flow problems are doable. Balanced and unbalanced

loads as well as shunt elements are modeled as an equivalent current injection. The

backward sweep calculates the currents through each line segment. Using these currents,

the voltage of each node is calculated in the forward sweep. The process continues until

convergence is achieved. The technique as described in [62] can accommodate neither

voltage-controlled (PV) busses nor weakly meshed networks in the algorithm.

2.2.1.2 Compensation-Based Algorithms

Current compensation PFA algorithm is developed in [63] to address weakly-meshed dis-

tribution networks with few number of PV buses. The algorithm is based on breaking

the loops at a number of breakpoints to convert the network to a radial equivalent. The


BFSA is then used to conduct the PFA of the equivalent radial network, where the break-

points current injections are calculated using the multi-port compensation method. The

PV busses are modeled as PQ busses with negative real power consumption and variable

reactive current injection. Subsequent to each iteration, the reactive current injection

is updated using the secant method to regulate the voltage magnitude of PV nodes.

However, this algorithm diverges as the number of PV buses and/or loops increases.

An improved PV-bus model is introduced in [64] and [65]. The new PV model is

a linearized approximation of the automatic voltage regulator (AVR) of synchronous

generators. The PV bus is initialized as PQ bus with reactive power injection set to

the minimum. The algorithm consists of three independent iterative subroutines: the

BFSA, the breakpoint voltage compensation, and the PV node voltage compensation.

Power compensation, instead of current compensation, is proposed in [48] to adjust the

PV bus voltage. The convergence rate of this algorithm is very sensitive to the degree of

unbalance [65]. In addition, the compensation-based PFA algorithm was not tested on

real-size distribution networks.

Different load connections and shunt capacitors are modeled in [66, 67] using their

equivalent current injections, and are incorporated in the compensation-based PFA method.

Power-controlled (PQ) DER units are modeled as balanced negative constant power loads.

High-resolution one-minute time-series data is used to model the loads in [68]. However,

all the lines are assumed to be perfectly transposed and balanced.

2.2.2 Three-Phase Power-Flow Algorithms for General Network

Topologies

To enable efficient and economic DER integration, radial topology is less likely to suit

the ADN requirements. As such, Newton-Raphson (N-R) [25, 69–74] and Gauss and/or

Gauss-Seidel (G-S) [30, 75] methods are more suitable for general network topologies.

Applying these methods for balanced PFA is well established in the literature [76]. The

former is known to have good convergence characteristics, but the continuous update of

the Jacobian matrix makes this approach less attractive. On the other, G-S method is

known to have oscillatory nature and more vulnerable to divergence.

2.2.2.1 Newton-Rapshon Method

In [25], a generalized three-phase power-flow solver is developed using the N-R method

in the rectangular co-ordinates. Phase-frame models of power lines, transformers, and

loads are developed. The only DER type considered in that work is the three-phase


directly-connected synchronous generator, which is modeled as a balanced 3ϕ voltage

source behind an impedance. However, the N-R PFA in the rectangular coordinates is

not common since the size of the Jacobean matrix increases as the number of PV busses

increases.

A modified N-R method is developed in [69]. The Jacobian matrix is decomposed into

a constant upper triangular matrix and a diagonal matrix whose elements are updated

prior to each iteration. However, the results indicate that this method suffers from weak

convergence patterns. In [70], new variables are defined to formulate the N-R power-flow

equations as a set of 3N equations (2N linear plus N non-linear equations), N being

the number of busses. The developed approach shows good convergence patterns when

applied to balanced networks.

In [71], optimal step-size multipliers are augmented with the N-R PFA algorithm to

improve its convergence when used to study networks with high R/X ratio. However, the

applicability of the algorithm for ADN is doubtful since it is not tested on distribution

networks with PV buses and loops.

Sequence-components frame is exploited in [72] and [73] to develop a three-phase

power-flow algorithm. The three-phase unbalanced power-flow problem is decomposed

into three sub-problems with weak mutuality. However, only three-phase four-wire con-

stant power loads are considered in the analysis. In addition, only the voltage-controlled

synchronous generator-based DER unit is considered and modeled as an ideal balanced

voltage source.

Phase- and sequence-frames are combined to solve the 3ϕ power-flow problem of

distribution networks with single-phase laterals [74]. The network is decomposed into

two parts, the three-phase trunk and the single-phase lateral. The algorithm of [72] and

the BFSA are iteratively interleaved leading to deteriorating the convergence speed of

the combined algorithm.

2.2.2.2 Gauss-Seidel Methods

In [30], optimal ordering and triangular factorization are used to develop a three-phase

distribution power-flow method using implicit bus impedance (Z-BUS) Gauss method.

Detailed phase-frame models of lines, loads and transformers are presented. The conver-

gence behavior of the method is highly dependent on the number of the PV buses and

loops, which hinders the applicability of this method to ADN applications.

Phase-decoupled formulation is developed in [75] to solve the three-phase power-flow

problem. After decoupling the three phases, the implicit Z-BUS Gauss method is used

to solve the power-flow equations. The formulation cannot accommodate PV busses.


2.3 Sequence-Frame Versus Phase-Frame in Three-

Phase Power-Flow Analysis

As indicated in Section 2.2, both the phase- and the sequence-frames are exploited in

developing three-phase power-flow algorithms. In the former method, the power system

components are modeled using their phase frame data. This method is very accurate since

it includes the coupling between the un-transposed lines as well as the phase shifts due to

different transformers’ connections. The main reported drawback of phase-frame-based

three-phase power-flow algorithms is the unaccepted computational time and require-

ments. For an N -bus power system, this is equivalent to solving a group of 6N strongly

coupled nonlinear simultaneous equations: real and imaginary parts of 3N equations,

one for each phase.

However, using the sequence-frame has the following merits:

• Using the sequence-components frame in the power-flow analysis effectively reduces

the problem size and the computational burden as compared to the phase-frame

approach. This is true since solving the power-flow equations in the sequence-frame

is equivalent to solving three sets of weakly coupled equations: 2N nonlinear simul-

taneous equations for the positive-sequence network, and two sets of N complex

linear simultaneous equations for the negative- and zero-sequence networks [73].

As will be discussed in Sections 2.4 and 2.5, the coupling between the three-phase

power-flow equations is due to the non-zero off-diagonal elements of the 3x3 admit-

tance matrices that represent untransposed power lines and unbalanced multi-phase

loads. However, the sequence-frame off-diagonal elements are smaller in magnitude

than their phase-frame counterparts [62].

• The three sets of sequence-frame power-flow equations are weakly coupled compared

to their phase-frame counterparts. As such, the sequence-frame PFA algorithms

are less vulnerable to divergence and faster to convergence compared to the phase-

frame algorithms [72]. In addition, the sequence-frame algorithms can easily be

implemented using the parallel programming techniques. Parallel implementation

of the sequence-frame power-flow analysis algorithm is beyond the scope of this

thesis.

• Under the unbalanced grid conditions, the VSC controllers are realized based on

two synchronously and oppositely rotating reference frames [35–37, 77–83]. Thus,

it is easier to develop three-phase models of the VSC-coupled DER units in the


sequence-components frame compared to the phase-frame, as will be detailed in

the next two chapters.

Motivated by the aforementioned merits of the sequence-frame PFA algorithms, this

chapter develops an integrated Sequence-Frame Power-flow Solver (SFPS) tool for the

ADN planning and operation. The developed tool incorporates models of electronically-

coupled DER units representing their control characteristics and operating limits under

balanced and unbalanced grid conditions. In addition, unlike the algorithms of [72]

and [73], the proposed SFPS accommodates different classes of loads including single-

phase, two-phase, and three-phase, three-wire (Wye and Delta connected) and four-wire

loads with constant power/current/impedance models.

2.4 Sequence-Frame Models of Basic ADN Compo-

nents

This section briefly describes the sequence-frame models of some basic ADN compo-

nents, i.e., synchronous generators, power distribution lines, three-phase transformers,

and loads, tailored for the SFPS. More details of the sequence-frame-based, fundamental-

frequency, steady-state models of multi-phase power-lines and loads are given in appen-

dices B and C, respectively.

2.4.1 Distributed Generation

Despite the fact that considerable attention has been paid to converter-based distribu-

tion generation technologies, e.g. fuel cells, photovoltaic arrays, and variable frequency

microturbines, some distributed generation sites in today’s distribution grid still employ

synchronous generators for power and heat co-generation [84]. The basic DG model de-

scribed in this section only encompasses TDSG in PV and PQ operating modes. The

next four chapters are dedicated to develop detailed sequence-frame-based, fundamental-

frequency, steady-state models of three-phase and single-phase VSC-coupled DER units

in the context of the SFPS.

Figure 2.2 shows the sequence-frame-based, fundamental-frequency, steady-state model

of a TDSG connected to Bus-k. The positive-sequence model, Fig. 2.2(a), represents its

control strategy. If the unit operates in the PV mode, it is modeled as an ideal voltage

source behind Bus-k. Under this mode of operation, the magnitude of the positive-

sequence component of the TDSG terminal voltage, |V1k|, and the corresponding injected


positive-sequence real power, P 1DER, both in per-unit, are given by

|V1k| = Vsp, (2.1)

P 1DER =

Psp−DER

3, (2.2)

where Vsp and Psp−DER are the specified per-unit positive-sequence terminal voltage and

the total three-phase injected real power of the TDSG unit respectively.

(a) (b) (c)

Figure 2.2: Sequence-frame, fundamental-frequency, steady-state model of a three-phasedirectly connected synchronous generator for the SFPS: (a) the positive-sequence model,(b) the negative-sequence model, (c) the zero-sequence model

If the TDSG unit operates in the PQ mode, its positive-sequence representation is a

constant power source (or negative constant power load) [85]. The positive-sequence real

power P 1DER is given by (2.2). The positive-sequence reactive power (Q1

DER) injected by

the TDSG unit, in per-unit, is

Q1DER =

Qsp−DER

3, (2.3)

where Qsp−DER is the total three-phase reactive power injected by the TDSG unit. The

factor 1/3 in (2.2) and (2.3) is used to calculate the sequence-frame power components

from their phase-frame counterparts, assuming the same base-power is used in both

reference frames.

The negative- and zero-sequence models of the TDSG unit are shown in Fig. 2.2(b)

and 2.2(c), respectively. The negative- and zero-sequence admittances (y2,0DER) are [86]

y2,0DER =

1(R2,0

SG + jX2,0SG

) , (2.4)


where

R2SG = Ra−SG,

R0SG = Ra−SG + 3Rn−SG, (2.5)

and

X2SG =

(X”

d−unsat + X”q−unsat

)/2,

X0SG =

X2SG

4+ 3Xn−SG, (2.6)

where X”d−unsat (X”

q−unsat) is the direct (quadrature) unsaturated sub-transient reactance,

Xn−SG (Rn−SG) is the TDSG neutral grounding reactance (resistance), and Ra−SG is the

armature resistance of the TDSG.

2.4.2 Unbalanced Three-phase Distribution Line

An (un)balanced three-phase distribution line connecting Bus-k and Bus-m, is modeled

as a single equivalent pi-section, Fig. 2.3. This model adequately addresses two-phase

and three-phase three-wire and four-wire multi-grounded distribution lines, which are

predominant the North American’s distribution systems [87–89].

Figure 2.3: Equivalent π-model of a three-phase distribution line

In Fig. 2.3, series and shunt branches are given by two 3×3 admittance matrices,

Y012series and Y012

shunt, respectively. Also, I012km and V012

k are 3×1 vectors, and represent

the sequence-frame fundamental-frequency, steady-state current flowing from Bus-k to

Bus-m and voltage components of Bus-k, respectively. I012km is given by

I012km =

Y012shunt

2V012

k + Y012series

(V012

k − V012m

), (2.7)


which is equivalent to

⎡⎢⎢⎢⎢⎣

I0km

I1km

I2km

⎤⎥⎥⎥⎥⎦ =

1

2

⎡⎢⎢⎢⎢⎣

y00shunt y01

shunt y02shunt

y10shunt y11

shunt y12shunt

y20shunt y21

shunt y22shunt

⎤⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎣

V0k

V1k

V2k

⎤⎥⎥⎥⎥⎦+⎡⎢⎢⎢⎢⎣

y00series y01

series y02series

y10series y11

series y12series

y20series y21

series y22series

⎤⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎣

V0k −V0

m

V1k −V1

m

V2k −V2

m

⎤⎥⎥⎥⎥⎦ .

(2.8)

Equation (2.8) is the coupled sequence-frame model of the distribution line of Fig. 2.3.

The coupling between the sequence networks is due to the off-diagonal elements in Y012series

and Y012shunt. These terms are zero for a perfectly transposed power line, an uncommon

case in the North-American distribution networks. The magnitudes of the off-diagonal

elements of Y012series and Y012

shunt are less than their diagonal counterparts [62, 73]. Thus,

(2.8) can be written as

⎡⎢⎢⎢⎢⎣

I0km

I1km

I2km

⎤⎥⎥⎥⎥⎦ =

1

2

⎡⎢⎢⎢⎢⎣

y00shunt 0 0

0 y11shunt 0

0 0 y22shunt

⎤⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎣

V0k

V1k

V2k

⎤⎥⎥⎥⎥⎦+

⎡⎢⎢⎢⎢⎣

y00series 0 0

0 y11series 0

0 0 y22series

⎤⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎣

V0k −V0

m

V1k −V1

m

V2k −V2

m

⎤⎥⎥⎥⎥⎦

−

⎡⎢⎢⎢⎢⎣�I0

shunt−km

�I1shunt−km

�I2shunt−km

⎤⎥⎥⎥⎥⎦−

⎡⎢⎢⎢⎢⎣�I0

series−km

�I1series−km

�I2series−km

⎤⎥⎥⎥⎥⎦ , (2.9)

where

⎡⎢⎢⎢⎢⎣�I0

shunt−km

�I1shunt−km

�I2shunt−km

⎤⎥⎥⎥⎥⎦ = −1

2

⎡⎢⎢⎢⎢⎣

y01shuntV

1k + y02

shuntV2k

y10shuntV

0k + y12

shuntV2k

y20shuntV

0k + y21

shuntV1k

⎤⎥⎥⎥⎥⎦ , (2.10)

⎡⎢⎢⎢⎢⎣�I0

series−km

�I1series−km

�I2series−km

⎤⎥⎥⎥⎥⎦ = −

⎡⎢⎢⎢⎢⎣

y01series

(V1

k −V1m

)+ y02

series

(V2

k −V2m

)y10

series

(V0

k −V0m

)+ y12

series

(V2

k −V2m

)y20

series

(V0

k −V0m

)+ y21

series

(V1

k −V1m

)

⎤⎥⎥⎥⎥⎦ , (2.11)

and ⎡⎢⎢⎢⎢⎣�I0

km

�I1km

�I2km

⎤⎥⎥⎥⎥⎦ =

⎡⎢⎢⎢⎢⎣�I0

shunt−km

�I1shunt−km

�I2shunt−km

⎤⎥⎥⎥⎥⎦+

⎡⎢⎢⎢⎢⎣�I0

series−km

�I1series−km

�I2series−km

⎤⎥⎥⎥⎥⎦ . (2.12)


Equation (2.12) represents the equivalent compensation currents that should be in-

jected into Bus-k to decouple the three sequence networks. The equivalent positive-

sequence compensation power (�S1km) injected at Bus-k is given by

�S1km = �P 1

km + j�Q1km = V1

k

(�I1

km

)∗. (2.13)

The decoupled sequence-frame model of the three-phase distribution line is given by (2.9)-

(2.13), and is depicted in Fig 2.4. Implementing the model of Fig. 2.4 in the SFPS is

discussed in Section 2.5

(a)

(b)

(c)

Figure 2.4: Decoupled sequence-frame, fundamental-frequency, steady-state model of athree-phase distribution line: (a) the positive-sequence model, (b) the negative-sequencemodel, (c) the zero-sequence model


2.4.3 Three-phase Power Transformers

Several three-phase transformer connections exist in distribution networks. They can

be categorized into: Δ/Yg, Yg/Yg, Δ/Y, Yg/Y , and Δ/Δ. These transformer connections

introduce different phase shifts between their primary and secondary sides. Accurate

transformer models must consider these phase shifts in the sequence-frame PFA.

In the SFPS, a three-phase transformer that connects Bus-k to Bus-m and has a

short circuit admittance of ySC , is modeled using three decoupled 2 × 2 admittance

matrices [73]. The entries of these three matrices depend on the transformer connection,

as shown in Table 2.1.

Table 2.1: Sequence-Frame, Fundamental-Frequency, Steady-State Model of A Three-Phase Power Transformer

Transformer ConnectionBus-k Bus-m Bus-k Bus-m Bus-k Bus-m Bus-k Bus-m Bus-k Bus-m

Yg Yg Yg Δ Y Δ Yg Y Δ ΔPositive-Sequence Model y1

tr−kk ySC ySC ySC ySC ySC⎡⎣ y1

tr−kk y1tr−km

y1tr−mk y1

tr−mm

⎤⎦ y1

tr−mm ySC ySC ySC ySC ySC

y1tr−km ySC ySC

� 30o ySC� 30o ySC ySC

y1tr−mk ySC ySC

� − 30o ySC� − 30o ySC ySC

Negative-Sequence Model y2tr−kk ySC ySC ySC ySC ySC⎡

⎣ y2tr−kk y2

tr−km

y2tr−mk y2

tr−mm

⎤⎦ y2

tr−mm ySC ySC ySC ySC ySC

y2tr−km ySC ySC

� − 30o ySC� − 30o ySC ySC

y2tr−mk ySC ySC

� 30o ySC� 30o ySC ySC

Zero-Sequence Model y0tr−kk ((ySC)−1 + 3zn)

−1((ySC)−1 + 3zn)

−10 ((ySC)−1 + 3zn)

−10⎡

⎣ y0tr−kk y0

tr−km

y0tr−mk y0

tr−mm

⎤⎦ y0

tr−mm ((ySC)−1 + 3zn)−1

0 0 0 0

y0tr−km ((ySC)−1 + 3zn)

−10 0 0 0

y0tr−mk ((ySC)−1 + 3zn)

−10 0 0 0

2.4.4 Loads

The sequence-frame, fundamental-frequency, steady-state models of four-wire, constant

power loads only are considered in [72] and [73]. However, electric loads in the dis-

tribution networks include single-phase, two-phase, or three-phase three-wire constant

power/current/impedance loads [62]. This section briefly describes the sequence-frame

models of 3ϕ constant power/current/impedance loads in the context of the SFPS. The

detailed development of different load models is covered in Appendix C.

2.4.4.1 Constant Power and Current Loads

Figure 2.5 shows a schematic diagram of a generic constant power/current load connected

to Bus-k. A unified sequence-frame model for these kinds of loads is depicted in Fig. 2.6.


Figure 2.5: Schematic diagram of a constant power/current load connected to Bus-k

(a) (b) (c)

Figure 2.6: Decoupled sequence-frame, fundamental-frequency, steady-state model of aconstant power/current load

The positive-sequence load model is a power source, Fig. 2.6(a), whose value S1load is

the product of the positive-sequence voltage at Bus-k V1k and the complex conjugate of

the positive-sequence load current injected into Bus-k I1load. Subsequent to each power-

flow iteration, V1k, I1

load, and consequently S1load are updated.

As shown in Fig. 2.6(b) and 2.6(c), the negative- and zero-sequence load models

are two current sources whose values are equal to the negative- and zero-sequence load

currents injected into Bus-k respectively (I2,0load). Three-wire load connection (Wye and

Delta) does not provide a path for the zero-sequence current. As such, I0load is set equal

to zero for such loads.

2.4.4.2 Constant Impedance Loads

Regardless of the load connection, the phase-frame representation of a constant impedance

load is a 3 × 3 diagonal admittance matrix, Fig. 2.7(a). The values of the three admit-

tances, yaaload, ybb

load, and yccload, depend on the load’s connection, rated voltage, and rated

power [62].


(a) (b)

Figure 2.7: Model of a constant impedance load connected to Bus-k: (a) phase-framemodel, (b) sequence-frame model

In the sequence-frame, the equivalent sequence-frame load admittance matrix is

⎡⎢⎢⎢⎢⎣

y00load y01

load y02load

y10load y11

load y12load

y20load y21

load y22load

⎤⎥⎥⎥⎥⎦ = T−1

⎡⎢⎢⎢⎢⎣

yaaload 0 0

0 ybbload 0

0 0 yccload

⎤⎥⎥⎥⎥⎦T, (2.14)

where

T =

⎡⎢⎢⎢⎢⎣

1 1 1

1 a2 a

1 a a2

⎤⎥⎥⎥⎥⎦ , a = 1� 120◦. (2.15)

The off-diagonal elements of the sequence-frame matrix are zero only for perfectly

balanced loads, i.e., yaaload = ybb

load = yccload.

The sequence-frame load currents (I012load) and voltages (V012

k ) of Fig. 2.7(b) are

⎡⎢⎢⎢⎢⎣

I0load

I1load

I2load

⎤⎥⎥⎥⎥⎦ = −

⎡⎢⎢⎢⎢⎣

y00load y01

load y02load

y10load y11

load y12load

y20load y21

load y22load

⎤⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎣

V0k

V1k

V2k

⎤⎥⎥⎥⎥⎦ . (2.16)

Eq. (2.16) can be written as

⎡⎢⎢⎢⎢⎣

I0load

I1load

I2load

⎤⎥⎥⎥⎥⎦ = −

⎡⎢⎢⎢⎢⎣

y00load 0 0

0 y11load 0

0 0 y22load

⎤⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎣

V0k

V1k

V2k

⎤⎥⎥⎥⎥⎦+

⎡⎢⎢⎢⎢⎣

ΔI0load

ΔI1load

ΔI2load

⎤⎥⎥⎥⎥⎦ , (2.17)


where ⎡⎢⎢⎢⎢⎣

ΔI0load

ΔI1load

ΔI2load

⎤⎥⎥⎥⎥⎦ = −

⎡⎢⎢⎢⎢⎣

y01loadV

1k + y02

loadV2k

y10loadV

0k + y12

loadV2k

y20loadV

0k + y21

loadV1k

⎤⎥⎥⎥⎥⎦ . (2.18)

Equation (2.18) represents the sequence-frame compensation currents required to

decouple the three sequence networks. The equivalent positive-sequence compensation

power (ΔS1load) injected into Bus-k is given by

ΔS1load = ΔP 1

load + jΔQ1load = V1

k

(ΔI1

load

)∗. (2.19)

The sequence-frame constant impedance load model incorporated in the SFPS is given

by (2.17)-(2.19), and is depicted in Fig. 2.8.

(a) (b) (c)

Figure 2.8: Decoupled sequence-frame model of a constant power/current load

2.5 The SFPS Algorithm

The SFPS algorithm is depicted in Fig. 2.9. The details of the SFPS steps follow.

Step 1: Construct the Sequence-Frame Bus Admittance Matrices:

The entry corresponding to the kth row and mth column of the positive-, negative-, and

zero-sequence bus admittance matrices (Y1,2,0BUS) is given by

y1BUS−km

=

⎧⎪⎨⎪⎩∑A

i=1 y11series−i + 1

2

∑Ai=1 y

11shunt−i +

∑Bi=1 y

1tr−km−i +

∑Ci=1 y

11load−i , k = m,

−∑Ai=1 y

11series−i −

∑Bi=1 y

1tr−km−i , k �= m,

(2.20)


Figure 2.9: Flow chart of the SFPS algorithm


y2,0BUS−km

=

⎧⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎩

∑Ai=1 y

22,00series−i + 1

2

∑Ai=1 y

22,00shunt−i +

∑Bi=1 y

2,0tr−km−i +

∑Ci=1 y

22,00load−i

+∑D

i=1 y2,0DER−i , k = m,

−∑Ai=1 y

22,00series−i −

∑Bi=1 y

2,0tr−km−i , k �= m,

(2.21)

where A is the total number of power lines connected to Bus-k, B is the total number

of transformers connected to Bus-k, C is the total number of constant impedance loads

connected to Bus-k, A is the total number of power-lines connecting Bus-k to Bus-m,

B is the total number of transformers connecting Bus-k to Bus-m, and D is the total

number of TDSG units connected to Bus-k.

Step 2: Check for the Zero-Sequence Blocking Condition:

In practical power systems, there will always be a path for zero sequence current. How-

ever, due to the components’ models incorporated in the SFPS, some buses of the zero-

sequence network might be isolated, Fig. 2.10. The clouded bus in Fig. 2.10(a) is

connected to a three-wire load and the delta side of a three-phase transformer. The

corresponding zero-sequence impedance diagram is given in Fig. 2.10(b). In the zero-

sequence network, the clouded bus becomes isolated from the rest of the network.

(a)

(b)

Figure 2.10: Zero-sequence blocking scenario: (a) phase-frame network, (b) zero-sequenceimpedance diagram

In the SFPS, this condition causes some rows and columns of the Y0BUS with all-zero

entries. This is called zero-sequence blocking [90]. If this situation occurs, Y0BUS becomes

singular. In this work, once the zero-sequence blocking flag is raised, a modified Y0BUS

is constructed by eliminating the corresponding all-zeros rows and columns.


Step 3: Initialize the Positive-, Negative-, and Zero-Sequence Bus Voltages:

The sequence-frame components of the voltages at Bus-k are initialized according to

V1k =

⎧⎪⎨⎪⎩

1.0 Bus-k is a PQ bus,

Vsp Bus-k is a PV or slack bus,

V0,2k = 0.0. (2.22)

If the zero-sequence blocking flag is raised, omit the corresponding entries of V0BUS.

Step 4: Reset the Algorithm Counter:

ct = 0. (2.23)

Step 5: Update the Negative- and Zero-Sequence Specified Bus-Current In-

jection Vectors:

Prior to the ctth iteration, the entry corresponding to the kth row of the negative- and

zero-sequence specified bus-current injection vectors (I2,0BUS,ct) is

I2,0BUS−k,ct =

A∑i=1

ΔI2,0km−i,ct +

C∑i=1

ΔI2,0load−i,ct +

E∑i=1

I2,0load−i,ct, (2.24)

where E is the total number of constant power/current loads connected to Bus-k. If the

zero-sequence blocking flag is raised, omit the corresponding entries of I0BUS.

Step 6: Update the Positive-Sequence Specified Bus-Power Injection Vectors:

Prior to the ctth iteration, the kth entry of the positive-sequence specified bus-power

injection vectors (P1BUS,ct and Q1

BUS,ct ) is given by

P 1BUS−k,ct =

D∑i=1

P 1DER−i + �

(E∑

i=1

S1load−i,ct

)+ P 1

k−comp,ct, (2.25)

Q1BUS−k,ct =

D∑i=1

αiQ1DER−i + �

(E∑

i=1

S1load−i,ct

)+ Q1

k−comp,ct, (2.26)

where

αi =

⎧⎪⎨⎪⎩

1 DER-i is PQ controlled,

0 DER-i is PV controlled.(2.27)


P 1k−comp,ct and Q1

k−comp,ct are the positive-sequence real and reactive power compensation

at Bus-k, and are calculated prior to the ctth iteration using

P 1k,comp = �

⎛⎝ A∑

i=1

ΔS1km−i,ct +

C∑i=1

ΔS1load−i,ct

⎞⎠ , (2.28)

Q1k,comp = �

⎛⎝ A∑

i=1

ΔS1km−i,ct +

C∑i=1

ΔS1load−i,ct

⎞⎠ . (2.29)

Step 7: Conduct the Positive-Sequence N-R PFA

Update the positive-sequence Jacobian matrix Jct and the positive-sequence power mis-

match vector ΔS1mismatch,ct. Solve (2.31) for the magnitudes and angles of the positive-

sequence bus voltages of the ct + 1th iteration.

−Jct

⎛⎜⎝⎡⎢⎣ θ1

BUS,ct+1

V1BUS,ct+1

⎤⎥⎦−

⎡⎢⎣ θ1

BUS,ct

V1BUS,ct

⎤⎥⎦⎞⎟⎠ = ΔS1

mismatch,ct, (2.30)

where

J =

⎡⎢⎣ ∂PBUS/∂θBUS ∂PBUS/∂VBUS

∂QBUS/∂θBUS ∂QBUS/∂VBUS

⎤⎥⎦ , (2.31)

ΔS1mismatch,ct =

⎡⎢⎣ P1

BUS,ct

Q1BUS,ct

⎤⎥⎦−

⎡⎢⎣ P1

calc.,ct

Q1calc.,ct

⎤⎥⎦ , (2.32)

and

P 1calc.−i = �

⎛⎝V1

i

(N∑

k=1

V1ky

1BUS−ik

)∗⎞⎠

Q1calc.−i = �

⎛⎝V1

i

(N∑

k=1

V1ky

1BUS−ik

)∗⎞⎠ (2.33)

Step 8: Conduct the Negative- and Zero-Sequence PFA:

Solve the two complex matrix equations (2.34) for the negative- and zero-sequence bus

voltages at iteration ct + 1.

I2,0BUS,ct = Y2,0

BUSV2,0BUS,ct+1. (2.34)


Step 9: Evaluate the Phase-Frame Bus Voltages:

Reconstruct V0BUS by inserting a zero entry corresponding to each bus with a raised

zero-sequence blocking flag. Evaluate the phase-frame bus-voltages using

⎡⎢⎢⎢⎢⎢⎣

(Va

BUS,ct+1

)′

(Vb

BUS,ct+1

)′

(Vc

BUS,ct+1

)′

⎤⎥⎥⎥⎥⎥⎦ = T

⎡⎢⎢⎢⎢⎢⎣

(V0

BUS,ct+1

)′

(V1

BUS,ct+1

)′

(V2

BUS,ct+1

)′

⎤⎥⎥⎥⎥⎥⎦ , (2.35)

where (.)′is the transpose of a vector.

Step 10: Evaluate the Termination Criterion:

Evaluate the termination criterion (ter − cri) using

ter − cri = max

⎡⎢⎢⎢⎢⎣|Va

BUS,ct+1| − |VaBUS,ct|

|VbBUS,ct+1| − |Vb

BUS,ct||Vc

BUS,ct+1| − |VcBUS,ct|

⎤⎥⎥⎥⎥⎦ (2.36)

The maximum power mismatch could also be used as a termination criterion:

ter − cri = max(ΔS1

mismatch,ct

)(2.37)

Update the algorithm counter (ct):

ct = ct + 1. (2.38)

If ter − cri is larger than a pre-specified tolerance, go to Step 5, else print the SFPS

results.

2.6 Summary and Discussion

This chapter presents the development of a three-phase power-flow analysis method for

the ADN applications, under balanced and unbalanced conditions. The power-flow

algorithm, Sequence-Frame Power-flow Solver (SFPS), is developed in the sequence-


component frame. This chapter also describes sequence-frame, fundamental-frequency,

steady-state models of:

• a three-phase directly-connected synchronous generator DG unit under balanced

and unbalanced power-flow scenarios with different control characteristics, i.e., con-

stant power (PQ) and voltage-regulated (PV) operating modes,

• (un)transposed three-phase three- and four-wire power lines,

• three-phase transformers with different connections,

• multi-phase constant power/current/impedance loads.

The SFPS algorithm, including the details of incorporating the aforementioned com-

ponents, is presented and discussed. The SFPS is the hub into which the VSC-based

DER models are incorporated and tested, as will be detailed in the next four chapters.

Chapter 3

Power-Flow Model of 3ϕ

VSC-Coupled DER Units1

3.1 Introduction

This chapter presents a unified fundamental-frequency, steady-state model of a three-

phase VSC, in the sequence-components frame, for PFA of VSC-interfaced DER units.

The proposed model is unified since it encompasses a wide array of DER units, e.g.,

battery energy storage systems (BESS), fuel cells (FC), solar photovoltaic units (SPV),

variable-speed wind turbine generators with full-scale power-electronic converters (Type-

4 WTG), and micro-turbine (MT) systems. In addition, the model represents (i) three-

wire and four-wire VSC configurations, (ii) balanced and unbalanced power-flow scenar-

ios, (iii) various VSC control strategies, and (iv) operating limits and constraints of the

VSC and its host DER unit. To achieve numerical and computational efficiency, the

SFPS algorithm, presented in Chapter 2, is modified to impose the the interface-VSC

operating limits. The accuracy of the developed model and the computational efficiency

of the modified SFPS are demonstrated based on several case studies. Where applicable,

the numerical accuracy of the VSC model is validated based on comparison with the

exact time-domain solution, using the PSCAD/EMTDC platform.

1The work presented in this chapter has been published and appears in M.Z. Kamh and R. Iravani,“A Unified Three-Phase Power-Flow Analysis Model for Electronically-Coupled Distributed Energy Re-sources,” IEEE Trans. Power Delivery, vol.26, no.2, pp.899-909, April 2011.

32

Chapter 3. Power-Flow Model of 3-ϕ VSC-Coupled DER Units 33

Figure 3.1: Schematic diagram of three-phase VSC-coupled DER unit

3.2 Model Scope and Assumptions

As earlier stated in Chapter 1, three-phase DC-AC VSC is the most widely-adopted

interface medium for DER units [12]. To obtain an accurate power-flow solution of

ADN, three-phase VSC-coupled DER units should be modeled and incorporated in the

SFPS. The proposed model encompasses:

• three-wire and four-wire VSC configurations under both balanced and unbalanced

power-flow scenarios,

• various VSC control strategies, i.e., voltage/frequency and four-quadrant real/reactive

power controls, and specific control actions to inject an/or respond to negative-

and/or zero-sequence components,

• various VSC operational modes, e.g., four-quadrant real-/reactive-power exchange,

• the VSC operational limits and constraints, i.e., maximum phase current, maximum

modulation index, and maximum reactive power limits.

Figure 3.1 shows a schematic diagram of a DER unit coupled to the host system at

Bus-k, which represents the point of connection (PC), via a three-wire or a four-wire

VSC. The primary source is connected to the VSC either (i) directly, e.g., BESS and

FC, (ii) by a DC-DC converter, e.g., SPV, or (iii) by an AC-DC converter, e.g., Type-4

WTG [12,34]. The following assumptions are made:

• The DER primary source is not directly represented in the model as the controllers

of the front-end interface-VSC or the back-end DC-DC converter are assumed to

fully regulate the DC-link voltage under steady-state conditions.


(a) (b) (c)

Figure 3.2: Proposed sequence-frame, fundamental-frequency, steady-state model of a3ϕ interface VSC, (a) positive-sequence model, (b) negative-sequence model, (c) zero-sequence model

• Only the fundamental frequency model of the interface-VSC is considered, i.e., the

harmonic effects are discarded.

• The VSC synchronization to the grid is based on a phase-locked loop (PLL) system

that also extracts the sequence-frame components of the PC voltage [36,77].

• The interface VSC is equipped with dedicated controllers to provide specific control

functions with respect to the negative- and/or zero-sequence components of the PC

variables.

• Double-frequency voltage and current components, present at the converter dc side

due to possible system unbalance, are assumed to be negligible.

• the VSC losses are neglected.

• The VSC negative- and zero-sequence power exchange with the host grid are neg-

ligibly small compared to their positive-sequence counterpart. As such, the VSC

positive-, negative-, and zero-sequence-frame models are assumed to be fully de-

coupled.

3.3 Proposed Sequence-Frame Model of 3ϕ VSC-Coupled

DER Units

Figure 3.2 shows the proposed sequence-frame, fundamental-frequency, steady-state rep-

resentation of a 3ϕ VSC interfacing a DER unit. Under balanced/unbalanced grid con-

ditions, the primary control objective of the interface VSC controllers is to either achieve

constant-power regulation (PQ) [91] or voltage and frequency regulation (PV) [92] at the


PC. This is realized by sensing the positive-sequence voltage and current components

at the PC, and utilizing them through a feedback process to control the coupling VSC

to generate the required positive-sequence voltage at its terminals. Thus, the positive-

sequence model of the VSC-coupled DER unit reflects either the PQ or the PV control

mode.

Should the DER unit be subjected to unbalanced power-flow, the negative- and/or

zero-sequence components of the PC variables also can be exploited to augment the

VSC switching process to provide specific control functions. For example, a three-wire

VSC can be controlled to inject (i) only balanced three-phase currents [36], or (ii) in

addition, a pre-specified amount of negative sequence current [37], to counteract the

system imbalance or for active islanding detection. If desired, a four-wire VSC can be

controlled also to compensate for the neutral (zero-sequence) current of a local unbalanced

three-phase load [35]. The developed negative- and zero-sequence frame VSC models in

this chapter are intended to reflect any/all of these VSC functionalities.

3.3.1 Interface VSC Positive-Sequence Model

The VSC positive-sequence model is similar to that of the TDSG shown in Fig. 2.2(a),

duplicated as Fig. 3.2(a) for ease of reference.

a) When the DER unit operates in the PV mode [92], its positive-sequence model with

respect to the PC is an ideal voltage source behind the PC bus. The specified volt-

age magnitude, |V1k|, at the PC and the positive-sequence real power injected (or

absorbed), P 1DER, by the unit are

|V1k| = Vsp, (3.1)

P 1DER =

Psp−DER

3, (3.2)

where Vsp and Psp−DER are the per-unit voltage and the three-phase real power refer-

ence set-points of the VSC.

b) When the DER unit is controlled to operate in the PQ mode, it is represented as a

constant power source. In this case, the real power injected/absorbed is given by (3.2)

and the exchanged reactive power, Q1DER, is

Q1DER =

Qsp−DER

3, (3.3)

where Qsp−DER is the per-unit three-phase reactive power reference set-point of the


VSC. In Fig. 3.2(a), I1DER is the positive-sequence current exchange between the DER

unit and the system.

3.3.2 Interface VSC Negative- and Zero-Sequence Models

The negative- and zero-sequence models of the interface VSC are shown in Figs. 3.2(b)

and 3.2(c), respectively. A parallel combination of a current source (I0,2CTRL) and fictitious

admittance (Y0,2CTRL) can represent any control objective for both the three-wire and four-

wire VSC, corresponding to negative- and zero-sequence frames. In Fig. 3.2(b) (3.2(c)),

the net current exchange between the VSC negative- (zero-) sequence model and the

system is presented by I2DER(I0

DER).

3.3.2.1 Three-Wire VSC Configuration

If a three-wire interface-VSC is controlled only based on the positive-sequence dq current

control method [91], the DER unit also exchanges negative-sequence current with the

unbalanced system. In this case, the negative and zero sequence-frame components of

the model are specified as

I0,2CTRL = 0,

Y2CTRL = 1/Zf , (3.4)

Y0CTRL = 0,

where Zf is the equivalent series impedance of the VSC output filter between the PC

and the short-circuited VSC terminals. The VSC output filter is used to reduce the

harmonic current injected in the utility system [93]. The simplest output filter topology

is a series-connected inductor, Fig. 3.1, for which Zf is given by

Zf = Rf + jXf , (3.5)

where Xf/Rf is the VSC output filter net reactance/resistance. Other output filter

configurations are reported in [94]. These alternative configurations lie under either one

of the two topologies shown in Fig. 3.3. The equivalent series impedance, Zf , for the


(a) (b)

Figure 3.3: Alternative VSC output filter configurations

filter configurations shown in Fig. 3.3(a) and Fig. 3.3(b), is calculated as

Zf =Z1Z2

Z1 + Z2

, (3.6)

Zf = Z3 +Z1Z2

Z1 + Z2

, (3.7)

respectively, where Z1, Z2, and Z3 are shown in Fig. 3.3.

If a three-wire VSC is equipped with both positive- and negative-sequence current con-

trol schemes, and the negative-sequence current control is assigned to prevent negative-

sequence current exchange with the system [36], then the negative- and zero-sequence

models components are

I0,2CTRL = 0,

Y0,2CTRL = 0. (3.8)

For some applications, the negative-sequence controller of the three-wire VSC is de-

signed to inject a pre-specified negative-sequence current into the system, e.g., for island-

ing detection [37]. In this case, the negative and zero-sequence models of the interface-

VSC are

I2CTRL = INSCI � φNSCI ,

I0CTRL = 0, (3.9)

Y0,2CTRL = 0,

where INSCI and φNSCI are the magnitude and phase angle of the pre-specified negative

sequence current injection. In (3.4), (3.8), and (3.9), the parameters of the zero-sequence

model of Fig. 3.2(c) are always zero since there is no path for zero-sequence current flow.


3.3.2.2 Four-Wire VSC Configuration

The split-capacitor and the four-leg interface-VSC configurations can enable neutral con-

nection and establish a four-wire VSC system [35]. With respect to the steady-state

power-flow, both configurations are equivalent as long as the assumptions stated in Sec-

tion 3.2 are applicable. In addition to the positive-sequence current control, a four-wire

interface-VSC can exchange controlled negative- and zero-sequence current components

with the system, e.g., to counteract the imbalance due to unbalanced load at the PC [35].

The models of Fig. 3.2(b) and Fig. 3.2(c) can represent this strategy by setting

I0,2CTRL =

N∑i=1

V0,2i y0,2

BUS−ki− I0,2

load−k,

Y 0,2CTRL = 0, (3.10)

where I0,2load−k is the equivalent zero- and negative-sequence load current components

injected into the PC (Bus-k).

If the four-wire interface-VSC only injects a controlled positive-sequence current in the

system and permits the system to determine the exchanged negative- and zero-sequence

current components, then the corresponding model parameters are

I0,2CTRL = 0,

Y2CTRL =

1

Rf + jXf

, (3.11)

Y0CTRL =

1

(Rf + 3Rn) + j(Xf + 3Xn),

where Rn and Xn are defined in Fig. 3.1.

3.4 Implementation of the VSC Unified Model in the

SFPS

3.4.1 Accommodating the VSC-Coupled DER Model in the

SFPS

Consider a VSC-interfaced DER unit coupled to the host distribution network at Bus-k

(DER-k). To embed the model of Fig. 3.2 in the SFPS algorithm:

1. Add the terms Y0,2CTRL to the entries of the zero- and negative-sequence bus admit-


Figure 3.4: Equivalent sequence-frame circuits of a VSC-coupled DER unit

tance matrices corresponding to the kth row and the kth column (y0,2BUS−kk

), given

by (2.21), respectively.

2. Add the terms I0,2CTRL to the kth entries of the zero- and negative-sequence bus-

current injection vectors (I0,2BUS−k), given by (2.24), respectively.

3. Add the terms P 1DER and Q1

DER, given by (3.2) and (3.3), to the kth entry of the

specified real and reactive power vectors (P 1BUS−k and Q1

BUS−k), given by (2.25)

and (2.26), respectively.

3.4.2 Calculating the Internal Parameters of the Interface VSC

To impose the operating limits of the interface-VSC of DER-k in the SFPS, its internal

parameters values, i.e., modulation indices, phase currents, and reactive power (for PV

units), must be determined first. Figure 3.4 shows the equivalent sequence-frame circuits

of the interface VSC used to determine these parameters.

Subsequent to each power-flow iteration, the PC terminal conditions are evaluated.

The VSC net sequence-frame current components injected into the PC are

I0,2DER = I0,2

CTRL −Y0,2CTRLV 0,2

k� θ0,2

k , (3.12)

I1DER =

P 1DER − jQ1

DER

V 1k� − θ1

k

, (3.13)

where the elements of the VSC net current injection vector I012DER =

[I0

DER I1DER I2

DER

]′are specified on Fig. 3.2. Then the three-phase current Iabc

DER injected by the DER unit

is calculated using

IabcDER = TI012

DER, (3.14)


Table 3.1: VSC ConstantModulation Strategy Kinv

Sinusoidal Pulse 12√

2Width Modulation (SPWM)Space Vector 1√

6Modulation (SVM)

where the matrix T is given by (2.15) and

IabcDER =

[Ia

DER IbDER Ic

DER

]′. (3.15)

Finally, the sequence components of the interface-VSC terminal voltage, Fig. 3.4, can be

determined using

V 0,2t

� θ0,2t = I0,2

DER

(R0,2 + jX0,2

)+ V 0,2

k� θ0,2

k , (3.16)

V 1t� θ1

t =

(P 1

DER − jQ1DER

V 1k� − θ1

k

)(R1 + jX1

)+ V 1

k� θ1

k, (3.17)

where

R1,2 = Rf ,

R0 = Rf + 3Rn, (3.18)

X1,2 = Xf ,

X0 = Xf + 3Xn.

The VSC sequence- and phase-frame modulation indices are given by

m012 =V012

t

KinvVdc

, (3.19)

mabc = Tm012, (3.20)

where Kinv is the phase-to-neutral converter constant and is determined based on the

adopted modulation technique, as shown in Table 3.1 [95], and

mabc =[

ma � θat mb � θb

t mc � θct

]′, (3.21)

m012 =[

m0 � θ0t m1 � θ1

t m2 � θ2t

]′. (3.22)


3.4.3 Mitigating the VSC Operating Limits Violation

Subsequent to evaluating the internal parameters of the interface-VSC, its operating

limits are checked to achieve a power-flow solution that satisfies all the VSC’s constraints.

If any violation is detected, the voltage and/or power set points of each converter, i.e.,

Vsp, Psp−DER, and Qsp−DER, are updated based on the following proposed strategies.

3.4.3.1 Mitigating the Phase Current Limit Violation

If any of the DER phase currents (Ia,b,cDER) exceeds the maximum phase current limit, the

specified real and reactive power components associated with each VSC unit are updated

using

P 1DER,ct+1|x =

1

3Psp−DER,ct × Iph−max

max − violate(Ia,b,cDER−ct

) ,

Q1DER,ct+1|x =

1

3Qsp−DER,ct × Iph−max

max − violate(Ia,b,cDER−ct

) , (3.23)

where ct is the SFPS current iteration index and max−violate(Ia,b,cDER,ct

)is the magnitude

of the VSC largest violating phase current corresponding to iteration ct. Suffix x refers to

the VSC power set-points satisfying the VSC maximum current constraint. It should be

noted that if the DER unit is controlled to operate at a constant power-factor, then the

real and reactive power set-points are simultaneously updated using (3.23). Otherwise,

the DER reactive power contribution is reduced first to alleviate the violation while the

real-power set-point remains unaltered.

3.4.3.2 Mitigating the Reactive Power Limit Violation

For PV-controlled DER units, if the reactive power limit is hit, the specified positive

sequence voltage for the corresponding bus is updated using

Vsp,ct+1|y =

√Qmax × X1

cct

, (3.24)

where

cct =V 1

t,ct × cos(θ1

t,ct − θ1k,ct

)Vsp,ct

− 1. (3.25)

Equation (3.24) is the solution of (3.17) after replacing Q1 with Qmax and assuming

that R1 is much smaller than X1. Suffix y refers to the VSC voltage set-point satisfying


the maximum reactive power constraint.

It should be noted that, unlike the conventional N-R power-flow algorithms where

the violating PV bus is switched to PQ bus [72, 96, 97], the proposed approach of Sec-

tion 3.4.3.2 uses the closed form given by (3.24) and (3.25) to update the specified bus

voltage for the next iteration, Vsp,ct+1, such that the reactive power remains within the

acceptable operating limits. Consequently, the Jacobean matrix and states vector do not

require restructuring, corresponding to bus-type changing. This simplifies the algorithm

implementation and programming.

3.4.3.3 Mitigating the Phase Modulation Index Limit Violation

If any of the DER phase modulation indices (ma,b,c) exceeds the maximum phase modu-

lation index limit (mph−max), the following procedure is executed:

1. Set the violating modulation index equal to mph−max

2. Re-evaluate V 1t using (3.19) and (3.20)

3. Update P 1DER,ct+1|z and Q1

DER,ct+1|z (P 1DER|z and V 1

sp|z) for PQ (PV) units using

(3.17). Suffix z refers to the VSC set-points satisfying the maximum modulation

index constraint.

3.4.3.4 Updating the Interface VSC Reference Set-Points

The VSC reference set-points, selected prior to the (ct + 1)st power-flow iteration, must

satisfy all the aforementioned limits. As such, the VSC reference set-points (P 1DER,ct+1,

Q1DER,ct+1, Vsp,ct+1) are selected as:

P 1DER,ct+1 = min(P 1

DER,ct+1|x, P 1DER,ct+1|z, Psp−DER/3), (3.26)

Q1DER,ct+1 = min(Q1

DER,ct+1|x, Q1DER,ct+1|z, Qsp−DER/3) for PQ DER units,(3.27)

Vsp,ct+1 = min(Vsp,ct+1|y, Vsp,ct+1|z, Vsp) for PV DER units. (3.28)

3.5 Sequential-SFPS

The procedures of Sections 3.4.2 and 3.4.3 are implemented as an interleaved step that

is iteratively executed subsequent to each SFPS iteration. The complete algorithm is

depicted in the flow chart of Fig. 3.5.

As seen from Fig. 3.5, the entire algorithm is decomposed into three main subroutines.

First, the system power-flow solution and the interface-VSC terminal conditions are


Figure 3.5: Flow chart of the proposed Sequential-SFPS


evaluated using the SFPS. Then, the interface-VSC internal currents and voltages are

calculated. Finally, the VSC reference set-points are updated to fulfil all the interface-

VSC’s constraints’ prior to proceeding to the next SFPS iteration. Thus, the algorithm

sequentially iterates between the SFPS and the updating algorithm. This is the reason

the term ”sequential” is emphasized for the proposed algorithm.

It should be noted that unlike the method presented in [32] and [34], where the

interface VSC constraints are evaluated after the final convergence of the power-flow

algorithm, the proposed method detects the violation once it occurs at any iteration of

the SFPS and automatically updates the VSC power and/or voltage set-points prior to

succeeding to the following power-flow iteration to ensure that all the constraints are

fulfilled. Hereafter, the method presented in [32] and [34] will be referred to as ”non-

sequential method”.

3.6 3ϕ VSC Model Validation

To evaluate the numerical accuracy of the proposed VSC models of Fig. 3.2 and verify

the validity of the Sequential-SPFS algorithm of Fig. 3.5, the six-bus study system of

Fig. A.1, duplicated as Fig. 3.6 for the ease of reference, is selected and four case stud-

ies (Case-1 to 4 ) are conducted. G1 is a voltage-controlled three-phase synchronous

generator with enough capacity to compensate the system slack, and is modeled as a

three-phase constant voltage source with negative and zero-sequence impedance. G2 is

a three-phase VSC-coupled DER unit, and is modeled as a controlled voltage source

behind the interface-VSC filter. As earlier stated in Chapter 1, the reason for selecting

this adequately small system is to be able to simulate the system in time-domain in the

PSCAD/EMTDC platform, and consequently, verifying the numerical accuracy of the

VSC models and the SFPS. The system parameters and loading profile are detailed in

Appendix A.1. The parameters of G1 and G2 are given in Table 3.2. Two applications of

the Sequential-SFPS to large distribution systems, with different R/X ratios and network

topologies, are presented in the next section.

To validate the proposed interface VSC model, the power-flow algorithm based on

the flow chart of Fig. 3.5, including the DER models of Section 3.3, is implemented

in the MATLAB® platform. The detailed model of the study system is also developed

in the PSCAD/EMTDC time-domain software to serve as the benchmark for valida-

tion of the interface-VSC model and the SPFS results. As discussed in Chapter 1, the

PSCAD/EMTDC simulation environment is selected since it contains detailed and widely

used time-domain models of power system components and allows incorporating various


Figure 3.6: Single line diagram of the six-bus test system

Table 3.2: Parameters of G1 and G2 of Fig. 3.6 (Sbase= 1000 kVA)G1 G2

Vbase=4.16 kV, Vbase=4.16 kV,X2=0.004, Rf=4 × 10−4, Xf= 0.105X0=0.02, Vdc=3.2, Qmax=±0.7Vsp=1.045 Iph−max=0.75, mph−max=1

Kinv = 12√

2


controls for the interface VSC.

For Case-1 to Case-3 , the system operating point is adjusted to prevent any vi-

olation of the converter operating constraints. This enables direct validation of the

interface-VSC model without considering the sequential part of the algorithm of Fig.

3.5.

3.6.0.5 Case-1

For this case study, G2 is a 3ϕ three-wire voltage-controlled VSC-coupled DER unit

equipped with voltage and real power controllers (PV mode) [92]. The unit is interfaced

to Bus-5 via a three-phase Δ/Yg transformer. G2 is to regulate the positive-sequence

component of the voltage at Bus 6 to 1.05 pu and injects 1 pu real power. The power-

flow results and the calculated internal parameters of G2 are given in Table 3.3 which

concludes that:

• The phase modulation indices of G2 from both solutions are equal and verify that

the DER unit is only generating balanced three-phase terminal voltage. The pos-

itive sequence component of Bus 6 is 1.05 as required. However, the voltage at

Bus-6 includes 0.011 pu of negative-sequence voltage due to the system unbalanced

conditions.

• Since the VSC is not controlled with respect to the negative-sequence frame, it is

subjected to negative-sequence current exchange of about 0.1 pu. The magnitude

of this current depends only on the magnitude of the negative-sequence component

of the voltage at bus-6 and the impedance of the VSC filter. The flow of excessive

negative-sequence current, in addition to the positive-sequence current, can subject

the converter switches to over-current conditions.

• Although G2 is controlled to inject 1.0 pu real-power, it actually injects 0.9994 pu

instead. The reason is that the uncontrolled negative-sequence current flow into

the DER unit causes 0.0006 pu of filter power losses.

3.6.0.6 Case-2

In this case study, G2 is a 3ϕ three-wire current-controlled VSC-coupled, DER unit

equipped with positive- and negative-sequence dq-current controllers [37]. G2 is con-

trolled to inject (i) 1.0 pu power at unity power factor and (ii) 0.03 pu negative-sequence

current for active islanding detection. The power flow results and the calculated internal

parameters of G2 are given in Table 3.4. Table 3.4 indicates:


Table 3.3: Power-Flow Results of Case-1

BusPhase A Phase B Phase C

Magnitude (pu) Angle(degrees) Magnitude (pu) Angle(degrees) Magnitude (pu) Angle(degrees)A B A B A B A B A B A B

1 1.045 1.046 -0.016 -0.013 1.043 1.044 -119.08 -120.026 1.045 1.045 120.09 120.0392 1.031 1.035 27.19 27.04 1.039 1.031 -93.021 -92.675 1.037 1.037 146.931 147.343 1.039 1.039 25.481 25.467 1.021 1.025 -94.201 -94.148 1.038 1.036 145.973 146.1414 1.047 1.044 25.193 25.219 1.024 1.024 -94.812 -94.707 1.04 1.037 145.968 146.0245 1.051 1.049 25.389 25.475 1.029 1.032 -94.563 -94.581 1.041 1.041 146.083 146.1996 1.056 1.058 -3.905 -3.801 1.049 1.052 -125.081 -124.714 1.041 1.041 115.891 116.068

Calculated IaDER = 0.556� − 66.73 Sa = 0.588� 62.93 ma = 0.982

Internal IbDER = 0.69� − 177.42 Sb = 0.731� 52.71 mb = 0.982

Parameters of G2 IcDER = 0.721� 48.73 Sc = 0.75� 67.34 mc = 0.982

A: PSCAD/EMTDC Results, B: SFPS Results




1 1.046 1.046 0.0 0.001 1.044 1.045 -119.991 -120.028 1.045 1.045 119.996 120.0262 1.022 1.021 27.701 27.624 1.016 1.016 -92.236 -92.231 1.018 1.02 147.828 147.8793 1.013 1.011 26.483 26.455 0.998 0.999 -92.967 -93.398 1.007 1.007 147.161 147.1384 1.003 1.009 26.391 26.276 0.988 0.989 -93.681 -93.599 1.005 1.004 147.159 147.2825 1.006 1.007 26.512 26.636 0.985 0.987 -92.812 -93.004 1.002 1.003 147.641 147.7176 1.009 1.012 -2.263 -2.567 0.994 0.994 -123.641 -123.364 0.991 0.991 117.832 117.939

Calculated IaDER = 0.364� − 2.44 Sa = 0.368� − 0.12 ma = 0.895

Internal IbDER = 0.321� − 127.43 Sb = 0.319� 4.06 mb = 0.882

Parameters of G2 IcDER = 0.318� 121.89 Sc = 0.316� − 3.95 mc = 0.875


• The three-phase modulation indices are not equal and can be decomposed into

positive (0.884) and negative (0.012) sequence modulation indices. The negative-

sequence modulation index corresponds to 0.03 pu negative-sequence current injec-

tion.

• The DER unit is controlled to inject 1.0 pu power at unity power factor. However,

the sum of the injected power components through the three phases of the VSC

is 1.002 pu. The 0.002 pu power corresponds to the 0.03 pu negative sequence

current injection. The total 3ϕ real-power is different from that of (Case-1 ),

which indicates the impact of the negative-sequence control strategy on the DER

power-flow.

3.6.0.7 Case-3

In this case, G2 is a 3ϕ four-wire current-controlled VSC-coupled DER unit controlled

to inject 1.0 pu power at unity power factor and compensate for the unbalanced load





1 1.044 1.046 0.12 0.007 1.043 1.045 -120.035 -120.033 1.049 1.045 119.823 120.0262 1.021 1.019 27.381 27.176 1.012 1.013 -92.326 -92.724 1.015 1.018 147.231 147.43 1.013 1.01 25.601 25.675 0.992 0.992 -93.921 -94.26 1.003 1.003 146.023 146.2344 1.014 1.01 25.135 25.307 0.981 0.980 -95.036 -94.752 0.998 0.998 145.968 146.1995 1.01 1.008 25.395 25.462 0.979 0.976 -94.643 -94.494 0.994 0.996 146.632 146.4556 1.005 1.005 25.091 25.091 0.971 0.967 -95.124 -94.868 0.991 0.990 146.256 146.329

Calculated IaDER = 0.322� 25.89 Sa = 0.324� − 0.8 ma = 0.889

Internal IbDER = 0.378� − 91.24 Sb = 0.365� − 3.63 mb = 0.853

Parameters of G2 IcDER = 0.315� 141.24 Sc = 0.311� 5.09 mc = 0.878

A: PSCAD/EMTDC Results, B: Developed Software Results

currents at Bus-6 (PQ mode) [35]. To study the unbalanced performance of G2, an

unbalanced load, identical to the load at bus-4, is connected to Bus-6. Transformer T2

of Fig. 3.6 is altered to a Yg/Yg configuration to allow four-wire VSC connection. The

power-flow results and the calculated internal parameters of G2 are given in Table 3.5.

Table 3.5 indicates:

• Since the VSC is controlled to compensate for the unbalanced load currents at Bus

6, the three-phase modulation indices force the VSC to generate negative (0.018

pu) and zero (0.006 pu) sequence voltages at its terminals corresponding to the

desired unbalanced currents.

• The DER unit is intended to inject 1 pu power at unity power factor. However, due

to the compensation of the negative- and zero-sequence load currents of Bus-6, the

net injected power is 0.998 pu. Again, this value is different from those of (Case-

1 ) and (Case-2 ). This difference could not been quantified unless the proposed

VSC model and the SFPS are used to study the DER 3ϕ PFA.

As concluded from Tables 3.3-3.5, the maximum voltage magnitude error for the six

busses, in all three case studies, is less than 0.8%. This is an acceptable error and it arises

due to the different nature of the two solvers. The PSCAD/EMTDC, as an EMTP soft-

ware, solves the system differential equations. On the other hand, the developed program

solves the system steady-state power-flow equations, which are linearized simultaneous

algebraic equations. The good agreement between the results of the two solvers indicates

that the unified VSC-coupled DER model and the SFPS are accurate.




Mag. Angle Mag. Angle Mag. Angle(pu) (deg.) (pu) (deg.) (pu) (deg.)

1 1.046 -0.012 1.044 -120.036 1.045 120.0482 1.032 26.741 1.027 -92.943 1.034 147.1393 1.032 24.860 1.016 -94.735 1.029 145.7494 1.037 24.424 1.012 -95.510 1.029 145.5675 1.044 24.733 1.019 -95.275 1.033 145.8216 1.054 -4.357 1.042 -125.583 1.028 115.620

3.6.1 Case-4: Sequential-SFPS Validation

The fourth case study (Case-4 ) is conducted to validate the entire algorithm of Fig. 3.5,

including the sequential evaluation of the VSC operating limits. In this case study, G2 is

interfaced to Bus-6 via a 3ϕ three-wire voltage-regulated VSC. The operating conditions

for Case-4 are identical to Case-1 except that the load at Bus-4 is 1.5 times higher.

However, when the algorithm of Fig. 3.5 is applied to scenario of Case-4 , without

imposing the operating limits of G2, the positive-sequence reactive power injected by

G2 is 0.734 pu and the phase modulation index is 1.005. According to Table 3.2, the

corresponding maximum positive-sequence reactive power injected by G2 and the phase

modulation index should not exceed 0.7 pu and 1.0 respectively. This indicates that the

power-flow solution is practically not acceptable and violates the limits.

When the operating limits of G2 are considered, the sequential-SFPS adjusts the

voltage set-point (Vsp) of G2 to 1.042 corresponding to 0.565 pu reactive power injection

at 0.971 phase modulation index. The maximum phase current injected by G2 is 0.713

pu. Thus, all the operating constraints of G2 are satisfied. The algorithm converges in

three iterations. The complete power-flow solution for Case-4 is given in Table 3.6.

3.7 Computation Efficiency of the Proposed Sequential-

SFPS

As indicated in Section 3.5, there are two distinct techniques to implement the interface-

VSC operating limits in the power-flow solver; the non-sequential [32,34] and the sequen-

tial approaches. This section reports the application of the Sequential-SFPS algorithm

of Fig. 3.5 to two benchmark distribution systems with different R/X ratios and network

topologies, i.e., the CIGRE MV distribution network [98] and the IEEE 34-bus feeder [99]


to (i) verify the feasibility of the developed Sequential-SFPS for large and realistic size

power systems and (ii) demonstrate the convergence superiority of the proposed approach

compared to the non-sequential method [32,34]. The single-line diagrams and parameters

of both test systems are detailed in Appendix A.2 and Appendix A.4, respectively.

The 12.47 kV, three-phase, four-wire CIGRE distribution network of Fig. A.2 is

equipped with two DER units:

1. DER1 is a 3ϕ three-wire voltage-controlled VSC-coupled DER unit connected to

Bus-8 via a three-phase transformer (200 kVA, 12.47/4.16 kV, Yg/�) and is rated at

200 kVA, 4.16 kV. DER1 operates as a PV unit to maintain the positive-sequence

voltage component of its corresponding bus at 1 pu and inject 200 kW into the

network.

2. DER2 is a 3ϕ three-wire current-controlled VSC-coupled DER unit connected to

Bus-3 via a three-phase transformer (150 kVA, 12.47/4.16 kV, Yg/�). DER2 is

rated at 150 kVA, 4.16 kV. DER2 operates as a PQ unit to inject 150 kVA at

unity power-factor and inject 0.03 pu negative-sequence current for active islanding

detection [37].

The 24.9 kV, three-phase, four-wire IEEE 34-bus feeder of Fig. A.4 is equipped with

three VSC-coupled DER units:

1. DER3 is a 3ϕ four-wire current-controlled VSC-coupled DER unit connected to

Bus-814 via a three-phase transformer (100 kVA, 24.9/4.16 kV, Yg/Yg). DER3 is

rated at 100 kVA, 4.16 kV and operates as a PQ unit to inject 100 kVA at unity

power-factor and compensate for the unbalanced load currents at Bus-814.

2. DER4 and DER5 are 3ϕ three-wire voltage-controlled VSC-coupled DER units

connected to Bus-858 and Bus-836, respectively. Each unit is connected to the grid

via a three-phase transformer (100 kVA, 24.9/4.16 kV, Yg/�). Each unit is rated

at 100 kVA and 4.16 kV. Both units operate as PV units to maintain the positive-

sequence voltage component of their corresponding bus at 1.0 pu and inject 1.0 pu

active power into the network.

The internal parameters of the DER1-DER5 are the same as those of unit G2 of Table

3.2.

The non-sequential power-flow algorithm, reported in [32, 34], is implemented in the

MATLAB® platform. The sequential and the non-sequential programs are applied to

evaluate the power-flow solution of the CIGRE MV distribution network and the IEEE

34-bus feeder.


Figure 3.7: Comparison between the sequential and the non-sequential power-flow algo-rithms in terms of the convergence speed

Table 3.7: Comparison Between the Sequential and the Non-Sequential Power-Flow Al-gorithms in Terms of the Total Number of Jacobean Matrix Evaluations/Inversions

Test Proposed Non-sequentialSystem sequential-SFPS methodSix-bus

3 6test systemCIGRE MV

4 6distribution network

IEEE 34-bus7 15

feeder

The power-flow results of both algorithms favorably agree. Fig. 3.7 compares the

convergence speed of the two algorithms and indicate that the Sequential-SFPS provides

a superior convergence rate.

Another figure of merit of the Sequential-SFPS with respect to the non-sequential

approach is the number of evaluations/inversions of the Jacobian matrix to obtain the

power-flow solution, as shown in Table 3.7. The results of Fig. 3.7 and Table 3.7 are

based an Intel® Core2Duo™, 3.16 GHz processor. Figure 3.7 and Table 3.7 show that

the sequential-SFPS outperforms the non-sequential method.

The computational efficiency of the Sequential-SFPS, as compared to the non-sequential

method, is explained as follows. As indicated in Table 3.7, the Sequential-SFPS requires

less number of Jacobian matrix evaluations/inversions, which is the most time-consuming

part of the power-flow algorithm. In the proposed sequential approach, the VSC con-

straint evaluation of the DER units, and consequently updating the voltage and/or power

set-points, is formulated as an interleaved step with each SFPS iteration. Thus, the sub-

sequent power-flow iteration is not executed until all the VSC constraints are fulfilled.


However, the non-sequential method evaluates the DER constraints subsequent to the

convergence of the entire SFPS algorithm. This results in larger number of power-flow

iterations and Jacobian matrix evaluations/inversions, as compared to the Sequential-

SFPS.


This chapter develops a unified sequence-frame-based, three-phase, fundamental-frequency

model for VSC-coupled DER units for balanced and unbalanced power-flow analysis. The

proposed model accommodates (i) both three-wire and four-wire VSC configurations, (ii)

various VSC control features/strategies, and (iii) the operating limits of the interface-

VSC, under balanced and unbalanced power-flow conditions.

This chapter also presents the necessary modifications to embed the unified model

in the SFPS. In contrast to the existing methods, the algorithm utilizes a sequential

iterative process with respect to the network and the VSC solutions to guarantee that

the power-flow solution adheres to the interface VSC constraints and operating limits.

Chapter 4

Power-Flow Model of Type-3 Wind

Generation Unit: Mathematical

Formulation1

4.1 Introduction

This chapter develops a comprehensive mathematical model of the Type-3 DER unit,

i.e., a doubly-fed asynchronous generator (DFAG) and its associated converter system,

for three-phase PFA using the SFPS. First, a sequence frame, steady-state, fundamental-

frequency model of a generic Type-3 DER unit is developed to represent (i) the control

capabilities and (ii) the operating limits of the rotor-side and the grid-side converters

under balanced and unbalanced power-flow conditions. New strategies to determine the

reference set-points of the controllers for compliance with the operating limits, are also

presented. The model, including the proposed strategies, is incorporated with SFPS. For

numerically accurate and computationally efficient solutions, the sequential approach,

proposed in Chapter 3, is used to impose the operating limits of the Type-3 DER unit.

Applications and validation of the developed model and the set-points update strategies,

and evaluation of the computational efficiency of the power-flow algorithm are covered

in Chapter 5.

1The work presented in this chapter has been accepted for publication, and will appear in M.Z. Kamhand R. Iravani, “Three-Phase Model and Power-Flow Analysis of Wind-Driven Doubly-Fed AsynchronousGenerators Part I: Model Development,” IEEE Trans. Sustainable Energy, April 2011, Manuscript IDTSTE-00186-2010.

53

Chapter 4. Power-Flow Model of Type-3 WTG DER Units 54

4.2 Classification of Wind Turbine Generators

Over the past two decades, wind energy has gained the most attention as a clean,

environmentally-friendly, and free source of electricity generation [53, 54, 100]. Wind

turbines generating units (WTGUs) are classified into three main categories:

• fixed speed units (Type-1 WTGUs)

• semi-variable speed units (Type-2 WTGUs)

• variable speed units (Type-3 and Type-4 WTGUs)

4.2.1 Type-1 WTGU

This category deploys the squirrel cage induction generator (SCIG) which is driven by

a wind turbine either having a fixed turbine blade angle (stall regulated fixed speed

WTGU) or having a pitch controller to regulate the blade angle (pitch regulated fixed

speed WTGU), Fig. 4.1(a) [100]. The rotor speed is almost fixed. Type-1 WTGUs

are directly connected to the grid via a step-up transformer. For rotor speeds higher

than the synchronous speed, the unit injects active power into the grid. Reactive power

compensation is provided to Type-1 generators through the grid and fixed shunt ca-

pacitors (for power factor correction purpose). The amount of real and reactive power

supplied/consumed by Type-1 WTGUs solely depend on the turbine and generator char-

acteristics, wind speed, and grid voltage.

4.2.2 Type-2 WTGU

Pitch controlled turbines and wound rotor induction generators (WRIG) are deployed in

this category. Rotor speed can be varied within a range of 10% using an electronically-

controlled variable resistor connected to the machine’s rotor, Fig. 4.1(b). Type-2 WTGUs

are directly connected to the grid via a step-up transformer. Reactive power compensa-

tion is identical to Type-1.

4.2.3 Type-3 WTGU

Figure 4.1(c) depicts a schematic diagram of a Type-3 variable-speed WTGU. A Type-3

unit consists of a (i) wind turbine and gear-box, (ii) a DFAG, (iii) a rotor-side converter

(RSC), and (iv) a grid-side converter (GSC). Both converters are VSCs, and connected


(a)

(b)

(c)

(d)

Figure 4.1: Schematic diagrams of the four types of wind-turbine generating systems:(a) Type-1, (b) Type-2, (c) Type-3, and (d) Type-4


using the back-to-back (B2B) configuration with a common DC link to operate as a

frequency-converter.

Among the four types of WTGUs, Type-3 WTGUs are the most deployed due to their

salient capabilities, i.e., (i) constant frequency/variable speed operation, (ii) independent

four-quadrant active and reactive power control, (iii) reactive power support, and (iv)

reduced converter ratings [101–103]. Hereafter, “Type-3” is used to refer to the DFAG,

RSC, GSC, and the DC link.

4.2.4 Type-4 WTGU

Variable-speed operation can also be achieved using direct-driven squirrel-cage induc-

tion/permanent magnet synchronous generator units with a full-scale B2B VSC to inter-

face the stator to the host grid, Fig. 4.1(d) [104]. For generators with large number of

poles, the gearbox may be eliminated to increase the overall system efficiency. Type-4

WTGU has the same advantage of the Type-3 units. However, the power-electronic con-

verter should be sized to overpass the full rating of the machine to provide the adequate

reactive power compensation [104].

4.3 Power-Flow Models of Type-3 DER Units: Re-

view

The existing WTGU steady-state models focus on Type-1 and Type-2 arrangements

[46,47,51–54,62,105]. While the DER model developed in Chapter 3 encompasses Type-

4 WTGU, the available Type-3 models neither consider the system unbalanced conditions

nor represent the unit operating limits [49,50].

In [50], a primitive steady-state Type-3 model is developed to assess the voltage

stability limits of electrical power systems, where PV bus with reactive power limits is

used to model voltage-regulated Type-3 units while constant PQ bus is used to model

power-factor controlled units. Such model can neither address the unbalanced operation

of the Type-3 unit nor the impacts of the power-electronic converters’ operating limits.

An iterative method is developed in [49] to consider the RSC current limits. However,

the model neither includes all the other Type-3 operational limits nor considered the

unbalanced grid conditions on the unit’s performance. The unbalanced models described

in [51] and [62] are developed in the sequence-components frame, but are only applicable

for fixed-speed wind-driven units. The impact of the operational limits of the interfacing


power electronic converters should be considered for accurate modeling of the WTGUs

[106].

4.4 The Scope of the Chapter

The Type-3 WTGU is either connected to a distribution system as a single distributed

generation (DG) unit [107] or constitutes a WTGU of a large wind farm which is inter-

faced to a transmission system [108]. The former case is the main focus of this chapter.

As earlier emphasized in Chapter 2, distribution systems are inherently unbalanced. For

the scenario that a Type-3 WTGU is interfaced to a distribution system, the voltage

unbalance should be properly addressed and quantified for control and operation of the

unit. Unbalanced voltage at the Type-3 terminal can lead to erroneous tripping due to

excessive DFAG stator current unbalance, excessive rotor surface heating, and mechanical

damage as a result of power/torque oscillations [78].

The scope of this chapter is to develop a steady-state model and a PFA algorithm for

a generic Type-3 DER unit, operating as a DG unit under balanced/unbalanced network

conditions. Considering various control capabilities of Type-3 unit, the developed model

addresses:

• voltage/frequency (PV) control mode (in case of islanded operation [109]) or con-

stant power-factor or active/reactive power (PQ) controls (in the grid-connected

mode),

• specific control actions to mitigate the stator voltage unbalance impact [78–83],

• operational limits of the unit and its associated power-electronic converters, i.e.,

maximum positive- and negative-sequence currents and modulation indices.

The developed model can also be adopted for power-flow analysis and parameter/set-

point adjustment of a wind farm composed of Type-3 WTGUs. The equivalent steady-

state model of a Type-3 based wind farm, with respect to the wind farm point of con-

nection, for power-flow analysis of an interconnected power system is provided in [110]

and not discussed in this chapter.


4.5 Proposed Sequence-Frame Model of A Type-3

DER Unit

This section extends the VSC model of Chapter 3 to develop a sequence-frame, steady-

state model of the Type-3 DER unit. The VSC positive-sequence model is a power/voltage

source, while the negative- or the zero-sequence counterpart comprises a shunt combina-

tion of (i) a controlled current source and (ii) a fictitious impedance.

4.5.1 Model Assumptions

Figure 4.2 shows a schematic diagram of a Type-3 DER unit coupled to the host system

at the PC. The proposed Type-3 model is based on the following assumptions:

• The GSC controllers regulate the common DC-link voltage under steady-state con-

ditions.

• The double-frequency component of the DC-link voltage, due to the system unbal-

ance, is negligible.

• Only the fundamental-frequency model of the Type-3 is of interest, i.e., the har-

monic effects are discarded.

• The DER unit is synchronized to the grid using a phase-locked loop (PLL) system

that also extracts the sequence-components frame of the PC voltage [36].

• The RSC and/or GSC are equipped with dedicated controllers to provide specific

control functions with respect to the negative- and/or zero-sequence components

of the PC variables.

• the losses associated with RSC and GSC are neglected.

• The DER negative- and zero-sequence power exchange with the host grid are neg-

ligibly small compared to their positive-sequence counterpart. As such, the Type-3

WTG-based DER positive-, negative-, and zero-sequence-frame models are assumed

to be fully decoupled.

4.5.2 Positive-Sequence Model of Type-3 DER Unit

Under (un)balanced grid conditions, the RSC is primarily controlled to (i) extract the

maximum stator real power (Ps) at a given wind speed, and (ii) regulate the stator


Figure 4.2: Detailed schematic diagram of a Type-3 wind-driven generation system

reactive power (Qs). This is realized by regulating the rotor real and reactive power

components (Pr, Qr), Fig. 4.2. At steady-state, (i)the GSC positive-sequence real power

set-point (Pg) is adjusted to exchange Pr with the grid. Depending on the control strategy,

(ii) the GSC reactive power is adjusted to provide reactive power support to regulate

either the power-factor or the stator terminal voltage [109]. In this work, the Type-

3 operates in the PQ (PV) mode if a constant reactive power/power-factor (terminal

voltage) is desired. Figure 4.3(a) shows the positive-sequence model of the Type-3 unit.

4.5.2.1 PV mode of operation

When the Type-3 DER unit operates in the PV mode [109], its positive-sequence model

with respect to the PC is an ideal voltage source behind the PC bus. The specified

voltage magnitude |V1PC | at the PC and the injected positive-sequence real power P 1

DER,

in per-unit, are

|V1PC | = Vsp, (4.1)

P 1DER =

Ps−spec + Pg−spec

3, (4.2)

where Vsp, and Ps−spec (Pg−spec) are the per-unit terminal voltage and three-phase stator

(GSC) real power reference set-points respectively. At steady-state, the relation between

Pg−spec, Pr−spec, and Ps−spec can be simplified to [111]

Pg−spec = −Pr−spec � −s1Ps−spec. (4.3)


(a)

(b)

(c)

Figure 4.3: Proposed sequence-frame, fundamental-frequency, steady-state model ofType-3 DER unit, (a) positive-sequence model, (b) negative-sequence model, (d) equiv-alent negative-sequence model.


In (4.3), s1 is the positive-sequence slip and is given by

s1 =ωs − ωr

ωs

, (4.4)

where ωs and ωr are the synchronous and rotor speeds, respectively.

4.5.2.2 PQ mode of operation

When the Type-3 unit is controlled in the PQ mode, it is represented as a constant power

source. In this case, the unit positive-sequence real power contribution is given by (4.2)

and the exchanged positive-sequence reactive power, Q1, is

Q1DER =

Qs−spec + Qg−spec

3. (4.5)

In Fig. 4.3(a), I1s−net/I

1g−net is the net positive-sequence current exchange between the

stator/ GSC and the PC bus.

4.5.3 Negative-Sequence Model of Type-3 DER Unit

As earlier discussed in Section 4.4, the unbalanced operation of a Type-3 unit is detri-

mental to its performance and lifetime [78]. The RSC and/or the GSC can be controlled

to inject negative-sequence currents to mitigate the effects of unbalanced stator voltage.

As discussed in Chapter 3, the VSC negative-sequence model is a parallel combination

of a current source (ICTRL) and an impedance (ZCTRL). Replacing the RSC and GSC

with this model yields the negative-sequence model of Fig. 4.3(b), where Rs (Xs) and Rr

(Xr) are the stator and rotor resistances (leakage reactances), Xm is the magnetizing re-

actance. I2r−CTRL, Z2

r−CTRL, I2g−CTRL, and Z2

g−CTRL are selected to realize the secondary

(negative-sequence) control objective. The negative-sequence slip, s2, is

s2 =ωs + ωr

ωs

= 2 − s1. (4.6)

4.5.4 Equivalent Negative-Sequence Model of Type-3 DER Unit

The negative-sequence model of Fig. 4.3(b) can be further simplified using the Norton cir-

cuit reduction technique, i.e., replacing the RSC and the asynchronous machine models,

shown in Fig. 4.3(b) inside the two leftmost dashed blocks, by an equivalent circuit con-

sisting of a current source (I2s−CTRL−equiv) in parallel with an impedance (Z2

s−CTRL−equiv),


Fig. 4.3(c). Z2s−CTRL−equiv and I2

s−CTRL−equiv are given by (4.7) and (4.8), respectively.

Z2s−CTRL−equiv = Rs + jXs +

jXm ×(

Rr

s2 + jXr + Z2r−CTRL

)Rr

s2 + j(Xr + Xm) + Z2r−CTRL

(4.7)

I2s−CTRL−equiv =

I2r−CTRL × Z2

r−CTRL × jXm(Z2

r−CTRL + Rr

s2 + jXr + jXm×(Rs+jXs)Rs+j(Xs+Xm)

)(Rs + j(Xs + Xm))

(4.8)

It should be noted that the zero-sequence model of the Type-3 unit is not required

since it is typically connected in delta or an un-grounded-Wye, and thus does not permit

the flow of zero-sequence current [62].

The next section describes the secondary control objectives that can be achieved

by the GSC/RSC controllers. Moreover, it provides the appropriate values of I2r−CTRL,

Z2r−CTRL, I2

g−CTRL, Z2g−CTRL, I2

s−CTRL−equiv, and Z2s−CTRL−equiv to realize these objectives.

4.6 Evaluating Type-3 Negative-Sequence Model Pa-

rameters

The RSC and/or the GSC can be controlled to provide secondary control objectives under

unbalanced conditions. These may include:

1. Balancing the rotor currents.

2. Balancing the stator currents.

3. Mitigating the stator real power double-frequency component.

4. Mitigating the electromagnetic torque/power double-frequency oscillations to pre-

vent rotor mechanical stresses.

5. Mitigating the double-frequency components of the electromagnetic torque/power

and the unit net real power contribution (Ps + Pg) double-frequency component.

A combination of these control objectives can be realized by either the RSC [78–80],

the GSC [81], or their coordinated operation [82,83]. This section deduces the parameters

of the Type-3 unit negative-sequence model, Figs. 4.3(b) and 4.3(c), to include the impact

of these control strategies on the power-flow analysis which is dominantly determined by

the positive-sequence model of Fig. 4.3(a).


4.6.1 Case A: Idle Secondary Control of Type-3 Unit

If both the RSC and the GSC are controlled only based on the positive-sequence dq-

current control method [91], the DER unit will exchange negative-sequence current with

the unbalanced grid. In this case (i) I2r−CTRL, Z2

r−CTRL, and I2g−CTRL are all set to zero,

and (ii) I2s−CTRL−equiv and Z2

s−CTRL−equiv are determined by (4.7) and (4.8) respectively.

Z2g−CTRL is given by

Z2g−CTRL = Rg + jXg, (4.9)

where Rg and Xg are defined on Fig. 4.2.

4.6.2 Case B: Balancing Rotor Currents

The negative-sequence control capability of the RSC can be used to prevent the negative-

sequence current flow in the rotor windings [78], [79], and [80]. The impact of this

control scenario on the steady-state power-flow is determined by setting I2r−CTRL = 0

and imposing Z2r−CTRL = ∞. As a result, I2

s−CTRL−equiv = 0, and by applying L’Hopital

rule to (4.7),

Z2s−CTRL−equiv = Rs + j(Xs + Xm). (4.10)

In addition, if the GSC is controlled to block its negative-sequence current exchange

with the PC bus, then

I2g−CTRL = 0, (4.11)

Z2g−CTRL = ∞. (4.12)

Otherwise, Z2g−CTRL is given by (4.9).

4.6.3 Case C: Balancing Stator Currents

The Type-3 unit can be controlled to block the negative-sequence stator current. This is

realized by controlling the RSC [78], [79], and [80] or the GSC [81] individually.

4.6.3.1 Case C-1: Balancing Stator Currents Via RSC

Applying the Kirchhoff’s voltage law to the stator circuit of Fig. 4.3(b), while neglecting

the stator resistance voltage drop, yields

−j(Xs + Xm)I2s−net + jXmI2

r−net = V2PC . (4.13)


Thus, the negative-sequence stator current I2s−net can be eliminated by controlling the

RSC to inject a net negative-sequence rotor current I2r−net, where

I2r−net =

V 2PC

jXm

. (4.14)

This is realized by setting

Z2r−CTRL = ∞, (4.15)

I2r−CTRL =

V2PC

jXm

. (4.16)

Consequently, Z2s−CTRL−equiv is given by (4.10) and I2

s−CTRL−equiv is given by

I2s−CTRL−equiv =

V2PC

Rs + j(Xs + Xm). (4.17)

4.6.3.2 Case C-2: Balancing Stator Currents Via GSC

The GSC is controlled to force a balanced stator current [81]. At steady-state, applying

Kirchhoff’s current law at the stator bus (bus-PC ) yields

I2s−net + I2

g−net + I2load−PC =

N∑i=1

V2iy

2PC−i

, (4.18)

where I2load−PC is the injected negative-sequence current corresponding to the loads at

the stator bus, V2i is the negative-sequence voltage at bus-i, y2

PC−iis the the negative-

sequence admittance matrix entry corresponding to the PCth row and the ith.

Consequently, the stator current can be balanced by setting Z2g−CTRL = ∞ and

I2g−CTRL =

N∑i=1

V2iy

2PC−i

− I2load−PC . (4.19)

For this case, the parameters of the RSC negative-sequence model, Figs. 4.3(b) and

4.3(c), are

Z2s−CTRL−equiv = ∞, (4.20)

I2s−CTRL−equiv = 0, (4.21)

Z2r−CTRL = I2

r−CTRL = 0, (4.22)


It should be noted that this scenario is unique since Z2s−CTRL−equiv and I2

s−CTRL−equiv

are not evaluated using (4.7) and (4.8), but instead selected based on (4.20) and (4.21),

respectively.

4.6.4 Case D: Mitigating Stator Real Power Double-Frequency

Component

The stator real power is

Ps = �(3VPCI∗s−net

). (4.23)

However, since a space phasor, e.g., F, can be decomposed into two oppositely and

synchronously rotating space vectors F1 and F2 [78], i.e.,

F = F1 + F2e−j2ωst. (4.24)

Thus, (4.23) can be expressed

Ps = �(V1

PC(I1s−net)

∗ + V2PC(I2

s−net)∗)+ �

(V1

PC(I2s−net)

∗ej2ωst)

+ �(V2

PC(I1s−net)

∗e−j2ωst)

, (4.25)

where the double-frequency stator power (Ps−2ωst) is the sum of the last two terms in

(4.25). Ps−2ωst can be eliminated by controlling the RSC to inject a negative-sequence

stator current (I2s−net) that satisfies (4.26) and (4.27).

�(V1

PC(I2s−net)

∗ + V2PC(I1

s−net)∗) = 0, (4.26)

�(V1

PC(I2s−net)

∗ −V2PC(I1

s−net)∗) = 0, (4.27)

where �(.) and �(.) are the real and imaginary parts of a complex quantity, respectively.

Solving (4.26) and (4.27) simultaneously yields

I2s−net = −V2

PC (Ps−spec + jQs−spec)

3|V1PC |2

, (4.28)

where |V1PC | is the magnitude of the positive-sequence stator voltage. Equation (4.28) is

used to calculate the following model parameters of Figs. 4.3(b) and 4.3(c) to guarantee


ripple-free stator output power

Z2r−CTRL = ∞ , (4.29)

I2r−CTRL =

I2s−net (Rs + jXs + jXm) + V2

PC

jXm

, (4.30)

From (4.29) and (4.30), I2s−CTRL−equiv is

I2s−CTRL−equiv = I2

s−net +V2

PC

Rs + jXs + jXm

, (4.31)

where I2s−net is given by (4.28) and Z2

s−CTRL−equiv is given by (4.10).

4.6.5 Case E: Mitigating Double-Frequency Electromagnetic Torque

(Power) Component

Mitigating the double-frequency component in the electromagnetic power of Type-3 unit

is equivalent to eliminating the corresponding component in the stator reactive power

(Qs) [78–80,82,83]. Similar to the analysis of Section 4.6.4, this is realized by controlling

the RSC to inject a negative-sequence stator current component (I2s−net) to impose

�(V1

PC(I2s−net)

∗ + V2PC(I1

s−net)∗) = 0, (4.32)

�(V1

PC(I2s−net)

∗ −V2PC(I1

s−net)∗) = 0. (4.33)

From (4.32) and (4.33), I2s−net is deduced as

I2s−net =

V2PC (Ps−spec + jQs−spec)

3|V1PC |2

. (4.34)

Equations (4.29)-(4.31) are then used to evaluate the parameters of the Type-3 DER

negative-sequence model, Figs. 4.3(b) and 4.3(c).

4.6.6 Case F: Coordinated Control of GSC and RSC

GSC and RSC can be simultaneously controlled to (i) mitigate the double-frequency

electromagnetic power/torque component and (ii) dampen the associated real power

oscillations (Ps−2ωst + Pg−2ωst) [82, 83]. The first objective is realized via the RSC as

discussed in Section 4.6.5. To achieve the second objective, the GSC is controlled to

inject a negative-sequence current component (I2g−net) that cancels out the summation of


Table 4.1: Parameters of the Type-3 Negative-Sequence Model For the Six Cases ofSection 4.6

Case A B C-1 C-2 D E FI2

r−CTRL 0 0 Eq. (4.16) 0 Eq. (4.28) and Eq. (4.30) Eq. (4.34) and Eq. (4.30) Eq. (4.34) and Eq. (4.30)Z2

r−CTRL 0 ∞ ∞ 0 ∞ ∞ ∞I2

s−CTRL−equiv 0 0 Eq. (4.17) 0 Eq. (4.28) and Eq. (4.31) Eq. (4.34) and Eq. (4.31) Eq. (4.34) and Eq. (4.31)

Z2s−CTRL−equiv Eq. (4.7) Eq. (4.10) Eq. (4.10) ∞ Eq. (4.10) Eq. (4.10) Eq. (4.10)

I2g−CTRL 0 0 0 Eq. (4.19) 0 0 Eq. (4.36)

Z2g−CTRL Eq. (4.9) ∞ or Eq. (4.9) ∞ or Eq. (4.9) ∞ ∞ or Eq. (4.9) ∞ or Eq. (4.9) ∞

Ps−2ωst and Pg−2ωst, i.e.,

�(V1

PC

(I2

s−net

)∗ej2ωst

)+ �

(V2

PC

(I1

s−net

)∗e−j2ωst

)+ �

(V1

PC

(I2

g−net

)∗ej2ωst

)+ �

(V2

PC

(I1

g−net

)∗e−j2ωst

)= 0, (4.35)

where I2s−net is given by (4.34). Equation (4.35) yields

I2g−net = −V2

PC (2Ps−spec + Pg−spec + j (2Qs−spec + Qg−spec))

3|V1PC |2

. (4.36)

The sum of the last two terms of (4.35) is equal to Pg−2ωst.

For the last three cases, D-F (Sections 4.6.4 - 4.6.6), the Type-3 DER negative-

sequence model of Fig. 4.3(c) is implemented in the SFPS by evaluating V1PC and V2

PC

subsequent to the ctth power-flow iteration, then updating (4.28) (or (4.34)), (4.30),

(4.31), and (4.36) prior to the (ct + 1)st iteration.

Sections 4.5 and 4.6 reveal that the proposed steady-state fundamental frequency

model of the Type-3 DER unit of Figs. 4.3(a)-4.3(c) can represent the impacts of different

control actions on the steady-state power-flow solution. The expressions describing the

Type-3 negative-sequence model, for the six cases of Section 4.6, are summarized in Table

4.1.

4.7 Type-3 DER Internal Parameters Calculation

Before considering the operational limits of Type-3 unit in the SFPS, the internal pa-

rameters of the RSC and GSC, i.e., modulation indices, converters currents, and reactive

power, should be calculated. Figure 4.4 shows the Type-3 sequence-frame circuit used to

determine these parameters. Using the sequence components of the stator voltage (V1,2PC),

which are evaluated subsequent to each power-flow iteration, the internal parameters of

the GSC and RSC are calculated as follows.


Figure 4.4: Type-3 sequence-frame circuit used to calculate the converters’ internal pa-rameters

4.7.1 Calculating Positive-Sequence Internal Parameters

The positive-sequence internal parameters are calculated based on controlling the DER

unit in the stator voltage oriented (SVO) synchronously rotating reference frame, in

which the positive-sequence q-axis stator voltage component is zero [78]. In the power-

flow analysis, this is achieved by decomposing any phasor (voltage or current) into two

components, in-phase with V1PC (with subscript d) and perpendicular to V1

PC (with

subscript q). If any of these parameters exceeds its limit, voltage and/or real/reactive

power set-points should be updated to satisfy the constraints, as will be discussed in

Section 4.8.3.

4.7.1.1 GSC Positive-Sequence Modulation Index

The GSC positive-sequence modulation index (m1g) can be decomposed into d-axis (m1

gd)

and q-axis (m1gq

) components satisfying

m1g =

√(m1

gd)2 + (m1

gq)2, (4.37)

where

m1gd

+ jm1gq

=V1

g

Kinv × Vdc

. (4.38)

Kinv is the converter constant and is determined based on the adopted modulation strat-

egy, as indicated in Table 3.1 [95]. V1g is given by

V1g = |V1

PC | + I1g−net (Rg + jXg) , (4.39)


where

I1g−net =

Pg−spec − jQg−spec

3|V1PC |

. (4.40)

Substituting for V1g and I1

g−net from (4.39) and (4.40) in (4.38), and considering that Rg

is negligible compared to Xg, yields

m1gd

=|V1

PC |Kinv × Vdc

+XgQg−spec

3Kinv × Vdc × |V1PC |

(4.41)

m1gq

=XgPg−spec

3Kinv × Vdc × |V1PC |

. (4.42)

4.7.1.2 GSC Positive-Sequence Current

The d-axis and q-axis components of the GSC positive-sequence current are

I1gd

=Pg−spec

3|V1PC |

, (4.43)

I1gq

=−Qg−spec

3|V1PC |

, (4.44)

and

|I1g−net| =

√(I1

gd)2 + (I1

gq)2 (4.45)

4.7.1.3 RSC Positive-Sequence Modulation Index

The RSC positive-sequence modulation index (m1r) can be decomposed into d-axis (m1

rd)

and q-axis (m1rq

) components, given by

m1rd

+ jm1rq

=|V1

r|Kinv × Vdc

, (4.46)

where

m1r =

√(m1

rd)2 + (m1

rq)2. (4.47)

Based on the circuit of Fig. 4.4, and exploiting Xs, Xr << Xm, (4.46) can be re-

written as

m1rd

= c1 + APs−spec + BQs−spec, (4.48)

m1rd

= c2 + BPs−spec − AQs−spec, (4.49)


where

c1 =s1|V1

PC |KinvVdc

, c2 =−Rr|V1

PC |KinvVdcXm

,

A =(Rr + s1Rs)

3KinvVdc|V1PC |

, B =s1(Xr + Xs)

3KinvVdc|V1PC |

, (4.50)

Equations (4.48)-(4.50) provide the RSC modulation index components m1rd

and m1rq

.

4.7.1.4 Stator Positive-Sequence Current Calculation

The d-axis and q-axis components of the stator positive-sequence current are

I1sd

=Ps−spec

3|V1PC |

, (4.51)

I1sq

=−Qs−spec

3|V1PC |

, (4.52)

and

|I1s−net| =

√(I1

sd)2 + (I1

sq)2 (4.53)

4.7.2 Evaluating Negative-Sequence Internal Parameters

4.7.2.1 GSC Negative-Sequence Modulation Index

The GSC negative-sequence modulation index (m2g) is related to the GSC negative-

sequence terminal voltage (V2g) based on

m2g =

|V2g|

Kinv × Vdc

, (4.54)

where

V2g = V2

PC + I2g−net (Rg + jXg) , (4.55)

and

I2g−net = I2

g−CTRL − V2PC

Z2g−CTRL

. (4.56)

4.7.2.2 GSC Negative-Sequence Current

The GSC negative-sequence current is given by (4.56).


4.7.2.3 RSC Negative-Sequence Modulation Index

Similar to (4.54), m2r is given by

m2r =

|V2r|

Kinv × Vdc

, (4.57)

where V 2r is given by

V2r

s2= V2

PC + I2r−net

(Rr

s2+ jXr

)+ I2

s−net (Rs + jXs) , (4.58)

and I2r−net is given by (4.13).

4.7.2.4 Stator Negative-Sequence Current

The stator negative-sequence current is determined by

I2s−net = I2

s−CTRL−equiv −V2

PC

Z2s−CTRL−equiv

. (4.59)

4.8 Implementing Type-3 Power-Flow Model

4.8.1 Accommodating the Type-3 DER Model in the SFPS

Consider a Type-3 unit connected to the host distribution system at Bus-k (TYPE3−k).

To embed the model of TYPE3−k, Fig. 4.3, in the SFPS algorithm:

1. Add the inverse of Z2s−CTRL−equiv and Z2

g−CTRL, corresponding to TYPE3−k, to the

entry corresponding to the kth row and the kth column (y2BUS−kk

), given by (2.21),

respectively.

2. Add the summation of the terms I2s−CTRL−equiv and I2

g−CTRL to the kth entry of the

negative-sequence bus-current injection vector (I2BUS−k), given by (2.24).

3. Add the terms P 1DER and Q1

DER, given by (4.2) and (4.5), to the kth entry of the

specified active and reactive power vectors (P 1BUS−k and Q1

BUS−k), given by (2.25)

and (2.26), respectively.

4.8.2 Estimating Type-3 Maximum Operating Limits

This section presents a simple and quick rule of thumb to estimate the maximum per-unit

sequence-frame operating limits for the Type-3 unit.


4.8.2.1 Estimating the Maximum RSC Modulation Index

Using Fig. 4.4, the rotor-side and stator-side voltages can be related using

V1,2r

s1,2= V1,2

PC + I1,2s−net (Rs + jXs) + I1,2

r−net

(Rr

s1,2+ jXr

), (4.60)

which can be roughly approximated to

|V1,2r |

|V1,2PC |

� s1,2. (4.61)

But

m1,2r =

|V1r|

Kinv × Vdc

. (4.62)

Thus,

m1,2r−max � s1,2

maxV1,2PC−max

Kinv × Vdc

. (4.63)

For example, if Kinv = 12√

2, Vdc = 2.7 pu, V 1

PC−max = 1.1 pu, V 2PC−max = 0.04 pu, and

s1max = 0.3, then m1

r−max � 0.4 and m2r−max � 0.1.

4.8.2.2 Estimating Maximum Stator Currents

Combining (4.51) and (4.52), the following relation can be deduced

I1s−net−max =

Ss−spec−max

3V 1PC−min

, (4.64)

where

Ss−spec−max =√

P 2s−spec−max + Q2

s−spec−max. (4.65)

To avoid excessive stator and rotor heating, the negative-sequence stator current I2s−net

can be limited to 10% of its positive-sequence counterpart. For example, if Ss−spec−max =

1.1 pu and V 1PC−min = 0.88 pu, then I1

s−net−max � 0.41 pu and I2s−net−max � 0.04 pu.

4.8.2.3 Estimating Maximum GSC Currents

Similar to (4.64), the following relation can be deduced

I1g−net−max =

Sg−spec−max

3V 1PC−min

. (4.66)


For the Type-3 units, it is a common practice to rate the GSC higher than the RSC

for reactive power support. Consequently, if the GSC is rated at 40% of the machine

rating, and for V 1PC−min = 0.88 pu, then I1

g−net−max � 0.16 pu. Moreover, if the negative-

sequence GSC current is arbitrarily limited to 40 % of its positive-sequence counterpart,

then I2g−net−max � 0.06 pu.

4.8.3 DER Operational Limits

To deduce a feasible power-flow solution, none of the Type-3 DER unit internal param-

eters should exceed their corresponding limits. To impose this requirement, the internal

parameters are calculated as described in Section 4.7. In case of a violation, the reference

set-points of the Type-3 controllers are re-evaluated. This section presents a systematic

approach to update the Type-3 controllers set-points to fulfil all the operational limits

within the context of the SFPS. These limits are:

• GSC positive-sequence modulation index (m1g−max).

• GSC negative-sequence modulation index (m2g−max).

• GSC positive-sequence current (I1g−max).

• GSC negative-sequence current (I2g−max).

• RSC positive-sequence modulation index (m1r−max).

• RSC negative-sequence modulation index (m2r−max).

• Stator positive-sequence current (I1s−max).

• Stator negative-sequence current (I2s−max).

4.8.3.1 Fulfilling GSC Positive-Sequence Modulation Index Limit

Subsequent to the ctth power-flow iteration, if m1ct

g > m1g−max, then re-calculate m1ct+1

gd

and m1ct+1

gqusing

m1ct+1

gd,q= m1ct

gd,q

m1g−max

m1ct

g

. (4.67)

Based on m1ct+1

gd,q, solve (4.41) and (4.42) to determine the new set points used in (ct+1)st

power-flow iteration, i.e., ( V ct+1sp |a and P ct+1

g−spec|a for PV mode, or P ct+1g−spec|a and Qct+1

g−spec|afor PQ mode). Suffix a identifies the reference set-point that satisfies the m1

g limit.


4.8.3.2 Fulfilling GSC Positive-Sequence Current Limit

If |I1ct

g−net| > I1g−net−max, re-calculate I1ct+1

gdand I1ct+1

gqusing

I1ct+1

gd,q= I1ct

gd,q

I1g−net−max

|I1ct

g−net|. (4.68)

Use I1ct+1

gd,qin (4.43) and (4.44) to calculate V ct+1

sp |b and P ct+1g−spec|b for PV mode (or P ct+1

g−spec|band Qct+1

g−spec|b for PQ mode). Suffix b identifies the reference set-point that satisfies the

I1g−net limit.

4.8.3.3 Fulfilling RSC Positive-Sequence Modulation Index Limit

If m1ct

r > m1r−max, re-calculate m1ct+1

rdand m1ct+1

rqusing

m1ct+1

rd,q= m1ct

rd,q

m1r−max

m1ct

r

. (4.69)

Use m1ct+1

gd,qin (4.48) and (4.49) to evaluate P ct+1

s−spec|c and Qct+1s−spec|c. P ct+1

g−spec|c is then

evaluated using (4.3). Suffix c refers to the reference set-point that satisfies the m1r limit.

4.8.3.4 Fulfilling Stator Positive-Sequence Current Limit

If |I1ct

s−net| > I1s−net−max, re-calculate I1ct+1

sdand I1ct+1

squsing

I1ct+1

sd,q= I1ct

sd,q

I1s−net−max

|I1ct

s−net|. (4.70)

I1ct+1

sdand I1ct+1

sqare used in (4.51) and (4.52), respectively, to evaluate P ct+1

s−spec|d and

Qct+1s−spec|d. P ct+1

g−spec|d is then evaluated using (4.3). Suffix d identifies the reference set-

point that satisfies the positive-sequence stator current limit.

4.8.3.5 Updating Positive-Sequence Reference Set-Points

The positive-sequence reference set-points, selected prior to the (ct + 1)st power-flow

iteration, must satisfy all the aforementioned positive-sequence limits. As such, GSC

real power set-point (P ct+1g−spec|) is selected as:

P ct+1g−spec = min(P ct+1

g−spec|a, P ct+1g−spec|b, P ct+1

g−spec|c, P ct+1g−spec|d). (4.71)


Consequently, P ct+1s−spec is calculated using

P ct+1s−spec = −P ct+1

g−spec

s1. (4.72)

For PQ units, Qh+1g−spec is given by

Qct+1g−spec = min(Qct+1

g−spec|a, Qct+1g−spec|b). (4.73)

Similarly, the terminal voltage of PV controlled units is selected as

V ct+1sp = min(V ct+1

sp |a, V ct+1sp |b). (4.74)

For both control strategies (PV or PQ modes), the stator reactive power is given by

Qct+1s−spec = min(Qct+1

s−spec|c, Qct+1s−spec|d). (4.75)

4.8.3.6 Fulfilling Negative-Sequence Operating Limits

The Type-3 negative-sequence operating limits are fulfilled by adjusting the RSC and/or

GSC negative-sequence current injections (I2g−CTRL, I2

s−CTRL−equiv) as follows.

Subsequent to the ctth power-flow iteration, if m2ct

g > m2g−max, set m2ct

g = m2g−max and

update I2ct

g−CTRL|e using (4.54)-(4.56). Suffix e is used to define the GSC current injection

that satisfies the m2g limit.

Similarly, if |I2ct

g−net| > I2g−net−max, set |I2ct

g−net| = I2g−max and use it to update I2ct+1

g−CTRL|fusing (4.56). Suffix f refers to the GSC current injection that satisfies the |I2

g−net| limit.

The GSC negative-sequence current injection used in the (ct+1)st iteration is selected

as

I2ct+1

g−CTRL = min(I2ct+1

g−CTRL|e, I2ct+1

g−CTRL|f ). (4.76)

Using (4.57)-(4.59), the same procedure is followed to specify I2ct+1

s−CTRL.

4.8.4 Sequential SPFS

Subsequent to evaluating the internal parameters of TYPE3−k, the corresponding op-

erating limits are checked, and updated if necessary, to ensure no violations occur. The

steps to determine the internal parameters, evaluate the operating limits, and update the

DER reference set-points are performed sequentially at the end of each power-flow iter-

ation. A flow chart of the Sequential-SFPS, accommodating the Type-3 DER operating


Figure 4.5: Flow chart of the proposed Sequential-SFPS algorithm including the Type-3DER constraints evaluation and the proposed reference-set point updating strategies


limits, is shown in Fig. 4.5.


This chapter introduces a comprehensive, sequence-frame based, three-phase, fundamental-

frequency, steady-state model of the Type-3 DER unit. The developed model can be

adopted for (i) power-flow analysis, (ii) determination of the operating limits, and (iii)

reference set-points adjustment of the Type-3 DER under balanced and unbalanced grid

conditions. The developed model is intended for steady-state/power-flow analysis of a

Type-3 unit that is utilized as a DER unit and interfaced to a distribution system. How-

ever, it can also be used for steady-state and power-flow analysis within a wind farm that

is composed of Type-3 units.

This chapter also incorporates the developed Type-3 sequence-frame model in the

SFPS. Subsequent to each power-flow iteration, the internal parameters of the Type-

3 unit are calculated. If any of the parameters violate the corresponding limits, the

positive- and/or negative-sequence reference set-points of the corresponding Type-3 unit

are updated prior to proceeding to the next power-flow iteration. Thus, the developed

algorithm sequentially iterates between the power-flow of the AC network and the Type-

3 unit to obtain a feasible power-flow solution. The applications and verification of the

developed Type-3 model and the power-flow algorithm are presented in Chapter 5.

Chapter 5

Power-Flow Model of Type-3 Wind

Generation Unit: Model Validation

and Applications1

5.1 Introduction

This chapter presents the implementation and validation of the steady-state, fundamental-

frequency, sequence-frame model of the Type-3 DER unit, accommodated within the

Sequential-SFPS algorithm, developed in Chapter 4. A set of case studies are reported to

(i) validate the numerical accuracy of the developed model and the power-flow algorithm,

(ii) quantify the impact of the Type-3 control strategy on the steady-state three-phase

power-flow solution, and (iii) demonstrate the computational efficiency of the Sequential-

SFPS with the imbedded Type-3 model. Three test systems of different topologies, sizes,

and parameters are examined. Where applicable the results are validated based on com-

parison with the exact time-domain solution, using the PSCAD/EMTDC simulation

platform.

5.2 Type-3 DER Model Validation

To evaluate the numerical accuracy of the proposed Type-3 DER model, accommodated

within the Sequential-SPFS algorithm of Chapter 4, the six-bus study system of Fig. A.1,

1The work presented in this chapter has been submitted for publication, and is in revision, in M.Z.Kamh and R. Iravani, “Three-Phase Model and Power-Flow Analysis of Wind-Driven Doubly-Fed Asyn-chronous Generators Part II: Validation and Applications,” IEEE Trans. Sustainable Energy, in Revi-sion, Nov. 2010, Manuscript ID TSTE-00187-2010.R1

78

Chapter 5. Applications and Validation of Type-3 WTG DER Model 79

Figure 5.1: Single line diagram of the six-bus test system

Table 5.1: Parameters of G2 of Fig. 5.1 (Sbase= 1000 kVA)G2

Vbase=2.3 kV, Vdc=2.7, Kinv = 12√

2, s1=-0.1

Rg=1.89 × 10−3, Xg= 0.032, Xr=Xs=0.0717,Xm=4.13, Rr=0.007,Rs=0.0092

m1g−max=0.94, m2

g−max=0.06m1

r−max=0.4, m2r−max = 0.1

I1s−max = 0.38, I2

s−max = 0.04I1g−max = 0.11, I2

g−max = 0.06

duplicated as Fig. 5.1 for the ease of reference, is selected and five case studies (Case-1

to Case-5 ) are conducted. In all cases, the DER unit is controlled to deliver 0.5 MW

at unity power-factor from its stator.

As earlier discussed in Chapter 1, the DER model validation is based on implementing

the Sequential-SFPS algorithm of Fig. 4.5, and its embedded Type-3 model, in the

MATLAB® platform. The detailed time-domain model of the study system of Fig. 5.1

is also developed in the PSCAD/EMTDC software platform to serve as the benchmark

for validation of the Type-3 model and the SPFS results.

In the system of Fig. 5.1, G1 regulates the voltage of the system slack bus at 1.043

pu. G2 is a Type-3 WTG-based DER unit. The system parameters and loads are given

in Appendix A.1. The parameters of G2 are given in Table 5.1.





1 1.043 1.043 -0.582 -0.591 1.042 1.043 -120.616 -120.609 1.043 1.043 119.351 119.3912 0.974 0.975 23.843 23.889 0.981 0.972 -96.386 -96.285 0.976 0.971 143.971 143.9723 0.880 0.879 18.513 18.501 0.908 0.899 -102.063 -102.063 0.894 0.891 138.129 138.1364 0.851 0.852 16.604 16.599 0.859 0.875 -103.402 -103.902 0.856 0.867 136.152 136.2225 0.886 0.886 18.931 18.939 0.876 0.895 -101.809 -101.409 0.885 0.894 138.194 138.6506 0.893 0.893 49.120 49.150 0.895 0.894 -71.024 -71.019 0.873 0.891 169.125 168.997

Calculated |I1g−net|=0.019 |I1

s−net|=0.187 |I2g−net|=0.062 |I2

s−net| = 0.012Internal m1

g = 0.936 m1r = 0.184 m2

g = 0 m2r = 0

Parameters of G2 Sa = 0.125 − 0.008i Sb = 0.219 − 0.047i Sc = 0.206 + 0.054i


5.2.1 Case-1: Inactive Negative-Sequence Controllers

In Case-1 , the negative-sequence current controllers of G2 are disabled. The detailed

power-flow solution of Case-1 and the calculated internal parameters of G2 are given

in Table 5.2. Table 5.2 indicates that:

• The RSC positive-sequence modulation index from both solutions is 0.184. This

verifies the accuracy of (4.48) and (4.49) of Section 4.7.1.3.

• The negative-sequence modulation indices of the RSC and GSC (m2r and m2

g) from

both solutions are equal to zero. This indicates that both converters only generate

balanced three-phase terminal voltages.

• The three-phase real power injected by the DER unit is 0.55 pu. This is the sum-

mation of the real power delivered through the stator and the GSC simultaneously.

• Since neither the RSC nor the GSC provides control with respect to the negative-

sequence components, both converters are subjected to negative-sequence currents

(I2g−net and I2

s−net) of 0.062 pu and 0.012 pu, respectively. The magnitudes of these

currents are the same for both solutions, and depend only on the magnitude of

the negative-sequence component of the voltage at Bus-6 and the impedance of the

asynchronous machine and the GSC interface filter. The close agreement between

the current magnitudes, obtained by both solvers, verifies the accuracy of the (4.56)

and (4.59).

5.2.2 Case-2: Balancing Rotor Current Via RSC

For this case study, the RSC is equipped with auxiliary controllers to balance the rotor

currents [79, 80], and the GSC negative-sequence controllers remain disabled. Table 5.3





1 1.042 1.042 -0.591 -0.591 1.043 1.043 -120.616 -120.607 1.043 1.043 119.379 119.3842 0.974 0.975 23.968 23.975 0.969 0.974 -96.249 -96.275 0.970 0.971 143.895 143.8893 0.881 0.879 18.395 18.589 0.911 0.902 -102.059 -102.040 0.892 0.891 137.989 137.9964 0.849 0.851 16.849 16.853 0.891 0.880 -103.743 -103.853 0.863 0.867 135.992 135.9975 0.885 0.884 19.148 19.243 0.909 0.902 -101.168 -101.328 0.892 0.894 138.335 138.3346 0.897 0.897 49.805 49.613 0.915 0.901 -71.313 -71.363 0.888 0.885 168.887 168.892


s−net|=0.186 |I2g−net|=0.281 |I2


g = 0.937 m1r = 0.186 m2

g = 0 m2r = 0.039

Parameters of G2 Sa = −0.061 − 0.067i Sb = 0.364 − 0.182i Sc = 0.246 + 0.242i


gives the power-flow solution of Case-2 and the internal parameters of G2. Based on

Table 5.3:

• Both solutions show that the RSC negative-sequence modulation index is 0.039.

This verifies the validity and accuracy of the formulae of Sections 4.6.2 and 4.7.2.3.

This value corresponds to the RSC terminal voltage component that is required to

balance the rotor currents.

• It is evident that the RSC control strategy affects the system power-flow solution.

This is shown by comparing the magnitude of the negative-sequence voltage at

Bus-6 for Case-1 (0.002 pu) and Case-2 (0.009 pu). This difference could not

be determined unless the proposed model of Fig. 4.3 of is deployed.

• The elevated negative-sequence voltage at Bus-6 increases the magnitude of I2g−net

beyond its corresponding limit. However, this cannot be prevented by the GSC

since its negative-sequence controllers are deactivated. The very good agreement

between the values of I2g−net, evaluated by both solvers and depicted in Table 5.3,

validates (4.56) of Section 4.7.2.1. It should be noted that the flow of excessive

negative-sequence current, in addition to the positive-sequence current, can subject

the GSC switches to over-current and can lead to tripping the DER unit.

• Although the DER unit is controlled to operate at unity power factor, i.e., Qg+Qs =

0, a three-phase reactive power of 0.007 pu is consumed by the unit. This reactive

power is due to the flow of negative-sequence currents into the stator windings and

the GSC interface filter. In addition, the total three-phase real power delivered

by the unit is 0.549 pu, as compared to 0.55 pu in Case-1 . The 0.001 pu real

power difference compensates for the GSC interface-filter losses(3|I2

g−net|2Rg

)due

to the excessive GSC negative-sequence current unbalance. Although the power





1 1.043 1.043 -0.546 -0.592 1.043 1.043 -121.012 -120.610 1.043 1.042 119.778 119.3802 0.975 0.974 23.981 23.962 0.973 0.973 -96.371 -96.295 0.965 0.966 143.998 143.8843 0.876 0.877 18.572 18.572 0.900 0.901 -102.090 -102.090 0.887 0.888 137.980 137.9804 0.848 0.848 16.854 16.838 0.877 0.877 -104.019 -103.920 0.863 0.864 136.110 135.9815 0.882 0.881 19.306 19.244 0.906 0.899 -101.727 -101.400 0.891 0.890 138.772 138.3266 0.891 0.893 49.469 49.558 0.894 0.896 -71.286 -71.414 0.880 0.881 168.607 168.910


s−net|=0.187 |I2g−net|=0.014 |I2


g = 0.934 m1r = 0.184 m2

g = 0.02 m2r = 0.000

Parameters of G2 Sa = 0.192 + 0.011i Sb = 0.172 + 0.001i Sc = 0.185 − 0.012i


differences are small, they can only be calculated and quantified using the developed

Type-3 model and the SFPS algorithm.

5.2.3 Case-3: Balancing Stator Current Via GSC

In Case-3 , the reference set-point of the GSC negative-sequence controller is adjusted

to balance the stator currents [81]. The power-flow results obtained using the devel-

oped SFPS and the time-domain solution are shown in Table 5.4. Table 5.4 shows the

magnitude of I2g−net, required to balance the stator currents, is 0.014 pu. This result

is obtained by incorporating (4.19) of Section 4.6.3.2 in the SFPS. The same value is

obtained from the PSCAD/EMTDC platform, and verifies the numerical accuracy of the

proposed algorithm.

5.2.4 Case-4: Mitigating Double-Frequency Stator Power Os-

cillations

In this case, the RSC is equipped with auxiliary controllers to mitigate the double-

frequency stator power oscillations (Ps−2ωst). Table 5.5 presents the detailed power-flow

solution and the internal parameters of G2 for Case-4 . Table 5.5 shows:

• The magnitude of I2s−net, associated with eliminating Ps−2ωst, is 0.002 pu for both

solutions. The corresponding RSC negative-sequence modulation index is 0.039.

This value is required to inject an adequate negative-sequence rotor current to

counteract Ps−2ωst. This verifies the correctness of the formulae in Section 4.6.4.

• The magnitude of I2g−net increases to 0.311 pu, compared to 0.281 pu in Case-2 ,

following an increase in the negative-sequence voltage at Bus-6 to 0.01 pu.





1 1.042 1.042 -0.557 -0.592 1.043 1.043 -120.608 -120.608 1.042 1.043 119.294 119.3842 0.974 0.975 23.952 23.964 0.975 0.974 -96.186 -96.284 0.969 0.970 143.615 143.8853 0.880 0.879 18.575 18.567 0.903 0.902 -102.180 -102.064 0.892 0.891 138.341 137.9874 0.850 0.851 16.823 16.823 0.878 0.879 -103.764 -103.886 0.863 0.867 135.768 135.9825 0.884 0.883 19.226 19.203 0.899 0.901 -101.488 -101.373 0.892 0.894 137.945 138.3126 0.895 0.896 49.729 49.556 0.901 0.901 -71.324 -71.404 0.882 0.881 168.698 168.855


s−net|=0.187 |I2g−net|=0.311 |I2


g = 0.936 m1r = 0.184 m2

g = 0.000 m2r = 0.039

Parameters of G2 Sa = −0.086 − 0.074i Sb = 0.383 − 0.201i Sc = 0.251 + 0.266i


• This increase is anticipated due to the larger contribution of the DER unit in

the negative-sequence bus-current injection vector I2BUS (I2

s−CTRL−equiv given by

(4.31) of Section 4.6.4) without changing the corresponding contribution in the

negative-sequence bus admittance matrix Y2BUS (sum of inverse of Z2

g−CTRL and

Z2s−CTRL−equiv given by (4.9) and (4.10) of Sections 4.6.1 and 4.6.2, respectively).

The increase in the magnitude of V2Bus−6 is an indication that the Type-3 negative-

sequence control strategy impacts the system power-flow solution.

5.2.5 Case-5: Mitigating Double-Frequency Torque Oscillations

and Balancing GSC Currents

To avoid excessive GSC negative-sequence current flow, the RSC and GSC are controlled

to simultaneously mitigate the double-frequency electromagnetic torque oscillations and

balance the GSC current exchange. The detailed power-flow solution and the internal

parameters of G2 are given in Table 5.6. Table 5.6 concludes that in order to cancel the

GSC negative-sequence current, its modulation index should include 0.0189 negative-

sequence component. This value is equal for both solutions, which verifies the accuracy

of the formulae of (4.11) and (4.12) in Section 4.6.2. In contrast to Case-3 , this control

strategy is highly effective to mitigate the GSC overload current caused by the negative-

sequence components.

As concluded from Tables 5.2-5.6, the maximum voltage magnitude difference for the

six busses, in all five case studies, is less than 0.9%. This is an acceptable difference

and arises due to the different nature of the two solvers. The PSCAD/EMTDC solves

the system differential equations while the SFPS solves the system algebraic steady-state

power-flow equations. The close agreement between the corresponding results of the two

solvers indicates that the proposed Type-3 DER model and the SFPS are accurate.





1 1.043 1.043 -0.582 -0.591 1.042 1.043 -120.515 -120.606 1.043 1.043 120.372 119.9722 0.975 0.974 23.995 23.984 0.974 0.974 -96.074 -96.255 0.971 0.970 144.015 143.9013 0.879 0.878 18.604 18.613 0.899 0.901 -102.264 -102.002 0.890 0.890 138.020 138.0204 0.848 0.845 16.794 16.894 0.879 0.878 -103.620 -103.783 0.865 0.866 136.170 136.0415 0.879 0.882 19.451 19.312 0.898 0.900 -100.951 -101.220 0.892 0.892 138.852 138.4066 0.891 0.894 49.641 49.726 0.901 0.899 -71.160 -71.226 0.885 0.883 168.664 168.967


s−net|=0.187 |I2g−net|=0.000 |I2


g = 0.934 m1r = 0.184 m2

g = 0.019 m2r = 0.04

Parameters of G2 Sa = 0.184 + 0.000i Sb = 0.186 + 0.000i Sc = 0.180 + 0.000i


Table 5.7: Load profile used in Section 5.3 (Vbase=13.8 kV, Sbase= 1 MVA)Phase A Phase B Phase C

S17.2958 0.000 7.2958

+2.8403i +0.000i +2.8403i

S22.2277 2.3391 2.1375

+1.1139i 1.0025i 1.2375i

S32.2277 0.000 0.000

+1.1139i 0.000i 0.000i

S40.0000 2.2275 2.2275

+0.0000i 1.1138i 1.1138i

5.3 Case 6: Validating the Sequential-SFPS Feasi-

bility

Tables 5.2-5.6 show that the internal parameters of G2 are within the acceptable operating

range. Consequently, the sequential part of the Sequential-SFPS algorithm of Fig. 4.5,

which updates the reference set-points of the Type-3 DER unit in case of a violation, is

effectively idle. To validate the entire algorithm, Case-6 is conducted.

In Case-6 , the positive-sequence controllers of G2 are designed to extract 1.0 pu real

power at unity power-factor from the DFAG stator, provided that the positive-sequence

slip is -28%. If the Type-3 unit is subjected to the stator voltage unbalance, (i) the

RSC negative-sequence controllers should mitigate the double-frequency electromagnetic

torque oscillations and (ii) the GSC controllers are to balance the GSC current. The load

profile of the six-bus system, used to conduct Case-6 , is given in Table 5.7. Although

the operating condition of this case is exaggerated, it explicitly verifies (i) the validity of

the proposed Type-3 model and (ii) the robustness of the Sequential-SFPS when applied

to heavily loaded and highly unbalanced networks.


Table 5.8: Power-Flow Results of Case-6: Operational Limits of G2 are Discarded



1 1.036 -0.162 1.044 -119.564 1.049 119.7262 0.922 20.869 0.973 -95.649 0.888 138.1333 0.877 16.356 0.881 -104.081 0.829 132.0234 0.891 16.148 0.850 -107.572 0.832 131.0755 0.928 18.284 0.836 -106.348 0.823 130.7186 0.909 44.434 0.829 -77.857 0.842 168.041


s−net|=0.389Internal |I2

g−net|=0.000 |I2s−net| = 0.037

Parameters m1g = 0.900 m1

r = 0.255of G2 m2

g= 0.052 m2r=0.123

Table 5.8 and Table 5.9 present the power-flow results and the calculated internal

parameters of G2 with and without relaxing the DER unit operating constraints. As

shown in Table 5.8, the positive-sequence stator current (I1s−net) and the RSC negative-

sequence modulation index (m2r) exceed their corresponding limits given in Table 5.1.

These parameters are shown in boldface in Table 5.8. Consequently the power-flow

solution of Table 5.8 is practically not feasible.

On the other hand, Table 5.9 shows that all the operating constraints of G2 are met

when the DER unit operating constraints are imposed. The Sequential-SFPS adjusts the

stator real power set-point (Ps−spec) of G2 to 0.977 pu, instead of 1.0 pu, corresponding

to positive-sequence stator current of 0.38 pu and RSC phase modulation index of 0.255.

Consequently, the GSC real-power set-point (Pg−spec) is adjusted to 0.273 pu, instead of

0.28 pu. Moreover, m2r is set to its limit. The magnitude of I2

s−net increases to 0.051 pu,

which guarantees that the double-frequency torque oscillations are partially counteracted.

5.4 Application of the Sequential-SFPS to Bench-

mark Distribution Systems

This section reports the application of the Sequential-SFPS and its embedded Type-3

model to two relatively large benchmark systems, i.e., the CIGRE distribution bench-

mark network [98] and the IEEE 34-bus feeder [99], to (i) verify the feasibility and (ii)

demonstrate the computational efficiency of the Sequential-SFPS for large power sys-

tems with different topologies and X/R ratios. The single-line diagrams and parameters


Table 5.9: Power-Flow Results of Case-6: Operational Limits of G2 are Imposed



1 1.036 -0.173 1.044 -119.561 1.049 119.7332 0.921 20.816 0.973 -95.615 0.889 138.1383 0.875 16.257 0.881 -104.043 0.831 132.0714 0.889 16.045 0.850 -107.511 0.834 131.1275 0.926 18.180 0.836 -106.260 0.825 130.7736 0.906 44.456 0.831 -77.702 0.842 167.870


s−net|=0.380Internal |I2

g−net|=0.000 |I2s−net| = 0.051

Parameters m1g = 0.900 m1

r = 0.255of G2 m2

g= 0.050 m2r=0.100

of both test systems are detailed in Appendix A.2 and Appendix A.4, respectively.

5.4.1 Case 7: CIGRE MV Distribution Network

The 12.47 kV, three-phase, four-wire CIGRE distribution network of Fig. A.2 is equipped

with two Type-3 DER units:

1. DER1 represents a voltage-controlled Type-3 DER unit (PV bus) connected to

Bus-8 via a three-phase transformer (150 kVA, 12.47/2.3 kV, Yg/�), and is con-

trolled to maintain the positive-sequence component of its terminal voltages at 1

pu while delivering 100 kW into the network. In addition to the positive-sequence

controllers, DER1 is controlled to balance the stator current via auxiliary GSC

negative-sequence current controllers. The GSC of DER1 is controlled to block the

negative-sequence GSC current exchange with the grid.

2. DER2 is a PQ unit that delivers 100 kW at unity power-factor, and is connected

to Bus-3 via a three-phase transformer (100 kVA, 12.47/2.3 kV, Yg/�). Moreover,

DER2 is equipped with additional controllers to mitigate the double-frequency

torque oscillations.

The three-phase voltage profile of the CIGRE distribution network, obtained using

the Sequential-SFPS algorithm, is depicted in Fig. 5.2. The operating constraints of

all the DER units are satisfied. This verifies the feasibility of the Sequential-SFPS for

non-radial ADN applications. The power-flow program converges in 0.264 seconds (3

iterations) using an Intel® Core2Duo™, 3.16 GHz processor, personal computer.


Figure 5.2: Voltage profile of the CIGRE distribution network with 2 Type-3 based DERunits

5.4.2 Case 8: IEEE 34-Bus Test System

In this case study, the 24.9 kV, three-phase, four-wire IEEE 34-bus feeder of Fig. A.4 is

equipped with three Type-3 DER units:

1. DER3 and DER4 are PV controlled units controlled to maintain the positive-

sequence voltage of the respective buses (Bus-814 and Bus-858 respectively) at

1 pu while injecting 100 kW power into the network. Each of these two units is

connected to the grid via a three-phase transformer (100 kVA, 24.9/2.3 kV, Yg/�).

Moreover, DER3 is equipped with auxiliary controllers to balance its rotor and

GSC currents simultaneously.

2. DER5 is connected to Bus-836 via a three-phase transformer (100 kVA, 24.9/2.3

kV, Yg/�), and is controlled to inject 100 kVA at unity power-factor.

Fig. 5.3 shows the three-phase voltage profile of the IEEE 34-bus distribution feeder.

The operating constraints of all the DER units are satisfied. This verifies the feasibility

of the Sequential-SFPS for radial ADN applications. The power-flow program converged

in 0.824 seconds (4 iterations) using an Intel® Core2Duo™, 3.16 GHz processor, personal

computer.

It should be noted that the computational time of Case-7 and Case-8 is larger than

that reported in Section 3.7. The reason is that the number of Type-3 DER constraints

evaluated subsequent to each power-flow iteration are much more than those of a VSC-

coupled DER unit. However, the convergence speed of the Sequential-SFPS, equipped


Figure 5.3: Voltage profile of the IEEE 34-bus distribution feeder with 3 Type-3 basedDER units

with the Type-3 model, is still acceptable for both test systems and could be even further

improved using the parallel programming techniques [73], which is beyond the scope of

this work.

5.5 Convergence Analysis

To further demonstrate the acceptable convergence behavior of the proposed algorithm,

regardless of the system parameters and topology, its convergence pattern is studied

for the three test systems. The value of the algorithm termination criterion (maximum

power mismatch) is changed and the corresponding number of iterations required by the

algorithm to converge is recorded. The algorithm convergence pattern is depicted in Fig.

5.4.

Figure 5.4 concludes that, regardless the system parameters and topology, the number

of iterations saturates when the termination criterion is reduced to 0.001 pu. This indi-

cates that the power mismatch is effectively reduced to a level less than the termination

criterion value in less than or equal to four iterations. This verifies that the computa-

tional efficiency of the proposed algorithm is independent of the network topology (mesh,

radial, or radial with loops) and parameters (X/R ratio).


This chapter presents the applications and validation of (i) the steady-state sequence-

frame-based model of a Type-3 DER unit of Chapter 4, (ii) the computational efficiency


Figure 5.4: Convergence pattern of the Sequential-SFPS algorithm accommodating theType-3 DER

of the Sequential-SFPS accommodating the proposed model, and (iii) the feasibility of the

power-flow solver for large distribution networks. The developed DER model takes into

account all the control features and the operating limits of its power-electronic converters

under balanced and unbalanced power-flow conditions.

The proposed DER model is integrated with the Sequential-SFPS , implemented in

MATLAB®, and applied to three test systems of different sizes (six, eleven, and thirty-

four bus systems), topologies (mesh, and radial), and parameters (low, medium, and high

X/R ratios). Several case studies are conducted and where applicable, the results are

compared and validated against those obtained via time-domain simulations using the

PSCAD/EMTDC software. The results demonstrate:

• the numerical accuracy of the proposed Type-3 DER model,

• the impact of the Type-3 unit negative-sequence control strategy on the distribution

system power-flow results,

• the accuracy and computational efficiency of the Sequential-SFPS power-flow algo-

rithm irrespective of the network topology and parameters,

• feasibility of the power-flow solver for large distribution networks.

Chapter 6

Power-Flow Model of Single-Phase

VSC-Coupled DER Units1

6.1 Introduction

This chapter presents the steady-state, fundamental-frequency model of a DER unit

which utilizes a single-phase VSC as the interface medium. The model represents (i)

different operating and control modes and (ii) the operational constraints and limits of

the VSC and the host system, e.g., maximum current, maximum modulation index, and

maximum voltage at the point of connection (PC). The model is tailored for the PFA of

(i) three-phase distribution networks using the SFPS of Chapter 2 and (ii) single-phase

radial laterals, widely spread in the North-American distribution systems, using the well-

established Backward-Forward Sweep Algorithm (BFSA). The interface-VSC operating

limits are modeled and imposed on the power-flow solution using the sequential approach,

presented in Chapters 3 and 4, to increase the computational efficiency of the PFA tool.

Case studies are conducted to evaluate and verify (i) the accuracy of the proposed model

and (ii) the computational efficiency of the sequential method to handle the constraints

of the single-phase VSC.

1The work presented in this chapter has been submitted for publication, and is in revision, in M.Z.Kamh and R. Iravani, “Steady State Model and Power-Flow Analysis of Single-Phase Electronically-Coupled Distributed Energy Resources,” IEEE Trans. Power Delivery, in Revision, Jan. 2011,Manuscript ID TPWRD-00003-2011.R1

90

Chapter 6. Power-Flow Model of 1ϕ VSC-Coupled DER Units 91

6.2 Background

The increasing demand for the clean and renewable energy resources and the govern-

mental policies, e.g., the feed-in tariff (FIT) and microFIT programs [112, 113] are the

main driving forces to the wide-spread penetration of the small-size DER units into the

medium- and low-voltage distribution grids. The expected presence of the plugged elec-

tric vehicle (PEV) [114] will also impact the distribution grids due to the additional

load of charging the vehicles batteries. Moreover, PEVs with the vehicle-to-grid (V2G)

power-transfer capability can inject power into the distribution network, thus also act as

small scale distributed storage (DS) units [115–119].

The single-phase AC-DC voltage-sourced converter (VSC) is the most widely-adopted

interface medium for small scale DER units [120–123]. The single-phase VSC is efficient,

compact, expandable, bidirectional, and can be connected to single- and three-phase dis-

tribution networks [124, 125]. However, the steady-state power-flow model of the single-

phase VSC-based DER units, including the operating constraints of the VSC and the host

grid, has not been previously reported. As such, this chapter develops and implements

a steady-state, fundamental frequency model of the single-phase VSC-coupled DER unit

for the three-phase PFA. The developed VSC-coupled DER model presents:

• the VSC operational and control modes, e.g., bidirectional power exchange, con-

stant power-factor, reactive power support [124],

• the VSC operational limits and constraints, e.g., maximum current, maximum mod-

ulation index, and maximum voltage at the PC bus.

6.3 Topologies and Control Objectives of Single-Phase

Interface VSC

The power-electronic converters used to interface small scale DER units to the host

network, according to their configurations, are classified into (i) single-stage and (ii)

dual-stage [121]. In the single-stage configuration, a single-phase full-bridge VSC is

directly connected to the primary source of the DER unit, and is equipped with (i) a

maximum power point tracking (MPPT) controller and (ii) a grid-current controller to

inject sinusoidal currents into the grid [124].

The dual-stage converter configuration is widely deployed as the interface for the

small scale DER applications where bidirectional power exchange is desired, e.g., (i)

integrating residential PV systems, energy storage, and plugged hybrid electric vehicles


Figure 6.1: Schematic diagram of dual-stage single-phase VSC-coupled DER unit

(PHEV) [120–122] and (ii) PEV with the V2G power transfer capability [115–118]. In this

configuration, a DC-DC converter is located between the single-phase front-end VSC and

the primary source of the DER unit to perform the MPPT function. The front-end VSC

(i) regulates the real power transfer with the grid, and (ii) can provide additional ancillary

services such as reactive power compensation and power factor correction [121, 124].

Figure 6.1 shows a schematic diagram of a DER unit coupled to the host grid, at the PC

bus, via a dual-stage single-phase VSC. The DC-DC converter is confined in a dashed

box to highlight that it is an optional block and if removed, the single stage converter is

realized.

6.4 Steady-State Model of Dual-Stage Single-Phase

Interface VSC

6.4.1 Model Assumptions

The VSC model presented in this chapter corresponds to the dual-stage VSC system.

However, the model can be also tailored to represent the less common single-stage con-

verter configurations. The following assumptions are made:

• The DER primary source is not directly represented in the model since the con-

trollers of the interface-VSC are assumed to perfectly regulate the DC-link voltage

under steady-state conditions.

• Only the fundamental-frequency model of the interface VSC is considered, i.e.,

the model does not represent the possible active harmonic filtering function of the

single-phase VSC [123,126].

• As per different codes and standards, the single-phase VSC is not permitted to

regulate the system voltage [121], i.e., the VSC is not equipped with voltage con-


Figure 6.2: Steady-state, fundamental frequency BFSA model of a single-phase VSC-coupled DER unit.

trollers. The VSC is only allowed to regulate the real and reactive power exchange

with the grid [124].

6.4.2 Incorporating Single-Phase VSC-Coupled DER Units in

Power Flow Algorithms

Under steady-state conditions, the interface VSC exchanges constant real and reactive

power with the grid. The power set points, PDER and QDER, dictate the VSC reference

current set points of the current controllers [120, 123, 124]. Based on the power-flow

algorithm into which the VSC model is incorporated, the following two VSC-coupled

DER models are developed.

6.4.2.1 VSC Model Tailored for the Single-Phase BFSA

Figure 6.2 shows the steady-state, fundamental frequency model of a single-phase VSC-

coupled DER unit, tailored for the single-phase BFSA. As earlier discussed in Chapter

2, the BFSA equations are developed based on the current injection rather than power

injection. Thus, the VSC is modeled as a current source given by

IDER,ct =

(PDER + jQDER

VPC,ct

)∗, (6.1)

where (.)∗ is the complex conjugate of a phasor quantity. In (6.1), VPC,ct and IDER,ct

are the phase-frame PC voltage and the DER current injection prior to the ctth BFSA

iteration.

The value of QDER depends on the VSC control mode as follows:

• In the power factor correction mode, QDER is given by

QDER = PDER tan(arccos(pf)), (6.2)


(a) (b)

Figure 6.3: Steady-state, fundamental frequency SFPS model of a single-phase VSC-coupled DER unit, (a) positive-sequence model, (b) zero- and negative-sequence models.

where pf is a constant power factor greater than or equal to 0.9, as specified by

the codes and standards [121].

• In the reactive power support mode, the interface VSC supplies the reactive power

requirements of the local load [124]. In this case QDER is a pre-specified value.

6.4.2.2 VSC Model Tailored for the SFPS

The single-phase VSC-coupled DER units also can be directly connected to the three-

phase trunk of a distribution system. In this case, the single-phase VSC model should be

incorporated with the SFPS of Chapter 2, to represent the unbalanced power exchange

between the single-phase DER unit and the three-phase power-flow of the grid. The

steady-state, fundamental-frequency SFPS-based model of a single-phase VSC-coupled

DER unit is illustrated in Fig. 6.3.

The positive-sequence SFPS-based VSC model, Fig. 6.3(a), is a constant power source

whose real and reactive power components are

P 1DER,ct + jQ1

DER,ct = VPC,ct(IDER,ct)∗, (6.3)

where (.)ct1 is the positive-sequence component of a three-phase quantity, prior to con-

ducting the ctth SFPS iteration. The zero- and negative-sequence SFPS-based models of

the single-phase VSC, Fig. 6.3(b), are constant current sources whose current injections

I0,2DER,ct are updated prior to each power-flow iteration. The positive-, negative-, and


zero-sequence current components of Fig. 6.3 are

I0DER,ct =

1

3IDER,ct,

I1DER,ct =

r

3IDER,ct, (6.4)

I2DER,ct =

r2

3IDER,ct,

where the multiplier r in (6.4) is

r =

⎧⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎩

1 DER unit connected to phase-A,

a = 1� 120o DER unit connected to phase-B,

a2 = 1� 240o DER unit connected to phase-C.

(6.5)

The phase-frame DER current used in (6.4), IDER,ct, is given by (6.1).

6.5 Evaluating the Interface VSC Internal Parame-

ters

To incorporate the operating constraints of the interface-VSC in the power-flow algo-

rithm, its internal parameters, i.e., modulation index and phase current, must be deter-

mined in the phase-frame. Regardless of the type of the power-flow algorithm (SFPS

or BFSA), subsequent to each iteration, the PC terminal voltage is evaluated in the

phase-frame and used to calculate the VSC modulation index (m) and the DER current

(IDER). Figure 6.4 shows the equivalent circuit of the single-phase VSC-interfaced DER

unit used to determine the converter parameters. The equivalent impedance of the VSC

series filter of Fig. 6.4 is

Rf−eq + jXf−eq =Rf + jωLf

(1 − ω2LfCf ) + jωRfCf

, (6.6)

where Rf , Lf , and Cf are identified on Fig. 6.1.

6.5.1 Calculating the VSC Phase Current

Similar to the approach used in Chapter 4, the VSC phase current IDER is decomposed

into two components: in-phase with (IDER−d) and perpendicular to (IDER−q) the PC

voltage phasor. Subsequent to the ctth power-flow iteration, these two current components


Figure 6.4: Equivalent circuit of the single-phase VSC-coupled DER unit used to calculatethe VSC internal parameters

are evaluated using

IDER−d,ct =PDER

|VPC,ct| , (6.7)

IDER−q,ct = − QDER

|VPC,ct| , (6.8)

where |.| is the magnitude of a phasor quantity. The net VSC current is given by

|IDER,ct| =√

(IDER−d,,ct)2 + (IDER−q,ct)2. (6.9)

6.5.2 Calculating the VSC Modulation Index

Analogous to the discussion in Section 6.5.1, the VSC modulation index is decomposed

into two perpendicular components, namely md and mq, such that

mct =√

(md,ct)2 + (mq,ct)

2, (6.10)

where mct is the VSC modulation index after the ctth power-flow iteration, and is related

to the VSC terminal voltage Vt,ct by

mct =|Vt,ct|

Kinv × Vdc

, (6.11)

where Kinv is the converter constant and is determined based on the adopted modulation

strategy [95]. For single-phase VSC, the most deployed modulation technique is the 3-

level, naturally sampled, sinusoidal PWM (SPWM), for which Kinv = 1√2. Vt,ct is given


by

Vt,ct =

(|VPC,ct| +

(PDER − jQDER

|VPC,ct|)

(Rf−eq + jXf−eq)

)((1 − ω2LfCf ) + jωRfCf

).

(6.12)

From (6.11) and (6.12)

md,ct = Act + c1,ctPDER + c2,ctQDER, (6.13)

mq,ct = Bk + c2,ctPDER − c1,ctQDER. (6.14)

The coefficients in (6.13) and (6.14) are

Act =|VPC,ct|KinvVdc

(1 + ω2CfLf ), Bct = −ωCfRf |VPC,ct|KinvVdc

,

c1,ct =Rf

KinvVdc|VPC,ct| , c2,ct =ωLf

KinvVdc|VPC,ct| .(6.15)

6.6 Imposing the VSC Operational Limits

To deduce a feasible power-flow solution, none of the interface VSC internal parameters

should exceed their corresponding limits. In addition, the single-phase DER contribution

(generation or storage) should be specified such that the corresponding PC bus voltage

does not exceed the maximum value dictated by the utility system (VPC−max).

The sequential technique, proposed in Chapter 3, imposes these constraints subse-

quent to each power-flow iteration by (i) calculating the VSC internal parameters as

discussed in Section 6.5 and (ii) modifying the reference power set-points (PDER and

QDER) of the VSC controllers to satisfy the constraints in case of contravention. This

section presents a systematic approach to update the VSC power set-points to satisfy all

the operational limits of the interface VSC and the host grid, i.e.,

• phase current limit (If−max)

• modulation index limit (mmax)

• PC bus voltage limit (VPC−max)


6.6.1 Phase Current Limit

A heavily loaded distribution network is often characterized by low-bus voltages, includ-

ing the head busses of single-phase laterals. Consequently, the DER units connected to

single-phase laterals need to inject higher currents to meet their real and reactive power

requirements. However, to obtain a feasible power-flow solution, each DER current should

be within the acceptable limits.

Subsequent to the ctth power-flow iteration, if the magnitude of the VSC phase-

frame current |IDER| (calculated by (6.7)-(6.9)) exceeds IDER−max, then IDER−d,ct+1 and

IDER−q,ct+1 are re-calculated using

IDER−d/q,ct+1 = IDER−d/q,ct × IDER−max

|IDER,ct| . (6.16)

Substituting for IDER−d,q from (6.16) into (6.7) and (6.8), and solving for PDER and

QDER, yields the power set points used in the (ct + 1)th iteration. The updated power

set points are given by (6.17) and (6.18).

PDER,ct+1|x = PDER,ct × IDER−max

|IDER,ct| , (6.17)

QDER,ct+1|x = QDER,ct × IDER−max

|IDER,ct| . (6.18)

Suffix x in (6.17) and (6.18) refers to the set-points that satisfy the DER phase current

limit.

6.6.2 Modulation Index Limit

Prior to proceeding to the (ct+1)th power-flow iteration, if m (evaluated by (6.11)-(6.15))

is greater than mmax (which is 1 for the SPWM [95]), then mk+1d and mk+1

q are updated

using

md/q,ct+1 = md/q,ct × mmax

mct

. (6.19)

The updated power set points, satisfying the modulation index limit, are evaluated

by substituting md,q from (6.19) into (6.13) and (6.14), and solving for PDER and QDER.

This procedure yields

PDER,ct+1|y =c1,ct(md,ct+1 − Act) + c2,ct(mq,ct+1 − Bct)

c1,ct2 + c2,ct

2, (6.20)


QDER,ct+1|y =c2,ct(md,ct+1 − Act) − c1,ct(mq,ct+1 − Bct)

c1,ct2 + c2,ct

2. (6.21)

Suffix y in (6.20) and (6.21) refers to the reference set-points fulfilling the modulation

index constraint.

6.6.3 PC Bus Voltage Limit

The uncoordinated high-depth penetration of single-phase DER units can result in ex-

cessive voltage rise at different busses of the system. It is the utility common practice to

adjust the system voltage via three-phase voltage regulators. However, these regulators

are much slower compared to the DER response and do not provide the desired solu-

tion to the overvoltage problem. Instead, one or more of the following can address the

overvoltage issue:

• A (relatively large) storage unit is connected to the substation bus. The stor-

age unit is controlled to absorb the excessive DER power causing the overvoltage

phenomenon.

• The real and reactive power set-points of the single-phase DER units, located at the

violated busses, are reduced until all the system busses comply with the maximum

voltage limit.

The latter solution is adopted in this work and implemented in the Sequential-SFPS as

follows. Subsequent to the ctth power-flow iteration, all the phase-frame bus voltages are

evaluated. If the three-phase voltage at a PC bus, to which a single-phase DER unit is

connected, exceeds the maximum allowable value, the DER power set points are updated

using

(P, Q)DER,ct+1|z =(P, Q)DER,ct × VPC−max

max − violate (VPC−ABC,ct), (6.22)

where max − violate (VPC−A,B,C) is the magnitude of the maximum violating PC phase

voltage, and VPC−max is the utility upper limit of the phase voltage magnitude at any

bus. For example, based on the Canadian Standards, the maximum voltage in the MV

networks (1 kV to 50 kV) should not exceed 1.06 pu [127]. As such, VPC−max is set to

1.06 pu in this work. In (6.22), suffix z refers to the reference set-points satisfying the

PC voltage constraint.

It should be noted that unlike (6.17)-(6.21), which are based on mathematical closed

forms, (6.22) is heuristically developed since deducing a closed form expression that

relates phase voltages at different busses to a specific DER contribution practically is not


feasible. In addition, since updating the real and reactive power set points of the DER

units at the violating busses is not based on a mathematical closed form, fulfilling the

bus voltage constraint is expected to be the most computationally demanding part of the

power-flow algorithm, as will be detailed in Section 6.7.

6.6.4 Updating the VSC Reference Power Set-Points

The power set-points, selected prior to the (ct+1)th power-flow iteration, must satisfy the

aforementioned three operating constraints. As such, the real power set-point (PDER,ct+1)

is selected based on:

PDER,ct+1 = min(PDER,ct+1|x, PDER,ct+1|y, PDER,ct+1|z). (6.23)

The same logic is deployed to select QDER,ct+1.

6.6.5 Sequential Power-Flow Algorithm

Subsequent to evaluating the phase-frame internal parameters of each single-phase VSC-

coupled DER unit, the corresponding operating limits are checked to ensure no violations

occur. Similar to the discussion in Chapters 3 and 4, the steps to determine the internal

parameters, evaluate the operating limits, and update the phase-frame reference power

set-points are conducted sequentially at the end of each power-flow iteration.

6.7 1ϕ VSC Model Validation

To verify the accuracy and evaluate the computational efficiency of the single-phase BFSA

and the three-phase SFPS, including the VSC model of Section 6.4 and the power set

point updating criteria described in Section 6.6, two benchmark feeders are used as test

systems. The first feeder is the single-phase radial feeder of the CIGRE MV benchmark

distribution network [98], and is used to evaluate the performance of the single-phase

Sequential-BFSA. The computational efficiency of the three-phase Sequential-SFPS is

evaluated based on the IEEE 34-bus feeder [99].

6.7.1 Validating the Single-Phase Sequential BFSA

The single-phase CIGRE radial lateral of Fig. A.3, duplicated as Fig. 6.5 for the ease of

reference, is equipped with three identical single-phase VSC-coupled DER units, namely


Figure 6.5: Single line diagram of the radial test feeder

G1, G2, and G3, connected to Bus-6, Bus-11, and Bus-12, respectively. Each DER unit

is controlled to inject 0.6 pu power at 0.9 power-factor. The system loads and parameters

are given in Appendix A.3. The DER parameters are extracted from [124], and are given

in Table 6.1. The sequential BFSA power-flow algorithm, including the proposed DER

model, is implemented in the MATLAB® platform and two case studies are conducted.

Table 6.1: Parameters of G1, G2, and G3 of Fig. 6.5 (Vbase = 7.2 kV and Sbase = 100kVA)

Rated Power 0.6 puRated Voltage 1.0 pu

ωLf 0.0254 puωCf 0.0 puRf 0.0 pu

IDER−max 0.66 puKinv

1√2

mmax 1.0Vdc 1.4


Table 6.2: Power-Flow Results of Case-1: Maximum Phase Current Limit is DiscardedBus Magnitude (pu) Angle(degrees)1 0.9 02 0.8996 -0.01263 0.8995 -0.01384 0.8994 -0.01445 0.8997 -0.01546 0.8998 -0.01737 0.8989 -0.02948 0.8992 -0.0259 0.8995 -0.019710 0.8997 -0.018711 0.9 -0.017112 0.8998 -0.0181

DER IDER (pu) mG1 0.6668 0.9073G2 0.6666 0.9075G3 0.6668 0.9073

Table 6.3: Case-1: Updated Real and Reactive Power Set Points of the three DER unitsDER P (pu) Q(pu)G1 0.5345 0.2588G2 0.5346 0.2589G3 0.5345 0.2588

6.7.1.1 Case-1: Maximum Phase Current Limit Violation

In Case-1, the head node (Bus-1) voltage is 0.9 pu. The corresponding power-flow

solution and the DER internal parameters, associated with relaxing the DER maximum

phase current limit, are given in Table 6.2. The DER violated parameters are shown in

boldface.

As indicated in Table 6.2, the phase currents of the three DER units (IDER) exceed

the maximum corresponding limit (0.66 pu) and indicate the power-flow solution is not

feasible.

If the DER current constraint of Section 6.6.1 is imposed, then once the violation is

detected subsequent to the first power-flow iteration, the real and reactive power reference

set points of the three DER units are updated based on (6.17) and (6.18), respectively.

The new real and reactive power reference set points of the three DER units are given in

Table 6.3. The corresponding power-flow solution, the DER currents, and the modulation

indices are shown in Table 6.4.


Table 6.4: Power-Flow Results of Case-1: Maximum Phase Current Limit is ImposedBus Magnitude (pu) Angle(degrees)1 0.9000 02 0.8996 -0.01263 0.8995 -0.01394 0.8994 -0.01455 0.8996 -0.01556 0.8997 -0.01747 0.8989 -0.02958 0.8992 -0.02519 0.8995 -0.019810 0.8997 -0.018911 0.9000 -0.017312 0.8998 -0.0182

DER IDER (pu) mG1 0.6600 0.9071G2 0.6600 0.9074G3 0.6600 0.9071

Table 6.4 shows that the constraints of the DER units are satisfied. The sequen-

tial power-flow algorithm adjusts the real and reactive power of G1, G2, and G3 to

0.5345+j0.2588, 0.5346+j0.2589, and 0.5345+j0.2588 pu, respectively. The results of

Tables 6.3 and 6.4 demonstrate the validity and accuracy of (6.17) and (6.18).

6.7.1.2 Case-2: Maximum Modulation Index Limit Violation

In Case-2 the head node (Bus-1) voltage is 1.0 pu. The corresponding power-flow

solution and the DER internal parameters, associated with relaxing the DER maximum

modulation index limit, are given in Table 6.5. The violated DER parameters are shown

in boldface.

Table 6.5 shows that the modulation indices of the three DER units (m) exceed their

maximum allowable limits. As such, this power-flow solution is not acceptable. However,

adjusting the real and reactive power set points of the three DER units to the values

given in Table 6.6 guarantees that the modulation indices of the three DER units are

bounded to 1.0 as required. The values in Table 6.6 are evaluated by (6.20) and (6.21).

The corresponding power-flow solution and the DER internal parameters are shown in

Table 6.7. The results of Tables 6.6 and 6.7 demonstrate the accuracy and validity of the

model given by (6.20) and (6.21).

As shown in Tables 6.2 and 6.5, all the bus voltages are below the maximum operating


Table 6.5: Power-Flow Results of Case-2: Maximum Modulation Index Limit is DiscardedBus Magnitude (pu) Angle(degrees)1 1.0000 02 0.9997 -0.01023 0.9995 -0.01124 0.9995 -0.01175 0.9997 -0.01256 0.9997 -0.0147 0.9990 -0.02398 0.9993 -0.02039 0.9996 -0.01610 0.9997 -0.015211 1.0000 -0.013912 0.9998 -0.0147

DER IDER (pu) mG1 0.6001 1.0065G2 0.6000 1.0067G3 0.6000 1.0066

Table 6.6: Case-2: Updated Real and Reactive Power Set Points of the three DER unitsDER P (pu) Q(pu)G1 0.5370 0.0451G2 0.5367 0.0372G3 0.5367 0.0412

limit of 1.06 pu. Consequently, updating the power set points according to Section 6.6.3

is neither required nor addressed in Case-1 and Case-2. The accuracy and validity of

(6.22) are presented in Section 6.7.2.

6.7.2 Validating the Three-Phase Sequential-SFPS

To investigate the overvoltage phenomenon associated with the DER penetration, (i)

the substation bus voltage (Bus 800) is adjusted to 1.05 pu, as recommended in [99],

and (ii) the feeder is equipped with multiple single-phase VSC-coupled DER units. The

SFPS is augmented with the DER model of Fig. 6.3 and implemented in the MATLAB®

platform, and the following case studies are conducted.

The Modified IEEE 34-bus system of Fig. A.5, duplicated as Fig. 6.6 for the ease of

reference, is used to investigate the overvoltage phenomenon associated with the DER

penetration. In this test system, (i) the substation bus voltage (Bus 800) is adjusted to

1.05 pu and (ii) the feeder is heavily equipped with multiple single-phase VSC-coupled


Table 6.7: Power-Flow Results of Case-2: Maximum Modulation Index Limit is ImposedBus Magnitude (pu) Angle(degrees)1 1.0000 0.00002 0.9995 0.00573 0.9993 0.00474 0.9993 0.00415 0.9994 0.00866 0.9994 0.01227 0.9987 0.00278 0.9990 0.00639 0.9993 0.010610 0.9994 0.016711 0.9996 0.023412 0.9995 0.0172

DER IDER (pu) mG1 0.5392 1.000G2 0.5382 1.000G3 0.5385 1.000

DER units. The SFPS is augmented with the DER model of Fig. 6.3 and implemented

in the MATLAB® platform, and the following two case studies are conducted.

6.7.2.1 Case-3: Violating the Maximum PCC Voltage Limit

In Case-3 , the system of Fig. 6.6 is equipped with 23 single-phase DER units, one unit

at each bus except at Bus-800. Each DER unit is controlled to inject 0.12 pu power (1

MVA base value) at 0.9 power-factor according to Table 6.8.

First, the maximum bus voltage constraint of Section 6.6.3 is discarded and the SFPS

Figure 6.6: Single line diagram of modified three-phase IEEE-34 bus radial feeder


Table 6.8: Case-3: DER Phase Distribution*Bus 800 802 806 808 812 814 850 816

DER at phase - C B B A B C A

Bus 824 828 830 854 852 832 858 834DER at phase A B C B A B C B

Bus 860 836 862 840 842 844 846 848DER at phase A B B C A B C A*Each DER unit injects 0.1080 + j0.0523 pu power.The base power is 1 MVA.

Table 6.9: Case-3: Three-Phase Voltage Profile Without Considering the Maximum BusVoltage Constraint

Bus 800 802 806 808 812 814|Va| 1.0523 1.0527 1.0529 1.0563 1.0596 1.0615|Vb| 1.0469 1.0473 1.0475 1.0509 1.0542 1.0561|Vc| 1.0507 1.0511 1.0513 1.0547 1.0580 1.0599

Bus 850 816 824 828 830 854|Va| 1.0615 1.0615 1.0620 1.0620 1.0623 1.0623|Vb| 1.0561 1.0561 1.0566 1.0566 1.0569 1.0569|Vc| 1.0599 1.0599 1.0604 1.0604 1.0607 1.0607

Bus 852 832 858 834 860 836|Va| 1.0614 1.0614 1.0614 1.0614 1.0615 1.0616|Vb| 1.0560 1.0560 1.0561 1.0561 1.0561 1.0562|Vc| 1.0597 1.0597 1.0598 1.0598 1.0599 1.06

Bus 862 840 842 844 846 848|Va| 1.0616 1.0616 1.0614 1.0614 1.0614 1.0614|Vb| 1.0562 1.0562 1.0560 1.0560 1.0561 1.0561|Vc| 1.0600 1.0600 1.0598 1.0597 1.0598 1.0598

is used to determine the power-flow solution. The corresponding three-phase voltage

profile is reported in Table 6.9. Phase voltages exceeding 1.06 pu are shown in boldface.

According to Table 6.9, all the bus voltages, except those of busses 800, 802, 806, 808,

and 812, exceed the voltage limit of 1.06 pu. Therefore, the power-flow solution is not

feasible. When the maximum voltage constraint is considered, the real and reactive power

set points of the DER units at the violated busses are updated, according to (6.22), to

address the overvoltage condition. The updated DER power set points and the resulting

three-phase voltage profile are given in Table 6.10 and Table 6.11, respectively.

Table 6.10 shows that the power set points of the DER units connected to Busses 802,

806, 808, and 812 remain at the original value (0.1080 + j0.0523 pu). The reason is the


Table 6.10: Case-3: Updated Real and Reactive Power Set Points of the DER Units.Sbase = 1 MVA.

Bus 802 806 808 812 814 850PDER (pu) 0.1080 0.1080 0.1080 0.1080 0.1038 0.1038QDER (pu) 0.0523 0.0523 0.0523 0.0523 0.0503 0.0502



Bus 840 842 844 846 848PDER (pu) 0.1057 0.1063 0.1065 0.1062 0.1062QDER (pu) 0.0512 0.0515 0.0516 0.0515 0.0515

Table 6.11: Case-3: Three-Phase Voltage Profile After Adjusting the DER Power SetPoints Using (6.22)

Bus 800 802 806 808 812 814|Va| 1.0519 1.0522 1.0524 1.0554 1.0581 1.0596|Vb| 1.0474 1.0477 1.0479 1.0509 1.0536 1.0551|Vc| 1.0507 1.0510 1.0512 1.0542 1.0570 1.0585

Bus 850 816 824 828 830 854|Va| 1.0596 1.0596 1.0600 1.0600 1.0600 1.0600|Vb| 1.0551 1.0552 1.0555 1.0555 1.0556 1.0556|Vc| 1.0585 1.0585 1.0588 1.0588 1.0589 1.0589

Bus 852 832 858 834 860 836|Va| 1.0589 1.0589 1.0590 1.0590 1.0590 1.0591|Vb| 1.0545 1.0545 1.0545 1.0545 1.0545 1.0546|Vc| 1.0578 1.0578 1.0578 1.0578 1.0578 1.0579

Bus 862 840 842 844 846 848|Va| 1.0591 1.0591 1.0589 1.0589 1.0590 1.0590|Vb| 1.0546 1.0546 1.0545 1.0544 1.0545 1.0545|Vc| 1.0579 1.0579 1.0578 1.0577 1.0578 1.0578

heuristic updating strategy of 6.22 does not affect the power contribution of the DER

units at the non-violated busses. In addition, the three-phase voltage profile given in

Table 6.11 comply with the imposed maximum voltage constraint, which demonstrates

the accuracy and validity of (6.22).


Table 6.12: Case-4: Three-Phase Voltage Profile Without Considering the Maximum BusVoltage Constraint

Bus 800 802 806 808 812 814|Va| 1.0521 1.0524 1.0526 1.0557 1.0586 1.0602|Vb| 1.0472 1.0475 1.0477 1.0508 1.0537 1.0553|Vc| 1.0508 1.0511 1.0513 1.0544 1.0573 1.0589

Bus 850 816 824 828 830 854|Va| 1.0602 1.0602 1.0606 1.0606 1.0605 1.0605|Vb| 1.0553 1.0553 1.0557 1.0557 1.0556 1.0556|Vc| 1.0589 1.0589 1.0593 1.0593 1.0592 1.0592

Bus 852 832 858 834 860 836|Va| 1.0590 1.0590 1.0590 1.0588 1.0589 1.0590|Vb| 1.0541 1.0541 1.0541 1.0539 1.0540 1.0541|Vc| 1.0577 1.0577 1.0576 1.0575 1.0576 1.0577

Bus 862 840 842 844 846 848|Va| 1.0590 1.0590 1.0588 1.0587 1.0587 1.0587|Vb| 1.0541 1.0541 1.0539 1.0538 1.0538 1.0538|Vc| 1.0577 1.0577 1.0575 1.0574 1.0574 1.0574

6.7.2.2 Case-4: No DER Units Connected to the Violating Bus

In Case-3 , all the violated busses of Table 6.9 are connected to DER units. However,

there might be a scenario where a bus experiences overvoltage due to DER units con-

nected to other busses. To investigate this scenario and verify the effectiveness of the

criterion of (6.22) in mitigating the corresponding overvoltages, Case-4 is conducted.

In Case-4 , the DER units at Busses 814 and 846 are removed. In addition, the power

set points of the remaining DER units is raised to 0.1102 + j0.0534 pu, as compared to

0.1080 + j0.0523 pu for Case-3 . The corresponding three-phase voltage profile, calcu-

lated by the SFPS when the maximum voltage constraint is relaxed, is given in Table

6.12. The voltages at the violated busses are shown in boldface.

In addition to the voltages at Busses 850, 816, 824, 828, 830, and 854, where a

DER unit is connected to each bus, Table 6.12 shows that the voltage at Bus 814 (not

connected to a DER unit) exceeds 1.06 pu. Thus the power-flow solution of Table 6.12

is not acceptable.

To be effective and valid, the updating criterion of Section 6.6.3 should address the

overvoltage at all busses, and not only at those with DER connections. The three-phase

voltage profile of Table 6.13 verifies this fact. The voltage violation at all the busses,

including those without DER units, is resolved by updating the power set points of the

DER units at Busses 850, 816, 824, 828, 830, and 854. The updated real and reactive


Table 6.13: Case-4: Three-Phase Voltage Profile After Adjusting the DER Power SetPoints Using (6.22)

Bus 800 802 806 808 812 814|Va| 1.0520 1.0523 1.0525 1.0555 1.0582 1.0597|Vb| 1.0473 1.0476 1.0478 1.0508 1.0535 1.0550|Vc| 1.0508 1.0511 1.0513 1.0543 1.0570 1.0585

Bus 850 816 824 828 830 854|Va| 1.0597 1.0597 1.0600 1.0600 1.0600 1.0599|Vb| 1.0550 1.0550 1.0554 1.0554 1.0553 1.0553|Vc| 1.0585 1.0585 1.0588 1.0588 1.0588 1.0587

Bus 852 832 858 834 860 836|Va| 1.0584 1.0584 1.0584 1.0582 1.0583 1.0584|Vb| 1.0537 1.0537 1.0537 1.0536 1.0536 1.0537|Vc| 1.0572 1.0572 1.0572 1.0570 1.0571 1.0572

Bus 862 840 842 844 846 848|Va| 1.0584 1.0584 1.0582 1.0581 1.0581 1.0581|Vb| 1.0537 1.0537 1.0536 1.0535 1.0535 1.0535|Vc| 1.0572 1.0572 1.0570 1.0569 1.0569 1.0569

Table 6.14: Case-4: Updated Real and Reactive Power Set Points of the DER Units atthe Violating Busses. Sbase = 1 MVA.

Bus PDER (pu) QDER (pu)850 0.1097 0.0531816 0.1096 0.0531824 0.1030 0.0499828 0.1023 0.0496830 0.1058 0.0512854 0.1061 0.0514

power set points of the six DER units of the violated busses are given in Table 6.14.

6.7.3 Computational Efficiency of the Sequential Algorithms

accommodating the 1ϕ VSC-Coupled DER Model

An Intel® Core2Duo™, 3.16 GHz processor is used to conduct the reported four case

studies. In both Case-1 and Case-2, the sequential power-flow algorithm converges in

two iterations and the computational times for the solutions, i.e., Tables 6.4 and 6.7, are

0.023 and 0.026 seconds, respectively. This demonstrates the computational efficiency of

the proposed algorithm.

When the voltage constraint of the three-phase SFPS is discarded, the algorithm con-


verges to the solution of either Case-3 or Case-4, given in Tables 6.9 and 6.12 respec-

tively, in 0.094 seconds. However, if the voltage constraint is imposed, the computational

time increases to 1.216 and 0.896 seconds for Case-3 and Case-4 , respectively. As

discussed in Section 6.6.3, satisfying the maximum voltage constraint, using the heuristic

expression of (6.22), is expected to be the most time demanding part of the algorithm

since it is not based on a mathematical closed form. This computational time can be

reduced using a fast parallel programming technique for the SFPS implementation [97],

which is beyond the scope of this work.


This chapter presents a steady-state, fundamental frequency model of the small-size DER

unit interfaced by a single-phase VSC to the distribution system. The proposed model ad-

dresses the converter’s different (i) operational modes, e.g., bidirectional power transfer,

constant power-factor, and reactive power compensation, and (ii) operational constraints,

i.e., maximum modulation index, maximum current, and maximum bus voltage. The de-

veloped model is incorporated in single-phase (BFSA) and three-phase (SFPS) power-flow

algorithms.

The developed model utilizes the sequential iterative process with respect to the net-

work and the VSC solutions, to guarantee the power-flow solution adheres to the network

and the VSC constraints and operating limits. The proposed model and the developed

sequential power-flow solvers are implemented in MATLAB® platform and applied to

single-phase and three-phase benchmark networks. Four case studies are conducted, and

the power-flow results demonstrate (i) the validity of the proposed VSC model and (ii)

the computational efficiency of the sequential power-flow algorithms accommodating the

1ϕ VSC model.

Chapter 7

Power Flow Analysis of Islanded

ADNs1

7.1 Introduction

In the context of real-time power management of islanded smart distribution systems, the

smart energy management system (SEMS) is anticipated to deploy optimal power-flow

(OPF) engines to dispatch the system components and update the associated power and

voltage set points every 15-30 minutes [23]. During this time interval, sudden incidents,

e.g., sudden load switching and/or sudden network reconfiguration, may happen. One

of the possible consequences of such incidents is that the reference bus DER output,

during islanded operation, exceeds its maximum permissible capacity. Due to the high

computational burden of running the OPF, which can be in the order of several minutes

for a medium-size distribution network [128], the SEMS should be equipped with a dif-

ferent tool that can rapidly estimate new set points, that are not necessarily optimal.

This is required to maintain the system integrity until the completion of the subsequent

OPF run. Distributing the real and reactive system slack among several DER units is an

emergency remedy to alleviate the violation of the reference bus power capacity limit.

This chapter proposes and develops a new distributed slack bus (DSB) model for real-

time power-flow analysis of islanded ADNs whose reference bus, unlike utility-connected

systems, has severe limited power capacity. A three-phase DSB-based PFA approach,

in the context of the SFPS, is proposed. The DSB-SFPS can be integrated within the

1The work presented in this chapter has been submitted for publication in M.Z. Kamh and R. Iravani,“A Sequence Frame-Based Distributed Slack Bus Model for Energy Management of Active DistributionNetworks,” IEEE Trans. Smart Grids, in Revision, July 2011, Manuscript ID TSG-00230-2011

111

Chapter 7. Power Flow Analysis of Islanded ADNs 112

SEMS to conduct real-rime three-phase PFA for islanded ADNs.

Existing DSB models only distribute the real slack among grid-forming (voltage-

controlled) DER units. Such a practice is not satisfactory for ADNs where the DER fleet

may consist of only one or two voltage-controlled (PV) sources and a majority of power-

controlled (PQ) DER units. In addition, distributing the reactive slack has not yet been

addressed in the technical literature. As will be shown in this chapter, distributing the

reactive slack can significantly reduce the reference bus output, thus alleviate its power

capacity limit violation. Moreover, non of the existing DSB models consider the power

capacity limit of the participating DER units.

The proposed DSB model incorporates (i) the participation of DER units with differ-

ent control strategies (PQ and PV) in the system real and reactive slack compensation

and (ii) the DER power capacity limits. Based on a new definition of the “participating

sources”, the SFPS is enhanced to incorporate the system real and reactive slack as state

variables in the power-flow equations. Case studies are conducted to evaluate the impacts

of adopting the proposed DSB model, instead of the conventional single-slack bus (SSB)

model, in the SFPS tool.

7.2 Background

Traditional power-flow analysis identifies the slack bus as (i) the reference for all the

bus voltage angles and (ii) the power-balancing bus that makes up for the difference

between the scheduled generation and the loads plus losses. As such, the slack bus

output compensates (i) the difference between generation at all the other busses and the

total system load and (ii) the total system losses. Hence, the slack bus is considered

a voltage source with infinite power capacity [129]. While this model is valid for the

utility-connected operation, where the utility bus can be assumed an “infinite power

source” with respect to the DER units, it lacks the practicality for ADNs operating in

the islanded mode. The slack bus in an islanded ADN is essentially a grid-forming DER

unit whose generation capacity is comparable to the other operating DER units. If the

reference bus output, i.e., the slack, exceeds its DER unit capacity, it becomes essential

to distribute the system slack among other participating units based on pre-specified

criteria. The single slack bus (SSB) model does not allow for slack distribution analysis

since it assigns all the system slack to one bus.

The DSB power-flow analysis is addressed in the technical literature for balanced

transmission networks [130–135] and three-phase unbalanced distribution grids [42, 129,

136–138]. The existing three-phase DSB models permit the grid-forming DER units (PV


busses) to share the system real slack. Several slack distribution criteria were developed

where the system slack is shared among the participating sources according to:

• constant participation factors based on the source scheduled output [130,131,138],

• constant participation factors based on the source quadratic cost function [132],

• constant participation factors based on the source characteristics and loads alloca-

tion strategy [133,134],

• iteratively calculated participation factors based on the source domains and com-

mons [42,129,136–138],

• iteratively calculated participation factors based on the network sensitivity and

penalty factors [129,137].

7.3 The Scope of the Chapter

The scope of this chapter is to:

• develop and incorporate a sequence frame-based DSB model in the SFPS for the

real-time PFA of ADNs in the autonomous operating mode, and

• extend the DSB model to include a sequence frame-based reactive slack distribution

model.

The rest of the chapter is as follows. Section 7.4 presents the sequence-frame DSB

model, and new bus types are proposed. In Section 7.5, several case studies are conducted

to investigate and quantify the impacts of deploying the proposed DSB -SFPS tool. Main

conclusions are stated in Section 7.6.

7.4 Proposed Distributed Slack Bus (DSB) Model

7.4.1 Assumptions

Although the voltage and current unbalance in a distribution grid could be significant, the

power unbalance (which is defined as the ratio of the negative- plus the zero-sequence

power components to the positive-sequence power component) at the reference bus is

much smaller. Thus, it is reasonable to assume that the total system three-phase slack

is approximately three times the total positive-sequence slack. This postulate is verified


through case studies in Section 7.5.1. Hence, the DSB model proposed in this work is

defined based on the positive-sequence power-flow, and is incorporated with the positive-

sequence power-flow equations of the SFPS of Chapter 2, where the bulk of the system

slack is associated with.

7.4.2 Participation Factors

Based on the adopted control strategy, a DER unit can be categorized as (i) a grid-forming

(voltage-controlled) unit that dictates the voltage [92] and (ii) a power-controlled (PQ)

unit that exchanges pre-specified real and reactive power with the system [91]. The later

can be further divided, based on the DER capacity, into a large or a small PQ unit. To

formulate the DSB model, the DER units that participate in compensating the system

slack must be predetermined. The participating units are classified as

1. PV and large PQ DER units with spare real power capacity to compensate for the

system real slack. The ratio of the real slack contribution of each participating unit

to the total system real slack is the “real-power participation factor”, Kp, where

m∑i=1

Kip +

N∑i=m+1

Kip = 1. (7.1)

In (7.1), i = 1 is the reference bus index, m − 1 is number of PV busses, and N is

the total number of system busses.

2. Large PQ DER units with spare reactive power capacity to compensate for the

system reactive slack. The “reactive-power participation factor”, Kq, is defined as

the ratio of the reactive slack contribution of each participating unit to the total

system reactive slack, where

KPVq +

N∑i=m+1

Kiq = 1, (7.2)

where KPVq is the combined reactive power participation factor for all the non-PQ

busses.

Developing formulae for the optimal real and reactive power participation factors is

not within the scope of this thesis. Therefore, constant participation factors are used to

demonstrate the concept.


7.4.3 Distributed Slack Bus Model

To augment the DSB model with the SFPS, the positive-sequence power-flow equations

are enhanced as follows.

7.4.3.1 Real Power Balance Equation

F ip1 = P 1

DER−i + KipP

1slack + P 1

i,comp − P i1load

−|V1i |

N∑k=1

|V1k||y1

BUS−ik| cos(θ1

i − θ1k − θY 1

ik)

= 0 , i = 1, 2, . . . , m, m + 1, . . . N, (7.3)

where P i1load

is the load positive-sequence real power consumed at Bus-i, P 1i,comp is the

positive-sequence real power compensation at Bus-i, and is given by (2.28), and P 1DER−i

is one-third of the DER three-phase real power contribution at Bus-i.

7.4.3.2 Reactive Power Balance Equation

F iq1 = Q1

DER−i + KiqQ

1slack + Q1

i,comp − Qi1load

−|V1i |

N∑k=1

|V1k||y1

BUS−ik| sin(θ1

i − θ1k − θY 1

ik)

= 0 , i = m + 1, . . . , N, (7.4)

where Qi1load

is the load positive-sequence reactive power at Bus-i, Q1i,comp is the positive-

sequence reactive power compensation at Bus-i, and is given by (2.29), and Q1DER−i is

one-third of the DER three-phase reactive power load contribution at Bus-i.

7.4.3.3 Super-PQ-Bus Equation

To incorporate the positive-sequence reactive slack (Q1slack) as a new state variable in

the power-flow problem, in addition to (7.3) and (7.4), one more equation is required.

The reactive slack consists of the combined reactive power contribution of the non-PQ

busses, i.e., contributions of the reference and the PV busses. Hence, the set of non-

PQ busses can be considered as a “super-PQ-bus” whose reactive power contribution is

the difference between the total system reactive load-plus-loss and the reactive power


injection of all the PQ sources. The corresponding power balance equation is given by

F 1Qslack

= 0 =N∑

i=1

Qi1load

+m∑

i=1

Q1i,comp

+KPVq Q1

slack −N∑

i=m+1

Q1DER−i

−m∑

i=1

|V1i |

N∑k=1

|V1k||y1

BUS−ik| sin(θ1

i − θ1k − θY 1

ik). (7.5)

Equation (7.5) is referred to as the “super-PQ-bus equation”. In (7.5),∑N

i=1 Qi1load

−∑Ni=m+1 Qi

1DERis the combined reactive load contribution of the non-PQ busses, and

KPVq Q1

slack is the combined reactive slack contribution of the reference and PV busses.

7.4.4 The Updating Equation

As earlier detailed in Chapter 2, the SFPS algorithm simultaneously solves the decoupled

positive, negative, and zero-sequence power-flow equations to calculate the phase-frame

bus voltages. The system of (7.3)-(7.5) constitutes the modified SFPS positive-sequence

power-flow equations including the proposed DSB model. This system of equations is

solved iteratively using the Newton-Raphson (N-R) method. The corresponding updating

matrix equation is given by (7.6).

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

�Fp11

�Fp12

...

�Fp1N

�Fq1m+1

...

�Fq1N

�F 1Qslack

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

=

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

K1p 0 ∂Fp1

1

∂θ12

. . . ∂Fp11

∂θ1N

∂Fp11

∂V 1m+1

. . . ∂Fp11

∂V 1N

K2p 0 ∂Fp1

2

∂θ12

. . . ∂Fp12

∂θ1N

∂Fp12

∂V 1m+1

. . . ∂Fp12

∂V 1N

......

.... . .

......

. . ....

KNp 0 ∂Fp1

N

∂θ12

. . . ∂Fp1N

∂θ1N

∂Fp1N

∂V 1m+1

. . . ∂Fp1N

∂V 1N

0 Km+1q

∂Fq1m+1

∂θ12

. . . ∂Fq1m+1

∂θ1N

∂Fq1m+1

∂V 1m+1

. . . ∂Fq1m+1

∂V 1N

......

.... . .

......

. . ....

0 KNq

∂Fq1N

∂θ12

. . . ∂Fq1N

∂θ1N

∂Fq1N

∂V 1m+1

. . . ∂Fq1N

∂V 1N

0 KPVq

∂F 1Qslack

∂θ12

. . .∂F 1

Qslack

∂θ1N

∂F 1Qslack

∂V 1m+1

. . .∂F 1

Qslack

∂V 1N

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

�P 1slack

�Q1slack

�θ12

...

�θ1N

�V 1m+1

...

�V 1N

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

.

(7.6)


7.4.5 DER Generation Limits

To obtain a feasible power-flow solution, the DER operating constraints must not be

violated. Thus, real and reactive power limits of the participating DER units must be

checked and imposed in each SFPS iteration. This section describes a strategy to impose

the DER real and reactive generation limits in the proposed DSB-SFPS algorithm.

Subsequent to each SFPS iteration, the real-power spinning reserve (SRip) of each

participating DER unit is calculated using

SRip,ct = P i

DER−max − P 1DER−i − Ki

p,ctP1slack,ct, (7.7)

where ct is the index for the current power-flow iteration. If SRip,ct is negative, the

real-power participation factor Kip,ct is updated by

Kip,ct+1 =

P iDER−max − P 1

DER−i

P 1slack,ct

. (7.8)

For (7.1) to hold, the real-power participation factor of the DER unit with the largest

positive real-power spinning reserve, e.g., DERj, is updated using

Kjp,ct+1 = Kj

p,ct + Kip,ct+1 − Ki

p,ct. (7.9)

Based on this strategy, the least loaded participating DER units help in alleviating the

real-power limit violation of the more stressed units. The same strategy is adopted to

enforce the DER reactive generation limit.

7.5 Validations and Case Studies

This section presents (i) the validation of the assumption stated in Section 7.4.1, (ii)

quantification of the impacts of deploying the proposed DSB model to conduct the power-

flow analysis, and (iii) verification of the numerical accuracy of the participation factor

updating strategy of Section 7.4.5.

7.5.1 Assumption Validation

The proposed DSB model is based on the assumption stated in Section 7.4.1. As such,

it is essential to test the validity of this assumption prior to deploying the DSB model

for further analysis.


The assumption stated in Section 7.4.1 is formulated as

P3ϕ−slack � 3P 1slack,

Q3ϕ−slack � 3Q1slack, (7.10)

where

P 1slack =

N∑i=1

|V1i |

N∑k=1

|V1k||y1

BUS−ik| cos(θ1

i − θ1k − θY 1

ik),

Q1slack =

N∑i=1

|V1i |

N∑k=1

|V1k||y1

BUS−ik| sin(θ1

i − θ1k − θY 1

ik),

(7.11)

P3ϕ−slack =∑

r=a,b,c

N∑i=1

P ri ,

Q3ϕ−slack =∑

r=a,b,c

N∑i=1

Qri , (7.12)

and

P ri = |Vr

i |∑

x=a,b,c

N∑k=1

|Vxk||yrx

BUS−ik| cos(θr

i − θxk − θY rx

ik),

Qri = |Vr

i |∑

x=a,b,c

N∑k=1

|Vxk||yrx

BUS−ik| sin(θr

i − θxk − θY rx

ik). (7.13)

To test the validity of this assumption, two benchmark distribution systems are used:

• The 12.47 kV CIGRE distribution benchmark network of Fig. A.2, duplicated as

Fig. 7.1 for the ease of reference. The total system load is 1808.61 + j898.46 kVA

on phase-A, 2220.11 + j1062.24 kVA on phase-B, and 1985.61 + j1010.84 kVA on

phase-C.

• The modified 24.9 kV IEEE 34-bus radial feeder of Fig. A.4, duplicated as Fig.

7.2 for the ease of reference. The total system load is set to 1212 + j714 kVA on

phase-A, 1168 + j688 kVA on phase-B, and 1158 + j686 kVA on phase-C.

The reference bus DER unit of each test system is a grid-forming gas-fired or diesel


Figure 7.1: Single line diagram of the CIGRE distribution benchmark network

Figure 7.2: Single line diagram of the modified IEEE 34-bus feeder


Figure 7.3: Validating the assumption stated in Section 7.4.1

synchronous generator [34]. Thus, both ADNs are operating autonomously, i.e., forming

an islanded μgrid.

For each test system, the total three-phase real (P3ϕ−slack) and reactive (Q3ϕ−slack)

slack are calculated by (7.10) and (7.12) for three distinct cases:

• Case-A: no additional DER units are installed in the system.

• Case-B: 10% of the total system load is supplied by one PQ-controlled electronically-

coupled DER unit.

• Case-C: 30% of the total system load is supplied by one PQ-controlled electronically-

coupled DER unit.

The difference between the total three-phase slack calculated by (7.10) and (7.12) is

expressed as a percentage of (7.12). All the reported power-flow calculations deploy the

conventional SSB concept. The results are plotted in Fig. 7.3, where the factor Γ is given

by

Γ = max

⎛⎜⎜⎜⎜⎝

P3ϕ−slack−3P 1slack

P3ϕ−slack× 100

Q3ϕ−slack−3Q1slack

Q3ϕ−slack× 100

⎞⎟⎟⎟⎟⎠ . (7.14)

As depicted in Fig. 7.3, the maximum difference between the total three-phase slack

calculated using (7.10) and (7.12) does not exceed 0.15% for the CIGRE distribution

benchmark network (with larger X/R ratio) and 0.23% for the IEEE 34-bus feeder (with

smaller X/R ratio). In addition, the difference tends to vanish as the DER depth of


penetration increases since the total system losses decrease. Fig. 7.3 verifies the validity

of the assumption stated in Section 7.4.1, i.e., the total three-phase slack is approximately

three times its positive sequence counterpart, regardless of the network topology and X/R

ratio.

7.5.2 Impacts of Deploying the Proposed DSB Model

The DSB model of Section 7.4 is augmented with the SFPS power-flow algorithm, and

the combined algorithm (DSB-SFPS) is (i) implemented in the MATLAB® platform

and (ii) used to investigate the impacts of using the proposed DSB model, instead of the

conventional SSB model, on the:

1. reference bus DER unit output,

2. total three-phase real-power losses,

3. voltage profile,

To quantify the aforementioned impacts, the modified IEEE 34-bus feeder of Fig. 7.2

is used. The electronically-coupled PQ-controlled DER unit at Bus-858 is rated at 760

kVA (0.76 pu), and is controlled to inject balanced three-phase power at unity power-

factor. The following seven study cases are conducted:

• Case-Base: The PQ DER unit injects 20% of the system real load while not par-

ticipating in the slack compensation, i.e., Kp = Kq = 0. This case represents the

conventional SSB power-flow.

• Case-1: Similar to Case-Base, but the PQ DER unit compensates for 10% of the

system real slack, i.e., Kp = 0.1 and Kp−ref,bus = 0.9.

• Case-2: Ditto, but the PQ DER unit compensates for 10% of the system real and

reactive slack, i.e., Kp = Kq = 0.1 and Kp−ref.bus = Kq−ref.bus = 0.9.

• Case-3: Similar to Case-1, but the PQ DER unit compensates for 15% of the system

real slack, i.e., Kp = 0.15 and Kp−ref,bus = 0.85.



• Case-5: Similar to Case-1, but the PQ DER unit compensates for 20% of the system

real slack, i.e., Kp = 0.2 and Kp−ref,bus = 0.8.


Figure 7.4: Effect of the proposed DSB model on the apparent power output of thereference bus DER unit



For each case, the DSB-SFPS tool is used to calculate the system voltage profile and

power-flow results. Fig. 7.4 illustrates the apparent power output of the reference-bus

DER unit. The real power losses of Case-1 through Case-6 are shown in Fig. 7.5 as a

percentage of the real power losses of Case-Base. The average voltage profile of the seven

cases is depicted in Fig. 7.6. Figs. 7.4-7.6 conclude the following.

7.5.2.1 Reference Bus Power Output

The apparent power output of the reference bus DER unit is reduced by 1.21% by reduc-

ing its real slack contribution from 100% to 80%, Fig. 7.4. The apparent power output

can be further reduced by 1.71% when the real and reactive slack contributions of the

reference bus DER unit are simultaneously reduced to 80%. In addition, comparing the

reference bus output for Case-1 versus Case-2, Case-3 versus Case-4, and Case-5 versus

Case-6 proves that simultaneously distributing the real and reactive slack reduces the

reference bus output power compared to distributing the real slack only.

It can also be concluded from Fig. 7.4 that if the reference bus DER unit capacity


Figure 7.5: Effect of the proposed DSB model on the real-power losses of the IEEE-34bus test feeder

is, for example, limited to 3.64 pu, then assigning 20% of the real slack to the PQ-

controlled DER would not alleviate the overload condition at the reference bus DER

unit. One option to mitigate the overload would be to shed some loads. Alternatively,

simultaneously distributing the total real and reactive slack, using the proposed DSB-

SFPS tool, guarantees that the reference bus DER unit does not exceed its capacity limit.

This verifies the effectiveness of simultaneously distributing the real and reactive slack

for real-time operation of islanded ADNs. It should be noted that, in this particular

example, if Kp exceeds 0.2, the PQ-controlled unit will be overloaded.

7.5.2.2 Real Power Losses

The three-phase real power losses (P3ϕ−loss) are approximately 6% of the total system

load. In the conventional SSB model, these losses are entirely compensated from the

reference bus. However, distributing the slack inherently distributes the system loss

compensation among the participating units. As Kp increases, the real power losses

decrease, Fig. 7.5. Moreover, distributing the reactive-power losses further reduces

P3ϕ−loss. This result is concluded by comparing the percentage reduction of the total

system losses, shown in Fig. 7.5, for Case-1 versus Case-2, Case-3 versus Case-4, and

Case-5 versus Case-6. As shown in Fig. 7.5, increasing Kp from 0.0 to 0.2 decreases

P3ϕ−loss by 3.19%. If Kq is also increased to the same value, the real power losses


Figure 7.6: Effect of the proposed DSB model on the voltage profile of the IEEE-34 bustest feeder

are further reduced by 4.4%. As such, the simultaneous distribution of the real and

reactive slack significantly reduces the system losses, and consequently the total slack,

thus increases the ADN overall efficiency.

7.5.2.3 Voltage Profile

The voltage profile is slightly improved by deploying the DSB model, Fig. 7.6. The

maximum voltage difference exists at Bus-848, whose average voltage is depicted in the

top-right corner of Fig. 7.6. Simultaneously distributing the real and reactive slack

improves the voltage profile compared to distributing the real slack only. This is con-

cluded by comparing the voltage profile of Case-1 versus Case-2, Case-3 versus Case-4,

and Case-5 versus Case-6. By increasing Kp of the PQ-controlled DER unit from 0 to

0.2, the average voltage at Bus-848 increases by 0.16% compared to Case-Base, i.e., the

SSB model. In addition, the voltage is further elevated by 0.22% when both real- and

reactive-power participation factors are simultaneously set to 0.2.

7.5.3 Imposing the DER Power Capacity Constraint

An additional case study, Case-7, is conducted to quantify the impact of the DER capacity

constraint on the performance of the DSB-SFPS, and to verify the numerical accuracy of

the participation factor update strategy proposed in Section 7.4.5. In Case-7, the rating

of the PQ-controlled DER unit of Fig. 7.2 is reduced to 0.75 pu instead of 0.76 pu, while

the unit continues to serve 20% of the system real power load.


Figure 7.7: Effect of imposing the DER power capacity constraint on the PQ-controlledDER output

As indicated in Case-5, setting Kp = 0.2 and Kq = 0 requires the PQ-controlled DER

unit to inject 0.752 pu real power. However, if the DER unit capacity is limited to 0.75 pu,

the power-flow solution becomes infeasible. To overcome this violation, the DSB-SFPS

algorithm, including the formulae of Section 7.4.5, updates the PQ-controlled DER real

power participation factor to 0.1913. Consequently, Kp−ref.bus increases to 0.8087 instead

of 0.8. Figure 7.7 compares the PQ-controlled DER power contribution before and after

imposing the DER capacity constraint.

As illustrated in Fig. 7.7, reducing Kp to 0.1913 successfully limits the DER output to

0.75 pu. Thus, the constraint violation is prevented and the power-flow solution becomes

feasible. The results of Fig. 7.7 verify the validity and the numerical accuracy of the

updating strategy proposed in Section 7.4.5.


This chapter introduces a comprehensive distributed slack bus (DSB) model for three-

phase power-flow analysis of islanded ADN. Unlike the existing DSB models, the proposed

formulation (i) simultaneously distributes both real and reactive slack and (ii) involves

DER units with different control strategies to compensate the total slack. In addition,

the DER generation capacity constraint is integrated in the proposed DSB model to

guarantee the power-flow solution adheres to the DER operating limits. The developed

model is also incorporated in the SFPS of Chapter 2.

The resulting DSB-SFPS tool is implemented in the MATLAB® platform, and ap-


plied to the modified IEEE 34-bus benchmark network. Eight different case studies are

conducted to investigate and quantify the impacts of distributing the real and reactive

slack. The results demonstrate

• the effectiveness of the proposed DSB model for islanded ADN real-time operation,

• the numerical accuracy of the developed DSB-SFPS tool, and

• that simultaneously distributing the real and reactive slack positively impacts the

operation of the islanded ADN by reducing the system losses, thus increasing the

system overall efficiency..

Chapter 8

Conclusions

8.1 Summary

This thesis presented the concept of the active distributions network (ADN) as the next

generation of existing distribution systems. Unlike the current distribution systems, the

ADN has a flexible topology, includes large number of electronically-coupled distributed

energy resource (DER) units, and requires voltage and power regulation in the utility-tied

and islanded modes of operation.

This thesis described component modeling and power-flow analysis algorithms for

the development of a fast and accurate three-phase power-flow analysis (PFA) tool, the

Sequence-F rame Power-flow Solver (SFPS), for the ADN applications. The developed

PFA tool represents the kernel of the ADN smart power and energy management system.

Accurate and detailed steady-state fundamental-frequency models of different types of

electronically-coupled DER units, i.e., (i) variable-speed wind-driven doubly-fed asyn-

chronous generator based and (ii) single-/three-phase voltage-sourced converter (VSC)-

coupled DER units, are developed and incorporated within with the proposed power-flow

analysis tool for the real-time operation and control of ADN. The developed tool and

models are used for the real-time adjustment of the reference set points of different DER

controllers to enable operation of the entire ADN.

8.2 General Conclusions

The thesis concludes that:

1. Developing the steady-state, fundamental-frequency models of VSC-based DER

units in the sequence-components frame provides flexibility to address any DER

127

Chapter 8. Conclusions 128

control objective under balanced and unbalanced power-flow scenarios. The reason

is that all the controllers of the VSC-based DER units adopt the sequence-frame

under unbalanced grid conditions.

2. Incorporating all of the interface VSC and the host DER constraints, e.g., modula-

tion index limit, current limit, power capacity limit, and the terminal voltage limit,

is essential to obtain an accurate power-flow solution.

3. Implementing the DER operating constraints, using the sequential approach, is

computationally more efficient compared to the other methods reported in the

literature, e.g., the non-sequential approach.

4. To mitigate the violation in the DER operating limits, the interface VSC reference

set points are updated based on closed forms or heuristic formulae. However, the

sequential implementation of the VSC-coupled DER constraints is computationally

more efficient when the DER reference-set point updating strategies are based on

accurate closed forms, rather than heuristic ones.

5. The PFA of ADN in the islanded operating mode should adopt the distributed slack

bus (DSB) model rather than the conventional single slack bus (SSB). In addition,

simultaneously distributing the real and reactive slack among several DER units

can noticeably (i) reduce the output power of the reference bus DER unit and (ii)

the total system losses, and (iii) improve the overall islanded system efficiency.

8.3 Quantifiable Conclusions

Based on the studies reported in this work, the following conclusions are deduced:

1. As indicated in Chapters 3 and 5, this thesis reported a negligible difference of less

than 1 % between the PFA results of the developed SFPS tool, accommodating

the proposed DER models, and the exact solution obtained by the time-domain

simulations using the PSCAD/EMTDC platform.

2. As indicated in Chapter 3, a computational time reduction of 54 %, compared to the

non-sequential approach, was achieved when the proposed sequential method is used

to impose the VSC constraints. Speed of convergence and ease of implementation

are crucial for real-time management and control of the ADN.


3. It was verified in Chapter 6 that the heuristic update of the VSC reference set-

points, to mitigate any operating constraint violations, reduces the SFPS conver-

gence speed. The SFPS converged about ten times slower when the single-phase

VSC power-set points are heuristically updated to alleviate the PCC voltage limit

violation, compared to updating the same set points using closed forms to mitigate

the phase-current or modulation index limit.

4. In Chapter 7, (i) 4.4 % reduction in the total system losses and (ii) 1.7 % reduction

in the reference-bus DER output power are reported by conducting the three-phase

PFA of the IEEE 34-bus test system using the proposed DSB model, compared to

its conventional SSB counterpart.

8.4 Contributions

8.4.1 Major Contributions

This thesis presents the following three main contributions:

1. Development of the SFPS: A fast, accurate, and robust power-flow analysis tool for

ADN applications. This tool is the kernel of the ADN smart energy management

system that optimally controls and operates the network.

2. Modeling of VSC-coupled DER units: The developed three-phase, steady-state,

fundamental-frequency models include accurate closed forms for updating the VSC

reference set-points to guarantee full compliance with the VSC and its associate

source constraints.

3. Development and integration of a sequence-frame DSB model for the power-flow

and cost analyses of islanded ADNs using the SFPS.

8.4.2 Other Contributions

In addition, this thesis introduces the sequential approach; a computationally efficient

method to impose the VSC constraints within the SFPS. This approach is integrated

with the SFPS to form the Sequential-SFPS algorithm.

8.5 Directions for Future Research

Future work in the continuation of the work in this thesis is to:


• develop steady-state power-flow tools and models of VSC for the applications of

overlayed DC-AC grids.

• incorporate the proposed three-phase PFA software tool and DER models in a

smart energy management system, where the performance of the entire control and

management system is tested using a real-time simulator.

Appendix A

Data for Test Systems

A.1 Six-Bus Test System

The six-bus test system, Fig. A.1, is used in Chapters 3 and 5 to verify the proposed

steady-state, fundamental frequency, sequence-frame-based models of the three-phase

VSC-coupled and Type-3 WTG-based DER units, respectively.

The six-bus distribution system is a three-phase, four-wire, multi-grounded, 13.8 kV

distribution network and includes untransposed lines and balanced/unbalanced loads.

The system is equipped with two DER units. G1 represents the system slack bus, and is

modeled as an ideal voltage source behind an impedance. G2 is an electronically-coupled

DER unit. The system parameters and loading profile are given in Tables A.1 and A.2,

respectively. The details of the system PSCAD model are given in Appendix D.

Although the six-bus system of Fig. A.1 is meshed and has relatively low R/X ratio,

which is not common for distribution networks, the performance of the Sequential-SFPS

algorithm is equally accurate when applied to a radial and loop network with a high R/X

ratio. This is verified using the test systems of Fig. A.2 and Fig. A.4.

A.2 Three-Phase CIGRE MV Test System

The three-phase CIGRE MV distribution network, Fig. A.2 [98], is used in Chapters 3

and 5 to verify the the computational efficiency and the applicability of the developed

Sequential-SFPS software tool, including models and constraints of three-phase VSC-

coupled and Type-3 WTG-based DER units, to non-radial distribution networks. In

addition, the same system is used in Chapter 7 to verify the validity of the DSB model

assumption.

131

Appendix A. Data for Test Systems 132

Figure A.1: Single line diagram of the six-bus test system used in Chapters 3 and 5

Table A.1: Power Lines Phase-Frame Parameters (in pu) of the Study System of Fig.A.1 (Vbase=13.8 kV, Sbase= 1000 kVA)

Zseries Yshunt

L1

0.0080 + 0.0550i 0.0040 + 0.0160i 0.0040 + 0.0110i

0.0040 + 0.0160i 0.0070 + 0.054i 0.0040 + 0.0160i

0.0040 + 0.0110i 0.0040 + 0.0160i 0.0080 + 0.0550i

0.14840i −0.0310i −0.0250i

−0.0310i 0.1495i −0.0300i

−0.0250i −0.0300i 0.1150i

L2

0.0066 + 0.0560i 0.0017 + 0.0270i 0.0012 + 0.0210i

0.0017 + 0.0270i 0.0045 + 0.0470i 0.0014 + 0.0220i

0.0012 + 0.0210i 0.0014 + 0.0220i 0.0062 + 0.0610i

0.1500i −0.0300i −0.0100i

−0.0300i 0.2500i −0.0200i

−0.0100i −0.0200i 0.1400i

L3 and L4

0.0033 + 0.0280i 0.0008 + 0.0135i 0.0006 + 0.0105i

0.0008 + 0.0135i 0.0022 + 0.0235i 0.0007 + 0.0110i

0.0006 + 0.0105i 0.0007 + 0.0110i 0.0031 + 0.0305i

0.1500i −0.0300i −0.0100i

−0.0300i 0.2500i −0.0200i

−0.0100i −0.0200i 0.1400i

Table A.2: Loads of the Study System of Fig. A.1 (Vbase=13.8 kV, Sbase= 1000 kVA)Phase A Phase B Phase C

S11.9652 1.9652 1.9652

+0.7651i +0.7651i +0.7651i

S2 0.6001 0.6301 0.5758and S3 +0.3000i 0.2700i 0.3333i

S40.6000 0.6000 0.6000

+0.3000i 0.3000i 0.3000i


Figure A.2: Single line diagram of the three-phase CIGRE MV distribution network usedin Chapters 3, 5, and 7

The 12.47 kV, three-phase, four-wire CIGRE MV distribution network includes total

unbalanced load of 4.9 MW/2.36 MVAR. The system comprises one loop and two radial

sections, with an R/X ratio equals to 0.4. The system parameters and loading profile are

given in Tables A.3 and A.4, respectively. The three-phase power lines of the CIGRE

MV distribution network are perfectly transposed.

A.3 CIGRE MV Single-Phase Radial Feeder

The CIGRE MV single-phase radial feeder, Fig A.3 is used in Chapter 6 to evaluate

the numerical accuracy of the sequential PFA algorithm, incorporating the single-phase

VSC-coupled DER model, when applied to single-phase radial laterals. The test feeder

is a 7.2 kV single-phase radial lateral with R/X ratio of 1.56. The total system load is

248.75 kW and 90.16 kVAr. The system load profile is given in Table A.5.

A.4 IEEE 34-Bus Test System

The IEEE 34-bus MV distribution test system, Fig. A.4, is an actual feeder located in

Arizona [99]. According to the IEEE distribution system analysis subcommittee, this

system is vulnerable to convergence problems when conducting three-phase PFA due to


Table A.3: Power Lines Phase-Frame Parameters (in ohms) of the Study System of Fig.A.2

From Bus To Bus Per-phase Resistance Per-phase Reactance1 2 0.3460 0.77762 3 0.5190 0.64803 4 0.6920 0.39743 8 1.3840 0.84244 5 0.8650 0.36284 11 1.9030 0.32405 6 1.0380 0.99797 8 1.3840 1.08438 9 1.5570 0.20749 10 1.7300 0.518410 11 1.9030 0.2160

Table A.4: Loads (in kVA) of the Study System of Fig. A.2Bus Phase-A Phase-B Phase-C1 161.68+j58.68 80+j60 260+j147.182 265+j136.58 217.5+j120.97 170+j105.363 64+j48 244+j135.18 109+j69.794 180+j87.18 90+j43.59 90+j43.595 232.5+j64.08 331.68+j136.14 42.5+j26.346 47.5+j15.61 95+j31.22 161.68+j58.687 95+j31.22 190+j62.45 95+j31.228 90+j43.59 135+j65.38 180+j87.189 95+j31.22 142.5+j46.84 95+j31.2210 135+j65.38 90+j43.59 225+j108.9711 175+j94.63 175+j94.63 127.5+j79.02


Figure A.3: Single line diagram of the CIGRE MV single-phase radial feeder used inChapter 6. All power lines are identical. The series impedance of any power line =0.219+j0.14 Ω

Table A.5: Loads (in kVA) of the Study System of Fig. A.3Bus Load (kVA)1 13.5000+j 6.53832 14.2500+j 4.68373 13.5000+j 6.53834 13.5000+j 6.53835 9.5000+j 3.12256 47.5000+j 15.61257 47.5000+j 15.61258 9.5000+j 3.12259 47.5000+j 15.612510 13.5000+j 6.538311 9.5000+j 3.122512 9.5000+j 3.1225


Figure A.4: Single line diagram of the IEEE 34-bus distribution system used in Chapters3 and 5

Table A.6: Power Lines Phase-Frame Parameters of the Study System of Fig. A.4From Bus To Bus Length (miles) Zseries (Ω/mile) Yshunt(μSimenes/mile)

800 802 0.49

1.3368 + 1.3343i 0.2101 + 0.5779i 0.213 + 0.5015i

0.2101 + 0.5779i 1.3238 + 1.3569i 0.2066 + 0.4591i

0.2130 + 0.5015i 0.2066 + 0.4591i 1.3294 + 1.3471i

5.3350i −1.5313i −0.9943i

1.5313i 5.0979i −0.6212i

0.9943i −0.6212i 4.8880i

802 806 0.33806 808 6.10808 810 1.10808 812 7.10812 814 5.63888 890 2.00

814 850 0.02

1.9300 + 1.4115i 0.2327 + 0.6442i 0.2359 + 0.5691i

0.2327 + 0.6442i 1.9157 + 1.4281i 0.2288 + 0.5238i

0.2359 + 0.5691i 0.2288 + 0.5238i 1.9219 + 1.4209i

5.1207i −1.4364i −0.9402i

−1.4364i 4.9055i −0.5951i

−0.9402i −0.5951i 4.7154i

816 824 1.93824 828 0.16828 830 3.87830 854 0.10832 858 0.93834 860 0.38834 842 0.05836 840 0.16836 862 0.05842 844 0.26844 846 0.69846 848 0.10850 816 0.06852 832 0.02854 852 6.98858 834 1.10860 836 0.51

816 818 0.322.7995+1.4855i (Phase A to ground) 4.2251i (Phase A to ground)818 820 9.12

820 822 2.60

824 826 0.572.7995+1.4855i (Phase B to ground) 4.2251i (Phase B to ground)854 856 4.42

858 864 0.31

862 838 0.92 1.9217+1.4212i (Phase B to ground) 4.3637i (Phase B to ground)


Figure A.5: Single line diagram of the Modified IEEE 34-bus distribution system usedin Chapters 6 and 7

the length of the feeder, the unbalanced loading conditions, and the high R/X ratio. [99].

As such, this feeder is used in Chapters 3 and 5 to verify the convergence robustness

of the proposed SFPS software tool, including models and constraints of three-phase

VSC-coupled and Type-3 WTG-based DER units.

The IEEE system is a 24.9 kV, three-phase, four-wire, radial system with total un-

balanced three-phase spot and distributed load of 1.8 MW/1.04 MVAR of mixed models

(ZIP load model). The distributed loads are lumped and equally divided between the

sending and receiving busses of each power line. The average of the system R/X ratio is

1.4. The system accommodates six single-phase laterals: from Bus-808 to Bus-810, from

Bus-816 to Bus-822, from Bus-824 to Bus-826, from Bus-854 to Bus-856, from Bus-858 to

Bus-864, and from Bus-862 to Bus-838. In the original system, The system parameters

and loading profile are given in Tables A.6 and A.7, respectively.

A.5 Modified IEEE 34-Bus Test System

In Chapters 6 and 7, a modified version of the IEEE 34-bus test system of Fig. A.4 is used

to (i) evaluate the numerical accuracy of the sequential PFA algorithm, incorporating

the single-phase VSC-coupled DER model of Chapter 6, when applied to a three-phase

radial network with high R/X ratio , (ii) verify the validity of the DSB model assumption

stated in Chapter 7, and (iii) quantify the differences between using the proposed DSB

and the conventional SSB models to conduct the three-phase PFA for islanded μgrids.

The modifications to the original system are summarized as follows:

• All the loads are modeled using the constant power load model.


Table A.7: Loads (in kVA) of the Study System of Fig. A.4Bus Phase-A Phase-B Phase-C802 0 15+j7.5 12.5+j7806 0 15+j7.5 12.5+j7808 0 8+j 4 0810 0 8+j 4 0816 0+j 0 2.5+j 1 0818 17+j 8.5 0 0820 84.5+j 43.5 0 0822 67.5+j 35 0 0824 0 22.5+j 11 2+j 1826 0 20+j 10 0828 3.5+j 1.5 0 2+j 1830 13.5+j 6.5 10+j 5 10+j 5832 3.5+j 1.5 1+j 0.5 3+j 1.5834 10+j 5 12.5+j 7 61.5+j 31836 24+j 12 16+j 8.5 21+j 11838 0 14+j 7 0840 18+j 11.5 20+j 12.5 9+j 7842 4.5+j 2.5 0 0844 139.5+j 109.5 147.5+j 111 145+j 110.5846 0 24+j 11.5 10+j 5848 20+j 16 44+j 27.5 30+j 21.5854 0 2+j 1 0856 0 2+j 1 0858 6.5+j 3 8.5+j 4.5 9.5+j 5860 43+j 27.5 35+j 24 96+j 54.5862 0 14+j 7 0+j 0864 1+j 0.5 0 0890 150+j 75 150+j 75 150 +j75

Total 606j 359 591.5j 348 574j 343


• All the single-phase laterals, and their loads, are merged into their corresponding

head nodes.

• The 4.16 kV three-phase lateral (Busses 888 and 890), including its associated

loads, is lumped into node 832 as a three-phase constant power load.

The single line diagram of the modified IEEE 34 bus feeder is depicted in Fig. A.5.

The modified system comprises 24 busses.

Appendix B

Steady-State Power-Flow Models of

Distribution Power Lines

The equivalent π-model is used to represent power lines in the phase-frame, Fig. B.1.

The series (shunt) branch of the line model is a 3× 3 matrix. This model can encompass

(i) three-phase, four-wire multi-grounded, (ii) three-phase, three-wire, (iii) two-phase,

three-wire multi-grounded, and (iv) two-phase, two-wire lines. In this work, “multi-

grounded” does not necessarily refer to directly grounding the sending and the receiving

ends of the line, but rather refers to keeping the neutral potential very close to the

ground potential. This assumption is particularly true for medium voltage distribution

networks where the neutral-to-earth (NEV) voltage is negligibly small compared to the

phase voltages [62, 88,89].

Figure B.1: Phase-frame model of three-phase power line

140

Appendix B. Steady-State Power-Flow Models of Distribution Power Lines141

B.1 Three-Phase Power Lines

The three-phase currents flowing from Bus-k to Bus-m, for a three-phase four-wire line,

are given by ⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

Iakm

Ibkm

Ickm

Inkm

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

=

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

Iaseries−km

Ibseries−km

Icseries−km

Inseries−km

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

+

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

Iashunt−km

Ibshunt−km

Icshunt−km

Inshunt−km

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

, (B.1)

where ⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

Vak −Va

m

Vbk −Vb

m

Vck −Vc

m

Vnk −Vn

m

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

=

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

zaaseries zab

series zacseries zan

series

zbaseries zbb

series zbcseries zbn

series

zcaseries zcb

series zccseries zcn

series

znaseries znb

series zncseries znn

series

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

Iaseries−km

Ibseries−km

Icseries−km

Inseries−km

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

, (B.2)

and ⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

Iashunt−km

Ibshunt−km

Icshunt−km

Inshunt−km

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

=1

2

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

yaashunt yab

shunt yacshunt yan

shunt

ybashunt ybb

shunt ybcshunt ybn

shunt

ycashunt ycb

shunt yccshunt ycn

series

ynashunt ynb

shunt yncshunt ynn

shunt

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣

Vak

Vbk

Vck

Vnk

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦

. (B.3)

For multi-grounded lines, Vnk and Vn

m are both zero. Thus (B.3) is reduced to

⎡⎢⎢⎢⎢⎣

Iashunt−km

Ibshunt−km

Icshunt−km

⎤⎥⎥⎥⎥⎦ =

1

2

⎡⎢⎢⎢⎢⎣

yaashunt yab

shunt yacshunt

ybashunt ybb

shunt ybcshunt

ycashunt ycb

shunt yccshunt

⎤⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎣

Vak

Vbk

Vck

⎤⎥⎥⎥⎥⎦ . (B.4)

Moreover, applying Kron matrix reduction technique to (B.2) effectively reduce it to

⎡⎢⎢⎢⎢⎣

Vak −Va

m

Vbk −Vb

m

Vck −Vc

m

⎤⎥⎥⎥⎥⎦ =

⎡⎢⎢⎢⎢⎣

zaaseries zab

series zacseries

zbaseries zbb

series zbcseries

zcaseries zcb

series zccseries

⎤⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎣

Iaseries−km

Ibseries−km

Icseries−km

⎤⎥⎥⎥⎥⎦ , (B.5)

where

zxyseries = zxy

series −zxn

seriesznyseries

znnseries

, x,y=a,b,c. (B.6)


For power-flow calculations, the equivalent phase-frame series admittance is given by

⎡⎢⎢⎢⎢⎣

yaaseries yab

series yacseries

ybaseries ybb

series ybcseries

ycaseries ycb

series yccseries

⎤⎥⎥⎥⎥⎦ =

⎡⎢⎢⎢⎢⎣

zaaseries zab

series zacseries

zbaseries zbb

series zbcseries

zcaseries zcb

series zccseries

⎤⎥⎥⎥⎥⎦

−1

. (B.7)

As indicated in Chapter 2, the SFPS requires evaluating the 3 × 3 series and shunt

admittance matrices. This is achieved using

⎡⎢⎢⎢⎢⎣

y00x y01

x y02x

y10x y11

x y12x

y20x y21

x y22x

⎤⎥⎥⎥⎥⎦ = T−1

⎡⎢⎢⎢⎢⎣

yaax yab

x yacx

ybax ybb

x ybcx

ycax ycb

x yccx

⎤⎥⎥⎥⎥⎦T , x=series or shunt, (B.8)

where

T =

⎡⎢⎢⎢⎢⎣

1 1 1

1 a2 a

1 a a2

⎤⎥⎥⎥⎥⎦ , a = 1� 120◦. (B.9)

Three-phase three-wire lines do not have a neutral conductor. The rows and the

columns corresponding to the neutral wire, in (B.1)-(B.3), are omitted. Consequently,

the Kron reduction step, conducted in (B.5), is unnecessary. Thus, (B.6) becomes

zxyseries = zxy

series , x,y=a,b,c. (B.10)

B.2 Two-phase Power Lines

Consider a two-phase, three-wire line connected between phase-a, phase-b, and the

grounded neutral. Eq. (B.2) and (B.3) become

⎡⎢⎢⎢⎢⎣

Vak −Va

m

Vbk −Vb

m

Vnk −Vn

m

⎤⎥⎥⎥⎥⎦ =

⎡⎢⎢⎢⎢⎣

zaaseries zab

series zanseries

zbaseries zbb

series zbnseries

znaseries znb

series znnseries

⎤⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎣

Iaseries−km

Ibseries−km

Inseries−km

⎤⎥⎥⎥⎥⎦ , (B.11)


and

fourline12

⎡⎢⎢⎢⎢⎣

Iashunt−km

Ibshunt−km

Inshunt−km

⎤⎥⎥⎥⎥⎦ =

1

2

⎡⎢⎢⎢⎢⎣

yaashunt yab

shunt yanshunt

ybashunt ybb

shunt ybnshunt

ynashunt ynb

shunt ynnshunt

⎤⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎣

Vak

Vbk

Vnk

⎤⎥⎥⎥⎥⎦ , (B.12)

respectively.

Since Vnk and Vn

m are both zero, (B.12) can be simplified to

⎡⎢⎣ Ia

shunt−km

Ibshunt−km

⎤⎥⎦ =

1

2

⎡⎢⎣ yaa

shunt yabshunt

ybashunt ybb

shunt

⎤⎥⎦⎡⎢⎣ Va

k

Vbk

⎤⎥⎦ . (B.13)

Using Kron matrix reduction, (B.11) is be reduced to

⎡⎢⎣ Va

k −Vam

Vbk −Vb

m

⎤⎥⎦ =

⎡⎢⎣ zaa

series zabseries

zbaseries zbb

series

⎤⎥⎦⎡⎢⎣ Ia

series−km

Ibseries−km

⎤⎥⎦ , (B.14)

where

zxyseries = zxy

series −zxn

seriesznyseries

znnseries

, x,y=a,b. (B.15)

The equivalent 2 × 2 phase-frame series admittance matrix is given by

⎡⎢⎣ yaa

series yabseries

ybaseries ybb

series

⎤⎥⎦ =

⎡⎢⎣ zaa

series zabseries

zbaseries zbb

series

⎤⎥⎦−1

. (B.16)

The 3 × 3 phase-frame series admittance matrix is reconstructed by adding a row

and a column with zero entries to the 2 × 2 admittance matrix of (B.16), corresponding

to phase-c. The same procedure is applied to the shunt admittance matrix of (B.13).

Finally, the two 3× 3 phase-frame admittance matrices are plugged in (B.8) to evaluate

their sequence-frame counterparts.

are modeled the same way as shown in Section B.2, except that the Kron reduction

step performed in (B.14) is not conducted.

For un-grounded two-phase lines (also known as V-lines [62]), the rows and the

columns corresponding to the neutral wire, in (B.12) and (B.11), are omitted. Thus,

(B.15) becomes

zxyseries = zxy

series , x,y=a,b. (B.17)

Appendix C

Steady-State Power-Flow Models of

Electrical Loads

As discussed in Chapter 2, electrical loads are incorporated in the SFPS using their

sequence-frame model. The following analysis evaluate the phase-frame load parameters

and convert them to their sequence-frame counterparts.

C.1 Constant Power Loads

C.1.1 Four-Wire/Three-Wire Wye-Connected Loads

Fig. C.1 shows a schematic diagram of a four-wire (or a three-wire wye-connected)

constant power load connected to Bus-k. The phase-frame currents injected by the load

are given by

Figure C.1: Phase-frame model of three-phase four-wire, constant power load

144

Appendix C. Steady-State Power-Flow Models of Electrical Loads 145

Figure C.2: Phase-frame model of three-phase delta-connected constant power load

⎡⎢⎢⎢⎢⎣

Iaload

Ibload

Icload

⎤⎥⎥⎥⎥⎦ = −

⎡⎢⎢⎢⎢⎣

(Saload/V

ak)

∗(Sb

load/Vbk

)∗(Sc

load/Vck)

∗

⎤⎥⎥⎥⎥⎦ , (C.1)

where Sxload is the complex power absorbed by phase-x. For single-phase and two-phase

loads, the corresponding missing phase current(s) is (are) substituted by zero in (C.1).

As indicated in Chapter 2, the load model incorporated in the SFPS requires evalu-

ating the sequence-frame line currents. This is achieved using

⎡⎢⎢⎢⎢⎣

I0load

I1load

I2load

⎤⎥⎥⎥⎥⎦ = T−1

⎡⎢⎢⎢⎢⎣

Iaload

Ibload

Icload

⎤⎥⎥⎥⎥⎦ , (C.2)

where T is given by

T =

⎡⎢⎢⎢⎢⎣

1 1 1

1 a2 a

1 a a2

⎤⎥⎥⎥⎥⎦ , a = 1� 120◦. (C.3)

It should be noted that, for three-wire loads, I0load is equal to zero.

C.1.2 Three-Wire Delta-Connected Loads

The schematic diagram of a delta-connected constant power load, connected to Bus-k, is

depicted in Fig. C.2. Prior to evaluating the line currents, the line-to-line voltages are

calculated using


⎡⎢⎢⎢⎢⎣

Vabk

Vbck

Vcak

⎤⎥⎥⎥⎥⎦ =

⎡⎢⎢⎢⎢⎣

1 −1 0

0 1 −1

−1 0 1

⎤⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎣

Vak

Vbk

Vck

⎤⎥⎥⎥⎥⎦ . (C.4)

The phase-to-phase currents injected by the load are given by

⎡⎢⎢⎢⎢⎣

Iabload

Ibcload

Icaload

⎤⎥⎥⎥⎥⎦ = −

⎡⎢⎢⎢⎢⎣

(Sab

load/Vabk

)∗(Sbc

load/Vbck

)∗(Sca

load/Vcak )∗

⎤⎥⎥⎥⎥⎦ , (C.5)

where Sxmload is the complex power absorbed by the load connected between phase-x and

phase-m. Finally, the phase-frame line currents injected by the load are given by

⎡⎢⎢⎢⎢⎣

Iaload

Ibload

Icload

⎤⎥⎥⎥⎥⎦ =

⎡⎢⎢⎢⎢⎣

1 0 −1

−1 1 0

0 −1 1

⎤⎥⎥⎥⎥⎦

⎡⎢⎢⎢⎢⎣

Iabload

Ibcload

Icaload

⎤⎥⎥⎥⎥⎦ . (C.6)

The phase-frame line currents of (C.6) are then used to evaluate their sequence-frame

counterparts using (C.2).

C.2 Constant Current Loads


Fig. C.3 shows a schematic diagram of a four-wire (or a three-wire wye-connected)

constant power load connected to Bus-k. Constant current loads are characterized by

their constant current magnitude and constant power-factor [62].

The phase-frame currents injected by the load are given by

⎡⎢⎢⎢⎢⎣

Iaload

Ibload

Icload

⎤⎥⎥⎥⎥⎦ =

⎡⎢⎢⎢⎢⎣

Iasp

�(π + θV a

k− ϕa

)Ibsp

�(π + θV b

k− ϕb

)Icsp

�(π + θV c

k− ϕc

)

⎤⎥⎥⎥⎥⎦ , (C.7)

where ϕx and θV xk

are the load power-factor and phase-x to neutral voltage angles,

respectively. Ixsp is the specified current magnitude of the load connected to phase-x, and


Figure C.3: Phase-frame model of three-phase four-wire, constant current load

is given by

Ixsp = Sx

load/Vxk , (C.8)

where Sxload and V x

k are the rated power and phase-to-neutral voltage of the load connected

to phase-x, respectively. For single-phase and two-phase loads, the corresponding missing

phase current(s) is (are) substituted by zero in (C.7). The phase-frame line currents of

(C.7) are then used to evaluate their sequence-frame counterparts using (C.2).


Fig. C.4 shows a schematic diagram of a delta-connected constant current load connected

to Bus-k. Prior to evaluating the line currents, the line-to-line voltages are calculated

using (C.4).

The phase-to-phase currents injected by the load are given by

⎡⎢⎢⎢⎢⎣

Iabload

Ibcload

Icaload

⎤⎥⎥⎥⎥⎦ =

⎡⎢⎢⎢⎢⎣

Iabsp

�(π + θV ab

k− ϕab

)Ibcsp

�(π + θV bc

k− ϕbc

)Icasp

�(π + θV ca

k− ϕca

)

⎤⎥⎥⎥⎥⎦ , (C.9)

where ϕxm and θV xmk

are the load power-factor and phase-x to phase-m voltage angles,

respectively. Ixmsp is the specified current magnitude of the load connected between phase-

x and phase-m, and is given by

Ixmsp = Sxm

load/Vxmk , (C.10)

where Sxmload and V xm

k are the rated power and phase-to-phase voltage of the load connected

between phase-x and phase-m, respectively. The phase-to-phase currents calculated in

(C.9) are used to evaluate the injected line currents using (C.6). Finally, the phase-frame


Figure C.4: Phase-frame model of three-phase delta-connected constant current load

Figure C.5: Phase-frame model of three-phase four-wire, constant impedance load.

line currents are used to evaluate their sequence-frame counterparts using (C.2).

C.3 Constant Impendence Loads


The phase-to-neutral admittances of the constant impedance load shown in Fig. C.5 are

given by

yxxload =

Sxload(

V xk

)2� − ϕx , x=a,b,c, (C.11)

where Sxload, V x

k , and ϕx are defined in Section C.2.1. The sequence-frame admittances

are calculated using


Figure C.6: Phase-frame model of three-phase delta-connected constant impedance load.

⎡⎢⎢⎢⎢⎣

y00load y01

load y02load

y10load y11

load y12load

y20load y21

load y22load

⎤⎥⎥⎥⎥⎦ = T−1

⎡⎢⎢⎢⎢⎣

yaaload 0 0

0 ybbload 0

0 0 yccload

⎤⎥⎥⎥⎥⎦T. (C.12)


The phase-to-phase admittances of the constant impedance load shown in Fig. C.6 are

given by

yxmload =

Sxmload(

V xmk

)2� − ϕxm , n, m = a,b,c; n �= m (C.13)

where Sxmload, V xm

k , and ϕxm are defined in Section C.2.2.

Using delta-star transformation, the equivalent phase-to-neutral admittances are given

by [76]

yaaload =

yabloady

caload

yabload + ybc

load + ycaload

,

ybbload =

yabloady

bcload

yabload + ybc

load + ycaload

, (C.14)

yccload =

ybcloady

caload

yabload + ybc

load + ycaload

.

The sequence-frame admittances are then calculated using (C.12).

Appendix D

Schematic Diagrams of the

PSCAD/EMTDC Models

The schematic diagram for the developed PSCAD/EMTDC model of the six bus test

system of Fig. A.1 is shown in Fig. D.1. The simulation model is composed of (i) an

equivalent model of G1 formed by a constant three-phase voltage source with a negative

and zero-sequence impedance, (ii) user-defined model of three-phase, four-wire, untrans-

posed, power-lines, (iii) three-phase constant power loads, (iv) three-phase transformers,

and (v) user-defined model of a three-phase VSC-based DER unit model.

Figure D.1: PSCAD model of the test system in Fig. A.1

The interface medium of a three-phase VSC-coupled DER unit is represented in

PSCAD by a controlled three-phase voltage source behind an RL filter impedance, Fig.

D.2. The VSC controllers are developed based on the methods described in [35–37,91,92].

150

Appendix D. Schematic Diagrams of the PSCAD/EMTDC Models 151

Figure D.2: PSCAD model of a three-phase VSC-coupled DER unit

Fig. D.3 illustrates the PSCAD model of a three-phase Type-3 (DFAG) -based DER

unit. The RSC and GSC controllers are developed based on the methods described

in [78–81,83]. All the elements constructing sub-circuits of both types of the three-phase

VSC-based DER units are selected from the PSCAD standard library.

Appendix D. Schematic Diagrams of the PSCAD/EMTDC Models 152

Figure D.3: PSCAD model of a three-phase Type-3 based DER unit

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