Computer-Aided Digital System Design and AnalysisUsing a Register Transfer Language

HERBERT SCHORR, MEMBER, IEEE

Summary-This paper presents the results of an attempt to describing a digital system in terms of sequential circuitautomate part of a formalized method of system design. Basic to this theory, nor how to present this information to a com-method are two languages, Boolean algebra and a register transfer puter, is known. In general, it appears that new tech-language. From a Boolean algebra description a digital system can beconstructed while the second language can be used in a step by step niques will have to be developed before integrated de-description of the execution of each instruction. To illustrate, a sign is possible.register transfer language is used to give a description of an adder The second possible way of automating the design ofconsidered as part of a digital system. This description is then trans- a digital system is to try to formalize the largely heuris-lated into a set of Boolean equations. tic methods used today in digital system design. Formal-

Next, the automation of this translation by using a syntax-directed izn and utomatinthese sys i esF Icompiler is explained. The compiler requires a syntactic description iZing and automating these heuristics involves the choiceof register transfers. This description is given using a meta-language of suitable formal languages in which the design can becalled Backus normal form. A Backus normal form description of described. The definition and translation of such lan-Boolean equations that is used for translating Boolean equations into guages and their application to automating part of theregister transfers is also given; this translation process is called

.. formal design procedure is the subject of this paper.analysis. The feasibility of computer-aided design and analysisis thereby demonstrated.is thereby demonstrated.

~~FORMALIZING THE LOGICAL DESIGN OFThe computer-aided design method described in this paper, be- ALI IGITHE LGCLESsides eliminating drudgery and error, would permit several system A DIGITAL SYSTEMdesigns to be attempted and evaluated; a permanent record of the A computer is described by a set of logic diagrams.chosen system would also be available for future modifications, These in turn can be represented b a set of Booleanmaintenance, and simulation. The analysis programs could be used to

.' F ycheck the effect on the system of any changes made in the Boolean equations. For almost all digital computers such a setequations (or equivalently the logical diagrams) and the effect of any of equations can be reduced to a sum of products formunused operation codes. in which all redundant terms have been removed [9].

Standard techniques and algorithms for doing this exist.The reverse problem of converting a set of minimal-sum-

V[HE UTILIZATION of computers in designing of-products Boolean equations into a set of logical dia-jdigital systems is a recent innovation. Computers grams or Boolean equations that represent them is moreare now being used to perform routine jobs: posi- difficult. This second set of equations must functionally

tioning the computer elements, providing the back panel represent the same computer but must also take intowiring, printing parts lists, checking and recording logi- account the fan-in, fan-out, amplifier, hazard, etc. re-cal diagrams, doing a large part of the drafting, etc. quirements, and the use of other than AND-OR logic[1]-[6]. Engineering and production times have been elements. Work on this problem is being pursued else-considerably reduced by these techniques. Computer where [10] and it is expected that at least a partial com-aid in the logical design of a digital system represents puter-aided solution will be obtained. In any case, aa natural extension of these automation procedures. hand solution to this problem is always possible. Hence,There are two possible ways of automating the logical any set of sum-of-products Boolean equations can be

design of a digital system. The first of these is to try to said to represent a constructional description of a digitaldesign a digital system as an integrated whole. This is a system.difficult problem; one approach to its solution is to view The digital system design problem can then be re-a digital system as a large sequential circuit [7]-[9]. duced to the problem of obtaining such a constructionalTheoretically, then, the techniques of sequential cir- description. The design of a digital system usually in-cuitry can be used to design a digital system as a single volves 1) the choice of a set of instructions appropriatesequential circuit. However, for a large system the for the job to be handled by the digital system, 2) theamount of information (i.e., the total number of states) choice of a set of registers to be used to execute theseto be handled is still excessive even if the designer is instructions, 3) the choice of a sequence of register trans-aided by a computer. Moreover, no adequate way of fers, that is, a sequence of transfers of information be-

Manuscript received March 23, 1964. This work was supported in twe th eitr,t xct teisrcin,4 hpart by the Bell Telephone Laboratories, Inc., Murray Hill, N. J. conversion of these transfers into Boolean equations,

The author is with the IBM Research Center, Yorktown Heights, and 5) the interaction of 1), 2), 3), and 4). However,N. Y. He was formerly with the Dept of Electrical Engineering, th en reuto tp3 a efraie ntrsoPrinceton University, Princeton, N. J. teedrslto tp3 a efraie ntrso

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Schorr: Computer-Aided Digital System Design and Analysis 731

microprograms [11] in which the step by step execution or more register transfers are initiated simultaneously,of each instruction is described; each step is a register the register transfers are separated by a semicolon,transfer. This paper describes a set of algorithms and C R + S T; U V;programs for converting a) a set of microprograms intoBoolean equations (synthesis), and b) a set of Boolean The notation presented above and the use of paren-equations into a set of register transfers (analysis). Be- theses to change the precedence of operators suffices forsides other advantages discussed later, this set of pro- the example below. The full language is presented in thegrams would automate step 4) of the above design pro- references cited and includes the obvious notation forcedure. Before these programs can be written, a lan- indirect addressing, decoding, addition, subtraction andguage suitable for describing register transfers in a pre- complementation, and notation to identify subregisters.cise, compact, and unambiguous way is required; one In addition, conditional register tranfers and derivedsuch language is presented in the next section. registers are introduced; the latter is used in the descrip-

tion of arithmetic algorithms.A REGISTER TRANSFER LANGUAGE

The language briefly described here is an adaptation SYNTHESIS OF MERCER's ADDERof a register transfer language first presented by Reed To illustrate, first, the use of the above language and,[12]- [14]. Each register in a digital system is identified second, the output produced by the synthesis programs,by a string of characters and is also considered to be a an adder will be designed. In Fig. 1 an adder originatedvector with n components. Thus, if R is a register identi- by Mercer [15] is reproduced. At pulse time 2 a bit-by-fier then R [i] is the ith flip-flop, or the ith component, bit addition is performed; any carries generated areof register R. Then R-*S causes the contents of register shifted left and stored in N. When there are no moreS to be replaced by the contents of register R, and carries, the addition is completed; this condition is de-R[i]->S[i] causes the contents of flip-flop i of register termined when D= 0. To the adder originated by Mer-S to be replaced by the contents of the flip-flop R[i]. cer the following changes are made: 1) Register M isThe usefulness of treating the contents of a register as added to hold the augend and eventually the result ofa vector becomes apparent when one considers the fol- the addition, 2) the overflow provision consists of light-lowing transfers: ing an overflow indicator bulb attached to register L

R + S Tand 3) a pulse time 5 is added. After finishing an addi-tion, the adder remains in pulse time 5 until the adder

R * S -> T is restarted by a signal from the ADD flip-flop. Table IR 0 S -> T results from Fig. 1 by incorporating these changes and

combining some of the transfers occurring at variousT. pulse times; the register transfer notation described

The connectives + , 0, and ' indicate, respectively, above is used.the logical operations of inclusive disjunction, conjunc- Ttion, sum modulo 2, and negation and are to be appliedcomponent by component. Octal literal constants (such To obtain a set of Boolean equations from Table I, theas 248) can be used in place of register identifiers in the flip-flops used to construct the registers must be speci-above transfers. If R is an n-bit register, then vR is an fied. To conform to the synthesis programs written, itabbreviation for R [1] +R [2] + *. +R [n]. The sym- is assumed that the registers of the adder are to be con-bol v is introduced to improve the readability of F+vR structed from set-reset flip-flops [9]. The notationswhich stands for F+R[1]+R[2]+ * *. +R[n]. A N[i]/1 and N[i]/0 are used to indicate that flip-flop icomma is used to indicate the concatenation of two or of register N is to be set, or reset, respectively. Withmore registers OF, N, A. Various operators to indicate Table I as its input, the synthesis programs would firstshifting can also be introduced. For example, LjR-*OF, derive the equations of Table II. These would then beN will be used to denote the left shift operation which combined by the synthesis programs into the equationsis an abbreviation for the three simultaneous transfers: of Table III.

For a large digital system these equations would cor-R[i]--OF[-i-J]; inj+1, n-j+2, *, n; respond to the equations of the arithmetic and logical

R[i-j]--yN[iJ; i=j+1,j+2, * , n; unit of the system. These equations are derived in termsOyN[i];i= 1, 2, * , j. of ti. The latter represent pulse times in Mercer's adder

but t. can also be interpreted as representing state t, ofIn any digital system these register transfers will be the control unit of a digital system. That is, when theinitiated by a control signal. If C is a control signal then control unit is in state tj, either one control signal (called|C |: R + S -> 7'; t~) or a whole set of control signals will be generated.

For the moment it will be assumed that t1 represents arepresents a microinstruction and indicates that the single control signal; the second possibility will be con-register transfer R+S-*T is executed when C= 1. If two sidered later.

732 IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS December

TABLE IIITUE BOOLEAN EQUATIONS FOR THE ALU

A[i]/l ==N[i].A[ijI'.t2N[i]'.A[i] t2 i=l, 2, , nOFN-REGISTER A[i]/O = N[i] -A [i' *t2+N[iJ'*A[i] *t2 i=1, 2, n

Dll -N-+* N[n1jtA2[n-21] *t2n-1

X g A-REGISTER 0g 00 - Z N[i] -*A [i] * t2i=l

Pulse time M icro-operations DIO =-t+D't3(1) Put augend in N; Llt =OF-DI'-t3Set D==OF==O L/O = OF'.D'-t3-ADDt4

(3) a) if D=i; set D=O, go to (2) M[iJ/0=A[i]'.D'.t3 i'=1, 2, , fl,,b) if D-=; (addition complete) Ni/lll =M[it-l+N[&i1;tA[i-1It2 i=2,3, n

if OF= 1, go to (4) N[i]/O =M[i]'.ti+N[i-1J'.t2---A[i-1P*t12 i=n2, 3,. nif OF=O0, (all done) N[11/11=M[1]*t,

(4) (provision for overflow) N[1]/O=M[1}' *tl +t2(all done, go to next machine instruction.) OF/i = N[nJ A[n] -t2OF/O =t1+N[nJ'.t2-j-A[nl'.t2Fig. 1-Adder originated by R. J. Mercer. (Reproduced by permis-

sion from R. J. Mercer, "Micro-programming," J. ACM, vol. 4,pp. 151-171; April 1957.)

TABLE IVTHE MICRO-OPERATION CONTROL SEQUENCE FOR THE ADDER

TABLE I it, I 1 -2FINAL MICRO-OPERATIONS OF ADDER It3ID1 -3t2

It3D' :1.itllMN; I~~~~~~~~~~~~~It4-ADD :1t

0- 40F; 1 I2 t4 * ADD' I| t42. t2 N1SA A;

L1(N-A)-*OF, N;v(N-A)--- lt;

3a. t3*D'j: A-M; tOF---->L; 0--O-ADD It4

3b. lt3.Dj: O-*D; lt24a. t4-ADD'1: Tlt44b. t4-ADD I: O-*L; 1 t:;

D

TABLE II t3*DPRELIMINARY FORM OF THE ALU BOOLEAN EQUATIONS

_ | I 14 121 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~3' DFrom 1:

N[i]/ = M[i] tl =1 *** n T ADDND]/0 =-t[l i= 1,*t , n P0 X |t-DD/O = t1OF/O = t1

-D

From 2: r4A [i]/lI = (N[i] (8)A [i]) *t2 i=1***,n U LA [i]/0 = (N[i] (g3A [i])' * t2 i1,***,nIN[i+11/i=N[iJ A[i] - i-1, n-1 Fig. 2-Delay line synthesis of the adder's control unit.N[i+1]/0 = (N[i] *A [i] )' * t2 i ,***,n-1OF/I = N[n] *A [n] * t2OF/0=(N[n]*A[n])' * t2D/1 =N[1] A[1I*t2+N[2j.A[2] *t2+ TABLE V

Df-DN[n -1]-A[n-liJ 2 THE CONTROL SEQUENCE IN TERMS OF THE STATES OFD/O =13.D THE FLIP-FLOPS OF THE CONTROL COUNTER TFrom 3:

lI[i/O=A[i}'D'At, i=1,I I *, n2. fT[1F'IT[2.T-*T[iI;

From 4: 5- IT[i].T[21'.ADDITj1l/O = ADD*t4 6. T[iJ* T[2]'*ADD' 1:

1964 Schorr: Computer-Aided Digital System Design and Analysis 733

TABLE VI complete decoding net [16] is introduced so that Fig. 3SET AND RESET EQUATIONS FOR REGISTER T results. A third type of control unit that can be used

follows the design introduced by Wilkes [Ii]. Since the(a) algorithm has not yet been programmed, it will not be

1. T[21/1 = T[1]' T[2]1 discussed further here.2. T[1]1/= T[1]'. T[213. T[2/O0=T[|1 T[2].D' As previously mentioned, the control unit instead of4. T[1]/O= T[1] T-[21 -D generating a single control signal ti, may generate a5.T*1]/O=T[1i T[2]'.ADD whole set of control signals. This is only possible for the

(b) second type of control unit. Instead of using a completeT[1/1=T[1]'T[2]C decoding net as in Fig. 3, the outputs of T[1] and T[2]T[1]/0_=T[l] .T[2iD-C+T[1]T[2]'-ADD.C could be used to directly initiate the appropriate registerT[2]/1 = Tf1]'. FfT2]'. C transfers. In this case the appropriate equations wouldT[2]/0=Tfl] T[2] .D'-C be obtained by the synthesis programs from Table VII

which is a combination of Tables I and V.

t4 t3 t2 ti ANALYSISThe synthesis and analysis programs themselves are

best introduced after the meaning of the "analysis" ofdigital systems has been discussed. The analysis prob-lem is the reverse of the synthesis problem and requiresthe conversion of Boolean equations into register trans-

Ttl[ )1 Tt2] fers. It is assumed that the registers of the digital sys-S R Sz R& tem to be analyzed are constructed from set-reset flip-

flops and that every Boolean equation in the construc-tional description has been converted into sum of prod-ucts form. Whenever any clause in such an equation hasthe value 1, a flip-flop is set (or reset). Therefore, each

. _ADD clause on the right side of an equation specifies a set ofconditions under which a flip-flop is to be set (or reset).

uTM' Unless information is transferred in a random mannerFig. 3-Logical diagram of the control register, T. such a clause can usually be divided into two parts: 1) a

control expression which is a conjunction of literals eachTABLE VII of which represents a control signal, and 2) a register ex-

MICRO-OPERATIONS OF THE ADDER iN TERMS OF STATES pression which is a conjunction of literals each of whichOF THE FLIP-FLOPS OF THE CONTROL COUNTER T represents a flip-flop.

T[1J'. T[2]'J: M-*N; 0-4D; ExampleT[1]'. T[2}' I: 0-OF 1-*T[2] Suppose that each flip-flop of register S is to be set

L,(N-A)--~OF, N; equal to the corresponding flip-flop of register R. ThisV(N -A)-->D; 1--T[1]; is to be done by clearing S to all zeros during time P,

T[1] T[2] D'I: A-+M; OF--LA; and setting to 1 those flip-flops of S corresponding to0-*ADD; 0- T[2]; flip-flops of R which are 1, during time Q. This requiresIT[l] T[2] D I: O--D; 0--T[l]; in addition to the clock signals, P and Q, that the con-TfI T[2]'.ADD'j:FT[1]-T[2]'-ADD 1: O-*L; 0-*T[1]; trol unit issue two signals, 1) CS-clear register S, and

2) SRS-set register S to 1 wherever register R is 1.The Boolean equations,

The prescribed sequence of the control signals t. isgiven in Table IV. This sequence could be provided by S[iJ/O = CS P 1, 2, * * *, n; (1)several different types of control units; three types will S[i]j1 = SRS.R[i] -Q i = 1, 2, * n; (2)be discussed here. The first control unit designed is con- yield the desired results. The clauses of these equationsstructed from delay lines and corresponds directly to .

Table IV; it isrshowninFig.2.Thf may be dvded into "two parts"; in (1),the registercontrol unit uses a register or control counter T con- exrsso pato h luei auu.Es 1 n 2

stuce wit tw flpflp in whc eac t isrpe can be rewritten as register transferssented by a state ofT. If the Gray encoding [9] of the | CS-P |: 0 -S[i] (3)states of T is used, Table V results. Then by using ISRS.QI: {R[i]} -S[i] i = 1,2, * , n; (4)Table V as the input to the synthesis programs, theequations of Tables VI(a) and VI(b) result. Finally, a where the brackets { , } have been introduced to indi-

734 IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS December

cate that flip-flop S[i] is to be set to 1 wherever flip-flop However, before this explanation can proceed a syntaxR[i] is 1. Transfers (3) and (4) are called elementary table must be obtained.register transfers because they can often be combined. To obtain a syntactic description of Boolean equa-For example, the equations, tions as used in the constructional description of a

QR[i]/lT1 QP[i] + i = 1, 2, 3 digital system, requires a precise definition, in a formTR.j]11QP[i]

-

T + j=

41 52 6 acceptable to the compiler, of a clause in such an equa-QR[j]/l= QR[j] T+ *. j =4, 5, 6 tion. Assuming that "control expression" and "registerexpression" have already been defined,are translated by the analysis programs into: y

IT rrP.[i] QR [i];i 1 2 3; 1) a control expression is a clause,1Tl:{QP[tJJ - QR[i]; i = 1, 2,3; 2) a register expression is a clause,T : {QP[j]} QR[j]; j = 4, 5, 6; 3) a clause concatenated with and a register expres-

sion is a clause,The e o t e analysis programs will convert 4) a clause concatenated with and a control expres-the above output into sion is a clause, and

TI: {QP[i]} - QR[i]; i = 1, 2, 3, 4, 5, 6; 5) the only clauses are those formed by rules 1), 2),3), and 4).

THE TRANSLATING MECHANISM ANDTHE ANALYSIS PROGRAMS "Control expression" may be defined recursively in

terms of "control signal";The synthesis and analysis programs use the syntaxdirected compiler developed by Irons [17], [14]. This 1) a control signal is a control expression,compiler was developed to translate programs written 2) a control expression concatenated with and ain a problem-oriented formal language, ALGOL 60 [18] control signal is a control expression, andinto assembly language programs. By changing partof 3) the only control expressions are those formed bythe compiler called the syntax table, the compiler can rules 1) and 2).be made to translate any formal language (Li) into an- If A, B, and C are control signals, then A, A *B, andother language (L2). In particular, Boolean equations C A -B, are both control expressions and clauses. Acan be translated into elementary register transfers and register expression can be similarly defined. The aboveregister transfers into clauses of Boolean equations. See definitions can be restated in a meta-language calledFig. 4. Backus normal form [19].

BOOLEAN TABLE VIII

EQULATINS CMILER REGISTEREQUATIONS TRANSFER ANALYsIS SYNTAXANALYSISSYNTAX (control expression):: - (control signal)

(a) THE ANALYSIS PROGRAM (control expression). (control signal)REGISTER CLAUSES OF (register expression): = (register variable)TRANSFERS MPILERBOOLEAN (register expression) - (register variable)

EQUATIONS (clause) : : = (register expression) (control expression)(clause) (control expression)(clause) (register expression)

(bI THE SYNTHESIS PROGRAM (range) : : = (register variable)/1 (register variable)/O(signal)Fig. 4-The use of a syntax directed compiler in the analysis (domain):c : = (clause) (domain)+ (clause)

and synthesis of digital systems. (logical equation):: (range) (domain)

The syntax table contains a syntax meta-language de- The Meta-Languagescription, or syntactic specification, of the formal lan- The Backus normal form meta-language consists ofguage to be translated. The syntax of the language is meta-linguistic variables, connectives and basic sym-used by the compiler to determine which formulas bols. A meta-variable denotes a member of a class of(Boolean equations or register transfers) are well- expressions. Thus, the meta-variable (control expression)formed or grammatically correct; in a formal language denotes a member of the class of control expressions,only the well-formed formulas are meaningful. The com- e.g., A, A -B. The previous definition by recursion of apiler determines the well-formed formulas by analyzing csk oeach of the parts or subformulas of a given formula ofRL and seeing whether or not these are well-formed. If (control expression):: = (control signal) (5)a subformula is well-formed, then it is translated into L2. (control expression):: = (control expression)By doing this for each subformula a translation of the(cnrlsga) (6entire formula is obtained. To further clarify the method(cnrlsga) (6of translation the operation of the analysis program will Eqs. (5) and (6) are calledformation rules, and the meta-be explained; the synthesis program operates similarly. variable to the left of :: = is the subject of the formation

1964 Schorr: Computer-Aided Digital System Design and Analysis 735

rule. Finally, (5) and (6) can be combined into definition output of (domain), (range), and (logical(control expression):: = (control signal) equation) are, respectively, ISRS Q {R [i]}*A,(control expression) -(control signal) (7) S[i], and I SRS Q | { R [i] } -S [i ].

Examplewhere is given the meaning of "or" or disjunction. The Thecombined definition (7) is called a syntactic formula. A Thesynaxwirecdmpiler intran l the lst

.. . ~~~~the syntax directed compiler in translating the lastregister expression may be similarly defined syntacti- equation. The input consists ofcally; these rules are given as part of Table VIII.

begin comment sample problem endTranslation into Elementary Register Transfers register variable (R[i], S[i]);Any equation which corresponds to the syntactic control signal (SRS, Q);

definition of Table VIII will be translated into one of dothe following elementary register transfers: S[i]/1=SRS R[i] Q

end sample problem end.|(control expression) | *rgister expression) en}ape polmed(ctlxei) (rengister)xpreso This input is examined in two passes. During pass I, the(range) compiler extracts the fact that R[i] and S[i] are register(control expression) :1 (range) variables and that SRS and Q are control register vari-(register expression)} (range). ables. It obtains this from the declaration which is the

second and third lines of the sample program.If the register expression or control expression part of a During pass II the equation is translated by the com-clause is vacuous, then the second or third translation, piler. The declaration has already assigned syntacticrespectively, results; otherwise the first translation re- variables or categories to the identifiers in the equation.sults. The compiler performs this translation by deter- For example, R[i] is a register variable. From this in-mining if a particular equation corresponds to the formation the compiler, by referring to the syntacticdefinition of a logical equation given in Table VIII. specification given in Table VIII, proceeds recursivelyThe compiler translates an equation by partially trans- to build up "larger" and "larger" categories. This islating every clause. The clause SRS R[i] Q of (2) is shown in Table IX which is called a formation diagram.translated into SRS. Q| {R [i] }-* * A where * A is adummy variable. * A is eventually replaced by the regis- TABLE IXter variable or signal part of the range, in this case by FORMATION DIAGRAM FOR THE EQUATION S[iJ/l = CRS R[]. QS [i . _The translation is obtained by associating a definition s)i] /I . cs * R[i) * Q

enclosed in the brackets { , } with each formation rulein the syntax table. If part of an equation correspondsto a formation rule, the sequence of output symbols range/S~ )specified by the definition of the formation rule formsthe definition output associated with that part of the contsig/CRS'equation. This definition is also associated with the sub-ject of the formation rule, and since every meta-variable contexp/CRSis a subject, every meta-variable has a definition output clauseassociated with it. The formation rules are used recur- ICRS*B5: *C*Asively to determine if the equation is well-formed; the rogvor/Risequence of output symbols is simultaneously changedand added to. This is accomplished by using the output rgexp/RWl]string designator pn. For example, P1 in the definition of , _l(range) = (domain) = (logical equation)4pl[*A < p3}cIuse/ICRS*8IR CAasserts that the definition output of this formation rule contslg/Qis formed from the definition output of the meta-vari- contexp/Qable (domain) which is one place to the left of =with all occurrences of the symbol * A replaced by the clauSe /ICRS.Q*B: {R(i] *C} *Adefinition output of (range). Notice that the order of ocnlRo I_*lthe formation rule has been "reversed" and the subjectdoan/RSQ:(ii.of the formation rule appears to the right of = : : . This logical equatian/ ICRS .Ql: fREi]} -eS(j].way of writing the formation rules corresponds to the KEYway they are tabled and used by the syntax directed regvar- register variable conteig- control signal

comile.Fo the eutinS[]/ SR *R [i. th regexp- register expression conteip- control expression

736 IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS December

TABLE XSYNTHESIS SYNTAX

(logical operator):: + D(expression):: = (variable) (expression)(logical operator)(variable)(control expression part):: = (expression)(register expression part):: (expression)--(variable)

I (expression) } --(variable) i1 -(variable) iO-*(variable)(register transfer):: = (control expression part): (register expression part);(register transfer)(register expression part);

The compiler proceeds until the category (logical equa- The transfers are to be executed for the values of I andtion) is either reached or determined to be unreachable. J specified by the first line of the program, also called aIf the input equation falls into the latter case the equa- for equation, except if the transfer is followed by a sub-tion is rejected and not translated; it is not well-formed. script expression. Thus, the third transfer applies forIf it does become a (logical equation), then the equation I= 0, 1, 2 and J= 0, 1, 2 but the first applies for I= 1is translated into elementary register transfers. The only. The intention is to precede a set of register trans-translation obtained at each step is shown after the fers by a for equation which gives the dimensions ofsolidus in Table IX. every register involved. If such a for equation is used,

any transfer involving the entire register can be writtenA mbiguity asAs illustrated in the example, a declaration is required VV :R[I] -* S[I];

in every syntax directed program. In the declaration theexplicit use of every literal appearing in the Boolean while those involving only part of a register must beequations as either a control signal or register variable followed by the appropriate subscript expression. Ais given. However, in some clauses a literal may repre- simplified syntactic description of the register transferssent a control signal and in others a register variable. To acceptable as input to the synthesis programs is givenhandle this problem requires a more complicated syn- in Table X. This syntactic description indicates thetactical description of Boolean equation. This essen- set of register transfers acceptable as input to the firsttially involves subdividing the literals that may appear trial version of these programs. This version did not ac-in an equation into those whose appearance is always un- cept the entire set of possible register transfers as pos-ambiguous and those that are ambiguous. If an ambigu- sible inputs; a sufficient set was chosen so that thoseous literal is then encountered in a clause, the following not acceptable could be described in terms of those ac-scheme is used: If the register expression part of a clause cepted. For example, 24-+T must be replaced byis vacuous, the ambiguous literal is assigned to the regis- 0-T[I]; 1= 1, 2, 3, 5, 7, 8; and 1-*T[I]; 1=4, 6; sinceter expression part of the clause; if the control expres- the only literal constants recognized by the synthesission part is vacuous, the reverse follows. This procedure programs are 0 and 1. This, of course, can be easilybreaks down if neither expression is vacuous, in which changed in a second expanded version.case an arbitrary predetermined choice is made. This,of course, only affects the interpretation of the resultingregister transfer but does not, for example, affect the Once the register transfers have been converted intocombination of elementary register transfers. clauses of Boolean equations they must be combined

as the equations of Table II were combined into theTHE SYNTHESIS PROGRAMS equations of Table III. This is a problem in symbol

In the reverse process of synthesis no ambiguity in manipulation; the left sides of the Boolean equationsthe meaning of a literal can occur. Hence the declara- must be compared to determine when matches occur.tions do not specify the types of variables present. In- Programs were written that used the syntax directedstead, they serve to give the dimensions (number of compiler to execute this task; it appears that a muchflip-flops) of the registers used in the system. In the ver- better solution would be to use a string manipulationsion of the synthesis programs that were programmed language such as COMIT [20]. Similar remarks applythese declarations were given as part of a program in the to the syntax directed programs written to combinefollowing form: elementary register transfers.

begin for 1=0, 1, 2; J=0, 1, 2; do CONCLUSION| AC| Q[-+2 QRI; I = 1; This report describes an attempt to automate theQP[I21QR[I]

~~~design and analysis of digital systems. The need for de-AJC + QP[2] 1:1 -*R[I]; veloping more powerful tools, including new languages,| AC + D'|{SI]Q[;in order to increase the degree of automation is recog-

I~~~ ~~2II'~~~~ nized. However, it is believed that the feasibility ofend automation and in particular the methods presented

1964 Schorr: Computer-Aided Digital System Design and Analysis 737

here has been demonstrated; the use of a similar set of analysis of serial computers is also under study. Theautomation programs in the actual design of a large economic utility of the programs themselves remains todigital system is a necessary next step. be shown. The cost of using the programs in the actualThe automation procedure presented in this paper re- design or analysis of a system is unknown. However, in

quires the designer to formalize his design by using a comparison with human beings a computer is both fasterregister transfer language. Once a register transfer de- and less liable to make an error in, for example, thescription of a digital system is obtained the set of pro- derivation of the complete Boolean equations of a digitalgrams would be used to derive the Boolean equations system; this may justify the cost of using such programsthereby eliminating both drudgery and error. These as the digital systems designed grow more complex.Boolean equations would be obtained faster by programthan by hand. In addition, the register transfer descrip- ACKNOWLEDGMENTtion provides a readily understood permanent record The author wishes to thank Prof. E. J. M\cCluskey,of the system. It could also be used for maintenance, who brought the subject of this paper to the author'ssimulation and future modifications of the system. The attention, for many helpful discussions and suggestions.programs also permit the designer to see rapidly the ef-fects of any changes made in the register transfer de-scription of the system; several versions of a system [1] M. Kloomak, P. W. Case, and H. H. Graff, "The printing re-cording, checking, and printing of logical diagrams," Proc.could be tried out to determine the best one. Some cost Eastern Joint Computer Conf., pp. 125-132; 1958.criteria, such as a diode count, might be added to the [2] W. L. Gordon, "Data processing techniques in design automa-tion," Proc. Eastern Joint Computer Conf., pp. 205-209; 1960.synthesis programs to help determine the best version. [3] V. A. Hannig and T. L. Mayes, "Impact of automation onThe analysis programs can be used to check that a digital computer design," Proc. Eastern Joint Computer Conf.,pp. 211-232; 1960.digital system meets all of the original specifications and [41 G. L. Baldwin, T. H. Crowley, and C. W. Rosenthal, "Design

to check the effect of any unused instruction codes. Automation-a Look at the Future," presented at the AIEEWinter Meeting, New York, N. Y., January 29-February 3,However, the analysis programs require the Boolean 1961.equations of a digital system 1) to be in sum of products [5] C. R. Warburton, "Automation of logic page printing," pre-sented at the AIEE Summer Meeting, Ithaca, N. Y., conf.form, 2) to be set-reset equations, and 3) to have all paper no. C.P. 61-726; June 18-23, 1961.literals appearing in them identified. The preliminary [6] A. L. Leiner, A. Weinberger, C. Coleman, and H. Loberman,

"Using digital computers in the design and maintenance of newproblem of obtaining the Boolean equations themselves computers," IRE TRANS. ON ELECTRONIC COMPUTERS, vol. EC-is usually hardest to solve (for existing machines); pro- 10, pp. 680-690; December, 1961.[7] D. A. Huffman, "The synthesis of sequential switching circuits,"grams can be written to 1) put any set of Boolean equa- J. Franklin Inst., vol. 257, pp. 161-190, pp. 275-303; Marchtions into sum of products form, and 2) to convert any and April, 1954.[8] E. F. Moore, "Gedanken-experiments on sequential machines,"equation written in terms of the memory elements dis- in "Automata Studies," C. E. Shannon and J. McCarthy, Eds.,cussed by Phister [21 ] into a set-reset equation; human Princeton University Press, Princeton, N. J., pp. 129-153; 1956.[9] S. H. Caldwell, "Switching Circuits and Logical Design," Johnintervention is needed to meet the third requirement. Wiley and Sons, Inc., New York, N. Y.; 1958.Similarly, the synthesis programs only generate sum-of [10] Private communication to the author.[11] M. V. Wilkes and J. B. Stringer, "Micro-programming and theproducts equations for set-reset equations. Programs to design of the control circuits in an electronic digital computer,"7convert these into equations for any memory element Proc. Cambridge Phil. Soc., vol. 44, pt. 2, pp. 230-238; April,1953.can be written [14]. However, only programs to gener- [12] I. S. Reed, "Symbolic Design Techniques Applied to a Gener-ate minimal two level AND-OR circuits from these eralized Computer," M.I.T. Lincoln Lab. Lexington, Mass.,TR. no. 141; Jan. 3, 1957.equations exist [22]; algorithms for obtaining other [131 T. C. Bartee, I. L. Lebow, and I. S. Reed, "Theory and Designtypes of circuit do not exist. Moreover, no practical con- of Digital Systems," The McGraw-Hill Book Co., Inc., NewYork, N. Y.; 1962.siderations such as fan-in and fan-out restrictions are [14] H. Schorr, "Towards the Automatic Analysis and Synthesis oftaken into account. These last problems, however, lie Digital Systems," Ph.D. dissertation, Dept. of Electrical Engi-

neering, Princeton Univ., N. J.; December, 1962.primarily in the area of combinational switching circuit [15] R. J. Mercer, "Micro-programming," J. Assoc. Comp. Mach.,theory research and are not of immediate interest here. vol. 4, pp. 157-171; April, 1957.16] D. R. Brown and N. Rochester, "Rectifier networks for multi-

Further study of the control unit algorithms is in positioning switching," PROC. IRE, vol. 37, pp. 139-147; Febru-progress. The problem of sorting the output of the anal- ary, 1949.[171 E. T. Irons, "A syntax-directed compiler for ALGOL 60,"ysis program into a set of microprograms where each Commun. Assoc. Comp. Mach., vol. 4, pp. 51-55; January, 1961.microprogram corresponds to the execution of a single [18] P. Naur, ed. "Revised report on the algorithmic languageALGOL 60," Commun. Assoc. Comp. Mach., vol. 6, pp. 1-17;instruction also awaits solution. For synchronous com- January, 1963.puters, a possible method of attack is to first collect all 119] J. XV. Backus, "The syntax and semantics of the proposed inter-

national algebraic language of the Zurich ACM-GAMM con-register transfers which contain the same operation code ference," Proc. Inter. Conf. Information Processes, UNESCOliterals in their control expression parts. These would pp.125-132; June, 1959.1201 V. H. Yngve, "A programming language for mechanical transla-then be ordered according to the timing signals appear- tion," Mech. Translation, vol. 5, pp. 25-41; 1958.ing in their control expression parts. A corresponding 1211 M. Phister, "Logical Design of Digital Computers," John Wileysolution for asynchronous digital systems would require [221 E. J. McCluskey, Jr. and H. Schorr, "EssentiaLl multiple-outputknowledge of the sequence of control signals initiated by prime implicants," Proc. Symp. Mathematical Theory of Au-tomata, Polytechnic Institute of Brooklynl Symposia Series,each operation code. Computer-aided synthesis and Brooklyn, N. Y., pp. 437-457; April, 1962.