Computer Architecture 2

Patrick Marshall

Gates per CPUGates per CPU

• Vacuum tube- 1946-157

• Transistor 1958-1964

• Small Scale integration –1965 on– Up to 100 devices on a chip

• Medium Scale integration – to 1971– 100-3,000 devices on a chip

• Large Scale integration 1971-1977– 3,000-100,000 devices on a chip

• Very Large Scale integration – 1978 to date– 100,000 – 100,000,000 devices on a chip

• Ultra large Scale integration– Over 100,000,000 devices on a chip

Moore’s LawMoore’s Law

• Increased density of components on chip

• Gordon Moore – cofounder of Intel

• Number of transistors on a chip will double every year

• Since 1970’s development has slowed a little– Number of transistors doubles every 18 months

• Cost of a chip has remained almost unchanged

• Higher packing density means shorter electrical paths, giving higher performance

• Smaller size gives increased flexibility

• Reduced power and cooling requirements

• Fewer interconnections increase reliability

Moore’s LawMoore’s Law

CPU ( revisited)CPU ( revisited)

• Control Unit

• ALU

• Bus

• Registers– Program Counter Register

– Intruction Register

– General Purpose Registers

Instructions within a CPUInstructions within a CPU

1. Add the number stored in box 9 to your secret agent code number

2. Divide the previous result by the number stored in box 10

3 Subtract the number stored in box 8

4 If the previous result is not equal to 30, go to box 7. Otherwise to the nexy box

5 Subtract 13 from the previous result

6 Return to HQ for more information

7 Bomb… too bad 8 20

9 11 10 2

Instructions within a CPUInstructions within a CPU

• Three different classes of instructions– Boxes 1,2,3,5 are arithmetic operations

– Box 4 contains a conditional jump or conditional branch

– Box 6 contains the return instruction, which is a control instruction which contains no data and refers to no other address

• Each arithmetic and conditional jump consists of two parts an operation and an address

Von-Neumann ArchitectureVon-Neumann Architecture

Registers ALUControl

Unit

CPU

Commmunication Bus

Memory (forIntructions and

date)I/O

The Von- Neumann Bottleneck

RegistersRegisters

• Not all registers are the same size– Data or Instructions need to be same size as a

memory location

– In an 8 bit Microprocessoer• Data registers are 8 bit wide

• Address registers are 16 bit wide– Giving 64K addressable

• Memory Locations need to be large enough to hold the highest memory location

– Intel 80806 has 20 bit memory register –Max addressable size was 1024k (1Mb)

– Motorola 68000 has 32 bit memory register• Max addressable size should be 232 which is 4096 Mb

• But is only 224 which is 16Mb

ALUALU

• ALU– Performs arithmetic and logic operations

– Data can come from memory or input devices or registers

– Most CPU has 8+ registers, 8 bit CPU’s have 1 register called the accumulator

ACC

ALUFlags (CCR)

Control Unit

Control UnitControl Unit

• To connect registers on the bus a control signal is required

• Everthing happens on a clock cycle, like the computers heartbeat

• Fetches and executes intructions– Translates macroinstructions into

microinstructions• Smallest event that can take place inside a CPU

– Clocking a flip-flop

– Moving data from one register to another

Register Transfer LanguageRegister Transfer Language

• A shorthand for expressing what happens inside a CPU.

• 1 or more letters followed by numbers indicates registers or memory location

• Square brackets means “the contents of”

• Left arrow means transfer

• MS means the computers memory Main Store MS(X) means the valuein the main store at memory location X

• E.G– [MAR] [PC]– [PC] [PC] + 1– [MS(20)] [PC]

Register Transfer LanguageRegister Transfer Language

• MAR –Memory Address Register

• MBR- Memory Buffer Register

• MDR – Memory Data Register

Operation of a computerOperation of a computer

• Known as the Fetch-Execute cycle or Machine Cycle

– Fetch the next instruction from memory into the control unit

– Decode instruction

– Obey the instruction

– Go back to 1

Fetch Execute in DetailFetch Execute in Detail

• Program counter contains (points to) the address of the next instruction in memory

• Step 1: [MAR] [PC] ‘ Contents of PC are moved into the MAR

– MAR holds the address of a location in memory into which data is being written or read

– MAR now holds the contents of the PC

• Step 2: [PC] [PC] + 1 ‘The program is incremented

• Step3: [MBR] [MS([MAR])– MBR takes the value of the memory location held in

MAR– MBR is temporary holding place for data received from

memory– MBR contains the bit pattern of the instruction to be

executed

Fetch Execute in DetailFetch Execute in Detail

• Step 4: [IR] [MBR] ‘Instruction register takes value of MBR

– IR now contains the bit pattern of the instruction to be executed

– Divided into fields, operator and operand

– Single address instructions

• Step 5: CU [IR(op-code)]– The control unit executes the instruction

Lets look at the Add instructionLets look at the Add instruction

• Example:– P=Q+R

• Single Accumulator

• Move Q,DO

• Add R,DO

• Move DO,P

– More complex instruction set,single clock cycle

• Add Q,R,P

Lets look at the Add instructionLets look at the Add instruction

• Step 1: [MAR] [IR(address)]– [MAR] takes the address part of the instruction

register

• Step 2:[MBR] [MS([MAR])]– Memory buffer takes the value of the data

stored in memory at the address in [MAR]

• Step 3: ALU [MBR],ALU [D0]– ALU adds the contents of the [MBR] with the

contents of data (accumulator register D0

• Step 4: [D0] ALU

More on OperationMore on Operation

• Fetch cycle is always the same

• Different execution cycles depending on the instruction, one per instuction

• Instruction Groups– ALU instructions

– Move or copy instructions

– Transfer of control

Branching/JumpingBranching/Jumping

• Branch forces the CPU to execute instructions out of the normal sequence

• Conditional Branch allows high level contructs such as IF THEN ELSE to be executed

– Based on values in the CCR

• CCR- Condition Code Register– After the CPU executes an instruction, it updates the

bits of the CCR

– C= Carry Flag

– Z=Zero Flag

– N=Negative Flag

– V= Overflow

CCR- Condition Control UnitCCR- Condition Control Unit

• CCR as we saw is connected to the Control Unit

• BCC Branch on carry clear C=0

• BCS Branch on carry set C=1

• BEQ Branch on zero result Z=1

• BNE Branch on non-zero result Z=0

• BMI Branch on minus result (two’s comp) N=1

• BPL Branch on positive result (tow’s comp) N=0

• BVC Branch on overflow clear (two’s comp) V=0

CCR- Condition Control UnitCCR- Condition Control Unit

• BVS Branch on overlfow set (two’s comp) V= 1

• BGE Branch on greater than or equal to N.V+N.V=1 used in two’s compliment arithmetic

• BGT Branch on greater than N.V.Z+N.V.Z=1

• BHI Branch if higher than C.Z=1 Used in unsigned arithemtic

• BLE Branch if less than Z+N.V+N.V=1 used in tow’s comp arithmetic

• BLS Branch if lover than or the same C+Z=1 Used in unsigned arithmetic

CCR- Condition Control UnitCCR- Condition Control Unit

• BCC adrs: IF [C]=0 THEN [PC] [IR(adrs)]

• Branch on carry clear ( jump to the target address of the carry bit in the CCR is 0)