Computer ArchitectureIntroduction
S. Coudert and R. Pacalet
Telecom ParisInstitut Mines-Telecom
March 2, 2021
1 / 64 March 2, 2021 Telecom Paris Institut Mines-Telecom Computer Architecture — Introduction
Outline
1 General introduction
2 General computer architectureComponentsCommunication, interconnectionIntegration
3 Multilevel architectureHardwareArchitecture, micro-architectureInstruction Set Architecture (ISA)Assembly languageSoftware execution (brief overview)
Invoking softwareOperating System (OS)Booting a computer
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Acknowledgements
David Wentzlaff (Princeton University)Agner Fog (Technical University of Denmark)David Andrew Patterson (University of California, Berkeley)John Leroy Hennessy (Stanford University)James R. Larus (École Polytechnique Fédérale de Lausanne)
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Course content
CompArch
Digital
Lev. 1:
Operating system
Problem−oriented languageLev. 5:
Lev. 3:
Lev. 2: Instruction set architecture
partial interpretation
interpretation or direct execution
translation: assembler
hardware
compiler or virtual machine
Lev. 4:
Microarchitecture
Lev. 0:
Assembly languageuser
System software
Application software
Environment
Hardware
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The CompArch course at a glance
Short introduction to computer architecture8 to 10 lectures, 3 hours each• discussions• lecture• exercises
4 to 5 labs, 3 hours each, 30% of final gradeMaybe 2 mini-conferences (2×1.5 hours), mandatoryExam, 2 hours, 70% of final grade• Questions• Problems• With documents (any document you like)
A WEB site: https://perso.telecom-paris.fr/pacalet/CompArch/A GitLab project for the labs: https://gitlab.eurecom.fr/renaud.pacalet/comparch
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General computer architecture
Hundreds of kinds of computersWork stations, servers, desktop and laptop PCs…Multiprocessor, networked computers, clustersEmbedded systems:• Smart phones, tablets…• Application specific architectures
— Satellites— Smart cards— Automotive…
• Micro-controllers• Systems on Chip (SoC)• IoT
Many different (standard) components, combined for specific applications
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Components (1)
Computing
CPU, GPU, dedicated
hardware accelerators...
Communication
Busses, networks,
dedicated devices...
antennas...
Receiving inputs
Memories, sensors,
Providing results
Memories, display
actuators, wires...
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Components (2)
Storage• Read-Only Memory: ROM• Programmable Memory: PROM, EPROM, EEPROM…• Random Access Memory: SRAM, DRAM…• Mass storage
— Hard Disk Drives (HDD, magnetic)— Solid State Drives (SSD, flash) non-volatile memories
Input/Output• Port or bus controller: UART, GPIO, USB, Ethernet…• Graphics controller, keyboard controller• Wireless card, sound card…• Analogue devices: (RF, microphone, sensors…)
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Components (3)
Computing• Integer unit, CPU, coprocessor, Floating Point Unit (FPU),…• Hardware accelerators
Communication (internal)• Buses & bridges, Network on Chip (NoC)• Point-to-point links: interrupt, on chip accelerator…
Performance improvement units:• Direct Memory Access (DMA) controller• Interrupt controller• Caches, Memory Management Unit (MMU)
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Interconnection, example architecture
CoP
InterruptHandler
CA
CH
E
MM
U
DMA
UART
(scanner,...)
(printer,...)
HardwareAccelerator
GraphicBoard (screen,...)
Busses
Bridges
(mouse, modem,...)ROM
CPU
CPU
RAM
USB
PIO
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Integration…
CHIP
RAM
DMA
UART
PIO
USB
DeviceBoard
Hard.Accel.
CPU
CoP
CA
CH
E
MM
U
IRQ
ROM
RAM
DMA
UART
PIO
USB
DeviceBoard
Hard.Accel.
CPU
CoP
CA
CH
E
MM
U
IRQ
CHIP
ROM
RAM
DMA
UART
PIO
USB
DeviceBoard
Hard.Accel.
CPU
CoP
CA
CH
E
MM
U
IRQ
CHIP
ROM
RAM
DMA
UART
PIO
USB
DeviceBoard
Hard.Accel.
CPU
CoP
CA
CH
E
MM
U
IRQ
CHIP
ROMCtrl.
Mem.
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PC architectures: variants, evolutionsMonitor
Keyboard Floppy disk drive
Hard disk drive
Hard disk
controller
Floppy disk
controller
Keyboard controller
Video controllerMemoryCPU
Bus
Single bus (ISA), 80’s����Memory bus
CPU PCI bridge
SCSI controller
SCSI disk
Network controller
Video controller
Printer controller
Sound card ModemISA
bridge
SCSI scanner
Main memorySCSI
bus
PCI bus
ISA bus
cache
Multi-bus (ISA + PCI), 90’s
(a) (b)
CPU
Shared memory
Bus
CPU CPU CPU
Local memories
CPU
Shared memory
Bus
CPU CPU CPU
Multiprocessor
ISA: Industry Standard ArchitecturePCI: Peripheral ComponentInterconnect
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PC architectures: variants, evolutions
VIA chipset KT400 for AMD Athlon XP, 2000’s
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PC architectures: variants, evolutions
PT894 for Intel Pentium IV, 2000’s
P55-iCore7, 2010’sDMI: Direct Media Interface
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PC architectures: variants, evolutions
http://www.gaisler.com/
Leon Sparc by Cobham Gaisler AB
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PC architectures: variants, evolutions
Leon Sparc by Cobham Gaisler AB21 / 64 March 2, 2021 Telecom Paris Institut Mines-Telecom Computer Architecture — Introduction
Multilevel architecture, principles
Level 0, language 𝐿0
Level 𝑛, language 𝐿𝑛
Level 𝑖, language 𝐿𝑖
Level 1, language 𝐿1
𝐿𝑖 sentences translated to 𝐿𝑖−1• Interpreted (on-the-fly)• Compiled (off-line)• Interpreted + Just-in-Time
CompiledSame principle, many use cases• Software (programming
languages)• Networking (protocols)
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Multilevel computer architecture
CompArch
compiler or virtual machine
Lev. 3: Operating system
Lev. 4: Assembly language
Problem−oriented languageLev. 5:
Lev. 2: Instruction set architecture
partial interpretation
interpretation or direct execution
translation: assembler
hardware
Lev. 0: Digital
Lev. 1: Microarchitecture
user
Hardware
System software
Environment
Application software
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Hardware
CPU, Instruction Set implementationMicro−Architecture
Digital
Physical
System
Micro−electronics, transistors
Logic gates, combinatorial logic
Memory elements, memories
Computer, CPU + peripherals
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Micro-electronics, logic gates
Micro-electronics: transistors. Signal: voltageDigital: logic gates. Signal: boolean (0,1)
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Combinatorial glue logic
input output
propagation
time
input events
output effects
Input changes immediately start propagating to outputsPropagation delays unavoidable (up to now)Frequent need to wait until signals stabilize
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Combinatorial circuits (1)
Data processing example: 1-bit adder (with carry)
A B Carry in Carry out Sum0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
Carry in
AB
Sum
Carry out
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Combinatorial circuits (2)
Signal selection: datapath controlMultiplexor: select one input among several
F
D0
D1
D2
D3
D4
D5
D6
D7
A B C
A A B CB C
form, 𝑛 bits)
𝐷0
𝐷𝑘
𝐷2𝑛−1
𝑘 (binary
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Combinatorial circuits (3)
Select by index: control signals, addressesDecoder: assert one output among several
D0
D1
D2
D3
D4
D5
D6
D7
A
C
B
A
B
C
B
C
A
form, 𝑛 bits)
𝐷0
𝐷𝑘
𝐷2𝑛−1
𝑘 (binary
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Combinatorial circuits (4)ALU: Arithmetic and Logical UnitInput function code selects the operation
AINVA
ENAB
Logical unit Carry in
AB
B
Enable lines
F0
F1
Decoder
Output
Sum
Carry out
Full adder
A + B
ENB
code op
ALU A op B
B
A
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Storage (1)
D Q
CK
(a)
D Q
CK
(b)
D Q
CK
(c)
D Q
(d)
CK
Memory elementsLatches and D-flip-flop: Q takes the value of D(a) D latches. When enable is 1(b) D latches. When enable is 0(c) D-flip-flops. On rising edge(d) D-flip-flops. On falling edge
D-flip-flops: input signal must be stable around clock edge
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Synchronous hardware
Clock driven: outputs production driven by clock signalExample: falling edge triggered D-flip-flopsToggling values considered only at clock falling edges (regularity)Simplified design: propagation delay can be ignored but……D-flip-flops based ⇒ input signals stable
Input events
Outputs
Outputs
Inputs
clock
clock
time
Falling edges
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Storage (2)
Multi-bit registersSRAM (Static RAM)
2 bits D-flip-flop register: 8 bits D-flip-flop register:
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Storage (3)
Memory arrays𝑘-bits cells ⇒ 𝑘-bits data bus2𝑛 cells ⇒ 𝑛-bits addressesMemory size: 2𝑛×𝑘 bits
deco
der
data bus
address bus
Cells
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
0
1
2
3
4
5
Example: three 96−bits memory orgnisations
6×16-bits cells𝑛 = 4, 𝑘 = 8 𝑛 = 3, 𝑘 = 12
8×12-bits cells12×8-bits cells𝑛 = 3, 𝑘 = 16
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Storage (4)Enable/disable register write, 2 approaches:
...but conbinatorial logicon clocks⇒ skews...
write enable
in outmultiplexer (mux)
inwrite enable
out
beware propagation delays
CLK CLK
Register access: asynchronous read, synchronous write
CLK CLK
decoder
address
output value
0 1 0
ci dia0
0
a0
a0
a1
1
ci
di
ai cibi di
write enable
input value
a1
R1
R1
R0 R0
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Storage (5)
Data in
Write gate
I0
I1
I2
QD
CKWord 0
Word 1
Word 2
Word 3
O1
O2
O3
CS
RD
OE
Word 0 select line
Word 1 select line
Word 2 select line
CS • RD
A0
A1
Output enable = CS • RD • OE
QD
CK
QD
CK
QD
CK
QD
CK
QD
CK
QD
CK
QD
CK
QD
CK
QD
CK
QD
CK
QD
CK D0
A0A1A2A3A4A5A6A7A8A9
A10A11A12A13A14A15A16A17A18
D1D2D3D4D5D6D7
WE
(a)
512K 3 8 Memory
chip
(4 Mbit)
CS OE
A0A1A2A3A4A5A6A7A8A9
A10
RAS
CAS
D
WE
(b)
4096K 3 1 Memory
chip
(4 Mbit)
CS OE
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From combinatorial to synchronous
Registers insertion for component synchronization
c
d
a cb
x
x
y
y
z
z
F(.) F(.)
F(.)
F(x)
F(x)
F(z)
F(y) F(x) F(y) F(w)
F(x) F(y) F(z)
F(x) F(y)
F(y) x y w
dcba
cba
a
b
c
x y z a
b
c
x y z w
a
b
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Exercise on synchronous logic
? Exercise #1: Complete the waveforms
5
14
o
x
s
b
a
i
t
1 1 0
a
b
s
i
k
o
10
11
0
7
0
8
12
1
1
9 2
0
6
1
5
9
0
8
2
8
5
6
9
5
5
3
+ m
u
x
+
a
b
s
0
10
o
i ?
k
m
u
x
m
u
x+
1
a
b
i
s
x
o0
1
0
t
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Micro-architecture: CPU
CPU instruction: binary code of “elementary” CPU operationRunning program = set of (ordered) instructions stored in memory
⇒ CPU loads instructions from memory, decodes and executes
CPU
Program counter
Register file
external}
devices
{on chip
Memory
ports
addresses
unmapped
Coprocessors, other CPU features
Control wires (interrupts,...)
Computing units
on boardregister
Instruction
Control logic INTERCONNECT
asso
ciat
es a
ddre
sses
to l
oca
tions
to execute instruction
Code of currentinstruction
(drive multiplexors, ...)
instruction address in memory
(optimisation)
(UAL,...)
fast access to local data
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CPU communication
Address bus (𝑛 bits) specify location, data bus convey data⇒ Address space = {0,…,2𝑛−1}Dedicated wires for interrupt signalling, coprocessors, surrounding hardware of multi-coreCPU….Note: CPU also export information about its internal state
Deviceinterfaceregisters
Unmappedwriteread
CPU
0
addr
data
addresses
Memories2 −1
n
interrupt
coprocessors,...
INTERCONNECT
Control
Internals...
Memory Mapping
Address Space
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CPU communication
Address bus and addressspace• Bus: n wires ⇒ 2𝑛
addresses• Memory map: component
locations in address space• Mapping logic: bus
controller, for example.
CoP
Controler
Interrupt
UART
send/receive
externalport
Dat
aB
us
Ad
dre
ssB
us
portdedicated
chip select
Bus
IU
CHIPCPU
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CPU communication (example)
CoP Dat
aB
us
Ad
dre
ssB
us
portdedicated
chip select
Bus
IU
CHIPCPU
Interrupt
UART
Controler
send/receive
portexternal
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CPU communication (example)
CoP Dat
aB
us
Ad
dre
ssB
us
portdedicated
chip select
Bus
CHIPCPU
UART
send/receive
externalport
Controler
Interrupt
managerinterruptprogram:
IU
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CPU communication (example)
CoP Bu
s
portdedicated
Bus
CHIPCPU
UART
send/receive
externalport
Controler
Interrupt
IU
READUART input
chip select
Bu
sA
dd
ress
Dat
a
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CPU communication (example)
CoP Dat
aB
us
Ad
dre
ssB
us
portdedicated
Bus
CHIPCPU
UART
send/receive
externalport
Controler
Interrupt
program:IU
UART inputRECEIVE
chip select
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CPU: instruction execution
Memories
CPU
write
Step 1: Instruction Fetch
addr
data
read
addressesUnmapped
Deviceinterfaceregisters
interrupt
InstructionRegister
counter
Program
coprocessors,...
Data
Code
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CPU: instruction execution
data
MemoriesStep 2: Execute and update
read
Return to step 1
program counter
addresses
Deviceinterfaceregisters
Unmapped
CPU
write
addr
interrupt
coprocessors,...
InstructionRegister
Code
DataUP
DATE
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CPU: instruction execution
interface
writeread
Execution can cause other accesses
data
addr
addressesUnmapped
Device
registers
MemoriesCPU
interrupt
UPDATE
Data
InstructionRegister
coprocessors,... Code
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CPU: instruction execution
program counter is set to specific interrupt service routine
addrCPU
writeread
data
Memories
Interrupt lines interrupt running programs :
addresses
Device
registersinterface
Unmapped
interrupt
Register
Codecounter
Data
Instruction
coprocessors,...
Program
Changed
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What an instruction can do
Read or write in address spaceRead or write in CPU data registersWrite Program Counter (PC)Write CPU configuration registersCompute values and store them somewhereDrive coprocessor…Chain several such action, that is…execute a microprogram…
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Instruction Set Architecture
An ISA is a well-define hardware/software interface:• An instruction set with a functional definition and a user manual• No guarantees regarding implementation and performance
History and practice: various instruction sets• Realisation: choices between hardware and software
Evolution:
Simple instructions
Hardware Hardware
Complex instructions
Software
Complex Programs
Software
Simple Programs
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Instruction set: evolution
CISC
Complex Instruction Set ComputerReduced number of simple instructions ⇒ long complex programsComplex instructions in hardware ⇒ increased performanceMicroprogrammed instructions ⇒ easier to extendSimple programs with complex instructions• lower CPU clock frequency or…• …more CPU clock cycles per instruction
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Instruction set: last 25 years trend
RISC
Reduced Instruction Set ComputerSimple instructions ⇒ one per clock cycleSimple instructions ⇒ higher clock frequencySimpler compilersElementary instructions faster than microprogramsPipeline: parallel execution of instructionsNote: RISC and CISC are sometimes combined (ex: Intel)
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Instruction Set / Micro-architecture
Pipelined architecture (typical of RISC)• Split instruction into elementary steps• Each step requires different hardware components• Parallel execution of instructions: one step per clock cycle for each instruction in pipeline• All hardware components are used simultaneously• Goal: start one new instruction per clock cycle
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ISA: Instruction Set Architecture
Instruction examples• Simple ones
— Load memory word in register: ld R1 Addr— Store register in memory: st R1 Addr— Add registers: add R1 R2 R3
• Complex ones (combining memory access and logic)— Load memory word and add to register: ladd R1 Addr
Instruction format: binary• Variable or fixed size• Structured format: fields• Duration: fixed or variable (1 cycle or more)
An ISA is often provided with an assembly language
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Assembly language
Binary code: 0100110110001010111010001010011101010Assembly language, a more readable format:• CPU instructions in textual form with parameters:
— ld R1 R2: load into R1, from address in R2.— jmp #0820: jump at address #0820.— beq R1 R2 #0840 branch at #0840 if R1 and R2 have the same content
• Macros and tools for easier programming:— Pseudo-instructions (abbreviate sequence of real instructions)— Labels:
label1: ld R1 R2;...jmp label1
Assembler (assembly language compiler): reads assembly language and produce binarycode.
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Running software: ways to invoke code
Succession of instructions from bootJumps allow to alter the sequence of instructions in memoryCalling subroutines (with return)
rs
PC
a1
aib1
bmai+1
an
call f: js b1
save ai+1
return: rs
restore ai+1
js b1ai
an
bm
tim
e
Memory
P
fb1
a1
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Running software: ways to invoke code
Interrupt ReQuest (IRQ) signalIRQ cause CPU to jump to Interrupt Service Routine (ISR)PC set to address of ISRUsually return to main code at end of ISR
PCsignal
tim
ea1
aib1
bmai+1
an
IRQ
signal
control
PC
CPU
b1
IRQ
0
1
0
0
0
0
save context
go to ISR
P
ISR
Memory
an
b1
bm
a1
rireturn: ri
restore context
mux
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Software: structuring
Structuring software:• Operating System (OS): services and task management
— Load and execute application software— When multi-task, control task access to resource (CPU, memory…)— Libraries: available code, system calls
• Application software— Focus on specific work, do not manage low level details— Use system calls (libraries)— Is loaded and cleanly terminated by OS
applicationsystem
Memory
CPU
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OS: executing programs
From software saved in binary file on disk to process running in memory1 Find free memory for software code2 Load code in memory3 Identify and locate external resource required by software
— External addresses— External code to load (libraries, system code…)
4 Update code to reflect addresses w.r.t. points 1 and 35 Set PC to entry point of code6 At software termination restore clean global state
� Files containing executable code must be packaged with associated meta-information� Dedicated binary file formats (e.g. ELF)
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Boot sequence
Run code at boot address (hard-wired)• Bare metal code (embedded systems, no-OS systems…)• Operating system (GNU/Linux, Windows, Android…)
— Installs system services: ISRs, device drivers…— If multi-task, installs scheduler— Run system processes (daemons…, depends on system)
• Example: PC boot sequence.— First instructions: hardware initialisation (BIOS)— System initialisation: load Master Boot Record (MBR) from disk— Execute MBR (first system instructions), usually jump to initialisation code located elsewhere— Initialisation code loads next stage— Next stage loads next stage…— System reaches stable state— Interactive programs wait for user inputs
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Course Content
Basics of binary representations and data typesISA and MIPS assembly languageMIPS architecture (mono-cycle, multi-cycle, pipeline)Pipelining, hazardsCaches and memoriesHardware support for OS (supervisor mode, atomic operations, MMU, interrupt controller,timer, DMA…)Labs: MIPS core simulationARM mini-conferences (ARM CPU architectures, design, validation)
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Summary
Questions?
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Further Reading I
D.A. Patterson and L. HennessyComputer Organisation & DesignMorgan Kaufmann, USA
D.A. Patterson and L. HennessyComputer Architecture, A Quantitative approachMorgan Kaufmann, USA
And a lot more in the library…
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