Computer Engineering Capstone DesignSummer A 1998–2000:

Handheld Video GamesJ. S. McDonald

IEEE/HKN Odd-Wednesday TalksMay 24, 2000

http://www.kettering.edu/~mcdonald/ece403/

PIC-Pong• By Rickard Gunee; uses a 4-MHz PIC16F84 and a TV(!)

• the game in action:

• the game:

IEEE/HKNSlide 1

Origi

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ameB

oyPat

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IEEE/H

KN

Slid

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Gam

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win

gs

IEEE/H

KN

Slid

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Gam

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Blo

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IEEE/H

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Slid

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GameBoy Schematic

IEEE/HKNSlide 5

Project Overview (1999)In a Nutshell

Design and build a hand-held video game.

Some Details

The game must

• use a Microchip PIC 16C74A microcontroller

• use a Micro Electronics SG128128 graphic LCD module

• have an appropriate soundtrack and/or sound effects

• be battery-powered, compact, and sturdily constructed

• survive evaluation by a dozen 5th-graders!?!!

IEEE/HKNSlide 6

Project History• 1998: “Original Edition Handheld Video Games”:

– no sound, makeshift buttons and cases

– Games: Street Fighter, Battleship, Breakout, PIC Pilot

• 1999: “Handheld Video Games II”:

– one- or two-track sound, real NES buttons, smaller cases

– Games: Combat!, Bowling, Go Banana!, Tetris, MissileCommand, Duel Tetris, PICman

• 2000: “Ultimate Handheld Video Games” (as in, the last):

– custom printed-circuit boards, even smaller cases, in-circuitemulator for development

– Games: ???IEEE/HKNSlide 7

PIC Overview• Harvard architecture (separate instruction and data memories)

– 14-bit instructions

– 8-bit data

• Single-cycle instruction execution via instruction pre-fetch

1997 Microchip Technology Inc. DS30390E-page 17

PIC16C7X

3.1�

Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided byfour to generate four non-overlapping quadratureclocks namely Q1, Q2, Q3 and Q4. Internally, the pro-gram counter (PC) is incremented every Q1, theinstruction is fetched from the program memory andlatched into the instruction register in Q4. The instruc-tion is decoded and executed during the following Q1through Q4. The clocks and instruction execution flowis shown in Figure 3-4.

3.2�

Instruction Flow/Pipelining�

An “Instruction Cycle” consists of four Q cycles (Q1,Q2, Q3 and Q4). The instruction fetch and execute arepipelined such that fetch takes one instruction cyclewhile decode and execute takes another instructioncycle. However, due to the pipelining, each instructioneffectively executes in one cycle. If an instructioncauses the program counter to change (e.g. GOTO)

�

then two cycles are required to complete the instruction(Example 3-1).

A fetch cycle begins with the program counter (PC)incrementing in Q1.

In the execution cycle, the fetched instruction is latchedinto the “Instruction Register" (IR) in cycle Q1. Thisinstruction is then decoded and executed during theQ2, Q3, and Q4 cycles. Data memory is read during Q2(operand read) and written during Q4 (destinationwrite).

FIGURE 3-4: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

Q1

Q2

Q3

Q4

PC

OSC2/CLKOUT(RC mode)

PC PC+1 PC+2

Fetch INST (PC)Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)Execute INST (PC+1)

Internalphase�cloc� k

All instructions are single cycle, except for any program branches. These take two cycles since the fetchinstruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

• 200-ns instruction cycle

• Reduced instruction set (35 total) . . .

IEEE/HKNSlide 8

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IEEE/H

KN

Slid

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PIC

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EE/H

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IEEE/H

KN

Slid

e11

Development Environment• PICDEM-2 demonstration board

• MPLAB IDE (Integrated Development Environment)

– assembler

– linker

– excellent simulator

Free for download, with many useful application notes

• Chipmaster 6000 device programmer

• U-V eraser

IEEE/HKNSlide 12

PICDEM-2 Demonstration Board

1998 M

icrochip Technology Inc.

DS

30374B-page 79

Ap

pen

dix A

. Hard

ware D

etail

Figu

re A-2:

PIC

DE

M-2 S

chem

atic

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13

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0.1

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+5V

C9 0.1

C13 0.1

R14 10

+5VR15

470GRN

POWER

D1

J8

Y1

TBDC4 20PF

C5 20PF

Not PopulatedOUT

TXCO

RC1 2 3 4 5 6 7 8

OSO OSI RC2 SCL SDA RC5

TX RX

(RC0) (RC1)

(RC3) (RC4)

(RC6) (RC7)

RD1 2 3 4 5 6 7 8

RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7

J41 2 3 4 5 6 7 8 9

KEYBOARD

9 P

IN H

EA

DE

R

RB0 RB1 RB2 RB3

RN3 RB4

RN3 RB5

RN3 RB6

RN3 RB7

RN1 RB0

RN1 RB1

RN1 RB2

RN1 RB3

RN2 RB4

RN2 RB5

RN2 RB6

RN2 RB7

D2

D3

D4

D5

D6

D7

D8

D9

J7

J6

OSC2

Provision Only, Not Populated

Y3

TBDC6 20pF

C7 20pF

+5V

R10 10

R11 10

R12 820

R8 10

R9 10

R13 820

+5V +5V

RA

Y2

J5

8

Breadboard

R19 470

R17 470

R18 470

4

3

RN3

4

4

4

3

3

IEEE/HKNSlide 13

MPLAB IDE

IEEE/HKNSlide 14

LCD Module Overview

Block Diagram:

SRAM8Kx8 bits

LCD128x128

T6963C

FS

RESET

C/D

CE

RD

WR

D7-D0

BiasCircuitVEE

VDDVSS

Toshiba

Controller

• 128× 128-pixel graphics and/or

• 16× 16 array of 8× 8-pixel characters (including user-defined)

IEEE/HKNSlide 15

Gra

phic

LCD

Con

trol

ler

(Tos

hiba

T69

63C)

IEEE/H

KN

Slid

e16

ISD

Chi

pCor

der

Bra

gsby

the

Com

pany

:

Fea

ture

s an

d B

enef

its o

f Chi

pCor

der

Pro

duct

s

Sin

gle-

Chi

p S

olut

ion

Opt

imal

for

ligh

twei

ght,

port

able

pro

duct

s.

Sim

ple

Inte

grat

ion

No

soft

war

e de

velo

pmen

t req

uire

d, q

uick

tim

e to

mar

ket

Exc

eptio

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ound

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atur

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er C

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ands

Chi

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duct

s O

ffer:

V

oice

rec

ord

and

play

back

sys

tem

on

a si

ngle

chi

p 6

seco

nds

to 8

min

utes

rec

ord

and

play

back

dur

atio

ns

Indu

stry

-lea

ding

sou

nd q

ualit

y Fu

lly in

tegr

ated

sys

tem

fun

ctio

ns: A

GC

, mic

pre

amp,

spe

aker

dri

vers

,fi

lters

, osc

illat

or, m

emor

y L

ow v

olta

ge o

pera

tion

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sage

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ible

arc

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e B

atte

ry-l

ess

mes

sage

sto

rage

·| H

ome

|·| A

bout

ISD

|·| P

rodu

cts

|·| A

pplic

atio

ns |·

| Fin

ance

|·| N

ews |

··|

Em

ploy

men

t |·|

Site

Map

|·| S

earc

h |·

| Qui

ckLi

nks

|·

IEEE/H

KN

Slid

e17

ChipCorder Interfacing

Interface to a Typical Microcontroller:

Application N

ote

�

Audible T

hermom

eter Schem

atics

�

AN

1292

�MO

TO

RO

LA19

Date: August 12, 1996 Sheet 1 of 1

Size Document Number REV

B O

Title

TALKING THERMOMETER

VCC

R3100K

C21uF

VDD 3

DQ 2

GND 1

U3

DS1820

VCC

S1

SW PUSHBUTTON

GND

GND

VCC

1

2

P1

GNDR2100K

C31uF VDD 9

VSS 10

RESET 20

IRQ 19

PA7 11

PA6 12

PA5 13

PA4 14

PA3 15

PA2 16

PA1 17

PA0 18PB5 3

PB4 4PB3 5PB2 6

PB1 7

PB0 8

OSC1 1

OSC2 2

U1

M68HC705J1A

VCC

VCC

GND

A9 10

A8 9

A7 8

A6 7

A5 6

A4 5

A3 4

A2 3

A1 2

PD 24

P/R 27

EOM 25

VCCD 28

VCCA 16

SP+ 14

SP- 15

MIC REF 18

MIC 17

VSSA 13

VSSD 12

AUX IN 11

ANA IN 20

ANA OUT 21

AGC 19

XCLK 26

OVF 22

CE 23

A0 1

U2

ISD2545

VCC�

LS1

SPEAKER

J1

PHONEJACK

P2

PHONEPLUG

GND

GND

GNDR1470K

C14.7uF

R4

10

GND

VCC

VCC

GND

NC 1 VCC 14

OUT 8GND 7

Y1

CAN_OSCGND

IEEE/HKNSlide 18

Chi

pCor

der

Dev

elop

men

t•

Qua

drav

oxQ

V-4

00de

velo

pmen

tbo

ard

and

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tpr

ogra

mm

ing

of.w

avfil

es

•Pro

ject

win

dow

:

�•

Wav

efor

med

itor:

IEEE/H

KN

Slid

e19

2000: Printed-Circuit Fab• Layout for Duel Tetris (using Linux freeware pcb):

• Fabrication cost at APC: ≈$100 for 2 copies

IEEE/HKNSlide 20

2000: MPLAB-ICE• MPLAB-compatible In-Circuit Emulation system:

MPLAB™-ICE User’s Gu ide

DS51159A-page 8 1998 Microchip Technology Inc.

1.4 Components of MPLAB- ICE SystemThe MPLAB-ICE system consists of these items (Figure 1.1):

1. Emulator pod2. Parallel cable to connect the emulator pod to a PC3.

�Power supply cable

4.�

Processor module with cable5.

�Device adapter to connect the processor module to the target system

6.�

Logic probe connector

Figur e 1.1: MPLAB -ICE Emulator Sys tem

The e�

mulator pod connects to the PC through a parallel port using the provided cable. It contains the hardware necessary to perform the common em� ulator functions, such as trace, break, and emulate.

The processor module inserts into a slot in the front of the emulator pod. It co� ntains the hardware necessary to emulate a specific device or family of dev

�ices.

The d�

evice adapter is located at the end of the processor module’s cable. It co� nnects to the target system.

A �

logic probe connector is also available. Logic probes may be connected here, or individual jumper leads may be used to connect to individual co� nnector pins. See Appendix A for more information on the connector and logic probes.

Parallel Cable

Power SupplyCable

Emulator Pod

Processor Modulewith Ca ble

Logic ProbeConnector

Device Adapter

• No more code, compile, simulate, burn, reset, crash, erase,code, compile, simulate, burn, reset, crash, erase, . . . cycle!

IEEE/HKNSlide 21