Topics covered:Arithmetic

Computer Organization

2

Number representation

Integers are represented as binary vectors

Suppose each word consists of 32 bits, labeled 0…31.

31 30 ....... ....... ........ ....... .... 1 0

MSB (most significant bit) LSB (least)

V(b) = b31.231 + b30.230 + b29.229 + .... + b1.21 + b0.20

Value of the binary vector interpreted as unsigned integer is:

More generally in N bits,

nNn

nnbbV 2)(

1

0

3

Number representation (contd..)

We need to represent both positive and negative integers.

Three schemes are available for representing both positive and negative integers: Sign and magnitude. 1’s complement. 2’s complement.

All schemes use the Most Significant Bit (MSB) to carry the sign information: If MSB = 0, bit vector represents a positive integer. If MSB = 1, bit vector represents a negative integer.

4

Number representation (contd..)

Sign and Magnitude: Lower N-1 bits represent the magnitude of the integer MSB is set to 0 or 1 to indicate positive or negative

1’s complement: Construct the corresponding positive integer (MSB = 0) Bitwise complement this integer

2’s complement: Construct the 1’s complement negative integer Add 1 to this

5

Number representation (contd..)

0000000011111111

00000000

1111

1111

1100110000110011

1010101001010101

1+

1-

2+3+4+5+6+7+

2-3-4-5-6-7-

8-0+0-

1+2+3+4+5+6+7+

0+7-6-5-4-3-2-1-0-

1+2+3+4+5+6+7+

0+

7-6-5-4-3-2-1-

b3 b2b1b0

Sign andmagnitude 1's complement 2's complement

B Values represented

6

Number representation (contd..)

Range of numbers that can be represented in N bits

Unsigned:

Sign and magnitude:

One’s complement::

Two’s complement::

12)(0 NbV

12)(12 11 NN bV

12)(12 11 NN bV

12)(2 11 NN bV

0 has both positive and negative representation

0 has both positive and negative representation

0 has a single representation, easier to add/subtract.

7

Value of a bit string in 2’s complement

How to determine the value of an integer given: Integer occupies N bits. 2’s complement system is in effect. Binary vector b represents a negative integer, what is V(b).

Writeb = 1 bn-1 bn-2 bn-3 ................ b1 b0

Then

V(b) = -2n-1 + bn-2 2n-2 + bn-3 2n-3 + ......... + b2 22 + b1 21 + b0 20

(v(b) = -2n-1 + bn-2 2n-2 + bn-3 2n-3 + ......... + b2 22 + b1 21 + b0 20

showing negative and positive parts of the expression )

So, in 4 bits, 1011 is

v(1011) = -8 + 3 = -5

8

Addition of positive numbers

Carry-out

1

1

+

011

0

1+

0

0

0

+

1

0

1

+

Add two one-bit numbers

To add multiple bit numbers:•Add bit pairs starting from the low-order or LSB (right end of bit vector)•Propagate carries towards the high-order or MSB (left end of bit vector)

9

Addition and subtraction of signed numbers

We need to add and subtract both positive and negative numbers.

Recall the three schemes of number representation. Sign-and-magnitude scheme is the simplest

representation, but it is the most awkward for addition and subtraction operations.

2’s complement is the most efficient method for performing addition and subtraction of signed numbers.

10

Addition and subtraction of signed numbers (contd..)

Consider addition modulo 16 operation

Example: (7+4) modulo 16: -Locate 7 on the circle. -Move 4 units in the clockwise direction. -Arrive at the answer 11.

Example: (9+14) modulo 16: -Locate 9 on the circle. -Move 14 units in the clockwise direction. -Arrive at the answer 7.

0 12

3

4

5

6

78910

11

12

13

14

15

11

Addition and subtraction of signed numbers (contd..)

00000001

0010

0011

0100

0101

0110

01111000

1001

1010

1011

1100

1101

1110

1111

1+1-2+

3+

4+

5+

6+7+

2-

3-

4-

5-

6-7- 8-

0

Different interpretation of mod 16 circle: - Values 0 through 15 represented by 4-bit binary vectors. - Reinterpret the binary numbers from –8 through 7 in 2’s complement method.

Example: Add +7 to –3 -2’s complement of +7 is 0111. -2’s complement of –3 is 1101. -Locate 0111 on the circle. -Move 1101 (13) steps clockwise. -Arrive at 4(0100) which is the answer.

0 1 1 1 +1 1 0 11 0 1 0 0

Ignore carry out

12

Rules for addition and subtraction of signed numbers in 2’s complement form

To add two numbers: Add their n-bit representations. Ignore the carry out from MSB position. Sum is the algebraically correct value in the 2’s

complement representation as long as the answer is in the range –2n-1 through +2n-1 –1 .

To subtract two numbers X and Y (X-Y): Form the 2’s complement of Y. Add it to X using Rule 1. Result is correct as long as the answer lies in the range –2n-1

through +2n-1 –1 .

13

Overflow in integer arithemtic

When the result of an arithmetic operation is outside the representable range an arithmetic overflow has occurred. Range is –2n-1 through +2n-1 –1 for n-bit vector.

When adding unsigned numbers, carry-out from the MSB position serves as the overflow indicator.

When adding signed numbers, this does not work. Using 4-bit signed numbers, add +7 and +4:

Result is 1011, which represents –5. Using 4-bit signed integers, add –4 and –6:

Result is 0110, which represents +6.

14

Overflow in integer arithmetic (contd..)

Overflow occurs when both the numbers have the same sign. Addition of numbers with different signs cannot cause an

overflow. Carry-out signal from the MSB (sign-bit) position is not a

sufficient indicator of overflow when adding signed numbers.

Detect overflow when adding X and Y: Examine the signs of X and Y. Examine the signs of the result S. When X and Y have the same sign, and the sign of the

result differs from the signs of X and Y, overflow has occurred.

15

Addition/subtraction of signed numbers

si =ci +1 =

13

7+ Y

1

00010

1

1

00110

11

0

01101001

0

0

0

0

1

1

1

1

00001111

Example:

10= = 0

01 1

11 1 0 0

1

1 1 10

Legend for stage i

xi yi Carry-in ci Sum s i Carry-out ci+1

X

Z

+ 6 0+xiyi

si

Carry-outci+1

Carry-inci

xiy

ic

ix

iy

ic

ix

iy

ic

ix

iy

ic

i x i yi ci =+ + +

yic

ix

ic

ix

iy

i+ +

At the ith stage:Input:ci is the carry-inOutput:si is the sumci+1 carry-out to (i+1)st

state

16

Addition logic for a single stage

Full adder(FA)

ci

ci 1+

si

Sum Carry

yi

xi

ci

yi

xi

ci

yi

xi

xi

ci

yi

si

ci 1+

Full Adder (FA): Symbol for the complete circuit for a single stage of addition.

17

n-bit subtractor

FA 1

y1

x1

s1

FA

c1

y0

x0

s0

FA

cn 1-

yn 1-

xn 1-

cn

sn 1-

Most significant bit(MSB) position

Least significant bit(LSB) position

•Recall X – Y is equivalent to adding 2’s complement of Y to X.•2’s complement is equivalent to 1’s complement + 1.•X – Y = X + Y + 1•2’s complement of positive and negative numbers is computed similarly.

18

n-bit adder/subtractor

FA 1

y1

x1

s1

FA

c1

y0

x0

s0

FA

cn 1-

yn 1-

xn 1-

cn

sn 1-

Most significant bit(MSB) position

Least significant bit(LSB) position

FA c0

y1

x1

s1

FA

c1

y0

x0

s0

FA

cn 1-

yn 1-

xn 1-

cn

sn 1-

Most significant bit(MSB) position

Least significant bit(LSB) position

Adder inputs:xi, yi, co=0

Subtractor inputs:xi, yi, co=1

19

n-bit adder/subtractor (contd..)

Add/Subcontrol

n-bit adder

xn 1-

x1

x0

cn

sn 1- s

1s

0

c0

yn 1-

y1

y0

•Add/sub control = 0, addition.•Add/sub control = 1, subtraction.

20

Detecting overflows

Overflows can only occur when the sign of the two operands is the same.

Overflow occurs if the sign of the result is different from the sign of the operands.

Recall that the MSB represents the sign. xn-1, yn-1, sn-1 represent the sign of operand x, operand y

and result s respectively. Circuit to detect overflow can be implemented by the

following logic expressions:

111111 nnnnnn syxsyxOverflow

1 nn ccOverflow

21

n-bit adder

•Cascade n full adder (FA) blocks to form a n-bit adder.•Carries propagate or ripple through this cascade, n-bit ripple carry adder.

FA c0

y1

x1

s1

FA

c1

y0

x0

s0

FA

cn 1-

yn 1-

xn 1-

cn

sn 1-

Most significant bit(MSB) position

Least significant bit(LSB) position

Carry-in c0 into the LSB position provides a convenient way toperform subtraction.

22

kn-bit adder

K n-bit numbers can be added by cascading k n-bit adders.

n-bit c0

yn

xn

sn

cn

y0

xn 1-

s0

ckn

sk 1- n

x0

yn 1-

y2n 1-

x2n 1-

ykn 1-

sn 1-

s2n 1-

skn 1-

xkn 1-

addern-bitadder

n-bitadder

Each n-bit adder forms a block, so this is cascading of blocks.Carries ripple or propagate through blocks, Blocked Ripple Carry Adder

23

Computing the add time

Consider 0th stage:x0

y0

c0c1

s0

FA

•c1 is available after 2 gate delays.•s1 is available after 1 gate delay.

ci

yi

xi

ci

yi

xi

xi

ci

yi

si

ci 1+

Sum Carry

24

Computing the add time (contd..)

x0y0

s2

FA

x0 y0x0y0

s1

FAc2

s0

FAc1c3

c0

x0y0

s3

FAc4

Cascade of 4 Full Adders, or a 4-bit adder

•s0 available after 1 gate delays, c1 available after 2 gate delays.•s1 available after 3 gate delays, c2 available after 4 gate delays.•s2 available after 5 gate delays, c3 available after 6 gate delays.•s3 available after 7 gate delays, c4 available after 8 gate delays.

For an n-bit adder, sn-1 is available after 2n-1 gate delays cn is available after 2n gate delays.

25

Fast addition

Recall the equations:

iiiiiii

iiii

cycxyxc

cyxs

1

Second equation can be written as:

iiiiii cyxyxc )(1

We can write:

iiiiii

iiii

yxPandyxGwhere

cPGc

1

•Gi is called generate function and Pi is called propagate function•Gi and Pi are computed only from xi and yi and not ci, thus they can be computed in one gate delay after X and Y are applied to the inputs of an n-bit adder.

26

Carry lookahead

ci1 Gi Pici

ci Gi 1 Pi 1ci 1

ci1 Gi Pi(Gi 1 Pi 1ci 1)

continuing

ci1 Gi Pi(Gi 1 Pi 1(Gi 2 Pi 2ci 2 ))

until

ci1 Gi PiGi 1 PiPi 1Gi 2 .. PiPi 1..P1G0 PiPi 1...P0c0

•All carries can be obtained 3 gate delays after X, Y and c0 are applied. -One gate delay for Pi and Gi

-Two gate delays in the AND-OR circuit for ci+1

•All sums can be obtained 1 gate delay after the carries are computed.•Independent of n, n-bit addition requires only 4 gate delays.•This is called Carry Lookahead adder.

27

Carry-lookahead adder

Carry-lookahead logic

B cell B cell B cell B cell

s3

P3G3

c3

P2G2

c2

s2

G1

c1

P1

s1

G0

c0

P0

s0

.c4

x1 y1x3 y3 x2 y2 x0 y0

Gi

ci

...

Pi si

xi yi

B cell

4-bit carry-lookahead adder.

B-cell for a single stage.

28

Carry lookahead adder (contd..)

Performing n-bit addition in 4 gate delays independent of n is good only theoretically because of fan-in constraints.

Last AND gate and OR gate require a fan-in of (n+1) for a n-bit adder. For a 4-bit adder (n=4) fan-in of 5 is required. Practical limit for most gates.

In order to add operands longer than 4 bits, we can cascade 4-bit Carry-Lookahead adders. Cascade of Carry-Lookahead adders is called Blocked Carry-Lookahead adder.

ci1

Gi P

iG

i 1 P

iP

i 1G

i 2 .. P

iP

i 1..P

1G

0 P

iP

i 1...P

0c0

29

Blocked Carry-Lookahead adder

c4 G3 P3G2 P3P2G1 P3P2 P1G0 P3P2 P1P0c0

Carry-out from a 4-bit block can be given as:

Rewrite this as:

P0I P3P2 P1P0

G0I G3 P3G2 P3P2G1 P3P2P1G0

Subscript I denotes the blocked carry lookahead and identifies the block.

Cascade 4 4-bit adders, c16 can be expressed as:

c16 G3I P3

IG2I P3

I P2IG1

I P3IP2

I P10G0

I P3I P2

I P10P0

0c0

30

Blocked Carry-Lookahead adder (contd..)

Carry-lookahead logic

4-bit adder 4-bit adder 4-bit adder 4-bit adder

s15-12

P3IG3

I

c12

P2IG2

I

c8

s11-8

G1I

c4

P1I

s7-4

G0I

c0

P0

I

s3-0

c16

x15-12

y15-12

x11-8

y11-8

x7-4

y7-4

x3-0

y3-0

.

After xi, yi and c0 are applied as inputs: - Gi and Pi for each stage are available after 1 gate delay. - PI is available after 2 and GI after 3 gate delays. - All carries are available after 5 gate delays. - c16 is available after 5 gate delays. - s15 which depends on c12 is available after 8 (5+3)gate delays (Recall that for a 4-bit carry lookahead adder, the last sum bit is available 3 gate delays after all inputs are available)

31

Multiplication of unsigned numbers

(13) Multiplicand M11

(143) Product P

(11) Multiplier Q10

01

11

1 1 0 1 Partial product (PP) #11 Partial product (PP) #2011

0 Partial product (PP) #30001 Partial product (PP) #4011

01 0 0 1 1 1 1

•Product of 2 n-bit numbers is at most a 2n-bit number. •We should expect to store a double-length result.

Unsigned multiplication can be viewed as addition of shifted versions of the multiplicand.

32

Multiplication of unsigned numbers (contd..)

We added the partial products at end. Alternative would be to add the partial products at each

stage. Rules to implement multiplication are:

If the ith bit of the multiplier is 1, shift the multiplicand and add the shifted multiplicand to the current value of the partial product.

Hand over the partial product to the next stage Value of the partial product at the start stage is 0.

33

Multiplication of unsigned numbers (contd..)

ith multiplier bit

carry incarry out

jth multiplicand bit

ith multiplier bit

Bit of incoming partial product (PPi)

Bit of outgoing partial product (PP(i+1))

FA

Typical multiplication cell

34

Combinatorial array multiplier

Mult

iplier

Multiplicand

m3 m2 m1 m00 0 0 0

q3

q2

q1

q00

p2

p1

p0

0

0

0

p3p4p5p6p7

PP1

PP2

PP3

(PP0)

,

Product is: p7,p6,..p0

Multiplicand is shifted by displacing it through an array of adders.

Combinatorial array multiplier

35

Combinatorial array multiplier (contd..)

Combinatorial array multipliers are: Extremely inefficient. Have a high gate count for multiplying numbers of

practical size such as 32-bit or 64-bit numbers. Perform only one function, namely, unsigned integer

product. Improve gate efficiency by using a mixture of

combinatorial array techniques and sequential techniques requiring less combinational logic.

36

Sequential multiplication

Recall the rule for generating partial products: If the ith bit of the multiplier is 1, add the appropriately

shifted multiplicand to the current partial product. Multiplicand has been shifted left when added to the

partial product. However, adding a left-shifted multiplicand to an

unshifted partial product is equivalent to adding an unshifted multiplicand to a right-shifted partial product.

37

Sequential multiplication (contd..)

Register A (initially 0)

qn 1-

mn 1-

n-bit

Multiplicand M

Controlsequencer

Multiplier Q

0

C

Shift right

adder

Add/Noaddcontrol

an 1- a0 q0

m0

0

MUX

•Load Register A with 0. •Registers are used to storemultiplier and multiplicand. •Each cycle repeat the following:steps:

1. If the LSB q0=1: -Add the multiplicand to A. -Store carry-out in flip-flop CElse if q0 = 0 -Do not add.2. Shift the contents of registerA and Q to the right, and discardq0.

38

Sequential multiplication (contd..)

Register A (initially 0)

qn 1-

mn 1-

n-bit

Multiplicand M

Controlsequencer

Multiplier Q

0

C

Shift right

adder

Add/Noaddcontrol

an 1- a0 q0

m0

0

MUX

1 1 1 1

1 0 1 1

1 1 1 11 1 1 0

1 1 1 01 1 0 1

1 1 0 1

Initial configuration

Add

M

1 1 0 1

C

First cycle

Second cycle

Third cycle

Fourth cycle

No add

Shift

ShiftAdd

Shift

ShiftAdd

1 1 1 1

0

00

10

00

10

0 0 0 0

0 1 1 01 1 0 1

0 0 1 1

1 0 0 10 1 0 0

0 0 0 11 0 0 0

1 0 0 1

1 0 1 1QA

Product

39

Unsigned division

•Division is a more tedious process than multiplication.•For the unsigned case, there are two standard approaches:

1 ).Restoring division. 2.) Non restoring division.

110110001001

0

10101

1101

1

11101101

10000

1101

1

1314

26

21

27413

Try dividing 13 into 2.Try dividing 13 into 26.

Try dividing 1101 into 1, 10, 100, 1000and 10001.

40

Restoring division

How do we know when the divisor has gone into part of the dividend correctly?

110110001001

0

10101

1101

1

11101101

10000

1101 Subtract 1101 from 1, result is negative

Subtract 1101 from 10, result is negative.Subtract 1101 from 100, result is negativeSubtract 1101 from 1000, result is negative.Subtract 1101 from 10001, result is positive.

41

Restoring division

Strategy for unsigned division:Shift the dividend one bit at a time starting from MSB into a register.Subtract the divisor from this register.If the result is negative (“didn’t go”):

- Add the divisor back into the register. - Record 0 into the result register .

If the result is positive: - Do not restore the intermediate result.

- Set a 1 into the result register.

42

Restoring division (contd..)

qn 1-

mn 1-

-bit

Divisor M

Controlsequencer

Dividend Q

Shift left

adder

an 1- a0 q0

m0

an

0

Add/Subtract

Quotientsetting

n 1+

A

Sign bit (result of sub)

Set Register A to 0.Load dividend in Q.Load divisor into M.Repeat n times:

- Shift A and Q left one bit.- Subtract M from A.

- Place the result in A.- If sign of A is 1, set q0 to

0 and add M back to A. Else set q0 to 1.

End of the process: - Quotient will be in Q.

- Remainder will be in A.

43

Restoring division (contd..)

10111

1 1 1 1 1

01111

0

0

0

1

000

0

0

00

0

00

00

0

1

00

0

00

SubtractShift

Restore

1 00001 0000

1 1

Initially

Subtract

Shift

10111100001100000000

SubtractShift

Restore

101110100010000

1 1

QuotientRemainder

Shift

101111 0000

Subtract

Second cycle

First cycle

Third cycle

Fourth cycle

00

0

0

00

1

01

10000

1 11 0000

11111Restore

q0Set

q0Set

q0Set

q0Set

101

1111

010001

44

Non-restoring division

Restoring division can be improved using non-restoring algorithm

The effect of restoring algorithm actually is:If A is positive, we shift it left and subtract M, that is compute 2A-MIf A is negative, we restore it (A+M), shift it left, and subtract M, thatis, 2(A+M) – M = 2A+M.Set q0 to 1 or 0 appropriately.

Non-restoring algorithm is:Set A to 0.Repeat n times:

If the sign of A is positive: Shift A and Q left and subtract M. Set q0 to

1. Else if the sign of A is negative:

Shift A and Q left and add M. Set q0 to 0.If the sign of A is 1, add A to M.

45

Non-restoring division (contd..)

Add

Remainder

0 0 0 01

1 1 1 1 1

0 0 0 1 1 Restore remainder

1

Quotient

0 0 1 01 1 1 1 1

0 0 0 01 1 1 1 1

Shift 0 0 01100001111

Add

0 0 0 1 10 0 0 0 1 0 0 01 1 1 0 1

ShiftSubtract

Initially 0 0 0 0 0 1 0 0 0

1 1 1 0 0000

1 1 1 0 00 0 0 1 1

0 0 0ShiftAdd

0 0 10 0 0 011 1 1 0 1

ShiftSubtract

0 0 0 110000

Fourth cycle

Third cycle

Second cycle

First cycle

q0Set

q0Set

q0Set

q0Set

101

1111

010001