Computer Orgnization

Rabie A. Ramadan

Lecture 7

Wired Control Unit

What are the states of the following design:

Memory Organization

Types of Memory

Cache Memory• Serves as a buffer for frequently accessed data

• Small High Cost

RAM (Main Memory)• Stores programs and data that the computer needs when executing a

program

• Dynamic RAM (DRAM) • Uses Tiny Capacitors

• Needs to be recharged every few milliseconds to keep the stored data

• Static RAM (SRAM)• Holds its data as long as the power is on

• D Flip Flop

Types of Memory (Cont.) ROM

• Stores critical information necessary to operate the system.

• Hardwired can not be programmed

Programmable Read Only Memory (PROM)• Can be programmed once using appropriate equipment

Erasable PROM (EPROM) • Can be programmed with special tool

• It has to be totally erased to be reprogrammed

Electrical Erasable PROM (EEPROM) • No special tools required

• Can erase a portion

Memory Hierarchy

The idea • Hide the slower memory behind the fast memory

• Cost and performance play major roles in selecting the memory.

Hit Vs. Miss Hit

• The requested data resides in a given level of memory.

Miss• The requested data is not found in the given level of memory

Hit rate• The percentage of memory accesses found in a given level of

memory.

Miss rate• The percentage of memory accesses not found in a given level of

memory.

Hit Vs. Miss (Cont.)

Hit time• The time required to access the requested information in a given

level of memory.

Miss penalty• The time required to process a miss,

• Replacing a block in an upper level of memory,

• The additional time to deliver the requested data to the processor.

Miss Scenario

The processor sends a request to the cache for location X• if found cache hit

• If not try next level

When the location is found load the whole block into the cache • Hoping that the processor will access one of the neighbor

locations next.

• One miss may lead to multiple hits Locality Can we compute the average access time based on this

memory Hierarchy?

Average Access Time Assume a memory hierarchy with three levels (L1, L2, and L3)

What is the memory average access time?

h1 hit at L1 (1-h1) miss at L1t1 L1 access time

h2 hit at L2(1-h2) miss at L2t2 L2 access time

h3 hit at L3=100%(1-h3) miss at L3t3 L3 access time

Locality of Reference One miss may lead to multiple hits Locality

Temporal locality• Recently accessed items tend to be accessed again in the near future.

Spatial locality• when a given address has been referenced, it is most likely that

addresses near it will be referenced within a short period of time. (for example, as in arrays or loops).

Sequential locality part of the spatial locality• Instructions tend to be accessed sequentially.

Cache memory

Cache • Stores recently used data closer to the CPU

Your home is the cache and the main memory is the grocery store • Buy what is most probably to be needed in the coming week

How a processor can know which block(s) to bring to the cache?• No way to know but can benefit from the locality concept

Impact of Temporal Locality

Assume that:• A loop instruction that is executed n times

• The request data created a cache miss requires tm to load the requested block from the main memory to the cache

• tc is the cache access time

What is the average access time?

n tavg

What does it mean?

Impact of Spatial Locality

Assume that: • m elements are requested due to spatial locality.

• The request data created a cache miss that requires tm to load the requested block from the main memory to the cache

• tc is the cache access time

What is the average access time?

What does it mean?

m tavg